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1 | /* |
2 | * Copyright 2013 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
aae95ca7 | 24 | #include "nv40.h" |
dceef5d8 BS |
25 | |
26 | static int | |
639c308e BS |
27 | nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, |
28 | struct nvkm_oclass *oclass, void *data, u32 size, | |
29 | struct nvkm_object **pobject) | |
dceef5d8 | 30 | { |
b1e4553c | 31 | struct nvkm_fb *fb = nvkm_fb(parent); |
aae95ca7 | 32 | struct nv40_ram *ram; |
b1e4553c | 33 | u32 fb474 = nv_rd32(fb, 0x100474); |
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34 | int ret; |
35 | ||
639c308e | 36 | ret = nvkm_ram_create(parent, engine, oclass, &ram); |
dceef5d8 BS |
37 | *pobject = nv_object(ram); |
38 | if (ret) | |
39 | return ret; | |
40 | ||
b1e4553c | 41 | if (fb474 & 0x00000004) |
aae95ca7 | 42 | ram->base.type = NV_MEM_TYPE_GDDR3; |
b1e4553c | 43 | if (fb474 & 0x00000002) |
aae95ca7 | 44 | ram->base.type = NV_MEM_TYPE_DDR2; |
b1e4553c | 45 | if (fb474 & 0x00000001) |
aae95ca7 | 46 | ram->base.type = NV_MEM_TYPE_DDR1; |
dceef5d8 | 47 | |
b1e4553c | 48 | ram->base.size = nv_rd32(fb, 0x10020c) & 0xff000000; |
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49 | ram->base.calc = nv40_ram_calc; |
50 | ram->base.prog = nv40_ram_prog; | |
51 | ram->base.tidy = nv40_ram_tidy; | |
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52 | return 0; |
53 | } | |
54 | ||
639c308e | 55 | struct nvkm_oclass |
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56 | nv44_ram_oclass = { |
57 | .handle = 0, | |
639c308e | 58 | .ofuncs = &(struct nvkm_ofuncs) { |
dceef5d8 | 59 | .ctor = nv44_ram_create, |
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60 | .dtor = _nvkm_ram_dtor, |
61 | .init = _nvkm_ram_init, | |
62 | .fini = _nvkm_ram_fini, | |
dceef5d8 BS |
63 | } |
64 | }; |