[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nvkm / subdev / mmu / nv04.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "vmm.h"

#include <nvif/class.h>

#define NV04_PDMA_SIZE (128 * 1024 * 1024)
#define NV04_PDMA_PAGE (  4 * 1024)

/*******************************************************************************
 * VM map/unmap callbacks
 ******************************************************************************/

static void
nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,
	       struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
	pte = 0x00008 + (pte * 4);
	nvkm_kmap(pgt);
	while (cnt) {
		u32 page = PAGE_SIZE / NV04_PDMA_PAGE;
		u32 phys = (u32)*list++;
		while (cnt && page--) {
			nvkm_wo32(pgt, pte, phys | 3);
			phys += NV04_PDMA_PAGE;
			pte += 4;
			cnt -= 1;
		}
	}
	nvkm_done(pgt);
}

static void
nv04_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
{
	pte = 0x00008 + (pte * 4);
	nvkm_kmap(pgt);
	while (cnt--) {
		nvkm_wo32(pgt, pte, 0x00000000);
		pte += 4;
	}
	nvkm_done(pgt);
}

static void
nv04_vm_flush(struct nvkm_vm *vm)
{
}

/*******************************************************************************
 * MMU subdev
 ******************************************************************************/

static int
nv04_mmu_oneinit(struct nvkm_mmu *mmu)
{
	mmu->vmm->pgt[0].mem[0] = mmu->vmm->pd->pt[0]->memory;
	mmu->vmm->pgt[0].refcount[0] = 1;
	return 0;
}

const struct nvkm_mmu_func
nv04_mmu = {
	.oneinit = nv04_mmu_oneinit,
	.limit = NV04_PDMA_SIZE,
	.dma_bits = 32,
	.pgt_bits = 32 - 12,
	.spg_shift = 12,
	.lpg_shift = 12,
	.map_sg = nv04_vm_map_sg,
	.unmap = nv04_vm_unmap,
	.flush = nv04_vm_flush,
	.vmm = {{ -1, -1, NVIF_CLASS_VMM_NV04}, nv04_vmm_new, true },
};

int
nv04_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
{
	return nvkm_mmu_new_(&nv04_mmu, device, index, pmmu);
}
Commit	Line	Data
3863c9bc BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
5b17f362	24	#include "vmm.h"
3863c9bc	25
5b17f362	26	#include <nvif/class.h>
3863c9bc	27
3863c9bc BS	28	#define NV04_PDMA_SIZE (128 * 1024 * 1024)
	29	#define NV04_PDMA_PAGE ( 4 * 1024)
	30
	31	/*******************************************************************************
	32	* VM map/unmap callbacks
	33	******************************************************************************/
	34
	35	static void
d0659d32	36	nv04_vm_map_sg(struct nvkm_vma vma, struct nvkm_memory pgt,
42594600	37	struct nvkm_mem mem, u32 pte, u32 cnt, dma_addr_t list)
3863c9bc BS	38	{
3863c9bc BS	39	pte = 0x00008 + (pte * 4);
cd821077	40	nvkm_kmap(pgt);
3863c9bc BS	41	while (cnt) {
	42	u32 page = PAGE_SIZE / NV04_PDMA_PAGE;
	43	u32 phys = (u32)*list++;
	44	while (cnt && page--) {
cd821077	45	nvkm_wo32(pgt, pte, phys \| 3);
3863c9bc BS	46	phys += NV04_PDMA_PAGE;
	47	pte += 4;
	48	cnt -= 1;
	49	}
	50	}
cd821077	51	nvkm_done(pgt);
3863c9bc BS	52	}
	53
	54	static void
d0659d32	55	nv04_vm_unmap(struct nvkm_vma vma, struct nvkm_memory pgt, u32 pte, u32 cnt)
3863c9bc BS	56	{
3863c9bc BS	57	pte = 0x00008 + (pte * 4);
cd821077	58	nvkm_kmap(pgt);
3863c9bc	59	while (cnt--) {
cd821077	60	nvkm_wo32(pgt, pte, 0x00000000);
3863c9bc BS	61	pte += 4;
3863c9bc BS	62	}
cd821077	63	nvkm_done(pgt);
3863c9bc BS	64	}
	65
	66	static void
42594600	67	nv04_vm_flush(struct nvkm_vm *vm)
3863c9bc BS	68	{
	69	}
	70
3863c9bc	71	/*******************************************************************************
5ce3bf3c	72	* MMU subdev
3863c9bc BS	73	******************************************************************************/
	74
	75	static int
5b17f362	76	nv04_mmu_oneinit(struct nvkm_mmu *mmu)
3863c9bc	77	{
5b17f362 BS	78	mmu->vmm->pgt[0].mem[0] = mmu->vmm->pd->pt[0]->memory;
5b17f362 BS	79	mmu->vmm->pgt[0].refcount[0] = 1;
3863c9bc BS	80	return 0;
	81	}
	82
c9582455 BS	83	const struct nvkm_mmu_func
	84	nv04_mmu = {
	85	.oneinit = nv04_mmu_oneinit,
c9582455 BS	86	.limit = NV04_PDMA_SIZE,
	87	.dma_bits = 32,
	88	.pgt_bits = 32 - 12,
	89	.spg_shift = 12,
	90	.lpg_shift = 12,
	91	.map_sg = nv04_vm_map_sg,
	92	.unmap = nv04_vm_unmap,
	93	.flush = nv04_vm_flush,
5b17f362	94	.vmm = {{ -1, -1, NVIF_CLASS_VMM_NV04}, nv04_vmm_new, true },
3863c9bc	95	};
c9582455 BS	96
	97	int
	98	nv04_mmu_new(struct nvkm_device device, int index, struct nvkm_mmu *pmmu)
	99	{
5b17f362	100	return nvkm_mmu_new_(&nv04_mmu, device, index, pmmu);
c9582455	101	}