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drm/omap: add PLL helper funcs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
736e60dd 42#include <linux/component.h>
80c39712 43
a0b38cc4 44#include <video/omapdss.h>
80c39712
TV		 45
46#include "dss.h"
a0acb557 47#include "dss_features.h"
9b372c2d 48#include "dispc.h"
80c39712
TV		 49
50/* DISPC */
8613b000 51#define DISPC_SZ_REGS SZ_4K
80c39712 52
5ed8cf5b
TV		 53enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57};
58
80c39712
TV		 59#define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
61
62#define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64
dcbe765b
CM		 65struct dispc_features {
66 u8 sw_start;
67 u8 fp_start;
68 u8 bp_start;
69 u16 sw_max;
70 u16 vp_max;
71 u16 hp_max;
33b89928
AT		 72 u8 mgr_width_start;
73 u8 mgr_height_start;
74 u16 mgr_width_max;
75 u16 mgr_height_max;
ca5ca69c
AT		 76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
0c6921de 78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 84 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 85 u16 width, u16 height, u16 out_width, u16 out_height,
86 bool mem_to_mem);
42a6961c 87 u8 num_fifos;
66a0f9e4
TV		 88
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
cffa947d
TV		 91
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
d0df9a2c
AT		 94
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
8bc65552
AT		 97
98 bool set_max_preload:1;
f2aee319
TV		 99
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
e5f80917
TV		 102
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
20efbc35
TV		 105
106 bool has_writeback:1;
3a38ed53
TV		 107
108 bool supports_double_pixel:1;
b7536d67
TV		 109
110 /*
111 * Field order for VENC is different than HDMI. We should handle this in
112 * some intelligent manner, but as the SoCs have either HDMI or VENC,
113 * never both, we can just use this flag for now.
114 */
115 bool reverse_ilace_field_order:1;
dcbe765b
CM		 116};
117
42a6961c
TV		 118#define DISPC_MAX_NR_FIFOS 5
119
80c39712 120static struct {
060b6d9c 121 struct platform_device *pdev;
80c39712 122 void __iomem *base;
4fbafaf3 123
affe360d 124 int irq;
0925afc9
TV		 125 irq_handler_t user_handler;
126 void *user_data;
80c39712 127
7b3926b3 128 unsigned long core_clk_rate;
5391e87d 129 unsigned long tv_pclk_rate;
7b3926b3 130
42a6961c
TV		 131 u32 fifo_size[DISPC_MAX_NR_FIFOS];
132 /* maps which plane is using a fifo. fifo-id -> plane-id */
133 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 134
49ea86f3 135 bool ctx_valid;
80c39712 136 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 137
dcbe765b 138 const struct dispc_features *feat;
0925afc9
TV		 139
140 bool is_enabled;
0006fd63
TV		 141
142 struct regmap *syscon_pol;
143 u32 syscon_pol_offset;
d49cd155
TV		 144
145 /* DISPC_CONTROL & DISPC_CONFIG lock*/
146 spinlock_t control_lock;
80c39712
TV		 147} dispc;
148
0d66cbb5
AJ		 149enum omap_color_component {
150 /* used for all color formats for OMAP3 and earlier
151 * and for RGB and Y color component on OMAP4
152 */
153 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
154 /* used for UV component for
155 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
156 * color formats on OMAP4
157 */
158 DISPC_COLOR_COMPONENT_UV = 1 << 1,
159};
160
efa70b3b
CM		 161enum mgr_reg_fields {
162 DISPC_MGR_FLD_ENABLE,
163 DISPC_MGR_FLD_STNTFT,
164 DISPC_MGR_FLD_GO,
165 DISPC_MGR_FLD_TFTDATALINES,
166 DISPC_MGR_FLD_STALLMODE,
167 DISPC_MGR_FLD_TCKENABLE,
168 DISPC_MGR_FLD_TCKSELECTION,
169 DISPC_MGR_FLD_CPR,
170 DISPC_MGR_FLD_FIFOHANDCHECK,
171 /* used to maintain a count of the above fields */
172 DISPC_MGR_FLD_NUM,
173};
174
5c348ba9
JS		 175struct dispc_reg_field {
176 u16 reg;
177 u8 high;
178 u8 low;
179};
180
efa70b3b
CM		 181static const struct {
182 const char *name;
183 u32 vsync_irq;
184 u32 framedone_irq;
185 u32 sync_lost_irq;
5c348ba9 186 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 187} mgr_desc[] = {
188 [OMAP_DSS_CHANNEL_LCD] = {
189 .name = "LCD",
190 .vsync_irq = DISPC_IRQ_VSYNC,
191 .framedone_irq = DISPC_IRQ_FRAMEDONE,
192 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
193 .reg_desc = {
194 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
195 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
196 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
197 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
198 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
199 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
200 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
201 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
202 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
203 },
204 },
205 [OMAP_DSS_CHANNEL_DIGIT] = {
206 .name = "DIGIT",
207 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 208 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 209 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
210 .reg_desc = {
211 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
212 [DISPC_MGR_FLD_STNTFT] = { },
213 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
214 [DISPC_MGR_FLD_TFTDATALINES] = { },
215 [DISPC_MGR_FLD_STALLMODE] = { },
216 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
217 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
218 [DISPC_MGR_FLD_CPR] = { },
219 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
220 },
221 },
222 [OMAP_DSS_CHANNEL_LCD2] = {
223 .name = "LCD2",
224 .vsync_irq = DISPC_IRQ_VSYNC2,
225 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
226 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
227 .reg_desc = {
228 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
229 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
230 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
231 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
232 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
233 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
234 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
235 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
236 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
237 },
238 },
e86d456a
CM		 239 [OMAP_DSS_CHANNEL_LCD3] = {
240 .name = "LCD3",
241 .vsync_irq = DISPC_IRQ_VSYNC3,
242 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
243 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
244 .reg_desc = {
245 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
246 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
247 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
248 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
249 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
250 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
251 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
252 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
253 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
254 },
255 },
efa70b3b
CM		 256};
257
6e5264b0
AT		 258struct color_conv_coef {
259 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
260 int full_range;
261};
262
65904155
TV		 263static unsigned long dispc_fclk_rate(void);
264static unsigned long dispc_core_clk_rate(void);
265static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
266static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
267
3e8a6ff2
AT		 268static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
269static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 270
55978cc2 271static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 272{
55978cc2 273 __raw_writel(val, dispc.base + idx);
80c39712
TV		 274}
275
55978cc2 276static inline u32 dispc_read_reg(const u16 idx)
80c39712 277{
55978cc2 278 return __raw_readl(dispc.base + idx);
80c39712
TV		 279}
280
efa70b3b
CM		 281static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
282{
5c348ba9 283 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 284 return REG_GET(rfld.reg, rfld.high, rfld.low);
285}
286
287static void mgr_fld_write(enum omap_channel channel,
288 enum mgr_reg_fields regfld, int val) {
5c348ba9 289 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
d49cd155
TV		 290 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
291 unsigned long flags;
292
293 if (need_lock)
294 spin_lock_irqsave(&dispc.control_lock, flags);
295
efa70b3b 296 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
d49cd155
TV		 297
298 if (need_lock)
299 spin_unlock_irqrestore(&dispc.control_lock, flags);
efa70b3b
CM		 300}
301
80c39712 302#define SR(reg) \
55978cc2 303 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 304#define RR(reg) \
55978cc2 305 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 306
4fbafaf3 307static void dispc_save_context(void)
80c39712 308{
c6104b8e 309 int i, j;
80c39712 310
4fbafaf3
TV		 311 DSSDBG("dispc_save_context\n");
312
80c39712
TV		 313 SR(IRQENABLE);
314 SR(CONTROL);
315 SR(CONFIG);
80c39712 316 SR(LINE_NUMBER);
11354dd5
AT		 317 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
318 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 319 SR(GLOBAL_ALPHA);
2a205f34
SS		 320 if (dss_has_feature(FEAT_MGR_LCD2)) {
321 SR(CONTROL2);
2a205f34
SS		 322 SR(CONFIG2);
323 }
e86d456a
CM		 324 if (dss_has_feature(FEAT_MGR_LCD3)) {
325 SR(CONTROL3);
326 SR(CONFIG3);
327 }
80c39712 328
c6104b8e
AT		 329 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
330 SR(DEFAULT_COLOR(i));
331 SR(TRANS_COLOR(i));
332 SR(SIZE_MGR(i));
333 if (i == OMAP_DSS_CHANNEL_DIGIT)
334 continue;
335 SR(TIMING_H(i));
336 SR(TIMING_V(i));
337 SR(POL_FREQ(i));
338 SR(DIVISORo(i));
339
340 SR(DATA_CYCLE1(i));
341 SR(DATA_CYCLE2(i));
342 SR(DATA_CYCLE3(i));
343
332e9d70 344 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 345 SR(CPR_COEF_R(i));
346 SR(CPR_COEF_G(i));
347 SR(CPR_COEF_B(i));
332e9d70 348 }
2a205f34 349 }
80c39712 350
c6104b8e
AT		 351 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
352 SR(OVL_BA0(i));
353 SR(OVL_BA1(i));
354 SR(OVL_POSITION(i));
355 SR(OVL_SIZE(i));
356 SR(OVL_ATTRIBUTES(i));
357 SR(OVL_FIFO_THRESHOLD(i));
358 SR(OVL_ROW_INC(i));
359 SR(OVL_PIXEL_INC(i));
360 if (dss_has_feature(FEAT_PRELOAD))
361 SR(OVL_PRELOAD(i));
362 if (i == OMAP_DSS_GFX) {
363 SR(OVL_WINDOW_SKIP(i));
364 SR(OVL_TABLE_BA(i));
365 continue;
366 }
367 SR(OVL_FIR(i));
368 SR(OVL_PICTURE_SIZE(i));
369 SR(OVL_ACCU0(i));
370 SR(OVL_ACCU1(i));
9b372c2d 371
c6104b8e
AT		 372 for (j = 0; j < 8; j++)
373 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 374
c6104b8e
AT		 375 for (j = 0; j < 8; j++)
376 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 377
c6104b8e
AT		 378 for (j = 0; j < 5; j++)
379 SR(OVL_CONV_COEF(i, j));
ab5ca071 380
c6104b8e
AT		 381 if (dss_has_feature(FEAT_FIR_COEF_V)) {
382 for (j = 0; j < 8; j++)
383 SR(OVL_FIR_COEF_V(i, j));
384 }
9b372c2d 385
c6104b8e
AT		 386 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
387 SR(OVL_BA0_UV(i));
388 SR(OVL_BA1_UV(i));
389 SR(OVL_FIR2(i));
390 SR(OVL_ACCU2_0(i));
391 SR(OVL_ACCU2_1(i));
ab5ca071 392
c6104b8e
AT		 393 for (j = 0; j < 8; j++)
394 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 395
c6104b8e
AT		 396 for (j = 0; j < 8; j++)
397 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 398
c6104b8e
AT		 399 for (j = 0; j < 8; j++)
400 SR(OVL_FIR_COEF_V2(i, j));
401 }
402 if (dss_has_feature(FEAT_ATTR2))
403 SR(OVL_ATTRIBUTES2(i));
ab5ca071 404 }
0cf35df3
MR		 405
406 if (dss_has_feature(FEAT_CORE_CLK_DIV))
407 SR(DIVISOR);
49ea86f3 408
49ea86f3
TV		 409 dispc.ctx_valid = true;
410
9229b516 411 DSSDBG("context saved\n");
80c39712
TV		 412}
413
4fbafaf3 414static void dispc_restore_context(void)
80c39712 415{
9229b516 416 int i, j;
4fbafaf3
TV		 417
418 DSSDBG("dispc_restore_context\n");
419
49ea86f3
TV		 420 if (!dispc.ctx_valid)
421 return;
422
75c7d59d 423 /*RR(IRQENABLE);*/
80c39712
TV		 424 /*RR(CONTROL);*/
425 RR(CONFIG);
80c39712 426 RR(LINE_NUMBER);
11354dd5
AT		 427 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
428 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 429 RR(GLOBAL_ALPHA);
c6104b8e 430 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 431 RR(CONFIG2);
e86d456a
CM		 432 if (dss_has_feature(FEAT_MGR_LCD3))
433 RR(CONFIG3);
80c39712 434
c6104b8e
AT		 435 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
436 RR(DEFAULT_COLOR(i));
437 RR(TRANS_COLOR(i));
438 RR(SIZE_MGR(i));
439 if (i == OMAP_DSS_CHANNEL_DIGIT)
440 continue;
441 RR(TIMING_H(i));
442 RR(TIMING_V(i));
443 RR(POL_FREQ(i));
444 RR(DIVISORo(i));
445
446 RR(DATA_CYCLE1(i));
447 RR(DATA_CYCLE2(i));
448 RR(DATA_CYCLE3(i));
2a205f34 449
332e9d70 450 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 451 RR(CPR_COEF_R(i));
452 RR(CPR_COEF_G(i));
453 RR(CPR_COEF_B(i));
332e9d70 454 }
2a205f34 455 }
80c39712 456
c6104b8e
AT		 457 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
458 RR(OVL_BA0(i));
459 RR(OVL_BA1(i));
460 RR(OVL_POSITION(i));
461 RR(OVL_SIZE(i));
462 RR(OVL_ATTRIBUTES(i));
463 RR(OVL_FIFO_THRESHOLD(i));
464 RR(OVL_ROW_INC(i));
465 RR(OVL_PIXEL_INC(i));
466 if (dss_has_feature(FEAT_PRELOAD))
467 RR(OVL_PRELOAD(i));
468 if (i == OMAP_DSS_GFX) {
469 RR(OVL_WINDOW_SKIP(i));
470 RR(OVL_TABLE_BA(i));
471 continue;
472 }
473 RR(OVL_FIR(i));
474 RR(OVL_PICTURE_SIZE(i));
475 RR(OVL_ACCU0(i));
476 RR(OVL_ACCU1(i));
9b372c2d 477
c6104b8e
AT		 478 for (j = 0; j < 8; j++)
479 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 480
c6104b8e
AT		 481 for (j = 0; j < 8; j++)
482 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 483
c6104b8e
AT		 484 for (j = 0; j < 5; j++)
485 RR(OVL_CONV_COEF(i, j));
ab5ca071 486
c6104b8e
AT		 487 if (dss_has_feature(FEAT_FIR_COEF_V)) {
488 for (j = 0; j < 8; j++)
489 RR(OVL_FIR_COEF_V(i, j));
490 }
9b372c2d 491
c6104b8e
AT		 492 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
493 RR(OVL_BA0_UV(i));
494 RR(OVL_BA1_UV(i));
495 RR(OVL_FIR2(i));
496 RR(OVL_ACCU2_0(i));
497 RR(OVL_ACCU2_1(i));
ab5ca071 498
c6104b8e
AT		 499 for (j = 0; j < 8; j++)
500 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 501
c6104b8e
AT		 502 for (j = 0; j < 8; j++)
503 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 504
c6104b8e
AT		 505 for (j = 0; j < 8; j++)
506 RR(OVL_FIR_COEF_V2(i, j));
507 }
508 if (dss_has_feature(FEAT_ATTR2))
509 RR(OVL_ATTRIBUTES2(i));
ab5ca071 510 }
80c39712 511
0cf35df3
MR		 512 if (dss_has_feature(FEAT_CORE_CLK_DIV))
513 RR(DIVISOR);
514
80c39712
TV		 515 /* enable last, because LCD & DIGIT enable are here */
516 RR(CONTROL);
2a205f34
SS		 517 if (dss_has_feature(FEAT_MGR_LCD2))
518 RR(CONTROL2);
e86d456a
CM		 519 if (dss_has_feature(FEAT_MGR_LCD3))
520 RR(CONTROL3);
75c7d59d 521 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 522 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 523
524 /*
525 * enable last so IRQs won't trigger before
526 * the context is fully restored
527 */
528 RR(IRQENABLE);
49ea86f3
TV		 529
530 DSSDBG("context restored\n");
80c39712
TV		 531}
532
533#undef SR
534#undef RR
535
4fbafaf3
TV		 536int dispc_runtime_get(void)
537{
538 int r;
539
540 DSSDBG("dispc_runtime_get\n");
541
542 r = pm_runtime_get_sync(&dispc.pdev->dev);
543 WARN_ON(r < 0);
544 return r < 0 ? r : 0;
545}
348be69d 546EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 547
548void dispc_runtime_put(void)
549{
550 int r;
551
552 DSSDBG("dispc_runtime_put\n");
553
0eaf9f52 554 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 555 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 556}
348be69d 557EXPORT_SYMBOL(dispc_runtime_put);
80c39712 558
3dcec4d6
TV		 559u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
560{
efa70b3b 561 return mgr_desc[channel].vsync_irq;
3dcec4d6 562}
348be69d 563EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 564
7d1365c9
TV		 565u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
566{
cffa947d
TV		 567 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
568 return 0;
569
efa70b3b 570 return mgr_desc[channel].framedone_irq;
7d1365c9 571}
348be69d 572EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 573
cb699200
TV		 574u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
575{
576 return mgr_desc[channel].sync_lost_irq;
577}
348be69d 578EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 579
0b23e5b8
AT		 580u32 dispc_wb_get_framedone_irq(void)
581{
582 return DISPC_IRQ_FRAMEDONEWB;
583}
584
26d9dd0d 585bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 586{
efa70b3b 587 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 588}
348be69d 589EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 590
26d9dd0d 591void dispc_mgr_go(enum omap_channel channel)
80c39712 592{
0bcfdba6 593 WARN_ON(!dispc_mgr_is_enabled(channel));
3c91ee8c 594 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 595
efa70b3b 596 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 597
efa70b3b 598 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 599}
348be69d 600EXPORT_SYMBOL(dispc_mgr_go);
80c39712 601
0b23e5b8
AT		 602bool dispc_wb_go_busy(void)
603{
604 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
605}
606
607void dispc_wb_go(void)
608{
609 enum omap_plane plane = OMAP_DSS_WB;
610 bool enable, go;
611
612 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
613
614 if (!enable)
615 return;
616
617 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
618 if (go) {
619 DSSERR("GO bit not down for WB\n");
620 return;
621 }
622
623 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
624}
625
f0e5caab 626static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 627{
9b372c2d 628 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 629}
630
f0e5caab 631static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 632{
9b372c2d 633 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 634}
635
f0e5caab 636static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 637{
9b372c2d 638 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 639}
640
f0e5caab 641static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 642{
643 BUG_ON(plane == OMAP_DSS_GFX);
644
645 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
646}
647
f0e5caab
TV		 648static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
649 u32 value)
ab5ca071
AJ		 650{
651 BUG_ON(plane == OMAP_DSS_GFX);
652
653 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
654}
655
f0e5caab 656static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 657{
658 BUG_ON(plane == OMAP_DSS_GFX);
659
660 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
661}
662
debd9074
CM		 663static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
664 int fir_vinc, int five_taps,
665 enum omap_color_component color_comp)
80c39712 666{
debd9074 667 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 668 int i;
669
debd9074
CM		 670 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
671 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 672
673 for (i = 0; i < 8; i++) {
674 u32 h, hv;
675
debd9074
CM		 676 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
677 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
678 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
679 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
680 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
681 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
682 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
683 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 684
0d66cbb5 685 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 686 dispc_ovl_write_firh_reg(plane, i, h);
687 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 688 } else {
f0e5caab
TV		 689 dispc_ovl_write_firh2_reg(plane, i, h);
690 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 691 }
692
80c39712
TV		 693 }
694
66be8f6c
GI		 695 if (five_taps) {
696 for (i = 0; i < 8; i++) {
697 u32 v;
debd9074
CM		 698 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
699 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 700 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 701 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 702 else
f0e5caab 703 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 704 }
80c39712
TV		 705 }
706}
707
80c39712 708
6e5264b0
AT		 709static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
710 const struct color_conv_coef *ct)
711{
80c39712
TV		 712#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
713
6e5264b0
AT		 714 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
715 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
716 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
717 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
718 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 719
6e5264b0 720 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 721
722#undef CVAL
80c39712
TV		 723}
724
6e5264b0
AT		 725static void dispc_setup_color_conv_coef(void)
726{
727 int i;
728 int num_ovl = dss_feat_get_num_ovls();
6e5264b0 729 const struct color_conv_coef ctbl_bt601_5_ovl = {
7d18bbee 730 /* YUV -> RGB */
6e5264b0
AT		 731 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
732 };
733 const struct color_conv_coef ctbl_bt601_5_wb = {
7d18bbee
TV		 734 /* RGB -> YUV */
735 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
6e5264b0
AT		 736 };
737
738 for (i = 1; i < num_ovl; i++)
739 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
740
20efbc35
TV		 741 if (dispc.feat->has_writeback)
742 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
6e5264b0 743}
80c39712 744
f0e5caab 745static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 746{
9b372c2d 747 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 748}
749
f0e5caab 750static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 751{
9b372c2d 752 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 753}
754
f0e5caab 755static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 756{
757 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
758}
759
f0e5caab 760static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 761{
762 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
763}
764
d79db853
AT		 765static void dispc_ovl_set_pos(enum omap_plane plane,
766 enum omap_overlay_caps caps, int x, int y)
80c39712 767{
d79db853
AT		 768 u32 val;
769
770 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
771 return;
772
773 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 774
775 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 776}
777
78b687fc
AT		 778static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
779 int height)
80c39712 780{
80c39712 781 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 782
36d87d95 783 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 784 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
785 else
786 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 787}
788
78b687fc
AT		 789static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
790 int height)
80c39712
TV		 791{
792 u32 val;
80c39712
TV		 793
794 BUG_ON(plane == OMAP_DSS_GFX);
795
796 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 797
36d87d95
AT		 798 if (plane == OMAP_DSS_WB)
799 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
800 else
801 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 802}
803
5b54ed3e
AT		 804static void dispc_ovl_set_zorder(enum omap_plane plane,
805 enum omap_overlay_caps caps, u8 zorder)
54128701 806{
5b54ed3e 807 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 808 return;
809
810 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
811}
812
813static void dispc_ovl_enable_zorder_planes(void)
814{
815 int i;
816
817 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
818 return;
819
820 for (i = 0; i < dss_feat_get_num_ovls(); i++)
821 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
822}
823
5b54ed3e
AT		 824static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
825 enum omap_overlay_caps caps, bool enable)
fd28a390 826{
5b54ed3e 827 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 828 return;
829
9b372c2d 830 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 831}
832
5b54ed3e
AT		 833static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
834 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 835{
b8c095b4 836 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 837 int shift;
838
5b54ed3e 839 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 840 return;
a0acb557 841
fe3cc9d6
TV		 842 shift = shifts[plane];
843 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 844}
845
f0e5caab 846static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 847{
9b372c2d 848 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 849}
850
f0e5caab 851static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 852{
9b372c2d 853 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 854}
855
f0e5caab 856static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 857 enum omap_color_mode color_mode)
858{
859 u32 m = 0;
f20e4220
AJ		 860 if (plane != OMAP_DSS_GFX) {
861 switch (color_mode) {
862 case OMAP_DSS_COLOR_NV12:
863 m = 0x0; break;
08f3267e 864 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 865 m = 0x1; break;
866 case OMAP_DSS_COLOR_RGBA16:
867 m = 0x2; break;
08f3267e 868 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 869 m = 0x4; break;
870 case OMAP_DSS_COLOR_ARGB16:
871 m = 0x5; break;
872 case OMAP_DSS_COLOR_RGB16:
873 m = 0x6; break;
874 case OMAP_DSS_COLOR_ARGB16_1555:
875 m = 0x7; break;
876 case OMAP_DSS_COLOR_RGB24U:
877 m = 0x8; break;
878 case OMAP_DSS_COLOR_RGB24P:
879 m = 0x9; break;
880 case OMAP_DSS_COLOR_YUV2:
881 m = 0xa; break;
882 case OMAP_DSS_COLOR_UYVY:
883 m = 0xb; break;
884 case OMAP_DSS_COLOR_ARGB32:
885 m = 0xc; break;
886 case OMAP_DSS_COLOR_RGBA32:
887 m = 0xd; break;
888 case OMAP_DSS_COLOR_RGBX32:
889 m = 0xe; break;
890 case OMAP_DSS_COLOR_XRGB16_1555:
891 m = 0xf; break;
892 default:
c6eee968 893 BUG(); return;
f20e4220
AJ		 894 }
895 } else {
896 switch (color_mode) {
897 case OMAP_DSS_COLOR_CLUT1:
898 m = 0x0; break;
899 case OMAP_DSS_COLOR_CLUT2:
900 m = 0x1; break;
901 case OMAP_DSS_COLOR_CLUT4:
902 m = 0x2; break;
903 case OMAP_DSS_COLOR_CLUT8:
904 m = 0x3; break;
905 case OMAP_DSS_COLOR_RGB12U:
906 m = 0x4; break;
907 case OMAP_DSS_COLOR_ARGB16:
908 m = 0x5; break;
909 case OMAP_DSS_COLOR_RGB16:
910 m = 0x6; break;
911 case OMAP_DSS_COLOR_ARGB16_1555:
912 m = 0x7; break;
913 case OMAP_DSS_COLOR_RGB24U:
914 m = 0x8; break;
915 case OMAP_DSS_COLOR_RGB24P:
916 m = 0x9; break;
08f3267e 917 case OMAP_DSS_COLOR_RGBX16:
f20e4220 918 m = 0xa; break;
08f3267e 919 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 920 m = 0xb; break;
921 case OMAP_DSS_COLOR_ARGB32:
922 m = 0xc; break;
923 case OMAP_DSS_COLOR_RGBA32:
924 m = 0xd; break;
925 case OMAP_DSS_COLOR_RGBX32:
926 m = 0xe; break;
927 case OMAP_DSS_COLOR_XRGB16_1555:
928 m = 0xf; break;
929 default:
c6eee968 930 BUG(); return;
f20e4220 931 }
80c39712
TV		 932 }
933
9b372c2d 934 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 935}
936
65e006ff
CM		 937static void dispc_ovl_configure_burst_type(enum omap_plane plane,
938 enum omap_dss_rotation_type rotation_type)
939{
940 if (dss_has_feature(FEAT_BURST_2D) == 0)
941 return;
942
943 if (rotation_type == OMAP_DSS_ROT_TILER)
944 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
945 else
946 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
947}
948
f427984e 949void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 950{
951 int shift;
952 u32 val;
2a205f34 953 int chan = 0, chan2 = 0;
80c39712
TV		 954
955 switch (plane) {
956 case OMAP_DSS_GFX:
957 shift = 8;
958 break;
959 case OMAP_DSS_VIDEO1:
960 case OMAP_DSS_VIDEO2:
b8c095b4 961 case OMAP_DSS_VIDEO3:
80c39712
TV		 962 shift = 16;
963 break;
964 default:
965 BUG();
966 return;
967 }
968
9b372c2d 969 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 970 if (dss_has_feature(FEAT_MGR_LCD2)) {
971 switch (channel) {
972 case OMAP_DSS_CHANNEL_LCD:
973 chan = 0;
974 chan2 = 0;
975 break;
976 case OMAP_DSS_CHANNEL_DIGIT:
977 chan = 1;
978 chan2 = 0;
979 break;
980 case OMAP_DSS_CHANNEL_LCD2:
981 chan = 0;
982 chan2 = 1;
983 break;
e86d456a
CM		 984 case OMAP_DSS_CHANNEL_LCD3:
985 if (dss_has_feature(FEAT_MGR_LCD3)) {
986 chan = 0;
987 chan2 = 2;
988 } else {
989 BUG();
990 return;
991 }
992 break;
c2665c41
TV		 993 case OMAP_DSS_CHANNEL_WB:
994 chan = 0;
995 chan2 = 3;
996 break;
2a205f34
SS		 997 default:
998 BUG();
c6eee968 999 return;
2a205f34
SS		 1000 }
1001
1002 val = FLD_MOD(val, chan, shift, shift);
1003 val = FLD_MOD(val, chan2, 31, 30);
1004 } else {
1005 val = FLD_MOD(val, channel, shift, shift);
1006 }
9b372c2d 1007 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 1008}
348be69d 1009EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 1010
2cc5d1af
TV		 1011static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1012{
1013 int shift;
1014 u32 val;
2cc5d1af
TV		 1015
1016 switch (plane) {
1017 case OMAP_DSS_GFX:
1018 shift = 8;
1019 break;
1020 case OMAP_DSS_VIDEO1:
1021 case OMAP_DSS_VIDEO2:
1022 case OMAP_DSS_VIDEO3:
1023 shift = 16;
1024 break;
1025 default:
1026 BUG();
c6eee968 1027 return 0;
2cc5d1af
TV		 1028 }
1029
1030 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1031
d7df5ad4
TV		 1032 if (FLD_GET(val, shift, shift) == 1)
1033 return OMAP_DSS_CHANNEL_DIGIT;
2cc5d1af 1034
d7df5ad4
TV		 1035 if (!dss_has_feature(FEAT_MGR_LCD2))
1036 return OMAP_DSS_CHANNEL_LCD;
1037
1038 switch (FLD_GET(val, 31, 30)) {
1039 case 0:
1040 default:
1041 return OMAP_DSS_CHANNEL_LCD;
1042 case 1:
1043 return OMAP_DSS_CHANNEL_LCD2;
1044 case 2:
1045 return OMAP_DSS_CHANNEL_LCD3;
c2665c41
TV		 1046 case 3:
1047 return OMAP_DSS_CHANNEL_WB;
d7df5ad4 1048 }
2cc5d1af
TV		 1049}
1050
d9ac773c
AT		 1051void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1052{
1053 enum omap_plane plane = OMAP_DSS_WB;
1054
1055 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1056}
1057
f0e5caab 1058static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1059 enum omap_burst_size burst_size)
1060{
8bbe09ee 1061 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1062 int shift;
80c39712 1063
fe3cc9d6 1064 shift = shifts[plane];
5ed8cf5b 1065 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1066}
1067
5ed8cf5b
TV		 1068static void dispc_configure_burst_sizes(void)
1069{
1070 int i;
1071 const int burst_size = BURST_SIZE_X8;
1072
1073 /* Configure burst size always to maximum size */
392faa0e 1074 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1075 dispc_ovl_set_burst_size(i, burst_size);
5b354af9
TV		 1076 if (dispc.feat->has_writeback)
1077 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
5ed8cf5b
TV		 1078}
1079
83fa2f2e 1080static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1081{
1082 unsigned unit = dss_feat_get_burst_size_unit();
1083 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1084 return unit * 8;
1085}
1086
d3862610
M		 1087void dispc_enable_gamma_table(bool enable)
1088{
1089 /*
1090 * This is partially implemented to support only disabling of
1091 * the gamma table.
1092 */
1093 if (enable) {
1094 DSSWARN("Gamma table enabling for TV not yet supported");
1095 return;
1096 }
1097
1098 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1099}
1100
c64dca40 1101static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1102{
efa70b3b 1103 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1104 return;
1105
efa70b3b 1106 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1107}
1108
c64dca40 1109static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1110 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1111{
1112 u32 coef_r, coef_g, coef_b;
1113
dd88b7a6 1114 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1115 return;
1116
1117 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1118 FLD_VAL(coefs->rb, 9, 0);
1119 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1120 FLD_VAL(coefs->gb, 9, 0);
1121 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1122 FLD_VAL(coefs->bb, 9, 0);
1123
1124 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1125 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1126 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1127}
1128
f0e5caab 1129static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1130{
1131 u32 val;
1132
1133 BUG_ON(plane == OMAP_DSS_GFX);
1134
9b372c2d 1135 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1136 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1137 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1138}
1139
d79db853
AT		 1140static void dispc_ovl_enable_replication(enum omap_plane plane,
1141 enum omap_overlay_caps caps, bool enable)
80c39712 1142{
b8c095b4 1143 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1144 int shift;
80c39712 1145
d79db853
AT		 1146 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1147 return;
1148
fe3cc9d6
TV		 1149 shift = shifts[plane];
1150 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1151}
1152
8f366162 1153static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1154 u16 height)
80c39712
TV		 1155{
1156 u32 val;
80c39712 1157
33b89928
AT		 1158 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1159 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1160
8f366162 1161 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1162}
1163
42a6961c 1164static void dispc_init_fifos(void)
80c39712 1165{
80c39712 1166 u32 size;
42a6961c 1167 int fifo;
a0acb557 1168 u8 start, end;
5ed8cf5b 1169 u32 unit;
47fc469b 1170 int i;
5ed8cf5b
TV		 1171
1172 unit = dss_feat_get_buffer_size_unit();
80c39712 1173
a0acb557 1174 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1175
42a6961c
TV		 1176 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1177 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1178 size *= unit;
42a6961c
TV		 1179 dispc.fifo_size[fifo] = size;
1180
1181 /*
1182 * By default fifos are mapped directly to overlays, fifo 0 to
1183 * ovl 0, fifo 1 to ovl 1, etc.
1184 */
1185 dispc.fifo_assignment[fifo] = fifo;
80c39712 1186 }
66a0f9e4
TV		 1187
1188 /*
1189 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1190 * causes problems with certain use cases, like using the tiler in 2D
1191 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1192 * giving GFX plane a larger fifo. WB but should work fine with a
1193 * smaller fifo.
1194 */
1195 if (dispc.feat->gfx_fifo_workaround) {
1196 u32 v;
1197
1198 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1199
1200 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1201 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1202 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1203 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1204
1205 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1206
1207 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1208 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1209 }
47fc469b
TV		 1210
1211 /*
1212 * Setup default fifo thresholds.
1213 */
1214 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1215 u32 low, high;
1216 const bool use_fifomerge = false;
1217 const bool manual_update = false;
1218
1219 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1220 use_fifomerge, manual_update);
1221
1222 dispc_ovl_set_fifo_threshold(i, low, high);
1223 }
65e116e1
TV		 1224
1225 if (dispc.feat->has_writeback) {
1226 u32 low, high;
1227 const bool use_fifomerge = false;
1228 const bool manual_update = false;
1229
1230 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1231 use_fifomerge, manual_update);
1232
1233 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1234 }
80c39712
TV		 1235}
1236
83fa2f2e 1237static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1238{
42a6961c
TV		 1239 int fifo;
1240 u32 size = 0;
1241
1242 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1243 if (dispc.fifo_assignment[fifo] == plane)
1244 size += dispc.fifo_size[fifo];
1245 }
1246
1247 return size;
80c39712
TV		 1248}
1249
6f04e1bf 1250void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1251{
a0acb557 1252 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1253 u32 unit;
1254
1255 unit = dss_feat_get_buffer_size_unit();
1256
1257 WARN_ON(low % unit != 0);
1258 WARN_ON(high % unit != 0);
1259
1260 low /= unit;
1261 high /= unit;
a0acb557 1262
9b372c2d
AT		 1263 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1264 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1265
3cb5d966 1266 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1267 plane,
9b372c2d 1268 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1269 lo_start, lo_end) * unit,
9b372c2d 1270 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1271 hi_start, hi_end) * unit,
1272 low * unit, high * unit);
80c39712 1273
9b372c2d 1274 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1275 FLD_VAL(high, hi_start, hi_end) |
1276 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1277
1278 /*
1279 * configure the preload to the pipeline's high threhold, if HT it's too
1280 * large for the preload field, set the threshold to the maximum value
1281 * that can be held by the preload register
1282 */
1283 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1284 plane != OMAP_DSS_WB)
1285 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712
TV		 1286}
1287
1288void dispc_enable_fifomerge(bool enable)
1289{
e6b0f884
TV		 1290 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1291 WARN_ON(enable);
1292 return;
1293 }
1294
80c39712
TV		 1295 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1296 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1297}
1298
83fa2f2e 1299void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1300 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1301 bool manual_update)
83fa2f2e
TV		 1302{
1303 /*
1304 * All sizes are in bytes. Both the buffer and burst are made of
1305 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1306 */
1307
1308 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1309 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1310 int i;
83fa2f2e
TV		 1311
1312 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1313 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1314
e0e405b9
TV		 1315 if (use_fifomerge) {
1316 total_fifo_size = 0;
392faa0e 1317 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1318 total_fifo_size += dispc_ovl_get_fifo_size(i);
1319 } else {
1320 total_fifo_size = ovl_fifo_size;
1321 }
1322
1323 /*
1324 * We use the same low threshold for both fifomerge and non-fifomerge
1325 * cases, but for fifomerge we calculate the high threshold using the
1326 * combined fifo size
1327 */
1328
3568f2a4 1329 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1330 *fifo_low = ovl_fifo_size - burst_size * 2;
1331 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1332 } else if (plane == OMAP_DSS_WB) {
1333 /*
1334 * Most optimal configuration for writeback is to push out data
1335 * to the interconnect the moment writeback pushes enough pixels
1336 * in the FIFO to form a burst
1337 */
1338 *fifo_low = 0;
1339 *fifo_high = burst_size;
e0e405b9
TV		 1340 } else {
1341 *fifo_low = ovl_fifo_size - burst_size;
1342 *fifo_high = total_fifo_size - buf_unit;
1343 }
83fa2f2e
TV		 1344}
1345
c64aa3a6
TV		 1346static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1347{
1348 int bit;
1349
1350 if (plane == OMAP_DSS_GFX)
1351 bit = 14;
1352 else
1353 bit = 23;
1354
1355 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1356}
1357
1358static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1359 int low, int high)
1360{
1361 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1362 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1363}
1364
1365static void dispc_init_mflag(void)
1366{
1367 int i;
1368
fe59e5cf
TV		 1369 /*
1370 * HACK: NV12 color format and MFLAG seem to have problems working
1371 * together: using two displays, and having an NV12 overlay on one of
1372 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1373 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1374 * remove the errors, but there doesn't seem to be a clear logic on
1375 * which values work and which not.
1376 *
1377 * As a work-around, set force MFLAG to always on.
1378 */
c64aa3a6 1379 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
fe59e5cf 1380 (1 << 0) | /* MFLAG_CTRL = force always on */
c64aa3a6
TV		 1381 (0 << 2)); /* MFLAG_START = disable */
1382
1383 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1384 u32 size = dispc_ovl_get_fifo_size(i);
1385 u32 unit = dss_feat_get_buffer_size_unit();
1386 u32 low, high;
1387
1388 dispc_ovl_set_mflag(i, true);
1389
1390 /*
1391 * Simulation team suggests below thesholds:
1392 * HT = fifosize * 5 / 8;
1393 * LT = fifosize * 4 / 8;
1394 */
1395
1396 low = size * 4 / 8 / unit;
1397 high = size * 5 / 8 / unit;
1398
1399 dispc_ovl_set_mflag_threshold(i, low, high);
1400 }
ecb0b366
TV		 1401
1402 if (dispc.feat->has_writeback) {
1403 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1404 u32 unit = dss_feat_get_buffer_size_unit();
1405 u32 low, high;
1406
1407 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1408
1409 /*
1410 * Simulation team suggests below thesholds:
1411 * HT = fifosize * 5 / 8;
1412 * LT = fifosize * 4 / 8;
1413 */
1414
1415 low = size * 4 / 8 / unit;
1416 high = size * 5 / 8 / unit;
1417
1418 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1419 }
c64aa3a6
TV		 1420}
1421
f0e5caab 1422static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1423 int hinc, int vinc,
1424 enum omap_color_component color_comp)
80c39712
TV		 1425{
1426 u32 val;
80c39712 1427
0d66cbb5
AJ		 1428 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1429 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1430
0d66cbb5
AJ		 1431 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1432 &hinc_start, &hinc_end);
1433 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1434 &vinc_start, &vinc_end);
1435 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1436 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1437
0d66cbb5
AJ		 1438 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1439 } else {
1440 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1441 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1442 }
80c39712
TV		 1443}
1444
f0e5caab 1445static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1446{
1447 u32 val;
87a7484b 1448 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1449
87a7484b
AT		 1450 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1451 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1452
1453 val = FLD_VAL(vaccu, vert_start, vert_end) |
1454 FLD_VAL(haccu, hor_start, hor_end);
1455
9b372c2d 1456 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1457}
1458
f0e5caab 1459static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1460{
1461 u32 val;
87a7484b 1462 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1463
87a7484b
AT		 1464 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1465 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1466
1467 val = FLD_VAL(vaccu, vert_start, vert_end) |
1468 FLD_VAL(haccu, hor_start, hor_end);
1469
9b372c2d 1470 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1471}
1472
f0e5caab
TV		 1473static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1474 int vaccu)
ab5ca071
AJ		 1475{
1476 u32 val;
1477
1478 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1479 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1480}
1481
f0e5caab
TV		 1482static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1483 int vaccu)
ab5ca071
AJ		 1484{
1485 u32 val;
1486
1487 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1488 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1489}
80c39712 1490
f0e5caab 1491static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1492 u16 orig_width, u16 orig_height,
1493 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1494 bool five_taps, u8 rotation,
1495 enum omap_color_component color_comp)
80c39712 1496{
0d66cbb5 1497 int fir_hinc, fir_vinc;
80c39712 1498
ed14a3ce
AJ		 1499 fir_hinc = 1024 * orig_width / out_width;
1500 fir_vinc = 1024 * orig_height / out_height;
80c39712 1501
debd9074
CM		 1502 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1503 color_comp);
f0e5caab 1504 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1505}
1506
05dd0f53
CM		 1507static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1508 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1509 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1510{
1511 int h_accu2_0, h_accu2_1;
1512 int v_accu2_0, v_accu2_1;
1513 int chroma_hinc, chroma_vinc;
1514 int idx;
1515
1516 struct accu {
1517 s8 h0_m, h0_n;
1518 s8 h1_m, h1_n;
1519 s8 v0_m, v0_n;
1520 s8 v1_m, v1_n;
1521 };
1522
1523 const struct accu *accu_table;
1524 const struct accu *accu_val;
1525
1526 static const struct accu accu_nv12[4] = {
1527 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1528 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1529 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1530 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1531 };
1532
1533 static const struct accu accu_nv12_ilace[4] = {
1534 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1535 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1536 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1537 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1538 };
1539
1540 static const struct accu accu_yuv[4] = {
1541 { 0, 1, 0, 1, 0, 1, 0, 1 },
1542 { 0, 1, 0, 1, 0, 1, 0, 1 },
1543 { -1, 1, 0, 1, 0, 1, 0, 1 },
1544 { 0, 1, 0, 1, -1, 1, 0, 1 },
1545 };
1546
1547 switch (rotation) {
1548 case OMAP_DSS_ROT_0:
1549 idx = 0;
1550 break;
1551 case OMAP_DSS_ROT_90:
1552 idx = 1;
1553 break;
1554 case OMAP_DSS_ROT_180:
1555 idx = 2;
1556 break;
1557 case OMAP_DSS_ROT_270:
1558 idx = 3;
1559 break;
1560 default:
1561 BUG();
c6eee968 1562 return;
05dd0f53
CM		 1563 }
1564
1565 switch (color_mode) {
1566 case OMAP_DSS_COLOR_NV12:
1567 if (ilace)
1568 accu_table = accu_nv12_ilace;
1569 else
1570 accu_table = accu_nv12;
1571 break;
1572 case OMAP_DSS_COLOR_YUV2:
1573 case OMAP_DSS_COLOR_UYVY:
1574 accu_table = accu_yuv;
1575 break;
1576 default:
1577 BUG();
c6eee968 1578 return;
05dd0f53
CM		 1579 }
1580
1581 accu_val = &accu_table[idx];
1582
1583 chroma_hinc = 1024 * orig_width / out_width;
1584 chroma_vinc = 1024 * orig_height / out_height;
1585
1586 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1587 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1588 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1589 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1590
1591 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1592 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1593}
1594
f0e5caab 1595static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1596 u16 orig_width, u16 orig_height,
1597 u16 out_width, u16 out_height,
1598 bool ilace, bool five_taps,
1599 bool fieldmode, enum omap_color_mode color_mode,
1600 u8 rotation)
1601{
1602 int accu0 = 0;
1603 int accu1 = 0;
1604 u32 l;
80c39712 1605
f0e5caab 1606 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1607 out_width, out_height, five_taps,
1608 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1609 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1610
87a7484b
AT		 1611 /* RESIZEENABLE and VERTICALTAPS */
1612 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1613 l |= (orig_width != out_width) ? (1 << 5) : 0;
1614 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1615 l |= five_taps ? (1 << 21) : 0;
80c39712 1616
87a7484b
AT		 1617 /* VRESIZECONF and HRESIZECONF */
1618 if (dss_has_feature(FEAT_RESIZECONF)) {
1619 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1620 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1621 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1622 }
80c39712 1623
87a7484b
AT		 1624 /* LINEBUFFERSPLIT */
1625 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1626 l &= ~(0x1 << 22);
1627 l |= five_taps ? (1 << 22) : 0;
1628 }
80c39712 1629
9b372c2d 1630 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1631
1632 /*
1633 * field 0 = even field = bottom field
1634 * field 1 = odd field = top field
1635 */
1636 if (ilace && !fieldmode) {
1637 accu1 = 0;
0d66cbb5 1638 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1639 if (accu0 >= 1024/2) {
1640 accu1 = 1024/2;
1641 accu0 -= accu1;
1642 }
1643 }
1644
f0e5caab
TV		 1645 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1646 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1647}
1648
f0e5caab 1649static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1650 u16 orig_width, u16 orig_height,
1651 u16 out_width, u16 out_height,
1652 bool ilace, bool five_taps,
1653 bool fieldmode, enum omap_color_mode color_mode,
1654 u8 rotation)
1655{
1656 int scale_x = out_width != orig_width;
1657 int scale_y = out_height != orig_height;
f92afae2 1658 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1659
1660 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1661 return;
1662 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1663 color_mode != OMAP_DSS_COLOR_UYVY &&
1664 color_mode != OMAP_DSS_COLOR_NV12)) {
1665 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1666 if (plane != OMAP_DSS_WB)
1667 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1668 return;
1669 }
36377357
TV		 1670
1671 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1672 out_height, ilace, color_mode, rotation);
1673
0d66cbb5
AJ		 1674 switch (color_mode) {
1675 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1676 if (chroma_upscale) {
1677 /* UV is subsampled by 2 horizontally and vertically */
1678 orig_height >>= 1;
1679 orig_width >>= 1;
1680 } else {
1681 /* UV is downsampled by 2 horizontally and vertically */
1682 orig_height <<= 1;
1683 orig_width <<= 1;
1684 }
1685
0d66cbb5
AJ		 1686 break;
1687 case OMAP_DSS_COLOR_YUV2:
1688 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1689 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1690 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1691 rotation == OMAP_DSS_ROT_180) {
1692 if (chroma_upscale)
1693 /* UV is subsampled by 2 horizontally */
1694 orig_width >>= 1;
1695 else
1696 /* UV is downsampled by 2 horizontally */
1697 orig_width <<= 1;
1698 }
1699
0d66cbb5
AJ		 1700 /* must use FIR for YUV422 if rotated */
1701 if (rotation != OMAP_DSS_ROT_0)
1702 scale_x = scale_y = true;
20fbb50b 1703
0d66cbb5
AJ		 1704 break;
1705 default:
1706 BUG();
c6eee968 1707 return;
0d66cbb5
AJ		 1708 }
1709
1710 if (out_width != orig_width)
1711 scale_x = true;
1712 if (out_height != orig_height)
1713 scale_y = true;
1714
f0e5caab 1715 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1716 out_width, out_height, five_taps,
1717 rotation, DISPC_COLOR_COMPONENT_UV);
1718
2a5561b1
AT		 1719 if (plane != OMAP_DSS_WB)
1720 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1721 (scale_x || scale_y) ? 1 : 0, 8, 8);
1722
0d66cbb5
AJ		 1723 /* set H scaling */
1724 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1725 /* set V scaling */
1726 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1727}
1728
f0e5caab 1729static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1730 u16 orig_width, u16 orig_height,
1731 u16 out_width, u16 out_height,
1732 bool ilace, bool five_taps,
1733 bool fieldmode, enum omap_color_mode color_mode,
1734 u8 rotation)
1735{
1736 BUG_ON(plane == OMAP_DSS_GFX);
1737
f0e5caab 1738 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1739 orig_width, orig_height,
1740 out_width, out_height,
1741 ilace, five_taps,
1742 fieldmode, color_mode,
1743 rotation);
1744
f0e5caab 1745 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1746 orig_width, orig_height,
1747 out_width, out_height,
1748 ilace, five_taps,
1749 fieldmode, color_mode,
1750 rotation);
1751}
1752
f0e5caab 1753static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1754 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1755 bool mirroring, enum omap_color_mode color_mode)
1756{
87a7484b
AT		 1757 bool row_repeat = false;
1758 int vidrot = 0;
1759
80c39712
TV		 1760 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1761 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1762
1763 if (mirroring) {
1764 switch (rotation) {
1765 case OMAP_DSS_ROT_0:
1766 vidrot = 2;
1767 break;
1768 case OMAP_DSS_ROT_90:
1769 vidrot = 1;
1770 break;
1771 case OMAP_DSS_ROT_180:
1772 vidrot = 0;
1773 break;
1774 case OMAP_DSS_ROT_270:
1775 vidrot = 3;
1776 break;
1777 }
1778 } else {
1779 switch (rotation) {
1780 case OMAP_DSS_ROT_0:
1781 vidrot = 0;
1782 break;
1783 case OMAP_DSS_ROT_90:
1784 vidrot = 1;
1785 break;
1786 case OMAP_DSS_ROT_180:
1787 vidrot = 2;
1788 break;
1789 case OMAP_DSS_ROT_270:
1790 vidrot = 3;
1791 break;
1792 }
1793 }
1794
80c39712 1795 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1796 row_repeat = true;
80c39712 1797 else
87a7484b 1798 row_repeat = false;
80c39712 1799 }
87a7484b 1800
3397cc6a
TV		 1801 /*
1802 * OMAP4/5 Errata i631:
1803 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1804 * rows beyond the framebuffer, which may cause OCP error.
1805 */
1806 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1807 rotation_type != OMAP_DSS_ROT_TILER)
1808 vidrot = 1;
1809
9b372c2d 1810 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1811 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1812 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1813 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1814
1815 if (color_mode == OMAP_DSS_COLOR_NV12) {
1816 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1817 (rotation == OMAP_DSS_ROT_0 ||
1818 rotation == OMAP_DSS_ROT_180);
1819 /* DOUBLESTRIDE */
1820 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1821 }
1822
80c39712
TV		 1823}
1824
1825static int color_mode_to_bpp(enum omap_color_mode color_mode)
1826{
1827 switch (color_mode) {
1828 case OMAP_DSS_COLOR_CLUT1:
1829 return 1;
1830 case OMAP_DSS_COLOR_CLUT2:
1831 return 2;
1832 case OMAP_DSS_COLOR_CLUT4:
1833 return 4;
1834 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1835 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1836 return 8;
1837 case OMAP_DSS_COLOR_RGB12U:
1838 case OMAP_DSS_COLOR_RGB16:
1839 case OMAP_DSS_COLOR_ARGB16:
1840 case OMAP_DSS_COLOR_YUV2:
1841 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1842 case OMAP_DSS_COLOR_RGBA16:
1843 case OMAP_DSS_COLOR_RGBX16:
1844 case OMAP_DSS_COLOR_ARGB16_1555:
1845 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1846 return 16;
1847 case OMAP_DSS_COLOR_RGB24P:
1848 return 24;
1849 case OMAP_DSS_COLOR_RGB24U:
1850 case OMAP_DSS_COLOR_ARGB32:
1851 case OMAP_DSS_COLOR_RGBA32:
1852 case OMAP_DSS_COLOR_RGBX32:
1853 return 32;
1854 default:
1855 BUG();
c6eee968 1856 return 0;
80c39712
TV		 1857 }
1858}
1859
1860static s32 pixinc(int pixels, u8 ps)
1861{
1862 if (pixels == 1)
1863 return 1;
1864 else if (pixels > 1)
1865 return 1 + (pixels - 1) * ps;
1866 else if (pixels < 0)
1867 return 1 - (-pixels + 1) * ps;
1868 else
1869 BUG();
c6eee968 1870 return 0;
80c39712
TV		 1871}
1872
1873static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1874 u16 screen_width,
1875 u16 width, u16 height,
1876 enum omap_color_mode color_mode, bool fieldmode,
1877 unsigned int field_offset,
1878 unsigned *offset0, unsigned *offset1,
aed74b55 1879 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1880{
1881 u8 ps;
1882
1883 /* FIXME CLUT formats */
1884 switch (color_mode) {
1885 case OMAP_DSS_COLOR_CLUT1:
1886 case OMAP_DSS_COLOR_CLUT2:
1887 case OMAP_DSS_COLOR_CLUT4:
1888 case OMAP_DSS_COLOR_CLUT8:
1889 BUG();
1890 return;
1891 case OMAP_DSS_COLOR_YUV2:
1892 case OMAP_DSS_COLOR_UYVY:
1893 ps = 4;
1894 break;
1895 default:
1896 ps = color_mode_to_bpp(color_mode) / 8;
1897 break;
1898 }
1899
1900 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1901 width, height);
1902
1903 /*
1904 * field 0 = even field = bottom field
1905 * field 1 = odd field = top field
1906 */
1907 switch (rotation + mirror * 4) {
1908 case OMAP_DSS_ROT_0:
1909 case OMAP_DSS_ROT_180:
1910 /*
1911 * If the pixel format is YUV or UYVY divide the width
1912 * of the image by 2 for 0 and 180 degree rotation.
1913 */
1914 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1915 color_mode == OMAP_DSS_COLOR_UYVY)
1916 width = width >> 1;
1917 case OMAP_DSS_ROT_90:
1918 case OMAP_DSS_ROT_270:
1919 *offset1 = 0;
1920 if (field_offset)
1921 *offset0 = field_offset * screen_width * ps;
1922 else
1923 *offset0 = 0;
1924
aed74b55
CM		 1925 *row_inc = pixinc(1 +
1926 (y_predecim * screen_width - x_predecim * width) +
1927 (fieldmode ? screen_width : 0), ps);
1928 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1929 break;
1930
1931 case OMAP_DSS_ROT_0 + 4:
1932 case OMAP_DSS_ROT_180 + 4:
1933 /* If the pixel format is YUV or UYVY divide the width
1934 * of the image by 2 for 0 degree and 180 degree
1935 */
1936 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1937 color_mode == OMAP_DSS_COLOR_UYVY)
1938 width = width >> 1;
1939 case OMAP_DSS_ROT_90 + 4:
1940 case OMAP_DSS_ROT_270 + 4:
1941 *offset1 = 0;
1942 if (field_offset)
1943 *offset0 = field_offset * screen_width * ps;
1944 else
1945 *offset0 = 0;
aed74b55
CM		 1946 *row_inc = pixinc(1 -
1947 (y_predecim * screen_width + x_predecim * width) -
1948 (fieldmode ? screen_width : 0), ps);
1949 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1950 break;
1951
1952 default:
1953 BUG();
c6eee968 1954 return;
80c39712
TV		 1955 }
1956}
1957
1958static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1959 u16 screen_width,
1960 u16 width, u16 height,
1961 enum omap_color_mode color_mode, bool fieldmode,
1962 unsigned int field_offset,
1963 unsigned *offset0, unsigned *offset1,
aed74b55 1964 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1965{
1966 u8 ps;
1967 u16 fbw, fbh;
1968
1969 /* FIXME CLUT formats */
1970 switch (color_mode) {
1971 case OMAP_DSS_COLOR_CLUT1:
1972 case OMAP_DSS_COLOR_CLUT2:
1973 case OMAP_DSS_COLOR_CLUT4:
1974 case OMAP_DSS_COLOR_CLUT8:
1975 BUG();
1976 return;
1977 default:
1978 ps = color_mode_to_bpp(color_mode) / 8;
1979 break;
1980 }
1981
1982 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1983 width, height);
1984
1985 /* width & height are overlay sizes, convert to fb sizes */
1986
1987 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1988 fbw = width;
1989 fbh = height;
1990 } else {
1991 fbw = height;
1992 fbh = width;
1993 }
1994
1995 /*
1996 * field 0 = even field = bottom field
1997 * field 1 = odd field = top field
1998 */
1999 switch (rotation + mirror * 4) {
2000 case OMAP_DSS_ROT_0:
2001 *offset1 = 0;
2002 if (field_offset)
2003 *offset0 = *offset1 + field_offset * screen_width * ps;
2004 else
2005 *offset0 = *offset1;
aed74b55
CM		 2006 *row_inc = pixinc(1 +
2007 (y_predecim * screen_width - fbw * x_predecim) +
2008 (fieldmode ? screen_width : 0), ps);
2009 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2010 color_mode == OMAP_DSS_COLOR_UYVY)
2011 *pix_inc = pixinc(x_predecim, 2 * ps);
2012 else
2013 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2014 break;
2015 case OMAP_DSS_ROT_90:
2016 *offset1 = screen_width * (fbh - 1) * ps;
2017 if (field_offset)
2018 *offset0 = *offset1 + field_offset * ps;
2019 else
2020 *offset0 = *offset1;
aed74b55
CM		 2021 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2022 y_predecim + (fieldmode ? 1 : 0), ps);
2023 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2024 break;
2025 case OMAP_DSS_ROT_180:
2026 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2027 if (field_offset)
2028 *offset0 = *offset1 - field_offset * screen_width * ps;
2029 else
2030 *offset0 = *offset1;
2031 *row_inc = pixinc(-1 -
aed74b55
CM		 2032 (y_predecim * screen_width - fbw * x_predecim) -
2033 (fieldmode ? screen_width : 0), ps);
2034 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2035 color_mode == OMAP_DSS_COLOR_UYVY)
2036 *pix_inc = pixinc(-x_predecim, 2 * ps);
2037 else
2038 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2039 break;
2040 case OMAP_DSS_ROT_270:
2041 *offset1 = (fbw - 1) * ps;
2042 if (field_offset)
2043 *offset0 = *offset1 - field_offset * ps;
2044 else
2045 *offset0 = *offset1;
aed74b55
CM		 2046 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2047 y_predecim - (fieldmode ? 1 : 0), ps);
2048 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2049 break;
2050
2051 /* mirroring */
2052 case OMAP_DSS_ROT_0 + 4:
2053 *offset1 = (fbw - 1) * ps;
2054 if (field_offset)
2055 *offset0 = *offset1 + field_offset * screen_width * ps;
2056 else
2057 *offset0 = *offset1;
aed74b55 2058 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 2059 (fieldmode ? screen_width : 0),
2060 ps);
aed74b55
CM		 2061 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2062 color_mode == OMAP_DSS_COLOR_UYVY)
2063 *pix_inc = pixinc(-x_predecim, 2 * ps);
2064 else
2065 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2066 break;
2067
2068 case OMAP_DSS_ROT_90 + 4:
2069 *offset1 = 0;
2070 if (field_offset)
2071 *offset0 = *offset1 + field_offset * ps;
2072 else
2073 *offset0 = *offset1;
aed74b55
CM		 2074 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2075 y_predecim + (fieldmode ? 1 : 0),
80c39712 2076 ps);
aed74b55 2077 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2078 break;
2079
2080 case OMAP_DSS_ROT_180 + 4:
2081 *offset1 = screen_width * (fbh - 1) * ps;
2082 if (field_offset)
2083 *offset0 = *offset1 - field_offset * screen_width * ps;
2084 else
2085 *offset0 = *offset1;
aed74b55 2086 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 2087 (fieldmode ? screen_width : 0),
2088 ps);
aed74b55
CM		 2089 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2090 color_mode == OMAP_DSS_COLOR_UYVY)
2091 *pix_inc = pixinc(x_predecim, 2 * ps);
2092 else
2093 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2094 break;
2095
2096 case OMAP_DSS_ROT_270 + 4:
2097 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2098 if (field_offset)
2099 *offset0 = *offset1 - field_offset * ps;
2100 else
2101 *offset0 = *offset1;
aed74b55
CM		 2102 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2103 y_predecim - (fieldmode ? 1 : 0),
80c39712 2104 ps);
aed74b55 2105 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2106 break;
2107
2108 default:
2109 BUG();
c6eee968 2110 return;
80c39712
TV		 2111 }
2112}
2113
65e006ff
CM		 2114static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2115 enum omap_color_mode color_mode, bool fieldmode,
2116 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2117 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2118{
2119 u8 ps;
2120
2121 switch (color_mode) {
2122 case OMAP_DSS_COLOR_CLUT1:
2123 case OMAP_DSS_COLOR_CLUT2:
2124 case OMAP_DSS_COLOR_CLUT4:
2125 case OMAP_DSS_COLOR_CLUT8:
2126 BUG();
2127 return;
2128 default:
2129 ps = color_mode_to_bpp(color_mode) / 8;
2130 break;
2131 }
2132
2133 DSSDBG("scrw %d, width %d\n", screen_width, width);
2134
2135 /*
2136 * field 0 = even field = bottom field
2137 * field 1 = odd field = top field
2138 */
2139 *offset1 = 0;
2140 if (field_offset)
2141 *offset0 = *offset1 + field_offset * screen_width * ps;
2142 else
2143 *offset0 = *offset1;
2144 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2145 (fieldmode ? screen_width : 0), ps);
2146 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2147 color_mode == OMAP_DSS_COLOR_UYVY)
2148 *pix_inc = pixinc(x_predecim, 2 * ps);
2149 else
2150 *pix_inc = pixinc(x_predecim, ps);
2151}
2152
7faa9233
CM		 2153/*
2154 * This function is used to avoid synclosts in OMAP3, because of some
2155 * undocumented horizontal position and timing related limitations.
2156 */
465ec13f 2157static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2158 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2159 u16 width, u16 height, u16 out_width, u16 out_height,
2160 bool five_taps)
7faa9233 2161{
230edc03 2162 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2163 unsigned long nonactive;
7faa9233
CM		 2164 static const u8 limits[3] = { 8, 10, 20 };
2165 u64 val, blank;
2166 int i;
2167
81ab95b7 2168 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2169
2170 i = 0;
2171 if (out_height < height)
2172 i++;
2173 if (out_width < width)
2174 i++;
81ab95b7 2175 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2176 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2177 if (blank <= limits[i])
2178 return -EINVAL;
2179
e4998634
ID		 2180 /* FIXME add checks for 3-tap filter once the limitations are known */
2181 if (!five_taps)
2182 return 0;
2183
7faa9233
CM		 2184 /*
2185 * Pixel data should be prepared before visible display point starts.
2186 * So, atleast DS-2 lines must have already been fetched by DISPC
2187 * during nonactive - pos_x period.
2188 */
2189 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2190 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2191 val, max(0, ds - 2) * width);
2192 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2193 return -EINVAL;
2194
2195 /*
2196 * All lines need to be refilled during the nonactive period of which
2197 * only one line can be loaded during the active period. So, atleast
2198 * DS - 1 lines should be loaded during nonactive period.
2199 */
2200 val = div_u64((u64)nonactive * lclk, pclk);
2201 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2202 val, max(0, ds - 1) * width);
2203 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2204 return -EINVAL;
2205
2206 return 0;
2207}
2208
8702ee50 2209static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2210 const struct omap_video_timings *mgr_timings, u16 width,
2211 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2212 enum omap_color_mode color_mode)
80c39712 2213{
8b53d991 2214 u32 core_clk = 0;
3e8a6ff2 2215 u64 tmp;
80c39712 2216
7282f1b7
CM		 2217 if (height <= out_height && width <= out_width)
2218 return (unsigned long) pclk;
2219
80c39712 2220 if (height > out_height) {
81ab95b7 2221 unsigned int ppl = mgr_timings->x_res;
80c39712 2222
c582935c 2223 tmp = (u64)pclk * height * out_width;
80c39712 2224 do_div(tmp, 2 * out_height * ppl);
8b53d991 2225 core_clk = tmp;
80c39712 2226
2d9c5597
VS		 2227 if (height > 2 * out_height) {
2228 if (ppl == out_width)
2229 return 0;
2230
c582935c 2231 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
80c39712 2232 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2233 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2234 }
2235 }
2236
2237 if (width > out_width) {
c582935c 2238 tmp = (u64)pclk * width;
80c39712 2239 do_div(tmp, out_width);
8b53d991 2240 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2241
2242 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2243 core_clk <<= 1;
80c39712
TV		 2244 }
2245
8b53d991 2246 return core_clk;
80c39712
TV		 2247}
2248
8702ee50 2249static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2250 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2251{
dcbe765b
CM		 2252 if (height > out_height && width > out_width)
2253 return pclk * 4;
2254 else
2255 return pclk * 2;
2256}
2257
8702ee50 2258static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2259 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2260{
2261 unsigned int hf, vf;
2262
2263 /*
2264 * FIXME how to determine the 'A' factor
2265 * for the no downscaling case ?
2266 */
2267
2268 if (width > 3 * out_width)
2269 hf = 4;
2270 else if (width > 2 * out_width)
2271 hf = 3;
2272 else if (width > out_width)
2273 hf = 2;
2274 else
2275 hf = 1;
80c39712
TV		 2276 if (height > out_height)
2277 vf = 2;
2278 else
2279 vf = 1;
2280
dcbe765b
CM		 2281 return pclk * vf * hf;
2282}
2283
8702ee50 2284static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2285 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2286{
8ba85306
AT		 2287 /*
2288 * If the overlay/writeback is in mem to mem mode, there are no
2289 * downscaling limitations with respect to pixel clock, return 1 as
2290 * required core clock to represent that we have sufficient enough
2291 * core clock to do maximum downscaling
2292 */
2293 if (mem_to_mem)
2294 return 1;
2295
dcbe765b
CM		 2296 if (width > out_width)
2297 return DIV_ROUND_UP(pclk, out_width) * width;
2298 else
2299 return pclk;
2300}
2301
0c6921de 2302static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2303 const struct omap_video_timings *mgr_timings,
2304 u16 width, u16 height, u16 out_width, u16 out_height,
2305 enum omap_color_mode color_mode, bool *five_taps,
2306 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2307 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2308{
2309 int error;
2310 u16 in_width, in_height;
2311 int min_factor = min(*decim_x, *decim_y);
2312 const int maxsinglelinewidth =
2313 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2314
dcbe765b
CM		 2315 *five_taps = false;
2316
2317 do {
eec77da2
TV		 2318 in_height = height / *decim_y;
2319 in_width = width / *decim_x;
8702ee50 2320 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2321 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2322 error = (in_width > maxsinglelinewidth || !*core_clk ||
2323 *core_clk > dispc_core_clk_rate());
2324 if (error) {
2325 if (*decim_x == *decim_y) {
2326 *decim_x = min_factor;
2327 ++*decim_y;
2328 } else {
2329 swap(*decim_x, *decim_y);
2330 if (*decim_x < *decim_y)
2331 ++*decim_x;
2332 }
2333 }
2334 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2335
3ce17b48
TV		 2336 if (error) {
2337 DSSERR("failed to find scaling settings\n");
2338 return -EINVAL;
2339 }
2340
dcbe765b
CM		 2341 if (in_width > maxsinglelinewidth) {
2342 DSSERR("Cannot scale max input width exceeded");
2343 return -EINVAL;
2344 }
2345 return 0;
2346}
2347
0c6921de 2348static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2349 const struct omap_video_timings *mgr_timings,
2350 u16 width, u16 height, u16 out_width, u16 out_height,
2351 enum omap_color_mode color_mode, bool *five_taps,
2352 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2353 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2354{
2355 int error;
2356 u16 in_width, in_height;
dcbe765b
CM		 2357 const int maxsinglelinewidth =
2358 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2359
2360 do {
eec77da2
TV		 2361 in_height = height / *decim_y;
2362 in_width = width / *decim_x;
e4998634 2363 *five_taps = in_height > out_height;
dcbe765b
CM		 2364
2365 if (in_width > maxsinglelinewidth)
2366 if (in_height > out_height &&
2367 in_height < out_height * 2)
2368 *five_taps = false;
e4998634
ID		 2369again:
2370 if (*five_taps)
2371 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2372 in_width, in_height, out_width,
2373 out_height, color_mode);
2374 else
8702ee50 2375 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2376 in_height, out_width, out_height,
2377 mem_to_mem);
dcbe765b 2378
e4998634
ID		 2379 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2380 pos_x, in_width, in_height, out_width,
2381 out_height, *five_taps);
2382 if (error && *five_taps) {
2383 *five_taps = false;
2384 goto again;
2385 }
2386
dcbe765b
CM		 2387 error = (error || in_width > maxsinglelinewidth * 2 ||
2388 (in_width > maxsinglelinewidth && *five_taps) ||
2389 !*core_clk || *core_clk > dispc_core_clk_rate());
ab6b2582
TV		 2390
2391 if (!error) {
2392 /* verify that we're inside the limits of scaler */
2393 if (in_width / 4 > out_width)
2394 error = 1;
2395
2396 if (*five_taps) {
2397 if (in_height / 4 > out_height)
2398 error = 1;
dcbe765b 2399 } else {
ab6b2582
TV		 2400 if (in_height / 2 > out_height)
2401 error = 1;
dcbe765b
CM		 2402 }
2403 }
ab6b2582 2404
7059e3d8
TV		 2405 if (error)
2406 ++*decim_y;
dcbe765b
CM		 2407 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2408
3ce17b48
TV		 2409 if (error) {
2410 DSSERR("failed to find scaling settings\n");
2411 return -EINVAL;
2412 }
2413
f5a73482
TV		 2414 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2415 in_height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2416 DSSERR("horizontal timing too tight\n");
2417 return -EINVAL;
7282f1b7 2418 }
dcbe765b
CM		 2419
2420 if (in_width > (maxsinglelinewidth * 2)) {
2421 DSSERR("Cannot setup scaling");
2422 DSSERR("width exceeds maximum width possible");
2423 return -EINVAL;
2424 }
2425
2426 if (in_width > maxsinglelinewidth && *five_taps) {
2427 DSSERR("cannot setup scaling with five taps");
2428 return -EINVAL;
2429 }
2430 return 0;
2431}
2432
0c6921de 2433static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2434 const struct omap_video_timings *mgr_timings,
2435 u16 width, u16 height, u16 out_width, u16 out_height,
2436 enum omap_color_mode color_mode, bool *five_taps,
2437 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2438 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2439{
2440 u16 in_width, in_width_max;
2441 int decim_x_min = *decim_x;
eec77da2 2442 u16 in_height = height / *decim_y;
dcbe765b
CM		 2443 const int maxsinglelinewidth =
2444 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2445 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2446
5d501085
AT		 2447 if (mem_to_mem) {
2448 in_width_max = out_width * maxdownscale;
2449 } else {
8ba85306
AT		 2450 in_width_max = dispc_core_clk_rate() /
2451 DIV_ROUND_UP(pclk, out_width);
5d501085 2452 }
dcbe765b 2453
dcbe765b
CM		 2454 *decim_x = DIV_ROUND_UP(width, in_width_max);
2455
2456 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2457 if (*decim_x > *x_predecim)
2458 return -EINVAL;
2459
2460 do {
eec77da2 2461 in_width = width / *decim_x;
dcbe765b
CM		 2462 } while (*decim_x <= *x_predecim &&
2463 in_width > maxsinglelinewidth && ++*decim_x);
2464
2465 if (in_width > maxsinglelinewidth) {
2466 DSSERR("Cannot scale width exceeds max line width");
2467 return -EINVAL;
2468 }
2469
8702ee50 2470 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2471 out_width, out_height, mem_to_mem);
dcbe765b 2472 return 0;
80c39712
TV		 2473}
2474
e4c5ae7f
TV		 2475#define DIV_FRAC(dividend, divisor) \
2476 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2477
74e16458 2478static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2479 enum omap_overlay_caps caps,
81ab95b7
AT		 2480 const struct omap_video_timings *mgr_timings,
2481 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2482 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2483 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2484 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2485{
0373cac6 2486 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2487 const int max_decim_limit = 16;
8b53d991 2488 unsigned long core_clk = 0;
dcbe765b 2489 int decim_x, decim_y, ret;
79ad75f2 2490
f95cb5eb
TV		 2491 if (width == out_width && height == out_height)
2492 return 0;
2493
fd2eac5a 2494 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
4e1d3ca0
TV		 2495 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2496 return -EINVAL;
2497 }
2498
5b54ed3e 2499 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2500 return -EINVAL;
79ad75f2 2501
74e16458 2502 if (mem_to_mem) {
1c031441
AT		 2503 *x_predecim = *y_predecim = 1;
2504 } else {
2505 *x_predecim = max_decim_limit;
2506 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2507 dss_has_feature(FEAT_BURST_2D)) ?
2508 2 : max_decim_limit;
2509 }
aed74b55
CM		 2510
2511 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2512 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2513 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2514 color_mode == OMAP_DSS_COLOR_CLUT8) {
2515 *x_predecim = 1;
2516 *y_predecim = 1;
2517 *five_taps = false;
2518 return 0;
2519 }
2520
2521 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2522 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2523
aed74b55 2524 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2525 return -EINVAL;
2526
aed74b55 2527 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2528 return -EINVAL;
2529
0c6921de 2530 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2531 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2532 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2533 mem_to_mem);
dcbe765b
CM		 2534 if (ret)
2535 return ret;
79ad75f2 2536
e4c5ae7f
TV		 2537 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2538 width, height,
2539 out_width, out_height,
2540 out_width / width, DIV_FRAC(out_width, width),
2541 out_height / height, DIV_FRAC(out_height, height),
2542
2543 decim_x, decim_y,
2544 width / decim_x, height / decim_y,
2545 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2546 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2547
2548 *five_taps ? 5 : 3,
2549 core_clk, dispc_core_clk_rate());
79ad75f2 2550
8b53d991 2551 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2552 DSSERR("failed to set up scaling, "
8b53d991
CM		 2553 "required core clk rate = %lu Hz, "
2554 "current core clk rate = %lu Hz\n",
2555 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2556 return -EINVAL;
2557 }
2558
aed74b55
CM		 2559 *x_predecim = decim_x;
2560 *y_predecim = decim_y;
79ad75f2
AT		 2561 return 0;
2562}
2563
84a880fd 2564static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2565 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2566 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2567 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2568 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2569 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2570 bool replication, const struct omap_video_timings *mgr_timings,
2571 bool mem_to_mem)
80c39712 2572{
7282f1b7 2573 bool five_taps = true;
62a83183 2574 bool fieldmode = false;
79ad75f2 2575 int r, cconv = 0;
80c39712
TV		 2576 unsigned offset0, offset1;
2577 s32 row_inc;
2578 s32 pix_inc;
6be0d73e 2579 u16 frame_width, frame_height;
80c39712 2580 unsigned int field_offset = 0;
84a880fd
AT		 2581 u16 in_height = height;
2582 u16 in_width = width;
aed74b55 2583 int x_predecim = 1, y_predecim = 1;
8050cbe4 2584 bool ilace = mgr_timings->interlace;
74e16458
TV		 2585 unsigned long pclk = dispc_plane_pclk_rate(plane);
2586 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2587
e566658f 2588 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2589 return -EINVAL;
2590
c4661b33
TV		 2591 switch (color_mode) {
2592 case OMAP_DSS_COLOR_YUV2:
2593 case OMAP_DSS_COLOR_UYVY:
2594 case OMAP_DSS_COLOR_NV12:
2595 if (in_width & 1) {
2596 DSSERR("input width %d is not even for YUV format\n",
2597 in_width);
2598 return -EINVAL;
2599 }
2600 break;
2601
2602 default:
2603 break;
2604 }
2605
84a880fd
AT		 2606 out_width = out_width == 0 ? width : out_width;
2607 out_height = out_height == 0 ? height : out_height;
cf073668 2608
84a880fd 2609 if (ilace && height == out_height)
62a83183 2610 fieldmode = true;
80c39712
TV		 2611
2612 if (ilace) {
2613 if (fieldmode)
aed74b55 2614 in_height /= 2;
8eeb7019 2615 pos_y /= 2;
aed74b55 2616 out_height /= 2;
80c39712
TV		 2617
2618 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2619 "out_height %d\n", in_height, pos_y,
2620 out_height);
80c39712
TV		 2621 }
2622
84a880fd 2623 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2624 return -EINVAL;
2625
74e16458 2626 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2627 in_height, out_width, out_height, color_mode,
2628 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2629 rotation_type, mem_to_mem);
79ad75f2
AT		 2630 if (r)
2631 return r;
80c39712 2632
eec77da2
TV		 2633 in_width = in_width / x_predecim;
2634 in_height = in_height / y_predecim;
aed74b55 2635
c4661b33
TV		 2636 if (x_predecim > 1 || y_predecim > 1)
2637 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2638 x_predecim, y_predecim, in_width, in_height);
2639
2640 switch (color_mode) {
2641 case OMAP_DSS_COLOR_YUV2:
2642 case OMAP_DSS_COLOR_UYVY:
2643 case OMAP_DSS_COLOR_NV12:
2644 if (in_width & 1) {
2645 DSSDBG("predecimated input width is not even for YUV format\n");
2646 DSSDBG("adjusting input width %d -> %d\n",
2647 in_width, in_width & ~1);
2648
2649 in_width &= ~1;
2650 }
2651 break;
2652
2653 default:
2654 break;
2655 }
2656
84a880fd
AT		 2657 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2658 color_mode == OMAP_DSS_COLOR_UYVY ||
2659 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2660 cconv = 1;
80c39712
TV		 2661
2662 if (ilace && !fieldmode) {
2663 /*
2664 * when downscaling the bottom field may have to start several
2665 * source lines below the top field. Unfortunately ACCUI
2666 * registers will only hold the fractional part of the offset
2667 * so the integer part must be added to the base address of the
2668 * bottom field.
2669 */
aed74b55 2670 if (!in_height || in_height == out_height)
80c39712
TV		 2671 field_offset = 0;
2672 else
aed74b55 2673 field_offset = in_height / out_height / 2;
80c39712
TV		 2674 }
2675
2676 /* Fields are independent but interleaved in memory. */
2677 if (fieldmode)
2678 field_offset = 1;
2679
c6eee968
TV		 2680 offset0 = 0;
2681 offset1 = 0;
2682 row_inc = 0;
2683 pix_inc = 0;
2684
6be0d73e
AT		 2685 if (plane == OMAP_DSS_WB) {
2686 frame_width = out_width;
2687 frame_height = out_height;
2688 } else {
2689 frame_width = in_width;
2690 frame_height = height;
2691 }
2692
84a880fd 2693 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2694 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2695 color_mode, fieldmode, field_offset,
65e006ff
CM		 2696 &offset0, &offset1, &row_inc, &pix_inc,
2697 x_predecim, y_predecim);
84a880fd 2698 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2699 calc_dma_rotation_offset(rotation, mirror, screen_width,
2700 frame_width, frame_height,
84a880fd 2701 color_mode, fieldmode, field_offset,
aed74b55
CM		 2702 &offset0, &offset1, &row_inc, &pix_inc,
2703 x_predecim, y_predecim);
80c39712 2704 else
84a880fd 2705 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2706 screen_width, frame_width, frame_height,
84a880fd 2707 color_mode, fieldmode, field_offset,
aed74b55
CM		 2708 &offset0, &offset1, &row_inc, &pix_inc,
2709 x_predecim, y_predecim);
80c39712
TV		 2710
2711 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2712 offset0, offset1, row_inc, pix_inc);
2713
84a880fd 2714 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2715
84a880fd 2716 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2717
b7536d67
TV		 2718 if (dispc.feat->reverse_ilace_field_order)
2719 swap(offset0, offset1);
2720
84a880fd
AT		 2721 dispc_ovl_set_ba0(plane, paddr + offset0);
2722 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2723
84a880fd
AT		 2724 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2725 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2726 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2727 }
2728
f2aee319
TV		 2729 if (dispc.feat->last_pixel_inc_missing)
2730 row_inc += pix_inc - 1;
2731
f0e5caab
TV		 2732 dispc_ovl_set_row_inc(plane, row_inc);
2733 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2734
84a880fd 2735 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2736 in_height, out_width, out_height);
80c39712 2737
84a880fd 2738 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2739
78b687fc 2740 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2741
5b54ed3e 2742 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2743 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2744 out_height, ilace, five_taps, fieldmode,
84a880fd 2745 color_mode, rotation);
78b687fc 2746 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2747 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2748 }
2749
c35eeb2e
AT		 2750 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2751 color_mode);
80c39712 2752
84a880fd
AT		 2753 dispc_ovl_set_zorder(plane, caps, zorder);
2754 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2755 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2756
d79db853 2757 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2758
80c39712
TV		 2759 return 0;
2760}
2761
84a880fd 2762int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2763 bool replication, const struct omap_video_timings *mgr_timings,
2764 bool mem_to_mem)
84a880fd
AT		 2765{
2766 int r;
16bf20c7 2767 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2768 enum omap_channel channel;
2769
2770 channel = dispc_ovl_get_channel_out(plane);
2771
24f13a66
AB		 2772 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2773 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2774 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd
AT		 2775 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2776 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2777
16bf20c7 2778 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2779 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2780 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2781 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2782 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2783
2784 return r;
2785}
348be69d 2786EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2787
749feffa 2788int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2789 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2790{
2791 int r;
9e4a0fc7 2792 u32 l;
749feffa
AT		 2793 enum omap_plane plane = OMAP_DSS_WB;
2794 const int pos_x = 0, pos_y = 0;
2795 const u8 zorder = 0, global_alpha = 0;
2796 const bool replication = false;
9e4a0fc7 2797 bool truncation;
749feffa
AT		 2798 int in_width = mgr_timings->x_res;
2799 int in_height = mgr_timings->y_res;
2800 enum omap_overlay_caps caps =
2801 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2802
2803 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2804 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2805 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2806 wi->mirror);
2807
2808 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2809 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2810 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2811 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2812 replication, mgr_timings, mem_to_mem);
2813
2814 switch (wi->color_mode) {
2815 case OMAP_DSS_COLOR_RGB16:
2816 case OMAP_DSS_COLOR_RGB24P:
2817 case OMAP_DSS_COLOR_ARGB16:
2818 case OMAP_DSS_COLOR_RGBA16:
2819 case OMAP_DSS_COLOR_RGB12U:
2820 case OMAP_DSS_COLOR_ARGB16_1555:
2821 case OMAP_DSS_COLOR_XRGB16_1555:
2822 case OMAP_DSS_COLOR_RGBX16:
2823 truncation = true;
2824 break;
2825 default:
2826 truncation = false;
2827 break;
2828 }
2829
2830 /* setup extra DISPC_WB_ATTRIBUTES */
2831 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2832 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2833 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
4c055ce0
TV		 2834 if (mem_to_mem)
2835 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
98cd5796
TV		 2836 else
2837 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
9e4a0fc7 2838 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa 2839
98cd5796
TV		 2840 if (mem_to_mem) {
2841 /* WBDELAYCOUNT */
2842 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2843 } else {
2844 int wbdelay;
2845
2846 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2847 mgr_timings->vbp, 255);
2848
2849 /* WBDELAYCOUNT */
2850 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2851 }
2852
749feffa
AT		 2853 return r;
2854}
2855
f0e5caab 2856int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2857{
e6d80f95
TV		 2858 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2859
9b372c2d 2860 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2861
2862 return 0;
80c39712 2863}
348be69d 2864EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2865
04bd8ac1
TV		 2866bool dispc_ovl_enabled(enum omap_plane plane)
2867{
2868 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2869}
348be69d 2870EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2871
7b9cb5ee
TV		 2872enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2873{
2874 return dss_feat_get_supported_outputs(channel);
2875}
2876EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);
2877
f1a813d3 2878void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2879{
efa70b3b
CM		 2880 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2881 /* flush posted write */
2882 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2883}
348be69d 2884EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2885
65398511
TV		 2886bool dispc_mgr_is_enabled(enum omap_channel channel)
2887{
2888 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2889}
348be69d 2890EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2891
0b23e5b8
AT		 2892void dispc_wb_enable(bool enable)
2893{
916188a4 2894 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2895}
2896
2897bool dispc_wb_is_enabled(void)
2898{
916188a4 2899 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2900}
2901
fb2cec1f 2902static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2903{
6ced40bf
AT		 2904 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2905 return;
2906
80c39712 2907 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2908}
2909
2910void dispc_lcd_enable_signal(bool enable)
2911{
6ced40bf
AT		 2912 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2913 return;
2914
80c39712 2915 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2916}
2917
2918void dispc_pck_free_enable(bool enable)
2919{
6ced40bf
AT		 2920 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2921 return;
2922
80c39712 2923 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2924}
2925
fb2cec1f 2926static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2927{
efa70b3b 2928 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2929}
2930
2931
fb2cec1f 2932static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2933{
d21f43bc 2934 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2935}
2936
65904155 2937static void dispc_set_loadmode(enum omap_dss_load_mode mode)
80c39712 2938{
80c39712 2939 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2940}
2941
2942
c64dca40 2943static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2944{
8613b000 2945 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2946}
2947
c64dca40 2948static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2949 enum omap_dss_trans_key_type type,
2950 u32 trans_key)
2951{
efa70b3b 2952 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2953
8613b000 2954 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2955}
2956
c64dca40 2957static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2958{
efa70b3b 2959 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2960}
11354dd5 2961
c64dca40
TV		 2962static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2963 bool enable)
80c39712 2964{
11354dd5 2965 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2966 return;
2967
80c39712
TV		 2968 if (ch == OMAP_DSS_CHANNEL_LCD)
2969 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2970 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2971 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2972}
11354dd5 2973
c64dca40 2974void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2975 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2976{
2977 dispc_mgr_set_default_color(channel, info->default_color);
2978 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2979 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2980 dispc_mgr_enable_alpha_fixed_zorder(channel,
2981 info->partial_alpha_enabled);
2982 if (dss_has_feature(FEAT_CPR)) {
2983 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2984 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2985 }
2986}
348be69d 2987EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2988
fb2cec1f 2989static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2990{
2991 int code;
2992
2993 switch (data_lines) {
2994 case 12:
2995 code = 0;
2996 break;
2997 case 16:
2998 code = 1;
2999 break;
3000 case 18:
3001 code = 2;
3002 break;
3003 case 24:
3004 code = 3;
3005 break;
3006 default:
3007 BUG();
3008 return;
3009 }
3010
efa70b3b 3011 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 3012}
3013
fb2cec1f 3014static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 3015{
3016 u32 l;
569969d6 3017 int gpout0, gpout1;
80c39712
TV		 3018
3019 switch (mode) {
569969d6
AT		 3020 case DSS_IO_PAD_MODE_RESET:
3021 gpout0 = 0;
3022 gpout1 = 0;
80c39712 3023 break;
569969d6
AT		 3024 case DSS_IO_PAD_MODE_RFBI:
3025 gpout0 = 1;
80c39712
TV		 3026 gpout1 = 0;
3027 break;
569969d6
AT		 3028 case DSS_IO_PAD_MODE_BYPASS:
3029 gpout0 = 1;
80c39712
TV		 3030 gpout1 = 1;
3031 break;
80c39712
TV		 3032 default:
3033 BUG();
3034 return;
3035 }
3036
569969d6
AT		 3037 l = dispc_read_reg(DISPC_CONTROL);
3038 l = FLD_MOD(l, gpout0, 15, 15);
3039 l = FLD_MOD(l, gpout1, 16, 16);
3040 dispc_write_reg(DISPC_CONTROL, l);
3041}
3042
fb2cec1f 3043static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 3044{
efa70b3b 3045 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 3046}
3047
fb2cec1f
TV		 3048void dispc_mgr_set_lcd_config(enum omap_channel channel,
3049 const struct dss_lcd_mgr_config *config)
3050{
3051 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3052
3053 dispc_mgr_enable_stallmode(channel, config->stallmode);
3054 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3055
3056 dispc_mgr_set_clock_div(channel, &config->clock_info);
3057
3058 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3059
3060 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3061
3062 dispc_mgr_set_lcd_type_tft(channel);
3063}
348be69d 3064EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 3065
8f366162
AT		 3066static bool _dispc_mgr_size_ok(u16 width, u16 height)
3067{
33b89928
AT		 3068 return width <= dispc.feat->mgr_width_max &&
3069 height <= dispc.feat->mgr_height_max;
8f366162
AT		 3070}
3071
80c39712
TV		 3072static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3073 int vsw, int vfp, int vbp)
3074{
dcbe765b
CM		 3075 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3076 hfp < 1 || hfp > dispc.feat->hp_max ||
3077 hbp < 1 || hbp > dispc.feat->hp_max ||
3078 vsw < 1 || vsw > dispc.feat->sw_max ||
3079 vfp < 0 || vfp > dispc.feat->vp_max ||
3080 vbp < 0 || vbp > dispc.feat->vp_max)
3081 return false;
80c39712
TV		 3082 return true;
3083}
3084
ca5ca69c
AT		 3085static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3086 unsigned long pclk)
3087{
3088 if (dss_mgr_is_lcd(channel))
3089 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3090 else
3091 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3092}
3093
8f366162 3094bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 3095 const struct omap_video_timings *timings)
80c39712 3096{
eadd33bb
TV		 3097 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3098 return false;
8f366162 3099
eadd33bb
TV		 3100 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3101 return false;
ca5ca69c
AT		 3102
3103 if (dss_mgr_is_lcd(channel)) {
beb8384d 3104 /* TODO: OMAP4+ supports interlace for LCD outputs */
eadd33bb
TV		 3105 if (timings->interlace)
3106 return false;
beb8384d 3107
eadd33bb 3108 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
ca5ca69c 3109 timings->hbp, timings->vsw, timings->vfp,
eadd33bb
TV		 3110 timings->vbp))
3111 return false;
ca5ca69c 3112 }
8f366162 3113
eadd33bb 3114 return true;
80c39712
TV		 3115}
3116
26d9dd0d 3117static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3118 int hfp, int hbp, int vsw, int vfp, int vbp,
3119 enum omap_dss_signal_level vsync_level,
3120 enum omap_dss_signal_level hsync_level,
3121 enum omap_dss_signal_edge data_pclk_edge,
3122 enum omap_dss_signal_level de_level,
3123 enum omap_dss_signal_edge sync_pclk_edge)
3124
80c39712 3125{
655e2941 3126 u32 timing_h, timing_v, l;
ed351881 3127 bool onoff, rf, ipc, vs, hs, de;
80c39712 3128
dcbe765b
CM		 3129 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3130 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3131 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3132 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3133 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3134 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3135
64ba4f74
SS		 3136 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3137 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 3138
ed351881
TV		 3139 switch (vsync_level) {
3140 case OMAPDSS_SIG_ACTIVE_LOW:
3141 vs = true;
3142 break;
3143 case OMAPDSS_SIG_ACTIVE_HIGH:
3144 vs = false;
3145 break;
3146 default:
3147 BUG();
3148 }
3149
3150 switch (hsync_level) {
3151 case OMAPDSS_SIG_ACTIVE_LOW:
3152 hs = true;
3153 break;
3154 case OMAPDSS_SIG_ACTIVE_HIGH:
3155 hs = false;
3156 break;
3157 default:
3158 BUG();
3159 }
3160
3161 switch (de_level) {
3162 case OMAPDSS_SIG_ACTIVE_LOW:
3163 de = true;
3164 break;
3165 case OMAPDSS_SIG_ACTIVE_HIGH:
3166 de = false;
3167 break;
3168 default:
3169 BUG();
3170 }
3171
655e2941
AT		 3172 switch (data_pclk_edge) {
3173 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3174 ipc = false;
3175 break;
3176 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3177 ipc = true;
3178 break;
655e2941
AT		 3179 default:
3180 BUG();
3181 }
3182
7a16360d
TV		 3183 /* always use the 'rf' setting */
3184 onoff = true;
3185
655e2941 3186 switch (sync_pclk_edge) {
655e2941 3187 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
655e2941
AT		 3188 rf = false;
3189 break;
3190 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
655e2941
AT		 3191 rf = true;
3192 break;
3193 default:
3194 BUG();
cf6ac4ce 3195 }
655e2941 3196
d80e02ef
TV		 3197 l = FLD_VAL(onoff, 17, 17) |
3198 FLD_VAL(rf, 16, 16) |
ed351881 3199 FLD_VAL(de, 15, 15) |
d80e02ef 3200 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 3201 FLD_VAL(hs, 13, 13) |
3202 FLD_VAL(vs, 12, 12);
d80e02ef 3203
e5f80917
TV		 3204 /* always set ALIGN bit when available */
3205 if (dispc.feat->supports_sync_align)
3206 l |= (1 << 18);
3207
655e2941 3208 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 3209
3210 if (dispc.syscon_pol) {
3211 const int shifts[] = {
3212 [OMAP_DSS_CHANNEL_LCD] = 0,
3213 [OMAP_DSS_CHANNEL_LCD2] = 1,
3214 [OMAP_DSS_CHANNEL_LCD3] = 2,
3215 };
3216
3217 u32 mask, val;
3218
3219 mask = (1 << 0) | (1 << 3) | (1 << 6);
3220 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3221
3222 mask <<= 16 + shifts[channel];
3223 val <<= 16 + shifts[channel];
3224
3225 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3226 mask, val);
3227 }
80c39712
TV		 3228}
3229
3230/* change name to mode? */
c51d921a 3231void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3232 const struct omap_video_timings *timings)
80c39712
TV		 3233{
3234 unsigned xtot, ytot;
3235 unsigned long ht, vt;
2aefad49 3236 struct omap_video_timings t = *timings;
80c39712 3237
2aefad49 3238 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3239
2aefad49 3240 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3241 BUG();
c6eee968
TV		 3242 return;
3243 }
80c39712 3244
dd88b7a6 3245 if (dss_mgr_is_lcd(channel)) {
2aefad49 3246 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3247 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3248 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3249
2aefad49
AT		 3250 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3251 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3252
d8d78941
TV		 3253 ht = timings->pixelclock / xtot;
3254 vt = timings->pixelclock / xtot / ytot;
c51d921a 3255
d8d78941 3256 DSSDBG("pck %u\n", timings->pixelclock);
c51d921a 3257 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3258 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3259 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3260 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3261 t.de_level, t.sync_pclk_edge);
80c39712 3262
c51d921a 3263 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3264 } else {
0bcfdba6 3265 if (t.interlace)
2aefad49 3266 t.y_res /= 2;
3a38ed53
TV		 3267
3268 if (dispc.feat->supports_double_pixel)
3269 REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0,
3270 19, 17);
c51d921a 3271 }
8f366162 3272
2aefad49 3273 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 3274}
348be69d 3275EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3276
26d9dd0d 3277static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3278 u16 pck_div)
80c39712
TV		 3279{
3280 BUG_ON(lck_div < 1);
9eaaf207 3281 BUG_ON(pck_div < 1);
80c39712 3282
ce7fa5eb 3283 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3284 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3 3285
0bcfdba6 3286 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
7b3926b3
TV		 3287 channel == OMAP_DSS_CHANNEL_LCD)
3288 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3289}
3290
26d9dd0d 3291static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3292 int *pck_div)
80c39712
TV		 3293{
3294 u32 l;
ce7fa5eb 3295 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3296 *lck_div = FLD_GET(l, 23, 16);
3297 *pck_div = FLD_GET(l, 7, 0);
3298}
3299
65904155 3300static unsigned long dispc_fclk_rate(void)
80c39712 3301{
2daea7af 3302 struct dss_pll *pll;
80c39712
TV		 3303 unsigned long r = 0;
3304
66534e8e 3305 switch (dss_get_dispc_clk_source()) {
3b63ca75 3306 case DSS_CLK_SRC_FCK:
5aaee69d 3307 r = dss_get_dispc_clk_rate();
66534e8e 3308 break;
3b63ca75 3309 case DSS_CLK_SRC_PLL1_1:
2daea7af 3310 pll = dss_pll_find("dsi0");
93550927
TV		 3311 if (!pll)
3312 pll = dss_pll_find("video0");
3313
2daea7af 3314 r = pll->cinfo.clkout[0];
66534e8e 3315 break;
3b63ca75 3316 case DSS_CLK_SRC_PLL2_1:
2daea7af 3317 pll = dss_pll_find("dsi1");
93550927
TV		 3318 if (!pll)
3319 pll = dss_pll_find("video1");
3320
2daea7af 3321 r = pll->cinfo.clkout[0];
5a8b572d 3322 break;
66534e8e
AT		 3323 default:
3324 BUG();
c6eee968 3325 return 0;
66534e8e
AT		 3326 }
3327
80c39712
TV		 3328 return r;
3329}
3330
65904155 3331static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3332{
2daea7af 3333 struct dss_pll *pll;
80c39712
TV		 3334 int lcd;
3335 unsigned long r;
3336 u32 l;
3337
c31cba8a
TV		 3338 if (dss_mgr_is_lcd(channel)) {
3339 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3340
c31cba8a 3341 lcd = FLD_GET(l, 23, 16);
80c39712 3342
c31cba8a 3343 switch (dss_get_lcd_clk_source(channel)) {
3b63ca75 3344 case DSS_CLK_SRC_FCK:
5aaee69d 3345 r = dss_get_dispc_clk_rate();
c31cba8a 3346 break;
3b63ca75 3347 case DSS_CLK_SRC_PLL1_1:
2daea7af 3348 pll = dss_pll_find("dsi0");
93550927
TV		 3349 if (!pll)
3350 pll = dss_pll_find("video0");
3351
2daea7af 3352 r = pll->cinfo.clkout[0];
c31cba8a 3353 break;
3b63ca75 3354 case DSS_CLK_SRC_PLL2_1:
2daea7af 3355 pll = dss_pll_find("dsi1");
93550927
TV		 3356 if (!pll)
3357 pll = dss_pll_find("video1");
3358
2daea7af 3359 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3360 break;
3361 default:
3362 BUG();
3363 return 0;
3364 }
80c39712 3365
c31cba8a
TV		 3366 return r / lcd;
3367 } else {
3368 return dispc_fclk_rate();
3369 }
80c39712
TV		 3370}
3371
65904155 3372static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3373{
80c39712 3374 unsigned long r;
80c39712 3375
dd88b7a6 3376 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3377 int pcd;
3378 u32 l;
80c39712 3379
c3dc6a7a 3380 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3381
c3dc6a7a 3382 pcd = FLD_GET(l, 7, 0);
80c39712 3383
c3dc6a7a
AT		 3384 r = dispc_mgr_lclk_rate(channel);
3385
3386 return r / pcd;
3387 } else {
5391e87d 3388 return dispc.tv_pclk_rate;
c3dc6a7a 3389 }
80c39712
TV		 3390}
3391
5391e87d
TV		 3392void dispc_set_tv_pclk(unsigned long pclk)
3393{
3394 dispc.tv_pclk_rate = pclk;
3395}
3396
65904155 3397static unsigned long dispc_core_clk_rate(void)
8b53d991 3398{
7b3926b3 3399 return dispc.core_clk_rate;
8b53d991
CM		 3400}
3401
3e8a6ff2
AT		 3402static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3403{
251886d8
TV		 3404 enum omap_channel channel;
3405
3406 if (plane == OMAP_DSS_WB)
3407 return 0;
3408
3409 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3410
3411 return dispc_mgr_pclk_rate(channel);
3412}
3413
3414static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3415{
251886d8
TV		 3416 enum omap_channel channel;
3417
3418 if (plane == OMAP_DSS_WB)
3419 return 0;
3420
3421 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3422
c31cba8a 3423 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3424}
c31cba8a 3425
6f1891fc 3426static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3427{
3428 int lcd, pcd;
dc0352d1 3429 enum dss_clk_source lcd_clk_src;
6f1891fc
CM		 3430
3431 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3432
3433 lcd_clk_src = dss_get_lcd_clk_source(channel);
3434
557a1544 3435 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
407bd564 3436 dss_get_clk_source_name(lcd_clk_src));
6f1891fc
CM		 3437
3438 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3439
3440 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3441 dispc_mgr_lclk_rate(channel), lcd);
3442 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3443 dispc_mgr_pclk_rate(channel), pcd);
3444}
3445
3446void dispc_dump_clocks(struct seq_file *s)
3447{
3448 int lcd;
0cf35df3 3449 u32 l;
dc0352d1 3450 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3451
4fbafaf3
TV		 3452 if (dispc_runtime_get())
3453 return;
80c39712 3454
80c39712
TV		 3455 seq_printf(s, "- DISPC -\n");
3456
557a1544 3457 seq_printf(s, "dispc fclk source = %s\n",
407bd564 3458 dss_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3459
3460 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3461
0cf35df3
MR		 3462 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3463 seq_printf(s, "- DISPC-CORE-CLK -\n");
3464 l = dispc_read_reg(DISPC_DIVISOR);
3465 lcd = FLD_GET(l, 23, 16);
3466
3467 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3468 (dispc_fclk_rate()/lcd), lcd);
3469 }
2a205f34 3470
6f1891fc 3471 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3472
6f1891fc
CM		 3473 if (dss_has_feature(FEAT_MGR_LCD2))
3474 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3475 if (dss_has_feature(FEAT_MGR_LCD3))
3476 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3477
3478 dispc_runtime_put();
80c39712
TV		 3479}
3480
e40402cf 3481static void dispc_dump_regs(struct seq_file *s)
80c39712 3482{
4dd2da15
AT		 3483 int i, j;
3484 const char *mgr_names[] = {
3485 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3486 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3487 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3488 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3489 };
3490 const char *ovl_names[] = {
3491 [OMAP_DSS_GFX] = "GFX",
3492 [OMAP_DSS_VIDEO1] = "VID1",
3493 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3494 [OMAP_DSS_VIDEO3] = "VID3",
06c525fe 3495 [OMAP_DSS_WB] = "WB",
4dd2da15
AT		 3496 };
3497 const char **p_names;
3498
9b372c2d 3499#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3500
4fbafaf3
TV		 3501 if (dispc_runtime_get())
3502 return;
80c39712 3503
5010be80 3504 /* DISPC common registers */
80c39712
TV		 3505 DUMPREG(DISPC_REVISION);
3506 DUMPREG(DISPC_SYSCONFIG);
3507 DUMPREG(DISPC_SYSSTATUS);
3508 DUMPREG(DISPC_IRQSTATUS);
3509 DUMPREG(DISPC_IRQENABLE);
3510 DUMPREG(DISPC_CONTROL);
3511 DUMPREG(DISPC_CONFIG);
3512 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3513 DUMPREG(DISPC_LINE_STATUS);
3514 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3515 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3516 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3517 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3518 if (dss_has_feature(FEAT_MGR_LCD2)) {
3519 DUMPREG(DISPC_CONTROL2);
3520 DUMPREG(DISPC_CONFIG2);
5010be80 3521 }
6f1891fc
CM		 3522 if (dss_has_feature(FEAT_MGR_LCD3)) {
3523 DUMPREG(DISPC_CONTROL3);
3524 DUMPREG(DISPC_CONFIG3);
3525 }
29fceeeb
TV		 3526 if (dss_has_feature(FEAT_MFLAG))
3527 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3528
3529#undef DUMPREG
3530
3531#define DISPC_REG(i, name) name(i)
4dd2da15 3532#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3533 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3534 dispc_read_reg(DISPC_REG(i, r)))
3535
4dd2da15 3536 p_names = mgr_names;
5010be80 3537
4dd2da15
AT		 3538 /* DISPC channel specific registers */
3539 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3540 DUMPREG(i, DISPC_DEFAULT_COLOR);
3541 DUMPREG(i, DISPC_TRANS_COLOR);
3542 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3543
4dd2da15
AT		 3544 if (i == OMAP_DSS_CHANNEL_DIGIT)
3545 continue;
5010be80 3546
4dd2da15
AT		 3547 DUMPREG(i, DISPC_TIMING_H);
3548 DUMPREG(i, DISPC_TIMING_V);
3549 DUMPREG(i, DISPC_POL_FREQ);
3550 DUMPREG(i, DISPC_DIVISORo);
5010be80 3551
4dd2da15
AT		 3552 DUMPREG(i, DISPC_DATA_CYCLE1);
3553 DUMPREG(i, DISPC_DATA_CYCLE2);
3554 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3555
332e9d70 3556 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3557 DUMPREG(i, DISPC_CPR_COEF_R);
3558 DUMPREG(i, DISPC_CPR_COEF_G);
3559 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3560 }
2a205f34 3561 }
80c39712 3562
4dd2da15
AT		 3563 p_names = ovl_names;
3564
3565 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3566 DUMPREG(i, DISPC_OVL_BA0);
3567 DUMPREG(i, DISPC_OVL_BA1);
3568 DUMPREG(i, DISPC_OVL_POSITION);
3569 DUMPREG(i, DISPC_OVL_SIZE);
3570 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3571 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3572 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3573 DUMPREG(i, DISPC_OVL_ROW_INC);
3574 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3575
4dd2da15
AT		 3576 if (dss_has_feature(FEAT_PRELOAD))
3577 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3578 if (dss_has_feature(FEAT_MFLAG))
3579 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3580
3581 if (i == OMAP_DSS_GFX) {
3582 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3583 DUMPREG(i, DISPC_OVL_TABLE_BA);
3584 continue;
3585 }
3586
3587 DUMPREG(i, DISPC_OVL_FIR);
3588 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3589 DUMPREG(i, DISPC_OVL_ACCU0);
3590 DUMPREG(i, DISPC_OVL_ACCU1);
3591 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3592 DUMPREG(i, DISPC_OVL_BA0_UV);
3593 DUMPREG(i, DISPC_OVL_BA1_UV);
3594 DUMPREG(i, DISPC_OVL_FIR2);
3595 DUMPREG(i, DISPC_OVL_ACCU2_0);
3596 DUMPREG(i, DISPC_OVL_ACCU2_1);
3597 }
3598 if (dss_has_feature(FEAT_ATTR2))
3599 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3600 }
5010be80 3601
20efbc35 3602 if (dispc.feat->has_writeback) {
06c525fe
TV		 3603 i = OMAP_DSS_WB;
3604 DUMPREG(i, DISPC_OVL_BA0);
3605 DUMPREG(i, DISPC_OVL_BA1);
3606 DUMPREG(i, DISPC_OVL_SIZE);
3607 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3608 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3609 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3610 DUMPREG(i, DISPC_OVL_ROW_INC);
3611 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3612
3613 if (dss_has_feature(FEAT_MFLAG))
3614 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3615
3616 DUMPREG(i, DISPC_OVL_FIR);
3617 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3618 DUMPREG(i, DISPC_OVL_ACCU0);
3619 DUMPREG(i, DISPC_OVL_ACCU1);
3620 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3621 DUMPREG(i, DISPC_OVL_BA0_UV);
3622 DUMPREG(i, DISPC_OVL_BA1_UV);
3623 DUMPREG(i, DISPC_OVL_FIR2);
3624 DUMPREG(i, DISPC_OVL_ACCU2_0);
3625 DUMPREG(i, DISPC_OVL_ACCU2_1);
3626 }
3627 if (dss_has_feature(FEAT_ATTR2))
3628 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3629 }
3630
5010be80
AT		 3631#undef DISPC_REG
3632#undef DUMPREG
3633
3634#define DISPC_REG(plane, name, i) name(plane, i)
3635#define DUMPREG(plane, name, i) \
4dd2da15 3636 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3637 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3638 dispc_read_reg(DISPC_REG(plane, name, i)))
3639
4dd2da15 3640 /* Video pipeline coefficient registers */
332e9d70 3641
4dd2da15
AT		 3642 /* start from OMAP_DSS_VIDEO1 */
3643 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3644 for (j = 0; j < 8; j++)
3645 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3646
4dd2da15
AT		 3647 for (j = 0; j < 8; j++)
3648 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3649
4dd2da15
AT		 3650 for (j = 0; j < 5; j++)
3651 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3652
4dd2da15
AT		 3653 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3654 for (j = 0; j < 8; j++)
3655 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3656 }
3657
3658 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3659 for (j = 0; j < 8; j++)
3660 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3661
3662 for (j = 0; j < 8; j++)
3663 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3664
3665 for (j = 0; j < 8; j++)
3666 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3667 }
332e9d70 3668 }
80c39712 3669
4fbafaf3 3670 dispc_runtime_put();
5010be80
AT		 3671
3672#undef DISPC_REG
80c39712
TV		 3673#undef DUMPREG
3674}
3675
80c39712
TV		 3676/* calculate clock rates using dividers in cinfo */
3677int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3678 struct dispc_clock_info *cinfo)
3679{
80c39712
TV		 3680 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3681 return -EINVAL;
9eaaf207 3682 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3683 return -EINVAL;
80c39712 3684
80c39712
TV		 3685 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3686 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3687
80c39712
TV		 3688 return 0;
3689}
80c39712 3690
7c284e6e
TV		 3691bool dispc_div_calc(unsigned long dispc,
3692 unsigned long pck_min, unsigned long pck_max,
3693 dispc_div_calc_func func, void *data)
3694{
3695 int lckd, lckd_start, lckd_stop;
3696 int pckd, pckd_start, pckd_stop;
3697 unsigned long pck, lck;
3698 unsigned long lck_max;
3699 unsigned long pckd_hw_min, pckd_hw_max;
3700 unsigned min_fck_per_pck;
3701 unsigned long fck;
80c39712 3702
7c284e6e
TV		 3703#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3704 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3705#else
3706 min_fck_per_pck = 0;
3707#endif
80c39712 3708
7c284e6e
TV		 3709 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3710 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3711
7c284e6e 3712 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3713
7c284e6e
TV		 3714 pck_min = pck_min ? pck_min : 1;
3715 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3716
7c284e6e
TV		 3717 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3718 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3719
7c284e6e
TV		 3720 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3721 lck = dispc / lckd;
80c39712 3722
7c284e6e
TV		 3723 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3724 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3725
7c284e6e
TV		 3726 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3727 pck = lck / pckd;
80c39712 3728
7c284e6e
TV		 3729 /*
3730 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3731 * clock, which means we're configuring DISPC fclk here
3732 * also. Thus we need to use the calculated lck. For
3733 * OMAP4+ the DISPC fclk is a separate clock.
3734 */
3735 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3736 fck = dispc_core_clk_rate();
3737 else
3738 fck = lck;
3739
3740 if (fck < pck * min_fck_per_pck)
3741 continue;
3742
3743 if (func(lckd, pckd, lck, pck, data))
3744 return true;
3745 }
3746 }
3747
3748 return false;
80c39712
TV		 3749}
3750
f0d08f89 3751void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3752 const struct dispc_clock_info *cinfo)
80c39712
TV		 3753{
3754 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3755 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3756
26d9dd0d 3757 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3758}
3759
26d9dd0d 3760int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3761 struct dispc_clock_info *cinfo)
80c39712
TV		 3762{
3763 unsigned long fck;
3764
3765 fck = dispc_fclk_rate();
3766
ce7fa5eb
MR		 3767 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3768 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3769
3770 cinfo->lck = fck / cinfo->lck_div;
3771 cinfo->pck = cinfo->lck / cinfo->pck_div;
3772
3773 return 0;
3774}
3775
4e0397cf
TV		 3776u32 dispc_read_irqstatus(void)
3777{
3778 return dispc_read_reg(DISPC_IRQSTATUS);
3779}
348be69d 3780EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3781
3782void dispc_clear_irqstatus(u32 mask)
3783{
3784 dispc_write_reg(DISPC_IRQSTATUS, mask);
3785}
348be69d 3786EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3787
3788u32 dispc_read_irqenable(void)
3789{
3790 return dispc_read_reg(DISPC_IRQENABLE);
3791}
348be69d 3792EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3793
3794void dispc_write_irqenable(u32 mask)
3795{
3796 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3797
3798 /* clear the irqstatus for newly enabled irqs */
3799 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3800
3801 dispc_write_reg(DISPC_IRQENABLE, mask);
3802}
348be69d 3803EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3804
80c39712
TV		 3805void dispc_enable_sidle(void)
3806{
3807 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3808}
3809
3810void dispc_disable_sidle(void)
3811{
3812 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3813}
3814
3815static void _omap_dispc_initial_config(void)
3816{
3817 u32 l;
3818
0cf35df3
MR		 3819 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3820 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3821 l = dispc_read_reg(DISPC_DIVISOR);
3822 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3823 l = FLD_MOD(l, 1, 0, 0);
3824 l = FLD_MOD(l, 1, 23, 16);
3825 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3826
3827 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3828 }
3829
80c39712 3830 /* FUNCGATED */
6ced40bf
AT		 3831 if (dss_has_feature(FEAT_FUNCGATED))
3832 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3833
6e5264b0 3834 dispc_setup_color_conv_coef();
80c39712
TV		 3835
3836 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3837
42a6961c 3838 dispc_init_fifos();
5ed8cf5b
TV		 3839
3840 dispc_configure_burst_sizes();
54128701
AT		 3841
3842 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3843
3844 if (dispc.feat->mstandby_workaround)
3845 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
c64aa3a6
TV		 3846
3847 if (dss_has_feature(FEAT_MFLAG))
3848 dispc_init_mflag();
80c39712
TV		 3849}
3850
ede92695 3851static const struct dispc_features omap24xx_dispc_feats = {
dcbe765b
CM		 3852 .sw_start = 5,
3853 .fp_start = 15,
3854 .bp_start = 27,
3855 .sw_max = 64,
3856 .vp_max = 255,
3857 .hp_max = 256,
33b89928
AT		 3858 .mgr_width_start = 10,
3859 .mgr_height_start = 26,
3860 .mgr_width_max = 2048,
3861 .mgr_height_max = 2048,
ca5ca69c 3862 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3863 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3864 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3865 .num_fifos = 3,
cffa947d 3866 .no_framedone_tv = true,
8bc65552 3867 .set_max_preload = false,
f2aee319 3868 .last_pixel_inc_missing = true,
dcbe765b
CM		 3869};
3870
ede92695 3871static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
dcbe765b
CM		 3872 .sw_start = 5,
3873 .fp_start = 15,
3874 .bp_start = 27,
3875 .sw_max = 64,
3876 .vp_max = 255,
3877 .hp_max = 256,
33b89928
AT		 3878 .mgr_width_start = 10,
3879 .mgr_height_start = 26,
3880 .mgr_width_max = 2048,
3881 .mgr_height_max = 2048,
ca5ca69c
AT		 3882 .max_lcd_pclk = 173000000,
3883 .max_tv_pclk = 59000000,
dcbe765b
CM		 3884 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3885 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3886 .num_fifos = 3,
cffa947d 3887 .no_framedone_tv = true,
8bc65552 3888 .set_max_preload = false,
f2aee319 3889 .last_pixel_inc_missing = true,
dcbe765b
CM		 3890};
3891
ede92695 3892static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
dcbe765b
CM		 3893 .sw_start = 7,
3894 .fp_start = 19,
3895 .bp_start = 31,
3896 .sw_max = 256,
3897 .vp_max = 4095,
3898 .hp_max = 4096,
33b89928
AT		 3899 .mgr_width_start = 10,
3900 .mgr_height_start = 26,
3901 .mgr_width_max = 2048,
3902 .mgr_height_max = 2048,
ca5ca69c
AT		 3903 .max_lcd_pclk = 173000000,
3904 .max_tv_pclk = 59000000,
dcbe765b
CM		 3905 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3906 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3907 .num_fifos = 3,
cffa947d 3908 .no_framedone_tv = true,
8bc65552 3909 .set_max_preload = false,
f2aee319 3910 .last_pixel_inc_missing = true,
dcbe765b
CM		 3911};
3912
ede92695 3913static const struct dispc_features omap44xx_dispc_feats = {
dcbe765b
CM		 3914 .sw_start = 7,
3915 .fp_start = 19,
3916 .bp_start = 31,
3917 .sw_max = 256,
3918 .vp_max = 4095,
3919 .hp_max = 4096,
33b89928
AT		 3920 .mgr_width_start = 10,
3921 .mgr_height_start = 26,
3922 .mgr_width_max = 2048,
3923 .mgr_height_max = 2048,
ca5ca69c
AT		 3924 .max_lcd_pclk = 170000000,
3925 .max_tv_pclk = 185625000,
dcbe765b
CM		 3926 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3927 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3928 .num_fifos = 5,
66a0f9e4 3929 .gfx_fifo_workaround = true,
8bc65552 3930 .set_max_preload = true,
e5f80917 3931 .supports_sync_align = true,
20efbc35 3932 .has_writeback = true,
3a38ed53 3933 .supports_double_pixel = true,
b7536d67 3934 .reverse_ilace_field_order = true,
dcbe765b
CM		 3935};
3936
ede92695 3937static const struct dispc_features omap54xx_dispc_feats = {
264236f8
AT		 3938 .sw_start = 7,
3939 .fp_start = 19,
3940 .bp_start = 31,
3941 .sw_max = 256,
3942 .vp_max = 4095,
3943 .hp_max = 4096,
3944 .mgr_width_start = 11,
3945 .mgr_height_start = 27,
3946 .mgr_width_max = 4096,
3947 .mgr_height_max = 4096,
ca5ca69c
AT		 3948 .max_lcd_pclk = 170000000,
3949 .max_tv_pclk = 186000000,
264236f8
AT		 3950 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3951 .calc_core_clk = calc_core_clk_44xx,
3952 .num_fifos = 5,
3953 .gfx_fifo_workaround = true,
d0df9a2c 3954 .mstandby_workaround = true,
8bc65552 3955 .set_max_preload = true,
e5f80917 3956 .supports_sync_align = true,
20efbc35 3957 .has_writeback = true,
3a38ed53 3958 .supports_double_pixel = true,
b7536d67 3959 .reverse_ilace_field_order = true,
264236f8
AT		 3960};
3961
ede92695 3962static int dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3963{
3964 const struct dispc_features *src;
3965 struct dispc_features *dst;
3966
84b47623 3967 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3968 if (!dst) {
84b47623 3969 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3970 return -ENOMEM;
3971 }
3972
b2c7d54f 3973 switch (omapdss_get_version()) {
84b47623 3974 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3975 src = &omap24xx_dispc_feats;
84b47623
TV		 3976 break;
3977
3978 case OMAPDSS_VER_OMAP34xx_ES1:
3979 src = &omap34xx_rev1_0_dispc_feats;
3980 break;
3981
3982 case OMAPDSS_VER_OMAP34xx_ES3:
3983 case OMAPDSS_VER_OMAP3630:
3984 case OMAPDSS_VER_AM35xx:
d6279d4a 3985 case OMAPDSS_VER_AM43xx:
84b47623
TV		 3986 src = &omap34xx_rev3_0_dispc_feats;
3987 break;
3988
3989 case OMAPDSS_VER_OMAP4430_ES1:
3990 case OMAPDSS_VER_OMAP4430_ES2:
3991 case OMAPDSS_VER_OMAP4:
dcbe765b 3992 src = &omap44xx_dispc_feats;
84b47623
TV		 3993 break;
3994
3995 case OMAPDSS_VER_OMAP5:
93550927 3996 case OMAPDSS_VER_DRA7xx:
264236f8 3997 src = &omap54xx_dispc_feats;
84b47623
TV		 3998 break;
3999
4000 default:
dcbe765b
CM		 4001 return -ENODEV;
4002 }
4003
4004 memcpy(dst, src, sizeof(*dst));
4005 dispc.feat = dst;
4006
4007 return 0;
4008}
4009
0925afc9
TV		 4010static irqreturn_t dispc_irq_handler(int irq, void *arg)
4011{
4012 if (!dispc.is_enabled)
4013 return IRQ_NONE;
4014
4015 return dispc.user_handler(irq, dispc.user_data);
4016}
4017
96e2e637
TV		 4018int dispc_request_irq(irq_handler_t handler, void *dev_id)
4019{
0925afc9
TV		 4020 int r;
4021
4022 if (dispc.user_handler != NULL)
4023 return -EBUSY;
4024
4025 dispc.user_handler = handler;
4026 dispc.user_data = dev_id;
4027
4028 /* ensure the dispc_irq_handler sees the values above */
4029 smp_wmb();
4030
4031 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4032 IRQF_SHARED, "OMAP DISPC", &dispc);
4033 if (r) {
4034 dispc.user_handler = NULL;
4035 dispc.user_data = NULL;
4036 }
4037
4038 return r;
96e2e637 4039}
348be69d 4040EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 4041
4042void dispc_free_irq(void *dev_id)
4043{
0925afc9
TV		 4044 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4045
4046 dispc.user_handler = NULL;
4047 dispc.user_data = NULL;
96e2e637 4048}
348be69d 4049EXPORT_SYMBOL(dispc_free_irq);
96e2e637 4050
060b6d9c 4051/* DISPC HW IP initialisation */
736e60dd 4052static int dispc_bind(struct device *dev, struct device *master, void *data)
060b6d9c 4053{
736e60dd 4054 struct platform_device *pdev = to_platform_device(dev);
060b6d9c 4055 u32 rev;
affe360d 4056 int r = 0;
ea9da36a 4057 struct resource *dispc_mem;
0006fd63 4058 struct device_node *np = pdev->dev.of_node;
ea9da36a 4059
060b6d9c
SG		 4060 dispc.pdev = pdev;
4061
d49cd155
TV		 4062 spin_lock_init(&dispc.control_lock);
4063
84b47623 4064 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4065 if (r)
4066 return r;
4067
ea9da36a
SG		 4068 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4069 if (!dispc_mem) {
4070 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4071 return -EINVAL;
ea9da36a 4072 }
cd3b3449 4073
6e2a14d2
JL		 4074 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4075 resource_size(dispc_mem));
060b6d9c
SG		 4076 if (!dispc.base) {
4077 DSSERR("can't ioremap DISPC\n");
cd3b3449 4078 return -ENOMEM;
affe360d 4079 }
cd3b3449 4080
affe360d
AT		 4081 dispc.irq = platform_get_irq(dispc.pdev, 0);
4082 if (dispc.irq < 0) {
4083 DSSERR("platform_get_irq failed\n");
cd3b3449 4084 return -ENODEV;
affe360d
AT		 4085 }
4086
0006fd63
TV		 4087 if (np && of_property_read_bool(np, "syscon-pol")) {
4088 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4089 if (IS_ERR(dispc.syscon_pol)) {
4090 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4091 return PTR_ERR(dispc.syscon_pol);
4092 }
4093
4094 if (of_property_read_u32_index(np, "syscon-pol", 1,
4095 &dispc.syscon_pol_offset)) {
4096 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4097 return -EINVAL;
4098 }
4099 }
4100
4fbafaf3
TV		 4101 pm_runtime_enable(&pdev->dev);
4102
4103 r = dispc_runtime_get();
4104 if (r)
4105 goto err_runtime_get;
060b6d9c
SG		 4106
4107 _omap_dispc_initial_config();
4108
060b6d9c 4109 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4110 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4111 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4112
4fbafaf3 4113 dispc_runtime_put();
060b6d9c 4114
e40402cf
TV		 4115 dss_debugfs_create_file("dispc", dispc_dump_regs);
4116
060b6d9c 4117 return 0;
4fbafaf3
TV		 4118
4119err_runtime_get:
4120 pm_runtime_disable(&pdev->dev);
affe360d 4121 return r;
060b6d9c
SG		 4122}
4123
736e60dd
TV		 4124static void dispc_unbind(struct device *dev, struct device *master,
4125 void *data)
060b6d9c 4126{
736e60dd 4127 pm_runtime_disable(dev);
736e60dd
TV		 4128}
4129
4130static const struct component_ops dispc_component_ops = {
4131 .bind = dispc_bind,
4132 .unbind = dispc_unbind,
4133};
04b1fc02 4134
736e60dd
TV		 4135static int dispc_probe(struct platform_device *pdev)
4136{
4137 return component_add(&pdev->dev, &dispc_component_ops);
4138}
4139
4140static int dispc_remove(struct platform_device *pdev)
4141{
4142 component_del(&pdev->dev, &dispc_component_ops);
060b6d9c
SG		 4143 return 0;
4144}
4145
4fbafaf3
TV		 4146static int dispc_runtime_suspend(struct device *dev)
4147{
0925afc9
TV		 4148 dispc.is_enabled = false;
4149 /* ensure the dispc_irq_handler sees the is_enabled value */
4150 smp_wmb();
4151 /* wait for current handler to finish before turning the DISPC off */
4152 synchronize_irq(dispc.irq);
4153
4fbafaf3 4154 dispc_save_context();
4fbafaf3
TV		 4155
4156 return 0;
4157}
4158
4159static int dispc_runtime_resume(struct device *dev)
4160{
9229b516
TV		 4161 /*
4162 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4163 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4164 * _omap_dispc_initial_config(). We can thus use it to detect if
4165 * we have lost register context.
4166 */
0925afc9
TV		 4167 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4168 _omap_dispc_initial_config();
9229b516 4169
0925afc9
TV		 4170 dispc_restore_context();
4171 }
be07dcd7 4172
0925afc9
TV		 4173 dispc.is_enabled = true;
4174 /* ensure the dispc_irq_handler sees the is_enabled value */
4175 smp_wmb();
4fbafaf3
TV		 4176
4177 return 0;
4178}
4179
4180static const struct dev_pm_ops dispc_pm_ops = {
4181 .runtime_suspend = dispc_runtime_suspend,
4182 .runtime_resume = dispc_runtime_resume,
4183};
4184
d7977f88
TV		 4185static const struct of_device_id dispc_of_match[] = {
4186 { .compatible = "ti,omap2-dispc", },
4187 { .compatible = "ti,omap3-dispc", },
4188 { .compatible = "ti,omap4-dispc", },
2e7e6b68 4189 { .compatible = "ti,omap5-dispc", },
93550927 4190 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 4191 {},
4192};
4193
060b6d9c 4194static struct platform_driver omap_dispchw_driver = {
736e60dd
TV		 4195 .probe = dispc_probe,
4196 .remove = dispc_remove,
060b6d9c
SG		 4197 .driver = {
4198 .name = "omapdss_dispc",
4fbafaf3 4199 .pm = &dispc_pm_ops,
d7977f88 4200 .of_match_table = dispc_of_match,
422ccbd5 4201 .suppress_bind_attrs = true,
060b6d9c
SG		 4202 },
4203};
4204
6e7e8f06 4205int __init dispc_init_platform_driver(void)
060b6d9c 4206{
736e60dd 4207 return platform_driver_register(&omap_dispchw_driver);
060b6d9c
SG		 4208}
4209
ede92695 4210void dispc_uninit_platform_driver(void)
060b6d9c 4211{
04c742c3 4212 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4213}
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