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drm/omap: fix YUV422 rotation with TILER
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
736e60dd 42#include <linux/component.h>
3e1d65cd 43#include <drm/drm_fourcc.h>
0bd97c42 44#include <drm/drm_blend.h>
80c39712 45
32043da7 46#include "omapdss.h"
80c39712 47#include "dss.h"
a0acb557 48#include "dss_features.h"
9b372c2d 49#include "dispc.h"
80c39712
TV		 50
51/* DISPC */
8613b000 52#define DISPC_SZ_REGS SZ_4K
80c39712 53
5ed8cf5b
TV		 54enum omap_burst_size {
55 BURST_SIZE_X2 = 0,
56 BURST_SIZE_X4 = 1,
57 BURST_SIZE_X8 = 2,
58};
59
80c39712
TV		 60#define REG_GET(idx, start, end) \
61 FLD_GET(dispc_read_reg(idx), start, end)
62
63#define REG_FLD_MOD(idx, val, start, end) \
64 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
65
dcbe765b
CM		 66struct dispc_features {
67 u8 sw_start;
68 u8 fp_start;
69 u8 bp_start;
70 u16 sw_max;
71 u16 vp_max;
72 u16 hp_max;
33b89928
AT		 73 u8 mgr_width_start;
74 u8 mgr_height_start;
75 u16 mgr_width_max;
76 u16 mgr_height_max;
ca5ca69c
AT		 77 unsigned long max_lcd_pclk;
78 unsigned long max_tv_pclk;
0c6921de 79 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
da11bbbb 80 const struct videomode *vm,
dcbe765b 81 u16 width, u16 height, u16 out_width, u16 out_height,
41aff42a 82 u32 fourcc, bool *five_taps,
dcbe765b 83 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 84 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 85 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 86 u16 width, u16 height, u16 out_width, u16 out_height,
87 bool mem_to_mem);
42a6961c 88 u8 num_fifos;
66a0f9e4
TV		 89
90 /* swap GFX & WB fifos */
91 bool gfx_fifo_workaround:1;
cffa947d
TV		 92
93 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
94 bool no_framedone_tv:1;
d0df9a2c
AT		 95
96 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
97 bool mstandby_workaround:1;
8bc65552
AT		 98
99 bool set_max_preload:1;
f2aee319
TV		 100
101 /* PIXEL_INC is not added to the last pixel of a line */
102 bool last_pixel_inc_missing:1;
e5f80917
TV		 103
104 /* POL_FREQ has ALIGN bit */
105 bool supports_sync_align:1;
20efbc35
TV		 106
107 bool has_writeback:1;
3a38ed53
TV		 108
109 bool supports_double_pixel:1;
b7536d67
TV		 110
111 /*
112 * Field order for VENC is different than HDMI. We should handle this in
113 * some intelligent manner, but as the SoCs have either HDMI or VENC,
114 * never both, we can just use this flag for now.
115 */
116 bool reverse_ilace_field_order:1;
acc3a231
JS		 117
118 bool has_gamma_table:1;
fbff010b
JS		 119
120 bool has_gamma_i734_bug:1;
dcbe765b
CM		 121};
122
42a6961c 123#define DISPC_MAX_NR_FIFOS 5
acc3a231 124#define DISPC_MAX_CHANNEL_GAMMA 4
42a6961c 125
80c39712 126static struct {
060b6d9c 127 struct platform_device *pdev;
80c39712 128 void __iomem *base;
4fbafaf3 129
affe360d 130 int irq;
0925afc9
TV		 131 irq_handler_t user_handler;
132 void *user_data;
80c39712 133
7b3926b3 134 unsigned long core_clk_rate;
5391e87d 135 unsigned long tv_pclk_rate;
7b3926b3 136
42a6961c
TV		 137 u32 fifo_size[DISPC_MAX_NR_FIFOS];
138 /* maps which plane is using a fifo. fifo-id -> plane-id */
139 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 140
49ea86f3 141 bool ctx_valid;
80c39712 142 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 143
acc3a231
JS		 144 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA];
145
dcbe765b 146 const struct dispc_features *feat;
0925afc9
TV		 147
148 bool is_enabled;
0006fd63
TV		 149
150 struct regmap *syscon_pol;
151 u32 syscon_pol_offset;
d49cd155
TV		 152
153 /* DISPC_CONTROL & DISPC_CONFIG lock*/
154 spinlock_t control_lock;
80c39712
TV		 155} dispc;
156
0d66cbb5
AJ		 157enum omap_color_component {
158 /* used for all color formats for OMAP3 and earlier
159 * and for RGB and Y color component on OMAP4
160 */
161 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
162 /* used for UV component for
3e1d65cd 163 * DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12
0d66cbb5
AJ		 164 * color formats on OMAP4
165 */
166 DISPC_COLOR_COMPONENT_UV = 1 << 1,
167};
168
efa70b3b
CM		 169enum mgr_reg_fields {
170 DISPC_MGR_FLD_ENABLE,
171 DISPC_MGR_FLD_STNTFT,
172 DISPC_MGR_FLD_GO,
173 DISPC_MGR_FLD_TFTDATALINES,
174 DISPC_MGR_FLD_STALLMODE,
175 DISPC_MGR_FLD_TCKENABLE,
176 DISPC_MGR_FLD_TCKSELECTION,
177 DISPC_MGR_FLD_CPR,
178 DISPC_MGR_FLD_FIFOHANDCHECK,
179 /* used to maintain a count of the above fields */
180 DISPC_MGR_FLD_NUM,
181};
182
5c348ba9
JS		 183struct dispc_reg_field {
184 u16 reg;
185 u8 high;
186 u8 low;
187};
188
acc3a231
JS		 189struct dispc_gamma_desc {
190 u32 len;
191 u32 bits;
192 u16 reg;
193 bool has_index;
194};
195
efa70b3b
CM		 196static const struct {
197 const char *name;
198 u32 vsync_irq;
199 u32 framedone_irq;
200 u32 sync_lost_irq;
acc3a231 201 struct dispc_gamma_desc gamma;
5c348ba9 202 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 203} mgr_desc[] = {
204 [OMAP_DSS_CHANNEL_LCD] = {
205 .name = "LCD",
206 .vsync_irq = DISPC_IRQ_VSYNC,
207 .framedone_irq = DISPC_IRQ_FRAMEDONE,
208 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
acc3a231
JS		 209 .gamma = {
210 .len = 256,
211 .bits = 8,
212 .reg = DISPC_GAMMA_TABLE0,
213 .has_index = true,
214 },
efa70b3b
CM		 215 .reg_desc = {
216 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
217 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
218 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
219 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
220 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
221 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
222 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
223 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
224 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
225 },
226 },
227 [OMAP_DSS_CHANNEL_DIGIT] = {
228 .name = "DIGIT",
229 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 230 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b 231 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
acc3a231
JS		 232 .gamma = {
233 .len = 1024,
234 .bits = 10,
235 .reg = DISPC_GAMMA_TABLE2,
236 .has_index = false,
237 },
efa70b3b
CM		 238 .reg_desc = {
239 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
240 [DISPC_MGR_FLD_STNTFT] = { },
241 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
242 [DISPC_MGR_FLD_TFTDATALINES] = { },
243 [DISPC_MGR_FLD_STALLMODE] = { },
244 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
245 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
246 [DISPC_MGR_FLD_CPR] = { },
247 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
248 },
249 },
250 [OMAP_DSS_CHANNEL_LCD2] = {
251 .name = "LCD2",
252 .vsync_irq = DISPC_IRQ_VSYNC2,
253 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
254 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
acc3a231
JS		 255 .gamma = {
256 .len = 256,
257 .bits = 8,
258 .reg = DISPC_GAMMA_TABLE1,
259 .has_index = true,
260 },
efa70b3b
CM		 261 .reg_desc = {
262 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
263 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
264 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
265 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
266 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
267 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
268 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
269 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
270 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
271 },
272 },
e86d456a
CM		 273 [OMAP_DSS_CHANNEL_LCD3] = {
274 .name = "LCD3",
275 .vsync_irq = DISPC_IRQ_VSYNC3,
276 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
277 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
acc3a231
JS		 278 .gamma = {
279 .len = 256,
280 .bits = 8,
281 .reg = DISPC_GAMMA_TABLE3,
282 .has_index = true,
283 },
e86d456a
CM		 284 .reg_desc = {
285 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
286 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
287 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
288 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
289 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
290 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
291 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
292 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
293 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
294 },
295 },
efa70b3b
CM		 296};
297
6e5264b0
AT		 298struct color_conv_coef {
299 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
300 int full_range;
301};
302
65904155
TV		 303static unsigned long dispc_fclk_rate(void);
304static unsigned long dispc_core_clk_rate(void);
305static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
306static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
307
864050c7
JS		 308static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane);
309static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane);
80c39712 310
5034b1fa
TV		 311static void dispc_clear_irqstatus(u32 mask);
312static bool dispc_mgr_is_enabled(enum omap_channel channel);
313static void dispc_clear_irqstatus(u32 mask);
314
55978cc2 315static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 316{
55978cc2 317 __raw_writel(val, dispc.base + idx);
80c39712
TV		 318}
319
55978cc2 320static inline u32 dispc_read_reg(const u16 idx)
80c39712 321{
55978cc2 322 return __raw_readl(dispc.base + idx);
80c39712
TV		 323}
324
efa70b3b
CM		 325static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
326{
5c348ba9 327 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 328 return REG_GET(rfld.reg, rfld.high, rfld.low);
329}
330
331static void mgr_fld_write(enum omap_channel channel,
332 enum mgr_reg_fields regfld, int val) {
5c348ba9 333 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
d49cd155
TV		 334 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
335 unsigned long flags;
336
337 if (need_lock)
338 spin_lock_irqsave(&dispc.control_lock, flags);
339
efa70b3b 340 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
d49cd155
TV		 341
342 if (need_lock)
343 spin_unlock_irqrestore(&dispc.control_lock, flags);
efa70b3b
CM		 344}
345
80c39712 346#define SR(reg) \
55978cc2 347 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 348#define RR(reg) \
55978cc2 349 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 350
4fbafaf3 351static void dispc_save_context(void)
80c39712 352{
c6104b8e 353 int i, j;
80c39712 354
4fbafaf3
TV		 355 DSSDBG("dispc_save_context\n");
356
80c39712
TV		 357 SR(IRQENABLE);
358 SR(CONTROL);
359 SR(CONFIG);
80c39712 360 SR(LINE_NUMBER);
11354dd5
AT		 361 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
362 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 363 SR(GLOBAL_ALPHA);
2a205f34
SS		 364 if (dss_has_feature(FEAT_MGR_LCD2)) {
365 SR(CONTROL2);
2a205f34
SS		 366 SR(CONFIG2);
367 }
e86d456a
CM		 368 if (dss_has_feature(FEAT_MGR_LCD3)) {
369 SR(CONTROL3);
370 SR(CONFIG3);
371 }
80c39712 372
c6104b8e
AT		 373 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
374 SR(DEFAULT_COLOR(i));
375 SR(TRANS_COLOR(i));
376 SR(SIZE_MGR(i));
377 if (i == OMAP_DSS_CHANNEL_DIGIT)
378 continue;
379 SR(TIMING_H(i));
380 SR(TIMING_V(i));
381 SR(POL_FREQ(i));
382 SR(DIVISORo(i));
383
384 SR(DATA_CYCLE1(i));
385 SR(DATA_CYCLE2(i));
386 SR(DATA_CYCLE3(i));
387
332e9d70 388 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 389 SR(CPR_COEF_R(i));
390 SR(CPR_COEF_G(i));
391 SR(CPR_COEF_B(i));
332e9d70 392 }
2a205f34 393 }
80c39712 394
c6104b8e
AT		 395 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
396 SR(OVL_BA0(i));
397 SR(OVL_BA1(i));
398 SR(OVL_POSITION(i));
399 SR(OVL_SIZE(i));
400 SR(OVL_ATTRIBUTES(i));
401 SR(OVL_FIFO_THRESHOLD(i));
402 SR(OVL_ROW_INC(i));
403 SR(OVL_PIXEL_INC(i));
404 if (dss_has_feature(FEAT_PRELOAD))
405 SR(OVL_PRELOAD(i));
406 if (i == OMAP_DSS_GFX) {
407 SR(OVL_WINDOW_SKIP(i));
408 SR(OVL_TABLE_BA(i));
409 continue;
410 }
411 SR(OVL_FIR(i));
412 SR(OVL_PICTURE_SIZE(i));
413 SR(OVL_ACCU0(i));
414 SR(OVL_ACCU1(i));
9b372c2d 415
c6104b8e
AT		 416 for (j = 0; j < 8; j++)
417 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 418
c6104b8e
AT		 419 for (j = 0; j < 8; j++)
420 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 421
c6104b8e
AT		 422 for (j = 0; j < 5; j++)
423 SR(OVL_CONV_COEF(i, j));
ab5ca071 424
c6104b8e
AT		 425 if (dss_has_feature(FEAT_FIR_COEF_V)) {
426 for (j = 0; j < 8; j++)
427 SR(OVL_FIR_COEF_V(i, j));
428 }
9b372c2d 429
c6104b8e
AT		 430 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
431 SR(OVL_BA0_UV(i));
432 SR(OVL_BA1_UV(i));
433 SR(OVL_FIR2(i));
434 SR(OVL_ACCU2_0(i));
435 SR(OVL_ACCU2_1(i));
ab5ca071 436
c6104b8e
AT		 437 for (j = 0; j < 8; j++)
438 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 439
c6104b8e
AT		 440 for (j = 0; j < 8; j++)
441 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 442
c6104b8e
AT		 443 for (j = 0; j < 8; j++)
444 SR(OVL_FIR_COEF_V2(i, j));
445 }
446 if (dss_has_feature(FEAT_ATTR2))
447 SR(OVL_ATTRIBUTES2(i));
ab5ca071 448 }
0cf35df3
MR		 449
450 if (dss_has_feature(FEAT_CORE_CLK_DIV))
451 SR(DIVISOR);
49ea86f3 452
49ea86f3
TV		 453 dispc.ctx_valid = true;
454
9229b516 455 DSSDBG("context saved\n");
80c39712
TV		 456}
457
4fbafaf3 458static void dispc_restore_context(void)
80c39712 459{
9229b516 460 int i, j;
4fbafaf3
TV		 461
462 DSSDBG("dispc_restore_context\n");
463
49ea86f3
TV		 464 if (!dispc.ctx_valid)
465 return;
466
75c7d59d 467 /*RR(IRQENABLE);*/
80c39712
TV		 468 /*RR(CONTROL);*/
469 RR(CONFIG);
80c39712 470 RR(LINE_NUMBER);
11354dd5
AT		 471 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
472 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 473 RR(GLOBAL_ALPHA);
c6104b8e 474 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 475 RR(CONFIG2);
e86d456a
CM		 476 if (dss_has_feature(FEAT_MGR_LCD3))
477 RR(CONFIG3);
80c39712 478
c6104b8e
AT		 479 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
480 RR(DEFAULT_COLOR(i));
481 RR(TRANS_COLOR(i));
482 RR(SIZE_MGR(i));
483 if (i == OMAP_DSS_CHANNEL_DIGIT)
484 continue;
485 RR(TIMING_H(i));
486 RR(TIMING_V(i));
487 RR(POL_FREQ(i));
488 RR(DIVISORo(i));
489
490 RR(DATA_CYCLE1(i));
491 RR(DATA_CYCLE2(i));
492 RR(DATA_CYCLE3(i));
2a205f34 493
332e9d70 494 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 495 RR(CPR_COEF_R(i));
496 RR(CPR_COEF_G(i));
497 RR(CPR_COEF_B(i));
332e9d70 498 }
2a205f34 499 }
80c39712 500
c6104b8e
AT		 501 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
502 RR(OVL_BA0(i));
503 RR(OVL_BA1(i));
504 RR(OVL_POSITION(i));
505 RR(OVL_SIZE(i));
506 RR(OVL_ATTRIBUTES(i));
507 RR(OVL_FIFO_THRESHOLD(i));
508 RR(OVL_ROW_INC(i));
509 RR(OVL_PIXEL_INC(i));
510 if (dss_has_feature(FEAT_PRELOAD))
511 RR(OVL_PRELOAD(i));
512 if (i == OMAP_DSS_GFX) {
513 RR(OVL_WINDOW_SKIP(i));
514 RR(OVL_TABLE_BA(i));
515 continue;
516 }
517 RR(OVL_FIR(i));
518 RR(OVL_PICTURE_SIZE(i));
519 RR(OVL_ACCU0(i));
520 RR(OVL_ACCU1(i));
9b372c2d 521
c6104b8e
AT		 522 for (j = 0; j < 8; j++)
523 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 524
c6104b8e
AT		 525 for (j = 0; j < 8; j++)
526 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 527
c6104b8e
AT		 528 for (j = 0; j < 5; j++)
529 RR(OVL_CONV_COEF(i, j));
ab5ca071 530
c6104b8e
AT		 531 if (dss_has_feature(FEAT_FIR_COEF_V)) {
532 for (j = 0; j < 8; j++)
533 RR(OVL_FIR_COEF_V(i, j));
534 }
9b372c2d 535
c6104b8e
AT		 536 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
537 RR(OVL_BA0_UV(i));
538 RR(OVL_BA1_UV(i));
539 RR(OVL_FIR2(i));
540 RR(OVL_ACCU2_0(i));
541 RR(OVL_ACCU2_1(i));
ab5ca071 542
c6104b8e
AT		 543 for (j = 0; j < 8; j++)
544 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 545
c6104b8e
AT		 546 for (j = 0; j < 8; j++)
547 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 548
c6104b8e
AT		 549 for (j = 0; j < 8; j++)
550 RR(OVL_FIR_COEF_V2(i, j));
551 }
552 if (dss_has_feature(FEAT_ATTR2))
553 RR(OVL_ATTRIBUTES2(i));
ab5ca071 554 }
80c39712 555
0cf35df3
MR		 556 if (dss_has_feature(FEAT_CORE_CLK_DIV))
557 RR(DIVISOR);
558
80c39712
TV		 559 /* enable last, because LCD & DIGIT enable are here */
560 RR(CONTROL);
2a205f34
SS		 561 if (dss_has_feature(FEAT_MGR_LCD2))
562 RR(CONTROL2);
e86d456a
CM		 563 if (dss_has_feature(FEAT_MGR_LCD3))
564 RR(CONTROL3);
75c7d59d 565 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 566 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 567
568 /*
569 * enable last so IRQs won't trigger before
570 * the context is fully restored
571 */
572 RR(IRQENABLE);
49ea86f3
TV		 573
574 DSSDBG("context restored\n");
80c39712
TV		 575}
576
577#undef SR
578#undef RR
579
4fbafaf3
TV		 580int dispc_runtime_get(void)
581{
582 int r;
583
584 DSSDBG("dispc_runtime_get\n");
585
586 r = pm_runtime_get_sync(&dispc.pdev->dev);
587 WARN_ON(r < 0);
588 return r < 0 ? r : 0;
589}
590
591void dispc_runtime_put(void)
592{
593 int r;
594
595 DSSDBG("dispc_runtime_put\n");
596
0eaf9f52 597 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 598 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 599}
600
5034b1fa 601static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
3dcec4d6 602{
efa70b3b 603 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 604}
605
5034b1fa 606static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
7d1365c9 607{
cffa947d
TV		 608 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
609 return 0;
610
efa70b3b 611 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 612}
613
5034b1fa 614static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
cb699200
TV		 615{
616 return mgr_desc[channel].sync_lost_irq;
617}
618
0b23e5b8
AT		 619u32 dispc_wb_get_framedone_irq(void)
620{
621 return DISPC_IRQ_FRAMEDONEWB;
622}
623
5034b1fa 624static void dispc_mgr_enable(enum omap_channel channel, bool enable)
03af8157
LP		 625{
626 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
627 /* flush posted write */
628 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
629}
03af8157
LP		 630
631static bool dispc_mgr_is_enabled(enum omap_channel channel)
632{
633 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
634}
635
5034b1fa 636static bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 637{
efa70b3b 638 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 639}
640
5034b1fa 641static void dispc_mgr_go(enum omap_channel channel)
80c39712 642{
0bcfdba6 643 WARN_ON(!dispc_mgr_is_enabled(channel));
3c91ee8c 644 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 645
efa70b3b 646 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 647
efa70b3b 648 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 649}
650
0b23e5b8
AT		 651bool dispc_wb_go_busy(void)
652{
653 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
654}
655
656void dispc_wb_go(void)
657{
864050c7 658 enum omap_plane_id plane = OMAP_DSS_WB;
0b23e5b8
AT		 659 bool enable, go;
660
661 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
662
663 if (!enable)
664 return;
665
666 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
667 if (go) {
668 DSSERR("GO bit not down for WB\n");
669 return;
670 }
671
672 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
673}
674
864050c7
JS		 675static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg,
676 u32 value)
80c39712 677{
9b372c2d 678 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 679}
680
864050c7
JS		 681static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg,
682 u32 value)
80c39712 683{
9b372c2d 684 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 685}
686
864050c7
JS		 687static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg,
688 u32 value)
80c39712 689{
9b372c2d 690 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 691}
692
864050c7
JS		 693static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg,
694 u32 value)
ab5ca071
AJ		 695{
696 BUG_ON(plane == OMAP_DSS_GFX);
697
698 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
699}
700
864050c7 701static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg,
f0e5caab 702 u32 value)
ab5ca071
AJ		 703{
704 BUG_ON(plane == OMAP_DSS_GFX);
705
706 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
707}
708
864050c7
JS		 709static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg,
710 u32 value)
ab5ca071
AJ		 711{
712 BUG_ON(plane == OMAP_DSS_GFX);
713
714 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
715}
716
864050c7 717static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc,
debd9074
CM		 718 int fir_vinc, int five_taps,
719 enum omap_color_component color_comp)
80c39712 720{
debd9074 721 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 722 int i;
723
debd9074
CM		 724 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
725 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 726
727 for (i = 0; i < 8; i++) {
728 u32 h, hv;
729
debd9074
CM		 730 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
731 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
732 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
733 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
734 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
735 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
736 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
737 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 738
0d66cbb5 739 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 740 dispc_ovl_write_firh_reg(plane, i, h);
741 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 742 } else {
f0e5caab
TV		 743 dispc_ovl_write_firh2_reg(plane, i, h);
744 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 745 }
746
80c39712
TV		 747 }
748
66be8f6c
GI		 749 if (five_taps) {
750 for (i = 0; i < 8; i++) {
751 u32 v;
debd9074
CM		 752 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
753 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 754 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 755 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 756 else
f0e5caab 757 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 758 }
80c39712
TV		 759 }
760}
761
80c39712 762
864050c7 763static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane,
6e5264b0
AT		 764 const struct color_conv_coef *ct)
765{
80c39712
TV		 766#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
767
6e5264b0
AT		 768 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
769 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
770 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
771 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
772 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 773
6e5264b0 774 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 775
776#undef CVAL
80c39712
TV		 777}
778
6e5264b0
AT		 779static void dispc_setup_color_conv_coef(void)
780{
781 int i;
782 int num_ovl = dss_feat_get_num_ovls();
6e5264b0 783 const struct color_conv_coef ctbl_bt601_5_ovl = {
7d18bbee 784 /* YUV -> RGB */
6e5264b0
AT		 785 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
786 };
787 const struct color_conv_coef ctbl_bt601_5_wb = {
7d18bbee
TV		 788 /* RGB -> YUV */
789 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
6e5264b0
AT		 790 };
791
792 for (i = 1; i < num_ovl; i++)
793 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
794
20efbc35
TV		 795 if (dispc.feat->has_writeback)
796 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
6e5264b0 797}
80c39712 798
864050c7 799static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr)
80c39712 800{
9b372c2d 801 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 802}
803
864050c7 804static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr)
80c39712 805{
9b372c2d 806 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 807}
808
864050c7 809static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr)
ab5ca071
AJ		 810{
811 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
812}
813
864050c7 814static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr)
ab5ca071
AJ		 815{
816 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
817}
818
864050c7 819static void dispc_ovl_set_pos(enum omap_plane_id plane,
d79db853 820 enum omap_overlay_caps caps, int x, int y)
80c39712 821{
d79db853
AT		 822 u32 val;
823
824 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
825 return;
826
827 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 828
829 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 830}
831
864050c7 832static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width,
78b687fc 833 int height)
80c39712 834{
80c39712 835 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 836
36d87d95 837 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 838 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
839 else
840 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 841}
842
864050c7 843static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width,
78b687fc 844 int height)
80c39712
TV		 845{
846 u32 val;
80c39712
TV		 847
848 BUG_ON(plane == OMAP_DSS_GFX);
849
850 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 851
36d87d95
AT		 852 if (plane == OMAP_DSS_WB)
853 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
854 else
855 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 856}
857
864050c7 858static void dispc_ovl_set_zorder(enum omap_plane_id plane,
5b54ed3e 859 enum omap_overlay_caps caps, u8 zorder)
54128701 860{
5b54ed3e 861 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 862 return;
863
864 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
865}
866
867static void dispc_ovl_enable_zorder_planes(void)
868{
869 int i;
870
871 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
872 return;
873
874 for (i = 0; i < dss_feat_get_num_ovls(); i++)
875 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
876}
877
864050c7 878static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane,
5b54ed3e 879 enum omap_overlay_caps caps, bool enable)
fd28a390 880{
5b54ed3e 881 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 882 return;
883
9b372c2d 884 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 885}
886
864050c7 887static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane,
5b54ed3e 888 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 889{
b8c095b4 890 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 891 int shift;
892
5b54ed3e 893 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 894 return;
a0acb557 895
fe3cc9d6
TV		 896 shift = shifts[plane];
897 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 898}
899
864050c7 900static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc)
80c39712 901{
9b372c2d 902 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 903}
904
864050c7 905static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc)
80c39712 906{
9b372c2d 907 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 908}
909
41aff42a 910static void dispc_ovl_set_color_mode(enum omap_plane_id plane, u32 fourcc)
80c39712
TV		 911{
912 u32 m = 0;
f20e4220 913 if (plane != OMAP_DSS_GFX) {
41aff42a 914 switch (fourcc) {
3e1d65cd 915 case DRM_FORMAT_NV12:
f20e4220 916 m = 0x0; break;
3e1d65cd 917 case DRM_FORMAT_XRGB4444:
f20e4220 918 m = 0x1; break;
3e1d65cd 919 case DRM_FORMAT_RGBA4444:
f20e4220 920 m = 0x2; break;
3e1d65cd 921 case DRM_FORMAT_RGBX4444:
f20e4220 922 m = 0x4; break;
3e1d65cd 923 case DRM_FORMAT_ARGB4444:
f20e4220 924 m = 0x5; break;
3e1d65cd 925 case DRM_FORMAT_RGB565:
f20e4220 926 m = 0x6; break;
3e1d65cd 927 case DRM_FORMAT_ARGB1555:
f20e4220 928 m = 0x7; break;
3e1d65cd 929 case DRM_FORMAT_XRGB8888:
f20e4220 930 m = 0x8; break;
3e1d65cd 931 case DRM_FORMAT_RGB888:
f20e4220 932 m = 0x9; break;
3e1d65cd 933 case DRM_FORMAT_YUYV:
f20e4220 934 m = 0xa; break;
3e1d65cd 935 case DRM_FORMAT_UYVY:
f20e4220 936 m = 0xb; break;
3e1d65cd 937 case DRM_FORMAT_ARGB8888:
f20e4220 938 m = 0xc; break;
3e1d65cd 939 case DRM_FORMAT_RGBA8888:
f20e4220 940 m = 0xd; break;
3e1d65cd 941 case DRM_FORMAT_RGBX8888:
f20e4220 942 m = 0xe; break;
3e1d65cd 943 case DRM_FORMAT_XRGB1555:
f20e4220
AJ		 944 m = 0xf; break;
945 default:
c6eee968 946 BUG(); return;
f20e4220
AJ		 947 }
948 } else {
41aff42a 949 switch (fourcc) {
3e1d65cd 950 case DRM_FORMAT_RGBX4444:
f20e4220 951 m = 0x4; break;
3e1d65cd 952 case DRM_FORMAT_ARGB4444:
f20e4220 953 m = 0x5; break;
3e1d65cd 954 case DRM_FORMAT_RGB565:
f20e4220 955 m = 0x6; break;
3e1d65cd 956 case DRM_FORMAT_ARGB1555:
f20e4220 957 m = 0x7; break;
3e1d65cd 958 case DRM_FORMAT_XRGB8888:
f20e4220 959 m = 0x8; break;
3e1d65cd 960 case DRM_FORMAT_RGB888:
f20e4220 961 m = 0x9; break;
3e1d65cd 962 case DRM_FORMAT_XRGB4444:
f20e4220 963 m = 0xa; break;
3e1d65cd 964 case DRM_FORMAT_RGBA4444:
f20e4220 965 m = 0xb; break;
3e1d65cd 966 case DRM_FORMAT_ARGB8888:
f20e4220 967 m = 0xc; break;
3e1d65cd 968 case DRM_FORMAT_RGBA8888:
f20e4220 969 m = 0xd; break;
3e1d65cd 970 case DRM_FORMAT_RGBX8888:
f20e4220 971 m = 0xe; break;
3e1d65cd 972 case DRM_FORMAT_XRGB1555:
f20e4220
AJ		 973 m = 0xf; break;
974 default:
c6eee968 975 BUG(); return;
f20e4220 976 }
80c39712
TV		 977 }
978
9b372c2d 979 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 980}
981
41aff42a 982static bool format_is_yuv(u32 fourcc)
5edec14c 983{
41aff42a 984 switch (fourcc) {
3e1d65cd
TV		 985 case DRM_FORMAT_YUYV:
986 case DRM_FORMAT_UYVY:
987 case DRM_FORMAT_NV12:
5edec14c
TV		 988 return true;
989 default:
990 return false;
991 }
992}
993
864050c7 994static void dispc_ovl_configure_burst_type(enum omap_plane_id plane,
65e006ff
CM		 995 enum omap_dss_rotation_type rotation_type)
996{
997 if (dss_has_feature(FEAT_BURST_2D) == 0)
998 return;
999
1000 if (rotation_type == OMAP_DSS_ROT_TILER)
1001 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
1002 else
1003 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
1004}
1005
864050c7
JS		 1006static void dispc_ovl_set_channel_out(enum omap_plane_id plane,
1007 enum omap_channel channel)
80c39712
TV		 1008{
1009 int shift;
1010 u32 val;
2a205f34 1011 int chan = 0, chan2 = 0;
80c39712
TV		 1012
1013 switch (plane) {
1014 case OMAP_DSS_GFX:
1015 shift = 8;
1016 break;
1017 case OMAP_DSS_VIDEO1:
1018 case OMAP_DSS_VIDEO2:
b8c095b4 1019 case OMAP_DSS_VIDEO3:
80c39712
TV		 1020 shift = 16;
1021 break;
1022 default:
1023 BUG();
1024 return;
1025 }
1026
9b372c2d 1027 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 1028 if (dss_has_feature(FEAT_MGR_LCD2)) {
1029 switch (channel) {
1030 case OMAP_DSS_CHANNEL_LCD:
1031 chan = 0;
1032 chan2 = 0;
1033 break;
1034 case OMAP_DSS_CHANNEL_DIGIT:
1035 chan = 1;
1036 chan2 = 0;
1037 break;
1038 case OMAP_DSS_CHANNEL_LCD2:
1039 chan = 0;
1040 chan2 = 1;
1041 break;
e86d456a
CM		 1042 case OMAP_DSS_CHANNEL_LCD3:
1043 if (dss_has_feature(FEAT_MGR_LCD3)) {
1044 chan = 0;
1045 chan2 = 2;
1046 } else {
1047 BUG();
1048 return;
1049 }
1050 break;
c2665c41
TV		 1051 case OMAP_DSS_CHANNEL_WB:
1052 chan = 0;
1053 chan2 = 3;
1054 break;
2a205f34
SS		 1055 default:
1056 BUG();
c6eee968 1057 return;
2a205f34
SS		 1058 }
1059
1060 val = FLD_MOD(val, chan, shift, shift);
1061 val = FLD_MOD(val, chan2, 31, 30);
1062 } else {
1063 val = FLD_MOD(val, channel, shift, shift);
1064 }
9b372c2d 1065 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1066}
1067
864050c7 1068static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane)
2cc5d1af
TV		 1069{
1070 int shift;
1071 u32 val;
2cc5d1af
TV		 1072
1073 switch (plane) {
1074 case OMAP_DSS_GFX:
1075 shift = 8;
1076 break;
1077 case OMAP_DSS_VIDEO1:
1078 case OMAP_DSS_VIDEO2:
1079 case OMAP_DSS_VIDEO3:
1080 shift = 16;
1081 break;
1082 default:
1083 BUG();
c6eee968 1084 return 0;
2cc5d1af
TV		 1085 }
1086
1087 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1088
d7df5ad4
TV		 1089 if (FLD_GET(val, shift, shift) == 1)
1090 return OMAP_DSS_CHANNEL_DIGIT;
2cc5d1af 1091
d7df5ad4
TV		 1092 if (!dss_has_feature(FEAT_MGR_LCD2))
1093 return OMAP_DSS_CHANNEL_LCD;
1094
1095 switch (FLD_GET(val, 31, 30)) {
1096 case 0:
1097 default:
1098 return OMAP_DSS_CHANNEL_LCD;
1099 case 1:
1100 return OMAP_DSS_CHANNEL_LCD2;
1101 case 2:
1102 return OMAP_DSS_CHANNEL_LCD3;
c2665c41
TV		 1103 case 3:
1104 return OMAP_DSS_CHANNEL_WB;
d7df5ad4 1105 }
2cc5d1af
TV		 1106}
1107
d9ac773c
AT		 1108void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1109{
864050c7 1110 enum omap_plane_id plane = OMAP_DSS_WB;
d9ac773c
AT		 1111
1112 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1113}
1114
864050c7 1115static void dispc_ovl_set_burst_size(enum omap_plane_id plane,
80c39712
TV		 1116 enum omap_burst_size burst_size)
1117{
8bbe09ee 1118 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1119 int shift;
80c39712 1120
fe3cc9d6 1121 shift = shifts[plane];
5ed8cf5b 1122 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1123}
1124
5ed8cf5b
TV		 1125static void dispc_configure_burst_sizes(void)
1126{
1127 int i;
1128 const int burst_size = BURST_SIZE_X8;
1129
1130 /* Configure burst size always to maximum size */
392faa0e 1131 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1132 dispc_ovl_set_burst_size(i, burst_size);
5b354af9
TV		 1133 if (dispc.feat->has_writeback)
1134 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
5ed8cf5b
TV		 1135}
1136
864050c7 1137static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane)
5ed8cf5b
TV		 1138{
1139 unsigned unit = dss_feat_get_burst_size_unit();
1140 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1141 return unit * 8;
1142}
1143
9c39d17e 1144static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane)
c283400a
TV		 1145{
1146 return dss_feat_get_supported_color_modes(plane);
1147}
c283400a 1148
5034b1fa 1149static int dispc_get_num_ovls(void)
c283400a
TV		 1150{
1151 return dss_feat_get_num_ovls();
1152}
c283400a 1153
c64dca40 1154static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1155{
efa70b3b 1156 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1157 return;
1158
efa70b3b 1159 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1160}
1161
c64dca40 1162static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1163 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1164{
1165 u32 coef_r, coef_g, coef_b;
1166
dd88b7a6 1167 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1168 return;
1169
1170 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1171 FLD_VAL(coefs->rb, 9, 0);
1172 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1173 FLD_VAL(coefs->gb, 9, 0);
1174 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1175 FLD_VAL(coefs->bb, 9, 0);
1176
1177 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1178 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1179 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1180}
1181
864050c7
JS		 1182static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane,
1183 bool enable)
80c39712
TV		 1184{
1185 u32 val;
1186
1187 BUG_ON(plane == OMAP_DSS_GFX);
1188
9b372c2d 1189 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1190 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1191 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1192}
1193
864050c7 1194static void dispc_ovl_enable_replication(enum omap_plane_id plane,
d79db853 1195 enum omap_overlay_caps caps, bool enable)
80c39712 1196{
b8c095b4 1197 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1198 int shift;
80c39712 1199
d79db853
AT		 1200 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1201 return;
1202
fe3cc9d6
TV		 1203 shift = shifts[plane];
1204 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1205}
1206
8f366162 1207static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1208 u16 height)
80c39712
TV		 1209{
1210 u32 val;
80c39712 1211
33b89928
AT		 1212 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1213 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1214
8f366162 1215 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1216}
1217
42a6961c 1218static void dispc_init_fifos(void)
80c39712 1219{
80c39712 1220 u32 size;
42a6961c 1221 int fifo;
a0acb557 1222 u8 start, end;
5ed8cf5b 1223 u32 unit;
47fc469b 1224 int i;
5ed8cf5b
TV		 1225
1226 unit = dss_feat_get_buffer_size_unit();
80c39712 1227
a0acb557 1228 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1229
42a6961c
TV		 1230 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1231 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1232 size *= unit;
42a6961c
TV		 1233 dispc.fifo_size[fifo] = size;
1234
1235 /*
1236 * By default fifos are mapped directly to overlays, fifo 0 to
1237 * ovl 0, fifo 1 to ovl 1, etc.
1238 */
1239 dispc.fifo_assignment[fifo] = fifo;
80c39712 1240 }
66a0f9e4
TV		 1241
1242 /*
1243 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1244 * causes problems with certain use cases, like using the tiler in 2D
1245 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1246 * giving GFX plane a larger fifo. WB but should work fine with a
1247 * smaller fifo.
1248 */
1249 if (dispc.feat->gfx_fifo_workaround) {
1250 u32 v;
1251
1252 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1253
1254 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1255 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1256 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1257 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1258
1259 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1260
1261 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1262 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1263 }
47fc469b
TV		 1264
1265 /*
1266 * Setup default fifo thresholds.
1267 */
1268 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1269 u32 low, high;
1270 const bool use_fifomerge = false;
1271 const bool manual_update = false;
1272
1273 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1274 use_fifomerge, manual_update);
1275
1276 dispc_ovl_set_fifo_threshold(i, low, high);
1277 }
65e116e1
TV		 1278
1279 if (dispc.feat->has_writeback) {
1280 u32 low, high;
1281 const bool use_fifomerge = false;
1282 const bool manual_update = false;
1283
1284 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1285 use_fifomerge, manual_update);
1286
1287 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1288 }
80c39712
TV		 1289}
1290
864050c7 1291static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane)
80c39712 1292{
42a6961c
TV		 1293 int fifo;
1294 u32 size = 0;
1295
1296 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1297 if (dispc.fifo_assignment[fifo] == plane)
1298 size += dispc.fifo_size[fifo];
1299 }
1300
1301 return size;
80c39712
TV		 1302}
1303
864050c7
JS		 1304void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
1305 u32 high)
80c39712 1306{
a0acb557 1307 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1308 u32 unit;
1309
1310 unit = dss_feat_get_buffer_size_unit();
1311
1312 WARN_ON(low % unit != 0);
1313 WARN_ON(high % unit != 0);
1314
1315 low /= unit;
1316 high /= unit;
a0acb557 1317
9b372c2d
AT		 1318 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1319 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1320
3cb5d966 1321 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1322 plane,
9b372c2d 1323 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1324 lo_start, lo_end) * unit,
9b372c2d 1325 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1326 hi_start, hi_end) * unit,
1327 low * unit, high * unit);
80c39712 1328
9b372c2d 1329 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1330 FLD_VAL(high, hi_start, hi_end) |
1331 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1332
1333 /*
1334 * configure the preload to the pipeline's high threhold, if HT it's too
1335 * large for the preload field, set the threshold to the maximum value
1336 * that can be held by the preload register
1337 */
1338 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1339 plane != OMAP_DSS_WB)
1340 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712
TV		 1341}
1342
1343void dispc_enable_fifomerge(bool enable)
1344{
e6b0f884
TV		 1345 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1346 WARN_ON(enable);
1347 return;
1348 }
1349
80c39712
TV		 1350 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1351 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1352}
1353
864050c7 1354void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
3568f2a4
TV		 1355 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1356 bool manual_update)
83fa2f2e
TV		 1357{
1358 /*
1359 * All sizes are in bytes. Both the buffer and burst are made of
1360 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1361 */
1362
1363 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1364 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1365 int i;
83fa2f2e
TV		 1366
1367 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1368 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1369
e0e405b9
TV		 1370 if (use_fifomerge) {
1371 total_fifo_size = 0;
392faa0e 1372 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1373 total_fifo_size += dispc_ovl_get_fifo_size(i);
1374 } else {
1375 total_fifo_size = ovl_fifo_size;
1376 }
1377
1378 /*
1379 * We use the same low threshold for both fifomerge and non-fifomerge
1380 * cases, but for fifomerge we calculate the high threshold using the
1381 * combined fifo size
1382 */
1383
3568f2a4 1384 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1385 *fifo_low = ovl_fifo_size - burst_size * 2;
1386 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1387 } else if (plane == OMAP_DSS_WB) {
1388 /*
1389 * Most optimal configuration for writeback is to push out data
1390 * to the interconnect the moment writeback pushes enough pixels
1391 * in the FIFO to form a burst
1392 */
1393 *fifo_low = 0;
1394 *fifo_high = burst_size;
e0e405b9
TV		 1395 } else {
1396 *fifo_low = ovl_fifo_size - burst_size;
1397 *fifo_high = total_fifo_size - buf_unit;
1398 }
83fa2f2e
TV		 1399}
1400
864050c7 1401static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable)
c64aa3a6
TV		 1402{
1403 int bit;
1404
1405 if (plane == OMAP_DSS_GFX)
1406 bit = 14;
1407 else
1408 bit = 23;
1409
1410 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1411}
1412
864050c7 1413static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane,
c64aa3a6
TV		 1414 int low, int high)
1415{
1416 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1417 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1418}
1419
1420static void dispc_init_mflag(void)
1421{
1422 int i;
1423
fe59e5cf
TV		 1424 /*
1425 * HACK: NV12 color format and MFLAG seem to have problems working
1426 * together: using two displays, and having an NV12 overlay on one of
1427 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1428 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1429 * remove the errors, but there doesn't seem to be a clear logic on
1430 * which values work and which not.
1431 *
1432 * As a work-around, set force MFLAG to always on.
1433 */
c64aa3a6 1434 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
fe59e5cf 1435 (1 << 0) | /* MFLAG_CTRL = force always on */
c64aa3a6
TV		 1436 (0 << 2)); /* MFLAG_START = disable */
1437
1438 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1439 u32 size = dispc_ovl_get_fifo_size(i);
1440 u32 unit = dss_feat_get_buffer_size_unit();
1441 u32 low, high;
1442
1443 dispc_ovl_set_mflag(i, true);
1444
1445 /*
1446 * Simulation team suggests below thesholds:
1447 * HT = fifosize * 5 / 8;
1448 * LT = fifosize * 4 / 8;
1449 */
1450
1451 low = size * 4 / 8 / unit;
1452 high = size * 5 / 8 / unit;
1453
1454 dispc_ovl_set_mflag_threshold(i, low, high);
1455 }
ecb0b366
TV		 1456
1457 if (dispc.feat->has_writeback) {
1458 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1459 u32 unit = dss_feat_get_buffer_size_unit();
1460 u32 low, high;
1461
1462 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1463
1464 /*
1465 * Simulation team suggests below thesholds:
1466 * HT = fifosize * 5 / 8;
1467 * LT = fifosize * 4 / 8;
1468 */
1469
1470 low = size * 4 / 8 / unit;
1471 high = size * 5 / 8 / unit;
1472
1473 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1474 }
c64aa3a6
TV		 1475}
1476
864050c7 1477static void dispc_ovl_set_fir(enum omap_plane_id plane,
0d66cbb5
AJ		 1478 int hinc, int vinc,
1479 enum omap_color_component color_comp)
80c39712
TV		 1480{
1481 u32 val;
80c39712 1482
0d66cbb5
AJ		 1483 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1484 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1485
0d66cbb5
AJ		 1486 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1487 &hinc_start, &hinc_end);
1488 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1489 &vinc_start, &vinc_end);
1490 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1491 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1492
0d66cbb5
AJ		 1493 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1494 } else {
1495 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1496 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1497 }
80c39712
TV		 1498}
1499
864050c7
JS		 1500static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu,
1501 int vaccu)
80c39712
TV		 1502{
1503 u32 val;
87a7484b 1504 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1505
87a7484b
AT		 1506 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1507 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1508
1509 val = FLD_VAL(vaccu, vert_start, vert_end) |
1510 FLD_VAL(haccu, hor_start, hor_end);
1511
9b372c2d 1512 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1513}
1514
864050c7
JS		 1515static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu,
1516 int vaccu)
80c39712
TV		 1517{
1518 u32 val;
87a7484b 1519 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1520
87a7484b
AT		 1521 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1522 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1523
1524 val = FLD_VAL(vaccu, vert_start, vert_end) |
1525 FLD_VAL(haccu, hor_start, hor_end);
1526
9b372c2d 1527 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1528}
1529
864050c7 1530static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu,
f0e5caab 1531 int vaccu)
ab5ca071
AJ		 1532{
1533 u32 val;
1534
1535 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1536 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1537}
1538
864050c7 1539static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu,
f0e5caab 1540 int vaccu)
ab5ca071
AJ		 1541{
1542 u32 val;
1543
1544 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1545 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1546}
80c39712 1547
864050c7 1548static void dispc_ovl_set_scale_param(enum omap_plane_id plane,
80c39712
TV		 1549 u16 orig_width, u16 orig_height,
1550 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1551 bool five_taps, u8 rotation,
1552 enum omap_color_component color_comp)
80c39712 1553{
0d66cbb5 1554 int fir_hinc, fir_vinc;
80c39712 1555
ed14a3ce
AJ		 1556 fir_hinc = 1024 * orig_width / out_width;
1557 fir_vinc = 1024 * orig_height / out_height;
80c39712 1558
debd9074
CM		 1559 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1560 color_comp);
f0e5caab 1561 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1562}
1563
864050c7 1564static void dispc_ovl_set_accu_uv(enum omap_plane_id plane,
05dd0f53 1565 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
41aff42a 1566 bool ilace, u32 fourcc, u8 rotation)
05dd0f53
CM		 1567{
1568 int h_accu2_0, h_accu2_1;
1569 int v_accu2_0, v_accu2_1;
1570 int chroma_hinc, chroma_vinc;
1571 int idx;
1572
1573 struct accu {
1574 s8 h0_m, h0_n;
1575 s8 h1_m, h1_n;
1576 s8 v0_m, v0_n;
1577 s8 v1_m, v1_n;
1578 };
1579
1580 const struct accu *accu_table;
1581 const struct accu *accu_val;
1582
1583 static const struct accu accu_nv12[4] = {
1584 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1585 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1586 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1587 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1588 };
1589
1590 static const struct accu accu_nv12_ilace[4] = {
1591 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1592 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1593 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1594 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1595 };
1596
1597 static const struct accu accu_yuv[4] = {
1598 { 0, 1, 0, 1, 0, 1, 0, 1 },
1599 { 0, 1, 0, 1, 0, 1, 0, 1 },
1600 { -1, 1, 0, 1, 0, 1, 0, 1 },
1601 { 0, 1, 0, 1, -1, 1, 0, 1 },
1602 };
1603
0bd97c42
TV		 1604 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
1605 switch (rotation & DRM_MODE_ROTATE_MASK) {
1606 default:
1607 case DRM_MODE_ROTATE_0:
05dd0f53
CM		 1608 idx = 0;
1609 break;
0bd97c42
TV		 1610 case DRM_MODE_ROTATE_90:
1611 idx = 3;
05dd0f53 1612 break;
0bd97c42 1613 case DRM_MODE_ROTATE_180:
05dd0f53
CM		 1614 idx = 2;
1615 break;
0bd97c42
TV		 1616 case DRM_MODE_ROTATE_270:
1617 idx = 1;
05dd0f53 1618 break;
05dd0f53
CM		 1619 }
1620
41aff42a 1621 switch (fourcc) {
3e1d65cd 1622 case DRM_FORMAT_NV12:
05dd0f53
CM		 1623 if (ilace)
1624 accu_table = accu_nv12_ilace;
1625 else
1626 accu_table = accu_nv12;
1627 break;
3e1d65cd
TV		 1628 case DRM_FORMAT_YUYV:
1629 case DRM_FORMAT_UYVY:
05dd0f53
CM		 1630 accu_table = accu_yuv;
1631 break;
1632 default:
1633 BUG();
c6eee968 1634 return;
05dd0f53
CM		 1635 }
1636
1637 accu_val = &accu_table[idx];
1638
1639 chroma_hinc = 1024 * orig_width / out_width;
1640 chroma_vinc = 1024 * orig_height / out_height;
1641
1642 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1643 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1644 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1645 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1646
1647 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1648 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1649}
1650
864050c7 1651static void dispc_ovl_set_scaling_common(enum omap_plane_id plane,
0d66cbb5
AJ		 1652 u16 orig_width, u16 orig_height,
1653 u16 out_width, u16 out_height,
1654 bool ilace, bool five_taps,
41aff42a 1655 bool fieldmode, u32 fourcc,
0d66cbb5
AJ		 1656 u8 rotation)
1657{
1658 int accu0 = 0;
1659 int accu1 = 0;
1660 u32 l;
80c39712 1661
f0e5caab 1662 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1663 out_width, out_height, five_taps,
1664 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1665 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1666
87a7484b
AT		 1667 /* RESIZEENABLE and VERTICALTAPS */
1668 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1669 l |= (orig_width != out_width) ? (1 << 5) : 0;
1670 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1671 l |= five_taps ? (1 << 21) : 0;
80c39712 1672
87a7484b
AT		 1673 /* VRESIZECONF and HRESIZECONF */
1674 if (dss_has_feature(FEAT_RESIZECONF)) {
1675 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1676 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1677 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1678 }
80c39712 1679
87a7484b
AT		 1680 /* LINEBUFFERSPLIT */
1681 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1682 l &= ~(0x1 << 22);
1683 l |= five_taps ? (1 << 22) : 0;
1684 }
80c39712 1685
9b372c2d 1686 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1687
1688 /*
1689 * field 0 = even field = bottom field
1690 * field 1 = odd field = top field
1691 */
1692 if (ilace && !fieldmode) {
1693 accu1 = 0;
0d66cbb5 1694 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1695 if (accu0 >= 1024/2) {
1696 accu1 = 1024/2;
1697 accu0 -= accu1;
1698 }
1699 }
1700
f0e5caab
TV		 1701 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1702 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1703}
1704
864050c7 1705static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane,
0d66cbb5
AJ		 1706 u16 orig_width, u16 orig_height,
1707 u16 out_width, u16 out_height,
1708 bool ilace, bool five_taps,
41aff42a 1709 bool fieldmode, u32 fourcc,
0d66cbb5
AJ		 1710 u8 rotation)
1711{
1712 int scale_x = out_width != orig_width;
1713 int scale_y = out_height != orig_height;
0cac5b61 1714 bool chroma_upscale = plane != OMAP_DSS_WB;
0d66cbb5
AJ		 1715
1716 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1717 return;
5edec14c 1718
41aff42a 1719 if (!format_is_yuv(fourcc)) {
0d66cbb5 1720 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1721 if (plane != OMAP_DSS_WB)
1722 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1723 return;
1724 }
36377357
TV		 1725
1726 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
41aff42a 1727 out_height, ilace, fourcc, rotation);
36377357 1728
41aff42a 1729 switch (fourcc) {
3e1d65cd 1730 case DRM_FORMAT_NV12:
20fbb50b
AT		 1731 if (chroma_upscale) {
1732 /* UV is subsampled by 2 horizontally and vertically */
1733 orig_height >>= 1;
1734 orig_width >>= 1;
1735 } else {
1736 /* UV is downsampled by 2 horizontally and vertically */
1737 orig_height <<= 1;
1738 orig_width <<= 1;
1739 }
1740
0d66cbb5 1741 break;
3e1d65cd
TV		 1742 case DRM_FORMAT_YUYV:
1743 case DRM_FORMAT_UYVY:
20fbb50b 1744 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0bd97c42 1745 if (!drm_rotation_90_or_270(rotation)) {
20fbb50b
AT		 1746 if (chroma_upscale)
1747 /* UV is subsampled by 2 horizontally */
1748 orig_width >>= 1;
1749 else
1750 /* UV is downsampled by 2 horizontally */
1751 orig_width <<= 1;
1752 }
1753
0d66cbb5 1754 /* must use FIR for YUV422 if rotated */
0bd97c42 1755 if ((rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0)
0d66cbb5 1756 scale_x = scale_y = true;
20fbb50b 1757
0d66cbb5
AJ		 1758 break;
1759 default:
1760 BUG();
c6eee968 1761 return;
0d66cbb5
AJ		 1762 }
1763
1764 if (out_width != orig_width)
1765 scale_x = true;
1766 if (out_height != orig_height)
1767 scale_y = true;
1768
f0e5caab 1769 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1770 out_width, out_height, five_taps,
1771 rotation, DISPC_COLOR_COMPONENT_UV);
1772
2a5561b1
AT		 1773 if (plane != OMAP_DSS_WB)
1774 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1775 (scale_x || scale_y) ? 1 : 0, 8, 8);
1776
0d66cbb5
AJ		 1777 /* set H scaling */
1778 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1779 /* set V scaling */
1780 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1781}
1782
864050c7 1783static void dispc_ovl_set_scaling(enum omap_plane_id plane,
0d66cbb5
AJ		 1784 u16 orig_width, u16 orig_height,
1785 u16 out_width, u16 out_height,
1786 bool ilace, bool five_taps,
41aff42a 1787 bool fieldmode, u32 fourcc,
0d66cbb5
AJ		 1788 u8 rotation)
1789{
1790 BUG_ON(plane == OMAP_DSS_GFX);
1791
f0e5caab 1792 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1793 orig_width, orig_height,
1794 out_width, out_height,
1795 ilace, five_taps,
41aff42a 1796 fieldmode, fourcc,
0d66cbb5
AJ		 1797 rotation);
1798
f0e5caab 1799 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1800 orig_width, orig_height,
1801 out_width, out_height,
1802 ilace, five_taps,
41aff42a 1803 fieldmode, fourcc,
0d66cbb5
AJ		 1804 rotation);
1805}
1806
273ffeaf 1807static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation,
4eebb80e 1808 enum omap_dss_rotation_type rotation_type, u32 fourcc)
80c39712 1809{
87a7484b
AT		 1810 bool row_repeat = false;
1811 int vidrot = 0;
1812
0bd97c42 1813 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */
41aff42a 1814 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) {
80c39712 1815
4eebb80e 1816 if (rotation & DRM_MODE_REFLECT_X) {
0bd97c42
TV		 1817 switch (rotation & DRM_MODE_ROTATE_MASK) {
1818 case DRM_MODE_ROTATE_0:
80c39712
TV		 1819 vidrot = 2;
1820 break;
0bd97c42
TV		 1821 case DRM_MODE_ROTATE_90:
1822 vidrot = 3;
80c39712 1823 break;
0bd97c42 1824 case DRM_MODE_ROTATE_180:
80c39712
TV		 1825 vidrot = 0;
1826 break;
0bd97c42
TV		 1827 case DRM_MODE_ROTATE_270:
1828 vidrot = 1;
80c39712
TV		 1829 break;
1830 }
1831 } else {
0bd97c42
TV		 1832 switch (rotation & DRM_MODE_ROTATE_MASK) {
1833 case DRM_MODE_ROTATE_0:
80c39712
TV		 1834 vidrot = 0;
1835 break;
0bd97c42
TV		 1836 case DRM_MODE_ROTATE_90:
1837 vidrot = 3;
80c39712 1838 break;
0bd97c42 1839 case DRM_MODE_ROTATE_180:
80c39712
TV		 1840 vidrot = 2;
1841 break;
0bd97c42
TV		 1842 case DRM_MODE_ROTATE_270:
1843 vidrot = 1;
80c39712
TV		 1844 break;
1845 }
1846 }
1847
0bd97c42 1848 if (drm_rotation_90_or_270(rotation))
87a7484b 1849 row_repeat = true;
80c39712 1850 else
87a7484b 1851 row_repeat = false;
80c39712 1852 }
87a7484b 1853
3397cc6a
TV		 1854 /*
1855 * OMAP4/5 Errata i631:
1856 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1857 * rows beyond the framebuffer, which may cause OCP error.
1858 */
41aff42a 1859 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER)
3397cc6a
TV		 1860 vidrot = 1;
1861
9b372c2d 1862 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1863 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1864 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1865 row_repeat ? 1 : 0, 18, 18);
c35eeb2e 1866
3e1d65cd 1867 if (dss_feat_color_mode_supported(plane, DRM_FORMAT_NV12)) {
6d86278c 1868 bool doublestride =
41aff42a 1869 fourcc == DRM_FORMAT_NV12 &&
6d86278c 1870 rotation_type == OMAP_DSS_ROT_TILER &&
0bd97c42 1871 !drm_rotation_90_or_270(rotation);
6d86278c 1872
c35eeb2e
AT		 1873 /* DOUBLESTRIDE */
1874 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1875 }
80c39712
TV		 1876}
1877
41aff42a 1878static int color_mode_to_bpp(u32 fourcc)
80c39712 1879{
41aff42a 1880 switch (fourcc) {
3e1d65cd 1881 case DRM_FORMAT_NV12:
80c39712 1882 return 8;
3e1d65cd
TV		 1883 case DRM_FORMAT_RGBX4444:
1884 case DRM_FORMAT_RGB565:
1885 case DRM_FORMAT_ARGB4444:
1886 case DRM_FORMAT_YUYV:
1887 case DRM_FORMAT_UYVY:
1888 case DRM_FORMAT_RGBA4444:
1889 case DRM_FORMAT_XRGB4444:
1890 case DRM_FORMAT_ARGB1555:
1891 case DRM_FORMAT_XRGB1555:
80c39712 1892 return 16;
3e1d65cd 1893 case DRM_FORMAT_RGB888:
80c39712 1894 return 24;
3e1d65cd
TV		 1895 case DRM_FORMAT_XRGB8888:
1896 case DRM_FORMAT_ARGB8888:
1897 case DRM_FORMAT_RGBA8888:
1898 case DRM_FORMAT_RGBX8888:
80c39712
TV		 1899 return 32;
1900 default:
1901 BUG();
c6eee968 1902 return 0;
80c39712
TV		 1903 }
1904}
1905
1906static s32 pixinc(int pixels, u8 ps)
1907{
1908 if (pixels == 1)
1909 return 1;
1910 else if (pixels > 1)
1911 return 1 + (pixels - 1) * ps;
1912 else if (pixels < 0)
1913 return 1 - (-pixels + 1) * ps;
1914 else
1915 BUG();
c6eee968 1916 return 0;
80c39712
TV		 1917}
1918
517a8a95 1919static void calc_offset(u16 screen_width, u16 width,
41aff42a 1920 u32 fourcc, bool fieldmode,
65e006ff 1921 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
c4df6e42
TV		 1922 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim,
1923 enum omap_dss_rotation_type rotation_type, u8 rotation)
65e006ff
CM		 1924{
1925 u8 ps;
1926
41aff42a 1927 ps = color_mode_to_bpp(fourcc) / 8;
65e006ff
CM		 1928
1929 DSSDBG("scrw %d, width %d\n", screen_width, width);
1930
c4df6e42
TV		 1931 if (rotation_type == OMAP_DSS_ROT_TILER &&
1932 (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) &&
1933 drm_rotation_90_or_270(rotation)) {
1934 /*
1935 * HACK: ROW_INC needs to be calculated with TILER units.
1936 * We get such 'screen_width' that multiplying it with the
1937 * YUV422 pixel size gives the correct TILER container width.
1938 * However, 'width' is in pixels and multiplying it with YUV422
1939 * pixel size gives incorrect result. We thus multiply it here
1940 * with 2 to match the 32 bit TILER unit size.
1941 */
1942 width *= 2;
1943 }
1944
65e006ff
CM		 1945 /*
1946 * field 0 = even field = bottom field
1947 * field 1 = odd field = top field
1948 */
185e23e1 1949 *offset0 = field_offset * screen_width * ps;
65e006ff 1950 *offset1 = 0;
185e23e1 1951
65e006ff
CM		 1952 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1953 (fieldmode ? screen_width : 0), ps);
41aff42a 1954 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY)
65e006ff
CM		 1955 *pix_inc = pixinc(x_predecim, 2 * ps);
1956 else
1957 *pix_inc = pixinc(x_predecim, ps);
1958}
1959
7faa9233
CM		 1960/*
1961 * This function is used to avoid synclosts in OMAP3, because of some
1962 * undocumented horizontal position and timing related limitations.
1963 */
465ec13f 1964static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
da11bbbb 1965 const struct videomode *vm, u16 pos_x,
e4998634
ID		 1966 u16 width, u16 height, u16 out_width, u16 out_height,
1967 bool five_taps)
7faa9233 1968{
230edc03 1969 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 1970 unsigned long nonactive;
7faa9233
CM		 1971 static const u8 limits[3] = { 8, 10, 20 };
1972 u64 val, blank;
1973 int i;
1974
da11bbbb
PU		 1975 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len +
1976 vm->hback_porch - out_width;
7faa9233
CM		 1977
1978 i = 0;
1979 if (out_height < height)
1980 i++;
1981 if (out_width < width)
1982 i++;
da11bbbb 1983 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) *
0a30e150 1984 lclk, pclk);
7faa9233
CM		 1985 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1986 if (blank <= limits[i])
1987 return -EINVAL;
1988
e4998634
ID		 1989 /* FIXME add checks for 3-tap filter once the limitations are known */
1990 if (!five_taps)
1991 return 0;
1992
7faa9233
CM		 1993 /*
1994 * Pixel data should be prepared before visible display point starts.
1995 * So, atleast DS-2 lines must have already been fetched by DISPC
1996 * during nonactive - pos_x period.
1997 */
1998 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1999 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2000 val, max(0, ds - 2) * width);
2001 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2002 return -EINVAL;
2003
2004 /*
2005 * All lines need to be refilled during the nonactive period of which
2006 * only one line can be loaded during the active period. So, atleast
2007 * DS - 1 lines should be loaded during nonactive period.
2008 */
2009 val = div_u64((u64)nonactive * lclk, pclk);
2010 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2011 val, max(0, ds - 1) * width);
2012 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2013 return -EINVAL;
2014
2015 return 0;
2016}
2017
8702ee50 2018static unsigned long calc_core_clk_five_taps(unsigned long pclk,
da11bbbb 2019 const struct videomode *vm, u16 width,
81ab95b7 2020 u16 height, u16 out_width, u16 out_height,
41aff42a 2021 u32 fourcc)
80c39712 2022{
8b53d991 2023 u32 core_clk = 0;
3e8a6ff2 2024 u64 tmp;
80c39712 2025
7282f1b7
CM		 2026 if (height <= out_height && width <= out_width)
2027 return (unsigned long) pclk;
2028
80c39712 2029 if (height > out_height) {
da11bbbb 2030 unsigned int ppl = vm->hactive;
80c39712 2031
c582935c 2032 tmp = (u64)pclk * height * out_width;
80c39712 2033 do_div(tmp, 2 * out_height * ppl);
8b53d991 2034 core_clk = tmp;
80c39712 2035
2d9c5597
VS		 2036 if (height > 2 * out_height) {
2037 if (ppl == out_width)
2038 return 0;
2039
c582935c 2040 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
80c39712 2041 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2042 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2043 }
2044 }
2045
2046 if (width > out_width) {
c582935c 2047 tmp = (u64)pclk * width;
80c39712 2048 do_div(tmp, out_width);
8b53d991 2049 core_clk = max_t(u32, core_clk, tmp);
80c39712 2050
41aff42a 2051 if (fourcc == DRM_FORMAT_XRGB8888)
8b53d991 2052 core_clk <<= 1;
80c39712
TV		 2053 }
2054
8b53d991 2055 return core_clk;
80c39712
TV		 2056}
2057
8702ee50 2058static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2059 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2060{
dcbe765b
CM		 2061 if (height > out_height && width > out_width)
2062 return pclk * 4;
2063 else
2064 return pclk * 2;
2065}
2066
8702ee50 2067static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2068 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2069{
2070 unsigned int hf, vf;
2071
2072 /*
2073 * FIXME how to determine the 'A' factor
2074 * for the no downscaling case ?
2075 */
2076
2077 if (width > 3 * out_width)
2078 hf = 4;
2079 else if (width > 2 * out_width)
2080 hf = 3;
2081 else if (width > out_width)
2082 hf = 2;
2083 else
2084 hf = 1;
80c39712
TV		 2085 if (height > out_height)
2086 vf = 2;
2087 else
2088 vf = 1;
2089
dcbe765b
CM		 2090 return pclk * vf * hf;
2091}
2092
8702ee50 2093static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2094 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2095{
8ba85306
AT		 2096 /*
2097 * If the overlay/writeback is in mem to mem mode, there are no
2098 * downscaling limitations with respect to pixel clock, return 1 as
2099 * required core clock to represent that we have sufficient enough
2100 * core clock to do maximum downscaling
2101 */
2102 if (mem_to_mem)
2103 return 1;
2104
dcbe765b
CM		 2105 if (width > out_width)
2106 return DIV_ROUND_UP(pclk, out_width) * width;
2107 else
2108 return pclk;
2109}
2110
0c6921de 2111static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
da11bbbb 2112 const struct videomode *vm,
dcbe765b 2113 u16 width, u16 height, u16 out_width, u16 out_height,
41aff42a 2114 u32 fourcc, bool *five_taps,
dcbe765b 2115 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2116 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2117{
2118 int error;
2119 u16 in_width, in_height;
2120 int min_factor = min(*decim_x, *decim_y);
2121 const int maxsinglelinewidth =
2122 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2123
dcbe765b
CM		 2124 *five_taps = false;
2125
2126 do {
eec77da2
TV		 2127 in_height = height / *decim_y;
2128 in_width = width / *decim_x;
8702ee50 2129 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2130 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2131 error = (in_width > maxsinglelinewidth || !*core_clk ||
2132 *core_clk > dispc_core_clk_rate());
2133 if (error) {
2134 if (*decim_x == *decim_y) {
2135 *decim_x = min_factor;
2136 ++*decim_y;
2137 } else {
2138 swap(*decim_x, *decim_y);
2139 if (*decim_x < *decim_y)
2140 ++*decim_x;
2141 }
2142 }
2143 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2144
3ce17b48
TV		 2145 if (error) {
2146 DSSERR("failed to find scaling settings\n");
2147 return -EINVAL;
2148 }
2149
dcbe765b
CM		 2150 if (in_width > maxsinglelinewidth) {
2151 DSSERR("Cannot scale max input width exceeded");
2152 return -EINVAL;
2153 }
2154 return 0;
2155}
2156
0c6921de 2157static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
da11bbbb 2158 const struct videomode *vm,
dcbe765b 2159 u16 width, u16 height, u16 out_width, u16 out_height,
41aff42a 2160 u32 fourcc, bool *five_taps,
dcbe765b 2161 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2162 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2163{
2164 int error;
2165 u16 in_width, in_height;
dcbe765b
CM		 2166 const int maxsinglelinewidth =
2167 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2168
2169 do {
eec77da2
TV		 2170 in_height = height / *decim_y;
2171 in_width = width / *decim_x;
e4998634 2172 *five_taps = in_height > out_height;
dcbe765b
CM		 2173
2174 if (in_width > maxsinglelinewidth)
2175 if (in_height > out_height &&
2176 in_height < out_height * 2)
2177 *five_taps = false;
e4998634
ID		 2178again:
2179 if (*five_taps)
da11bbbb 2180 *core_clk = calc_core_clk_five_taps(pclk, vm,
e4998634 2181 in_width, in_height, out_width,
41aff42a 2182 out_height, fourcc);
e4998634 2183 else
8702ee50 2184 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2185 in_height, out_width, out_height,
2186 mem_to_mem);
dcbe765b 2187
da11bbbb 2188 error = check_horiz_timing_omap3(pclk, lclk, vm,
e4998634
ID		 2189 pos_x, in_width, in_height, out_width,
2190 out_height, *five_taps);
2191 if (error && *five_taps) {
2192 *five_taps = false;
2193 goto again;
2194 }
2195
dcbe765b
CM		 2196 error = (error || in_width > maxsinglelinewidth * 2 ||
2197 (in_width > maxsinglelinewidth && *five_taps) ||
2198 !*core_clk || *core_clk > dispc_core_clk_rate());
ab6b2582
TV		 2199
2200 if (!error) {
2201 /* verify that we're inside the limits of scaler */
2202 if (in_width / 4 > out_width)
2203 error = 1;
2204
2205 if (*five_taps) {
2206 if (in_height / 4 > out_height)
2207 error = 1;
dcbe765b 2208 } else {
ab6b2582
TV		 2209 if (in_height / 2 > out_height)
2210 error = 1;
dcbe765b
CM		 2211 }
2212 }
ab6b2582 2213
7059e3d8
TV		 2214 if (error)
2215 ++*decim_y;
dcbe765b
CM		 2216 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2217
3ce17b48
TV		 2218 if (error) {
2219 DSSERR("failed to find scaling settings\n");
2220 return -EINVAL;
2221 }
2222
da11bbbb 2223 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width,
f5a73482 2224 in_height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2225 DSSERR("horizontal timing too tight\n");
2226 return -EINVAL;
7282f1b7 2227 }
dcbe765b
CM		 2228
2229 if (in_width > (maxsinglelinewidth * 2)) {
2230 DSSERR("Cannot setup scaling");
2231 DSSERR("width exceeds maximum width possible");
2232 return -EINVAL;
2233 }
2234
2235 if (in_width > maxsinglelinewidth && *five_taps) {
2236 DSSERR("cannot setup scaling with five taps");
2237 return -EINVAL;
2238 }
2239 return 0;
2240}
2241
0c6921de 2242static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
da11bbbb 2243 const struct videomode *vm,
dcbe765b 2244 u16 width, u16 height, u16 out_width, u16 out_height,
41aff42a 2245 u32 fourcc, bool *five_taps,
dcbe765b 2246 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2247 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2248{
2249 u16 in_width, in_width_max;
2250 int decim_x_min = *decim_x;
eec77da2 2251 u16 in_height = height / *decim_y;
dcbe765b
CM		 2252 const int maxsinglelinewidth =
2253 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2254 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2255
5d501085
AT		 2256 if (mem_to_mem) {
2257 in_width_max = out_width * maxdownscale;
2258 } else {
8ba85306
AT		 2259 in_width_max = dispc_core_clk_rate() /
2260 DIV_ROUND_UP(pclk, out_width);
5d501085 2261 }
dcbe765b 2262
dcbe765b
CM		 2263 *decim_x = DIV_ROUND_UP(width, in_width_max);
2264
2265 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2266 if (*decim_x > *x_predecim)
2267 return -EINVAL;
2268
2269 do {
eec77da2 2270 in_width = width / *decim_x;
dcbe765b
CM		 2271 } while (*decim_x <= *x_predecim &&
2272 in_width > maxsinglelinewidth && ++*decim_x);
2273
2274 if (in_width > maxsinglelinewidth) {
2275 DSSERR("Cannot scale width exceeds max line width");
2276 return -EINVAL;
2277 }
2278
41aff42a 2279 if (*decim_x > 4 && fourcc != DRM_FORMAT_NV12) {
1b30ab0c
JS		 2280 /*
2281 * Let's disable all scaling that requires horizontal
2282 * decimation with higher factor than 4, until we have
2283 * better estimates of what we can and can not
2284 * do. However, NV12 color format appears to work Ok
2285 * with all decimation factors.
2286 *
2287 * When decimating horizontally by more that 4 the dss
2288 * is not able to fetch the data in burst mode. When
2289 * this happens it is hard to tell if there enough
2290 * bandwidth. Despite what theory says this appears to
2291 * be true also for 16-bit color formats.
2292 */
2293 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)", *decim_x);
2294
2295 return -EINVAL;
2296 }
2297
8702ee50 2298 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2299 out_width, out_height, mem_to_mem);
dcbe765b 2300 return 0;
80c39712
TV		 2301}
2302
e4c5ae7f
TV		 2303#define DIV_FRAC(dividend, divisor) \
2304 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2305
74e16458 2306static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2307 enum omap_overlay_caps caps,
da11bbbb 2308 const struct videomode *vm,
81ab95b7 2309 u16 width, u16 height, u16 out_width, u16 out_height,
41aff42a 2310 u32 fourcc, bool *five_taps,
d557a9cf 2311 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2312 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2313{
0373cac6 2314 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2315 const int max_decim_limit = 16;
8b53d991 2316 unsigned long core_clk = 0;
dcbe765b 2317 int decim_x, decim_y, ret;
79ad75f2 2318
f95cb5eb
TV		 2319 if (width == out_width && height == out_height)
2320 return 0;
2321
da11bbbb 2322 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
4e1d3ca0
TV		 2323 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2324 return -EINVAL;
2325 }
2326
5b54ed3e 2327 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2328 return -EINVAL;
79ad75f2 2329
74e16458 2330 if (mem_to_mem) {
1c031441
AT		 2331 *x_predecim = *y_predecim = 1;
2332 } else {
2333 *x_predecim = max_decim_limit;
2334 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2335 dss_has_feature(FEAT_BURST_2D)) ?
2336 2 : max_decim_limit;
2337 }
aed74b55 2338
aed74b55
CM		 2339 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2340 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2341
aed74b55 2342 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2343 return -EINVAL;
2344
aed74b55 2345 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2346 return -EINVAL;
2347
da11bbbb 2348 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height,
41aff42a 2349 out_width, out_height, fourcc, five_taps,
8ba85306
AT		 2350 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2351 mem_to_mem);
dcbe765b
CM		 2352 if (ret)
2353 return ret;
79ad75f2 2354
e4c5ae7f
TV		 2355 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2356 width, height,
2357 out_width, out_height,
2358 out_width / width, DIV_FRAC(out_width, width),
2359 out_height / height, DIV_FRAC(out_height, height),
2360
2361 decim_x, decim_y,
2362 width / decim_x, height / decim_y,
2363 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2364 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2365
2366 *five_taps ? 5 : 3,
2367 core_clk, dispc_core_clk_rate());
79ad75f2 2368
8b53d991 2369 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2370 DSSERR("failed to set up scaling, "
8b53d991
CM		 2371 "required core clk rate = %lu Hz, "
2372 "current core clk rate = %lu Hz\n",
2373 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2374 return -EINVAL;
2375 }
2376
aed74b55
CM		 2377 *x_predecim = decim_x;
2378 *y_predecim = decim_y;
79ad75f2
AT		 2379 return 0;
2380}
2381
864050c7 2382static int dispc_ovl_setup_common(enum omap_plane_id plane,
3e8a6ff2
AT		 2383 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2384 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
41aff42a 2385 u16 out_width, u16 out_height, u32 fourcc,
4eebb80e 2386 u8 rotation, u8 zorder, u8 pre_mult_alpha,
3e8a6ff2 2387 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
da11bbbb 2388 bool replication, const struct videomode *vm,
8ba85306 2389 bool mem_to_mem)
80c39712 2390{
7282f1b7 2391 bool five_taps = true;
62a83183 2392 bool fieldmode = false;
79ad75f2 2393 int r, cconv = 0;
80c39712
TV		 2394 unsigned offset0, offset1;
2395 s32 row_inc;
2396 s32 pix_inc;
6be0d73e 2397 u16 frame_width, frame_height;
80c39712 2398 unsigned int field_offset = 0;
84a880fd
AT		 2399 u16 in_height = height;
2400 u16 in_width = width;
aed74b55 2401 int x_predecim = 1, y_predecim = 1;
da11bbbb 2402 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
74e16458
TV		 2403 unsigned long pclk = dispc_plane_pclk_rate(plane);
2404 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2405
e566658f 2406 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2407 return -EINVAL;
2408
41aff42a 2409 if (format_is_yuv(fourcc) && (in_width & 1)) {
5edec14c
TV		 2410 DSSERR("input width %d is not even for YUV format\n", in_width);
2411 return -EINVAL;
c4661b33
TV		 2412 }
2413
84a880fd
AT		 2414 out_width = out_width == 0 ? width : out_width;
2415 out_height = out_height == 0 ? height : out_height;
cf073668 2416
84a880fd 2417 if (ilace && height == out_height)
62a83183 2418 fieldmode = true;
80c39712
TV		 2419
2420 if (ilace) {
2421 if (fieldmode)
aed74b55 2422 in_height /= 2;
8eeb7019 2423 pos_y /= 2;
aed74b55 2424 out_height /= 2;
80c39712
TV		 2425
2426 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2427 "out_height %d\n", in_height, pos_y,
2428 out_height);
80c39712
TV		 2429 }
2430
41aff42a 2431 if (!dss_feat_color_mode_supported(plane, fourcc))
8dad2ab6
AT		 2432 return -EINVAL;
2433
da11bbbb 2434 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width,
41aff42a 2435 in_height, out_width, out_height, fourcc,
84a880fd 2436 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2437 rotation_type, mem_to_mem);
79ad75f2
AT		 2438 if (r)
2439 return r;
80c39712 2440
eec77da2
TV		 2441 in_width = in_width / x_predecim;
2442 in_height = in_height / y_predecim;
aed74b55 2443
c4661b33
TV		 2444 if (x_predecim > 1 || y_predecim > 1)
2445 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2446 x_predecim, y_predecim, in_width, in_height);
2447
41aff42a 2448 if (format_is_yuv(fourcc) && (in_width & 1)) {
5edec14c
TV		 2449 DSSDBG("predecimated input width is not even for YUV format\n");
2450 DSSDBG("adjusting input width %d -> %d\n",
2451 in_width, in_width & ~1);
c4661b33 2452
5edec14c 2453 in_width &= ~1;
c4661b33
TV		 2454 }
2455
41aff42a 2456 if (format_is_yuv(fourcc))
79ad75f2 2457 cconv = 1;
80c39712
TV		 2458
2459 if (ilace && !fieldmode) {
2460 /*
2461 * when downscaling the bottom field may have to start several
2462 * source lines below the top field. Unfortunately ACCUI
2463 * registers will only hold the fractional part of the offset
2464 * so the integer part must be added to the base address of the
2465 * bottom field.
2466 */
aed74b55 2467 if (!in_height || in_height == out_height)
80c39712
TV		 2468 field_offset = 0;
2469 else
aed74b55 2470 field_offset = in_height / out_height / 2;
80c39712
TV		 2471 }
2472
2473 /* Fields are independent but interleaved in memory. */
2474 if (fieldmode)
2475 field_offset = 1;
2476
c6eee968
TV		 2477 offset0 = 0;
2478 offset1 = 0;
2479 row_inc = 0;
2480 pix_inc = 0;
2481
6be0d73e
AT		 2482 if (plane == OMAP_DSS_WB) {
2483 frame_width = out_width;
2484 frame_height = out_height;
2485 } else {
2486 frame_width = in_width;
2487 frame_height = height;
2488 }
2489
517a8a95 2490 calc_offset(screen_width, frame_width,
41aff42a 2491 fourcc, fieldmode, field_offset,
517a8a95 2492 &offset0, &offset1, &row_inc, &pix_inc,
c4df6e42
TV		 2493 x_predecim, y_predecim,
2494 rotation_type, rotation);
80c39712
TV		 2495
2496 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2497 offset0, offset1, row_inc, pix_inc);
2498
41aff42a 2499 dispc_ovl_set_color_mode(plane, fourcc);
80c39712 2500
84a880fd 2501 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2502
b7536d67
TV		 2503 if (dispc.feat->reverse_ilace_field_order)
2504 swap(offset0, offset1);
2505
84a880fd
AT		 2506 dispc_ovl_set_ba0(plane, paddr + offset0);
2507 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2508
41aff42a 2509 if (fourcc == DRM_FORMAT_NV12) {
84a880fd
AT		 2510 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2511 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2512 }
2513
f2aee319
TV		 2514 if (dispc.feat->last_pixel_inc_missing)
2515 row_inc += pix_inc - 1;
2516
f0e5caab
TV		 2517 dispc_ovl_set_row_inc(plane, row_inc);
2518 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2519
84a880fd 2520 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2521 in_height, out_width, out_height);
80c39712 2522
84a880fd 2523 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2524
78b687fc 2525 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2526
5b54ed3e 2527 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2528 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2529 out_height, ilace, five_taps, fieldmode,
41aff42a 2530 fourcc, rotation);
78b687fc 2531 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2532 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2533 }
2534
4eebb80e 2535 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, fourcc);
80c39712 2536
84a880fd
AT		 2537 dispc_ovl_set_zorder(plane, caps, zorder);
2538 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2539 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2540
d79db853 2541 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2542
80c39712
TV		 2543 return 0;
2544}
2545
864050c7 2546static int dispc_ovl_setup(enum omap_plane_id plane,
273ffeaf 2547 const struct omap_overlay_info *oi,
49a3057a
TV		 2548 const struct videomode *vm, bool mem_to_mem,
2549 enum omap_channel channel)
84a880fd
AT		 2550{
2551 int r;
16bf20c7 2552 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
be2d68c6 2553 const bool replication = true;
84a880fd 2554
24f13a66 2555 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
4eebb80e 2556 " %dx%d, cmode %x, rot %d, chan %d repl %d\n",
24f13a66 2557 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd 2558 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
4eebb80e 2559 oi->fourcc, oi->rotation, channel, replication);
84a880fd 2560
49a3057a
TV		 2561 dispc_ovl_set_channel_out(plane, channel);
2562
16bf20c7 2563 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2 2564 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
41aff42a 2565 oi->out_width, oi->out_height, oi->fourcc, oi->rotation,
4eebb80e 2566 oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
da11bbbb 2567 oi->rotation_type, replication, vm, mem_to_mem);
84a880fd
AT		 2568
2569 return r;
2570}
2571
749feffa 2572int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
da11bbbb 2573 bool mem_to_mem, const struct videomode *vm)
749feffa
AT		 2574{
2575 int r;
9e4a0fc7 2576 u32 l;
864050c7 2577 enum omap_plane_id plane = OMAP_DSS_WB;
749feffa
AT		 2578 const int pos_x = 0, pos_y = 0;
2579 const u8 zorder = 0, global_alpha = 0;
be2d68c6 2580 const bool replication = true;
9e4a0fc7 2581 bool truncation;
da11bbbb
PU		 2582 int in_width = vm->hactive;
2583 int in_height = vm->vactive;
749feffa
AT		 2584 enum omap_overlay_caps caps =
2585 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2586
2587 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
4eebb80e
TV		 2588 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width,
2589 in_height, wi->width, wi->height, wi->fourcc, wi->rotation);
749feffa
AT		 2590
2591 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2592 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
4eebb80e 2593 wi->height, wi->fourcc, wi->rotation, zorder,
749feffa 2594 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
da11bbbb 2595 replication, vm, mem_to_mem);
9e4a0fc7 2596
41aff42a 2597 switch (wi->fourcc) {
3e1d65cd
TV		 2598 case DRM_FORMAT_RGB565:
2599 case DRM_FORMAT_RGB888:
2600 case DRM_FORMAT_ARGB4444:
2601 case DRM_FORMAT_RGBA4444:
2602 case DRM_FORMAT_RGBX4444:
2603 case DRM_FORMAT_ARGB1555:
2604 case DRM_FORMAT_XRGB1555:
2605 case DRM_FORMAT_XRGB4444:
9e4a0fc7
AT		 2606 truncation = true;
2607 break;
2608 default:
2609 truncation = false;
2610 break;
2611 }
2612
2613 /* setup extra DISPC_WB_ATTRIBUTES */
2614 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2615 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2616 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
4c055ce0
TV		 2617 if (mem_to_mem)
2618 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
98cd5796
TV		 2619 else
2620 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
9e4a0fc7 2621 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa 2622
98cd5796
TV		 2623 if (mem_to_mem) {
2624 /* WBDELAYCOUNT */
2625 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2626 } else {
2627 int wbdelay;
2628
da11bbbb
PU		 2629 wbdelay = min(vm->vfront_porch +
2630 vm->vsync_len + vm->vback_porch, (u32)255);
98cd5796
TV		 2631
2632 /* WBDELAYCOUNT */
2633 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2634 }
2635
749feffa
AT		 2636 return r;
2637}
2638
864050c7 2639static int dispc_ovl_enable(enum omap_plane_id plane, bool enable)
80c39712 2640{
e6d80f95
TV		 2641 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2642
9b372c2d 2643 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2644
2645 return 0;
80c39712
TV		 2646}
2647
5034b1fa 2648static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
7b9cb5ee
TV		 2649{
2650 return dss_feat_get_supported_outputs(channel);
2651}
7b9cb5ee 2652
fb2cec1f 2653static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2654{
6ced40bf
AT		 2655 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2656 return;
2657
80c39712 2658 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2659}
2660
2661void dispc_lcd_enable_signal(bool enable)
2662{
6ced40bf
AT		 2663 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2664 return;
2665
80c39712 2666 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2667}
2668
2669void dispc_pck_free_enable(bool enable)
2670{
6ced40bf
AT		 2671 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2672 return;
2673
80c39712 2674 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2675}
2676
5034b1fa 2677static int dispc_get_num_mgrs(void)
c283400a
TV		 2678{
2679 return dss_feat_get_num_mgrs();
2680}
c283400a 2681
fb2cec1f 2682static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2683{
efa70b3b 2684 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2685}
2686
2687
fb2cec1f 2688static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2689{
d21f43bc 2690 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2691}
2692
65904155 2693static void dispc_set_loadmode(enum omap_dss_load_mode mode)
80c39712 2694{
80c39712 2695 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2696}
2697
2698
c64dca40 2699static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2700{
8613b000 2701 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2702}
2703
c64dca40 2704static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2705 enum omap_dss_trans_key_type type,
2706 u32 trans_key)
2707{
efa70b3b 2708 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2709
8613b000 2710 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2711}
2712
c64dca40 2713static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2714{
efa70b3b 2715 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2716}
11354dd5 2717
c64dca40
TV		 2718static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2719 bool enable)
80c39712 2720{
11354dd5 2721 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2722 return;
2723
80c39712
TV		 2724 if (ch == OMAP_DSS_CHANNEL_LCD)
2725 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2726 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2727 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2728}
11354dd5 2729
5034b1fa 2730static void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2731 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2732{
2733 dispc_mgr_set_default_color(channel, info->default_color);
2734 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2735 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2736 dispc_mgr_enable_alpha_fixed_zorder(channel,
2737 info->partial_alpha_enabled);
2738 if (dss_has_feature(FEAT_CPR)) {
2739 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2740 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2741 }
2742}
80c39712 2743
fb2cec1f 2744static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2745{
2746 int code;
2747
2748 switch (data_lines) {
2749 case 12:
2750 code = 0;
2751 break;
2752 case 16:
2753 code = 1;
2754 break;
2755 case 18:
2756 code = 2;
2757 break;
2758 case 24:
2759 code = 3;
2760 break;
2761 default:
2762 BUG();
2763 return;
2764 }
2765
efa70b3b 2766 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2767}
2768
fb2cec1f 2769static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2770{
2771 u32 l;
569969d6 2772 int gpout0, gpout1;
80c39712
TV		 2773
2774 switch (mode) {
569969d6
AT		 2775 case DSS_IO_PAD_MODE_RESET:
2776 gpout0 = 0;
2777 gpout1 = 0;
80c39712 2778 break;
569969d6
AT		 2779 case DSS_IO_PAD_MODE_RFBI:
2780 gpout0 = 1;
80c39712
TV		 2781 gpout1 = 0;
2782 break;
569969d6
AT		 2783 case DSS_IO_PAD_MODE_BYPASS:
2784 gpout0 = 1;
80c39712
TV		 2785 gpout1 = 1;
2786 break;
80c39712
TV		 2787 default:
2788 BUG();
2789 return;
2790 }
2791
569969d6
AT		 2792 l = dispc_read_reg(DISPC_CONTROL);
2793 l = FLD_MOD(l, gpout0, 15, 15);
2794 l = FLD_MOD(l, gpout1, 16, 16);
2795 dispc_write_reg(DISPC_CONTROL, l);
2796}
2797
fb2cec1f 2798static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2799{
efa70b3b 2800 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2801}
2802
5034b1fa 2803static void dispc_mgr_set_lcd_config(enum omap_channel channel,
fb2cec1f
TV		 2804 const struct dss_lcd_mgr_config *config)
2805{
2806 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2807
2808 dispc_mgr_enable_stallmode(channel, config->stallmode);
2809 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2810
2811 dispc_mgr_set_clock_div(channel, &config->clock_info);
2812
2813 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2814
2815 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2816
2817 dispc_mgr_set_lcd_type_tft(channel);
2818}
2819
8f366162
AT		 2820static bool _dispc_mgr_size_ok(u16 width, u16 height)
2821{
33b89928
AT		 2822 return width <= dispc.feat->mgr_width_max &&
2823 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2824}
2825
4dc2250d 2826static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp,
80c39712
TV		 2827 int vsw, int vfp, int vbp)
2828{
4dc2250d 2829 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max ||
dcbe765b
CM		 2830 hfp < 1 || hfp > dispc.feat->hp_max ||
2831 hbp < 1 || hbp > dispc.feat->hp_max ||
2832 vsw < 1 || vsw > dispc.feat->sw_max ||
2833 vfp < 0 || vfp > dispc.feat->vp_max ||
2834 vbp < 0 || vbp > dispc.feat->vp_max)
2835 return false;
80c39712
TV		 2836 return true;
2837}
2838
ca5ca69c
AT		 2839static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2840 unsigned long pclk)
2841{
2842 if (dss_mgr_is_lcd(channel))
0cac5b61 2843 return pclk <= dispc.feat->max_lcd_pclk;
ca5ca69c 2844 else
0cac5b61 2845 return pclk <= dispc.feat->max_tv_pclk;
ca5ca69c
AT		 2846}
2847
da11bbbb 2848bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm)
80c39712 2849{
da11bbbb 2850 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive))
eadd33bb 2851 return false;
8f366162 2852
da11bbbb 2853 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock))
eadd33bb 2854 return false;
ca5ca69c
AT		 2855
2856 if (dss_mgr_is_lcd(channel)) {
beb8384d 2857 /* TODO: OMAP4+ supports interlace for LCD outputs */
da11bbbb 2858 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
eadd33bb 2859 return false;
beb8384d 2860
da11bbbb
PU		 2861 if (!_dispc_lcd_timings_ok(vm->hsync_len,
2862 vm->hfront_porch, vm->hback_porch,
2863 vm->vsync_len, vm->vfront_porch,
2864 vm->vback_porch))
eadd33bb 2865 return false;
ca5ca69c 2866 }
8f366162 2867
eadd33bb 2868 return true;
80c39712
TV		 2869}
2870
3b592939 2871static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
da11bbbb 2872 const struct videomode *vm)
80c39712 2873{
655e2941 2874 u32 timing_h, timing_v, l;
ed351881 2875 bool onoff, rf, ipc, vs, hs, de;
80c39712 2876
da11bbbb
PU		 2877 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) |
2878 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) |
2879 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20);
2880 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) |
2881 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) |
2882 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20);
80c39712 2883
64ba4f74
SS		 2884 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2885 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 2886
da11bbbb 2887 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
ed351881 2888 vs = false;
6b44cd27
PU		 2889 else
2890 vs = true;
ed351881 2891
da11bbbb 2892 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
ed351881 2893 hs = false;
6b44cd27
PU		 2894 else
2895 hs = true;
ed351881 2896
da11bbbb 2897 if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
ed351881 2898 de = false;
3fa3ab4a
PU		 2899 else
2900 de = true;
ed351881 2901
da11bbbb 2902 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
655e2941 2903 ipc = false;
f149e17a 2904 else
655e2941 2905 ipc = true;
655e2941 2906
7a16360d
TV		 2907 /* always use the 'rf' setting */
2908 onoff = true;
2909
da11bbbb 2910 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
655e2941 2911 rf = true;
d34afb73
PU		 2912 else
2913 rf = false;
655e2941 2914
d80e02ef
TV		 2915 l = FLD_VAL(onoff, 17, 17) |
2916 FLD_VAL(rf, 16, 16) |
ed351881 2917 FLD_VAL(de, 15, 15) |
d80e02ef 2918 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 2919 FLD_VAL(hs, 13, 13) |
2920 FLD_VAL(vs, 12, 12);
d80e02ef 2921
e5f80917
TV		 2922 /* always set ALIGN bit when available */
2923 if (dispc.feat->supports_sync_align)
2924 l |= (1 << 18);
2925
655e2941 2926 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 2927
2928 if (dispc.syscon_pol) {
2929 const int shifts[] = {
2930 [OMAP_DSS_CHANNEL_LCD] = 0,
2931 [OMAP_DSS_CHANNEL_LCD2] = 1,
2932 [OMAP_DSS_CHANNEL_LCD3] = 2,
2933 };
2934
2935 u32 mask, val;
2936
2937 mask = (1 << 0) | (1 << 3) | (1 << 6);
2938 val = (rf << 0) | (ipc << 3) | (onoff << 6);
2939
2940 mask <<= 16 + shifts[channel];
2941 val <<= 16 + shifts[channel];
2942
2943 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
2944 mask, val);
2945 }
80c39712
TV		 2946}
2947
956d4f93
TV		 2948static int vm_flag_to_int(enum display_flags flags, enum display_flags high,
2949 enum display_flags low)
2950{
2951 if (flags & high)
2952 return 1;
2953 if (flags & low)
2954 return -1;
2955 return 0;
2956}
2957
80c39712 2958/* change name to mode? */
5034b1fa 2959static void dispc_mgr_set_timings(enum omap_channel channel,
da11bbbb 2960 const struct videomode *vm)
80c39712
TV		 2961{
2962 unsigned xtot, ytot;
2963 unsigned long ht, vt;
da11bbbb 2964 struct videomode t = *vm;
80c39712 2965
fb7f3c43 2966 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
80c39712 2967
2aefad49 2968 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2969 BUG();
c6eee968
TV		 2970 return;
2971 }
80c39712 2972
dd88b7a6 2973 if (dss_mgr_is_lcd(channel)) {
3b592939 2974 _dispc_mgr_set_lcd_timings(channel, &t);
80c39712 2975
a85f4a80 2976 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
458540c6 2977 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
80c39712 2978
da11bbbb
PU		 2979 ht = vm->pixelclock / xtot;
2980 vt = vm->pixelclock / xtot / ytot;
c51d921a 2981
da11bbbb 2982 DSSDBG("pck %lu\n", vm->pixelclock);
4dc2250d 2983 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
a85f4a80 2984 t.hsync_len, t.hfront_porch, t.hback_porch,
458540c6 2985 t.vsync_len, t.vfront_porch, t.vback_porch);
655e2941 2986 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
956d4f93
TV		 2987 vm_flag_to_int(t.flags, DISPLAY_FLAGS_VSYNC_HIGH, DISPLAY_FLAGS_VSYNC_LOW),
2988 vm_flag_to_int(t.flags, DISPLAY_FLAGS_HSYNC_HIGH, DISPLAY_FLAGS_HSYNC_LOW),
2989 vm_flag_to_int(t.flags, DISPLAY_FLAGS_PIXDATA_POSEDGE, DISPLAY_FLAGS_PIXDATA_NEGEDGE),
2990 vm_flag_to_int(t.flags, DISPLAY_FLAGS_DE_HIGH, DISPLAY_FLAGS_DE_LOW),
2991 vm_flag_to_int(t.flags, DISPLAY_FLAGS_SYNC_POSEDGE, DISPLAY_FLAGS_SYNC_NEGEDGE));
80c39712 2992
c51d921a 2993 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2994 } else {
53058299 2995 if (t.flags & DISPLAY_FLAGS_INTERLACED)
fb7f3c43 2996 t.vactive /= 2;
3a38ed53
TV		 2997
2998 if (dispc.feat->supports_double_pixel)
531efb38
PU		 2999 REG_FLD_MOD(DISPC_CONTROL,
3000 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK),
3001 19, 17);
c51d921a 3002 }
8f366162 3003
fb7f3c43 3004 dispc_mgr_set_size(channel, t.hactive, t.vactive);
80c39712
TV		 3005}
3006
26d9dd0d 3007static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3008 u16 pck_div)
80c39712
TV		 3009{
3010 BUG_ON(lck_div < 1);
9eaaf207 3011 BUG_ON(pck_div < 1);
80c39712 3012
ce7fa5eb 3013 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3014 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3 3015
0bcfdba6 3016 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
7b3926b3
TV		 3017 channel == OMAP_DSS_CHANNEL_LCD)
3018 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3019}
3020
26d9dd0d 3021static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3022 int *pck_div)
80c39712
TV		 3023{
3024 u32 l;
ce7fa5eb 3025 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3026 *lck_div = FLD_GET(l, 23, 16);
3027 *pck_div = FLD_GET(l, 7, 0);
3028}
3029
65904155 3030static unsigned long dispc_fclk_rate(void)
80c39712 3031{
ef03b401
TV		 3032 unsigned long r;
3033 enum dss_clk_source src;
80c39712 3034
ef03b401
TV		 3035 src = dss_get_dispc_clk_source();
3036
3037 if (src == DSS_CLK_SRC_FCK) {
5aaee69d 3038 r = dss_get_dispc_clk_rate();
ef03b401
TV		 3039 } else {
3040 struct dss_pll *pll;
3041 unsigned clkout_idx;
93550927 3042
ef03b401
TV		 3043 pll = dss_pll_find_by_src(src);
3044 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
93550927 3045
ef03b401 3046 r = pll->cinfo.clkout[clkout_idx];
66534e8e
AT		 3047 }
3048
80c39712
TV		 3049 return r;
3050}
3051
65904155 3052static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712
TV		 3053{
3054 int lcd;
3055 unsigned long r;
01575776 3056 enum dss_clk_source src;
80c39712 3057
01575776
TV		 3058 /* for TV, LCLK rate is the FCLK rate */
3059 if (!dss_mgr_is_lcd(channel))
3060 return dispc_fclk_rate();
80c39712 3061
01575776 3062 src = dss_get_lcd_clk_source(channel);
93550927 3063
01575776
TV		 3064 if (src == DSS_CLK_SRC_FCK) {
3065 r = dss_get_dispc_clk_rate();
3066 } else {
3067 struct dss_pll *pll;
3068 unsigned clkout_idx;
93550927 3069
01575776
TV		 3070 pll = dss_pll_find_by_src(src);
3071 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
80c39712 3072
01575776 3073 r = pll->cinfo.clkout[clkout_idx];
c31cba8a 3074 }
01575776
TV		 3075
3076 lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3077
3078 return r / lcd;
80c39712
TV		 3079}
3080
65904155 3081static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3082{
80c39712 3083 unsigned long r;
80c39712 3084
dd88b7a6 3085 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3086 int pcd;
3087 u32 l;
80c39712 3088
c3dc6a7a 3089 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3090
c3dc6a7a 3091 pcd = FLD_GET(l, 7, 0);
80c39712 3092
c3dc6a7a
AT		 3093 r = dispc_mgr_lclk_rate(channel);
3094
3095 return r / pcd;
3096 } else {
5391e87d 3097 return dispc.tv_pclk_rate;
c3dc6a7a 3098 }
80c39712
TV		 3099}
3100
5391e87d
TV		 3101void dispc_set_tv_pclk(unsigned long pclk)
3102{
3103 dispc.tv_pclk_rate = pclk;
3104}
3105
65904155 3106static unsigned long dispc_core_clk_rate(void)
8b53d991 3107{
7b3926b3 3108 return dispc.core_clk_rate;
8b53d991
CM		 3109}
3110
864050c7 3111static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane)
3e8a6ff2 3112{
251886d8
TV		 3113 enum omap_channel channel;
3114
3115 if (plane == OMAP_DSS_WB)
3116 return 0;
3117
3118 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3119
3120 return dispc_mgr_pclk_rate(channel);
3121}
3122
864050c7 3123static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane)
3e8a6ff2 3124{
251886d8
TV		 3125 enum omap_channel channel;
3126
3127 if (plane == OMAP_DSS_WB)
3128 return 0;
3129
3130 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3131
c31cba8a 3132 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3133}
c31cba8a 3134
6f1891fc 3135static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3136{
3137 int lcd, pcd;
dc0352d1 3138 enum dss_clk_source lcd_clk_src;
6f1891fc
CM		 3139
3140 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3141
3142 lcd_clk_src = dss_get_lcd_clk_source(channel);
3143
557a1544 3144 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
407bd564 3145 dss_get_clk_source_name(lcd_clk_src));
6f1891fc
CM		 3146
3147 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3148
3149 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3150 dispc_mgr_lclk_rate(channel), lcd);
3151 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3152 dispc_mgr_pclk_rate(channel), pcd);
3153}
3154
3155void dispc_dump_clocks(struct seq_file *s)
3156{
3157 int lcd;
0cf35df3 3158 u32 l;
dc0352d1 3159 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3160
4fbafaf3
TV		 3161 if (dispc_runtime_get())
3162 return;
80c39712 3163
80c39712
TV		 3164 seq_printf(s, "- DISPC -\n");
3165
557a1544 3166 seq_printf(s, "dispc fclk source = %s\n",
407bd564 3167 dss_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3168
3169 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3170
0cf35df3
MR		 3171 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3172 seq_printf(s, "- DISPC-CORE-CLK -\n");
3173 l = dispc_read_reg(DISPC_DIVISOR);
3174 lcd = FLD_GET(l, 23, 16);
3175
3176 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3177 (dispc_fclk_rate()/lcd), lcd);
3178 }
2a205f34 3179
6f1891fc 3180 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3181
6f1891fc
CM		 3182 if (dss_has_feature(FEAT_MGR_LCD2))
3183 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3184 if (dss_has_feature(FEAT_MGR_LCD3))
3185 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3186
3187 dispc_runtime_put();
80c39712
TV		 3188}
3189
e40402cf 3190static void dispc_dump_regs(struct seq_file *s)
80c39712 3191{
4dd2da15
AT		 3192 int i, j;
3193 const char *mgr_names[] = {
3194 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3195 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3196 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3197 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3198 };
3199 const char *ovl_names[] = {
3200 [OMAP_DSS_GFX] = "GFX",
3201 [OMAP_DSS_VIDEO1] = "VID1",
3202 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3203 [OMAP_DSS_VIDEO3] = "VID3",
06c525fe 3204 [OMAP_DSS_WB] = "WB",
4dd2da15
AT		 3205 };
3206 const char **p_names;
3207
9b372c2d 3208#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3209
4fbafaf3
TV		 3210 if (dispc_runtime_get())
3211 return;
80c39712 3212
5010be80 3213 /* DISPC common registers */
80c39712
TV		 3214 DUMPREG(DISPC_REVISION);
3215 DUMPREG(DISPC_SYSCONFIG);
3216 DUMPREG(DISPC_SYSSTATUS);
3217 DUMPREG(DISPC_IRQSTATUS);
3218 DUMPREG(DISPC_IRQENABLE);
3219 DUMPREG(DISPC_CONTROL);
3220 DUMPREG(DISPC_CONFIG);
3221 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3222 DUMPREG(DISPC_LINE_STATUS);
3223 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3224 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3225 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3226 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3227 if (dss_has_feature(FEAT_MGR_LCD2)) {
3228 DUMPREG(DISPC_CONTROL2);
3229 DUMPREG(DISPC_CONFIG2);
5010be80 3230 }
6f1891fc
CM		 3231 if (dss_has_feature(FEAT_MGR_LCD3)) {
3232 DUMPREG(DISPC_CONTROL3);
3233 DUMPREG(DISPC_CONFIG3);
3234 }
29fceeeb
TV		 3235 if (dss_has_feature(FEAT_MFLAG))
3236 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3237
3238#undef DUMPREG
3239
3240#define DISPC_REG(i, name) name(i)
4dd2da15 3241#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3242 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3243 dispc_read_reg(DISPC_REG(i, r)))
3244
4dd2da15 3245 p_names = mgr_names;
5010be80 3246
4dd2da15
AT		 3247 /* DISPC channel specific registers */
3248 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3249 DUMPREG(i, DISPC_DEFAULT_COLOR);
3250 DUMPREG(i, DISPC_TRANS_COLOR);
3251 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3252
4dd2da15
AT		 3253 if (i == OMAP_DSS_CHANNEL_DIGIT)
3254 continue;
5010be80 3255
4dd2da15
AT		 3256 DUMPREG(i, DISPC_TIMING_H);
3257 DUMPREG(i, DISPC_TIMING_V);
3258 DUMPREG(i, DISPC_POL_FREQ);
3259 DUMPREG(i, DISPC_DIVISORo);
5010be80 3260
4dd2da15
AT		 3261 DUMPREG(i, DISPC_DATA_CYCLE1);
3262 DUMPREG(i, DISPC_DATA_CYCLE2);
3263 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3264
332e9d70 3265 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3266 DUMPREG(i, DISPC_CPR_COEF_R);
3267 DUMPREG(i, DISPC_CPR_COEF_G);
3268 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3269 }
2a205f34 3270 }
80c39712 3271
4dd2da15
AT		 3272 p_names = ovl_names;
3273
3274 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3275 DUMPREG(i, DISPC_OVL_BA0);
3276 DUMPREG(i, DISPC_OVL_BA1);
3277 DUMPREG(i, DISPC_OVL_POSITION);
3278 DUMPREG(i, DISPC_OVL_SIZE);
3279 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3280 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3281 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3282 DUMPREG(i, DISPC_OVL_ROW_INC);
3283 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3284
4dd2da15
AT		 3285 if (dss_has_feature(FEAT_PRELOAD))
3286 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3287 if (dss_has_feature(FEAT_MFLAG))
3288 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3289
3290 if (i == OMAP_DSS_GFX) {
3291 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3292 DUMPREG(i, DISPC_OVL_TABLE_BA);
3293 continue;
3294 }
3295
3296 DUMPREG(i, DISPC_OVL_FIR);
3297 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3298 DUMPREG(i, DISPC_OVL_ACCU0);
3299 DUMPREG(i, DISPC_OVL_ACCU1);
3300 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3301 DUMPREG(i, DISPC_OVL_BA0_UV);
3302 DUMPREG(i, DISPC_OVL_BA1_UV);
3303 DUMPREG(i, DISPC_OVL_FIR2);
3304 DUMPREG(i, DISPC_OVL_ACCU2_0);
3305 DUMPREG(i, DISPC_OVL_ACCU2_1);
3306 }
3307 if (dss_has_feature(FEAT_ATTR2))
3308 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3309 }
5010be80 3310
20efbc35 3311 if (dispc.feat->has_writeback) {
06c525fe
TV		 3312 i = OMAP_DSS_WB;
3313 DUMPREG(i, DISPC_OVL_BA0);
3314 DUMPREG(i, DISPC_OVL_BA1);
3315 DUMPREG(i, DISPC_OVL_SIZE);
3316 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3317 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3318 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3319 DUMPREG(i, DISPC_OVL_ROW_INC);
3320 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3321
3322 if (dss_has_feature(FEAT_MFLAG))
3323 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3324
3325 DUMPREG(i, DISPC_OVL_FIR);
3326 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3327 DUMPREG(i, DISPC_OVL_ACCU0);
3328 DUMPREG(i, DISPC_OVL_ACCU1);
3329 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3330 DUMPREG(i, DISPC_OVL_BA0_UV);
3331 DUMPREG(i, DISPC_OVL_BA1_UV);
3332 DUMPREG(i, DISPC_OVL_FIR2);
3333 DUMPREG(i, DISPC_OVL_ACCU2_0);
3334 DUMPREG(i, DISPC_OVL_ACCU2_1);
3335 }
3336 if (dss_has_feature(FEAT_ATTR2))
3337 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3338 }
3339
5010be80
AT		 3340#undef DISPC_REG
3341#undef DUMPREG
3342
3343#define DISPC_REG(plane, name, i) name(plane, i)
3344#define DUMPREG(plane, name, i) \
4dd2da15 3345 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3346 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3347 dispc_read_reg(DISPC_REG(plane, name, i)))
3348
4dd2da15 3349 /* Video pipeline coefficient registers */
332e9d70 3350
4dd2da15
AT		 3351 /* start from OMAP_DSS_VIDEO1 */
3352 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3353 for (j = 0; j < 8; j++)
3354 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3355
4dd2da15
AT		 3356 for (j = 0; j < 8; j++)
3357 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3358
4dd2da15
AT		 3359 for (j = 0; j < 5; j++)
3360 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3361
4dd2da15
AT		 3362 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3363 for (j = 0; j < 8; j++)
3364 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3365 }
3366
3367 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3368 for (j = 0; j < 8; j++)
3369 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3370
3371 for (j = 0; j < 8; j++)
3372 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3373
3374 for (j = 0; j < 8; j++)
3375 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3376 }
332e9d70 3377 }
80c39712 3378
4fbafaf3 3379 dispc_runtime_put();
5010be80
AT		 3380
3381#undef DISPC_REG
80c39712
TV		 3382#undef DUMPREG
3383}
3384
80c39712
TV		 3385/* calculate clock rates using dividers in cinfo */
3386int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3387 struct dispc_clock_info *cinfo)
3388{
80c39712
TV		 3389 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3390 return -EINVAL;
9eaaf207 3391 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3392 return -EINVAL;
80c39712 3393
80c39712
TV		 3394 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3395 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3396
80c39712
TV		 3397 return 0;
3398}
80c39712 3399
7c284e6e
TV		 3400bool dispc_div_calc(unsigned long dispc,
3401 unsigned long pck_min, unsigned long pck_max,
3402 dispc_div_calc_func func, void *data)
3403{
3404 int lckd, lckd_start, lckd_stop;
3405 int pckd, pckd_start, pckd_stop;
3406 unsigned long pck, lck;
3407 unsigned long lck_max;
3408 unsigned long pckd_hw_min, pckd_hw_max;
3409 unsigned min_fck_per_pck;
3410 unsigned long fck;
80c39712 3411
7c284e6e
TV		 3412#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3413 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3414#else
3415 min_fck_per_pck = 0;
3416#endif
80c39712 3417
7c284e6e
TV		 3418 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3419 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3420
7c284e6e 3421 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3422
7c284e6e
TV		 3423 pck_min = pck_min ? pck_min : 1;
3424 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3425
7c284e6e
TV		 3426 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3427 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3428
7c284e6e
TV		 3429 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3430 lck = dispc / lckd;
80c39712 3431
7c284e6e
TV		 3432 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3433 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3434
7c284e6e
TV		 3435 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3436 pck = lck / pckd;
80c39712 3437
7c284e6e
TV		 3438 /*
3439 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3440 * clock, which means we're configuring DISPC fclk here
3441 * also. Thus we need to use the calculated lck. For
3442 * OMAP4+ the DISPC fclk is a separate clock.
3443 */
3444 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3445 fck = dispc_core_clk_rate();
3446 else
3447 fck = lck;
3448
3449 if (fck < pck * min_fck_per_pck)
3450 continue;
3451
3452 if (func(lckd, pckd, lck, pck, data))
3453 return true;
3454 }
3455 }
3456
3457 return false;
80c39712
TV		 3458}
3459
f0d08f89 3460void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3461 const struct dispc_clock_info *cinfo)
80c39712
TV		 3462{
3463 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3464 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3465
26d9dd0d 3466 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3467}
3468
26d9dd0d 3469int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3470 struct dispc_clock_info *cinfo)
80c39712
TV		 3471{
3472 unsigned long fck;
3473
3474 fck = dispc_fclk_rate();
3475
ce7fa5eb
MR		 3476 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3477 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3478
3479 cinfo->lck = fck / cinfo->lck_div;
3480 cinfo->pck = cinfo->lck / cinfo->pck_div;
3481
3482 return 0;
3483}
3484
5034b1fa 3485static u32 dispc_read_irqstatus(void)
4e0397cf
TV		 3486{
3487 return dispc_read_reg(DISPC_IRQSTATUS);
3488}
3489
5034b1fa 3490static void dispc_clear_irqstatus(u32 mask)
4e0397cf
TV		 3491{
3492 dispc_write_reg(DISPC_IRQSTATUS, mask);
3493}
3494
5034b1fa 3495static void dispc_write_irqenable(u32 mask)
4e0397cf
TV		 3496{
3497 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3498
3499 /* clear the irqstatus for newly enabled irqs */
3500 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3501
3502 dispc_write_reg(DISPC_IRQENABLE, mask);
2e953d83
TV		 3503
3504 /* flush posted write */
3505 dispc_read_reg(DISPC_IRQENABLE);
4e0397cf
TV		 3506}
3507
80c39712
TV		 3508void dispc_enable_sidle(void)
3509{
3510 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3511}
3512
3513void dispc_disable_sidle(void)
3514{
3515 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3516}
3517
5034b1fa 3518static u32 dispc_mgr_gamma_size(enum omap_channel channel)
acc3a231
JS		 3519{
3520 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3521
3522 if (!dispc.feat->has_gamma_table)
3523 return 0;
3524
3525 return gdesc->len;
3526}
acc3a231
JS		 3527
3528static void dispc_mgr_write_gamma_table(enum omap_channel channel)
3529{
3530 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3531 u32 *table = dispc.gamma_table[channel];
3532 unsigned int i;
3533
3534 DSSDBG("%s: channel %d\n", __func__, channel);
3535
3536 for (i = 0; i < gdesc->len; ++i) {
3537 u32 v = table[i];
3538
3539 if (gdesc->has_index)
3540 v |= i << 24;
3541 else if (i == 0)
3542 v |= 1 << 31;
3543
3544 dispc_write_reg(gdesc->reg, v);
3545 }
3546}
3547
3548static void dispc_restore_gamma_tables(void)
3549{
3550 DSSDBG("%s()\n", __func__);
3551
3552 if (!dispc.feat->has_gamma_table)
3553 return;
3554
3555 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD);
3556
3557 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT);
3558
3559 if (dss_has_feature(FEAT_MGR_LCD2))
3560 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2);
3561
3562 if (dss_has_feature(FEAT_MGR_LCD3))
3563 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3);
3564}
3565
3566static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3567 { .red = 0, .green = 0, .blue = 0, },
3568 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3569};
3570
5034b1fa 3571static void dispc_mgr_set_gamma(enum omap_channel channel,
acc3a231
JS		 3572 const struct drm_color_lut *lut,
3573 unsigned int length)
3574{
3575 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3576 u32 *table = dispc.gamma_table[channel];
3577 uint i;
3578
3579 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3580 channel, length, gdesc->len);
3581
3582 if (!dispc.feat->has_gamma_table)
3583 return;
3584
3585 if (lut == NULL || length < 2) {
3586 lut = dispc_mgr_gamma_default_lut;
3587 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut);
3588 }
3589
3590 for (i = 0; i < length - 1; ++i) {
3591 uint first = i * (gdesc->len - 1) / (length - 1);
3592 uint last = (i + 1) * (gdesc->len - 1) / (length - 1);
3593 uint w = last - first;
3594 u16 r, g, b;
3595 uint j;
3596
3597 if (w == 0)
3598 continue;
3599
3600 for (j = 0; j <= w; j++) {
3601 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3602 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3603 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w;
3604
3605 r >>= 16 - gdesc->bits;
3606 g >>= 16 - gdesc->bits;
3607 b >>= 16 - gdesc->bits;
3608
3609 table[first + j] = (r << (gdesc->bits * 2)) |
3610 (g << gdesc->bits) | b;
3611 }
3612 }
3613
3614 if (dispc.is_enabled)
3615 dispc_mgr_write_gamma_table(channel);
3616}
acc3a231
JS		 3617
3618static int dispc_init_gamma_tables(void)
3619{
3620 int channel;
3621
3622 if (!dispc.feat->has_gamma_table)
3623 return 0;
3624
3625 for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) {
3626 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3627 u32 *gt;
3628
3629 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3630 !dss_has_feature(FEAT_MGR_LCD2))
3631 continue;
3632
3633 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3634 !dss_has_feature(FEAT_MGR_LCD3))
3635 continue;
3636
3637 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len,
3638 sizeof(u32), GFP_KERNEL);
3639 if (!gt)
3640 return -ENOMEM;
3641
3642 dispc.gamma_table[channel] = gt;
3643
3644 dispc_mgr_set_gamma(channel, NULL, 0);
3645 }
3646 return 0;
3647}
3648
80c39712
TV		 3649static void _omap_dispc_initial_config(void)
3650{
3651 u32 l;
3652
0cf35df3
MR		 3653 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3654 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3655 l = dispc_read_reg(DISPC_DIVISOR);
3656 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3657 l = FLD_MOD(l, 1, 0, 0);
3658 l = FLD_MOD(l, 1, 23, 16);
3659 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3660
3661 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3662 }
3663
acc3a231
JS		 3664 /* Use gamma table mode, instead of palette mode */
3665 if (dispc.feat->has_gamma_table)
3666 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
3667
3668 /* For older DSS versions (FEAT_FUNCGATED) this enables
3669 * func-clock auto-gating. For newer versions
3670 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables.
3671 */
3672 if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table)
6ced40bf 3673 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3674
6e5264b0 3675 dispc_setup_color_conv_coef();
80c39712
TV		 3676
3677 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3678
42a6961c 3679 dispc_init_fifos();
5ed8cf5b
TV		 3680
3681 dispc_configure_burst_sizes();
54128701
AT		 3682
3683 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3684
3685 if (dispc.feat->mstandby_workaround)
3686 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
c64aa3a6
TV		 3687
3688 if (dss_has_feature(FEAT_MFLAG))
3689 dispc_init_mflag();
80c39712
TV		 3690}
3691
ede92695 3692static const struct dispc_features omap24xx_dispc_feats = {
dcbe765b
CM		 3693 .sw_start = 5,
3694 .fp_start = 15,
3695 .bp_start = 27,
3696 .sw_max = 64,
3697 .vp_max = 255,
3698 .hp_max = 256,
33b89928
AT		 3699 .mgr_width_start = 10,
3700 .mgr_height_start = 26,
3701 .mgr_width_max = 2048,
3702 .mgr_height_max = 2048,
ca5ca69c 3703 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3704 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3705 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3706 .num_fifos = 3,
cffa947d 3707 .no_framedone_tv = true,
8bc65552 3708 .set_max_preload = false,
f2aee319 3709 .last_pixel_inc_missing = true,
dcbe765b
CM		 3710};
3711
ede92695 3712static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
dcbe765b
CM		 3713 .sw_start = 5,
3714 .fp_start = 15,
3715 .bp_start = 27,
3716 .sw_max = 64,
3717 .vp_max = 255,
3718 .hp_max = 256,
33b89928
AT		 3719 .mgr_width_start = 10,
3720 .mgr_height_start = 26,
3721 .mgr_width_max = 2048,
3722 .mgr_height_max = 2048,
ca5ca69c
AT		 3723 .max_lcd_pclk = 173000000,
3724 .max_tv_pclk = 59000000,
dcbe765b
CM		 3725 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3726 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3727 .num_fifos = 3,
cffa947d 3728 .no_framedone_tv = true,
8bc65552 3729 .set_max_preload = false,
f2aee319 3730 .last_pixel_inc_missing = true,
dcbe765b
CM		 3731};
3732
ede92695 3733static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
dcbe765b
CM		 3734 .sw_start = 7,
3735 .fp_start = 19,
3736 .bp_start = 31,
3737 .sw_max = 256,
3738 .vp_max = 4095,
3739 .hp_max = 4096,
33b89928
AT		 3740 .mgr_width_start = 10,
3741 .mgr_height_start = 26,
3742 .mgr_width_max = 2048,
3743 .mgr_height_max = 2048,
ca5ca69c
AT		 3744 .max_lcd_pclk = 173000000,
3745 .max_tv_pclk = 59000000,
dcbe765b
CM		 3746 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3747 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3748 .num_fifos = 3,
cffa947d 3749 .no_framedone_tv = true,
8bc65552 3750 .set_max_preload = false,
f2aee319 3751 .last_pixel_inc_missing = true,
dcbe765b
CM		 3752};
3753
ede92695 3754static const struct dispc_features omap44xx_dispc_feats = {
dcbe765b
CM		 3755 .sw_start = 7,
3756 .fp_start = 19,
3757 .bp_start = 31,
3758 .sw_max = 256,
3759 .vp_max = 4095,
3760 .hp_max = 4096,
33b89928
AT		 3761 .mgr_width_start = 10,
3762 .mgr_height_start = 26,
3763 .mgr_width_max = 2048,
3764 .mgr_height_max = 2048,
ca5ca69c
AT		 3765 .max_lcd_pclk = 170000000,
3766 .max_tv_pclk = 185625000,
dcbe765b
CM		 3767 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3768 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3769 .num_fifos = 5,
66a0f9e4 3770 .gfx_fifo_workaround = true,
8bc65552 3771 .set_max_preload = true,
e5f80917 3772 .supports_sync_align = true,
20efbc35 3773 .has_writeback = true,
3a38ed53 3774 .supports_double_pixel = true,
b7536d67 3775 .reverse_ilace_field_order = true,
acc3a231 3776 .has_gamma_table = true,
fbff010b 3777 .has_gamma_i734_bug = true,
dcbe765b
CM		 3778};
3779
ede92695 3780static const struct dispc_features omap54xx_dispc_feats = {
264236f8
AT		 3781 .sw_start = 7,
3782 .fp_start = 19,
3783 .bp_start = 31,
3784 .sw_max = 256,
3785 .vp_max = 4095,
3786 .hp_max = 4096,
3787 .mgr_width_start = 11,
3788 .mgr_height_start = 27,
3789 .mgr_width_max = 4096,
3790 .mgr_height_max = 4096,
ca5ca69c
AT		 3791 .max_lcd_pclk = 170000000,
3792 .max_tv_pclk = 186000000,
264236f8
AT		 3793 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3794 .calc_core_clk = calc_core_clk_44xx,
3795 .num_fifos = 5,
3796 .gfx_fifo_workaround = true,
d0df9a2c 3797 .mstandby_workaround = true,
8bc65552 3798 .set_max_preload = true,
e5f80917 3799 .supports_sync_align = true,
20efbc35 3800 .has_writeback = true,
3a38ed53 3801 .supports_double_pixel = true,
b7536d67 3802 .reverse_ilace_field_order = true,
acc3a231 3803 .has_gamma_table = true,
fbff010b 3804 .has_gamma_i734_bug = true,
264236f8
AT		 3805};
3806
ede92695 3807static int dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3808{
3809 const struct dispc_features *src;
3810 struct dispc_features *dst;
3811
84b47623 3812 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3813 if (!dst) {
84b47623 3814 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3815 return -ENOMEM;
3816 }
3817
b2c7d54f 3818 switch (omapdss_get_version()) {
84b47623 3819 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3820 src = &omap24xx_dispc_feats;
84b47623
TV		 3821 break;
3822
3823 case OMAPDSS_VER_OMAP34xx_ES1:
3824 src = &omap34xx_rev1_0_dispc_feats;
3825 break;
3826
3827 case OMAPDSS_VER_OMAP34xx_ES3:
3828 case OMAPDSS_VER_OMAP3630:
3829 case OMAPDSS_VER_AM35xx:
d6279d4a 3830 case OMAPDSS_VER_AM43xx:
84b47623
TV		 3831 src = &omap34xx_rev3_0_dispc_feats;
3832 break;
3833
3834 case OMAPDSS_VER_OMAP4430_ES1:
3835 case OMAPDSS_VER_OMAP4430_ES2:
3836 case OMAPDSS_VER_OMAP4:
dcbe765b 3837 src = &omap44xx_dispc_feats;
84b47623
TV		 3838 break;
3839
3840 case OMAPDSS_VER_OMAP5:
93550927 3841 case OMAPDSS_VER_DRA7xx:
264236f8 3842 src = &omap54xx_dispc_feats;
84b47623
TV		 3843 break;
3844
3845 default:
dcbe765b
CM		 3846 return -ENODEV;
3847 }
3848
3849 memcpy(dst, src, sizeof(*dst));
3850 dispc.feat = dst;
3851
3852 return 0;
3853}
3854
0925afc9
TV		 3855static irqreturn_t dispc_irq_handler(int irq, void *arg)
3856{
3857 if (!dispc.is_enabled)
3858 return IRQ_NONE;
3859
3860 return dispc.user_handler(irq, dispc.user_data);
3861}
3862
5034b1fa 3863static int dispc_request_irq(irq_handler_t handler, void *dev_id)
96e2e637 3864{
0925afc9
TV		 3865 int r;
3866
3867 if (dispc.user_handler != NULL)
3868 return -EBUSY;
3869
3870 dispc.user_handler = handler;
3871 dispc.user_data = dev_id;
3872
3873 /* ensure the dispc_irq_handler sees the values above */
3874 smp_wmb();
3875
3876 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3877 IRQF_SHARED, "OMAP DISPC", &dispc);
3878 if (r) {
3879 dispc.user_handler = NULL;
3880 dispc.user_data = NULL;
3881 }
3882
3883 return r;
96e2e637
TV		 3884}
3885
5034b1fa 3886static void dispc_free_irq(void *dev_id)
96e2e637 3887{
0925afc9
TV		 3888 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3889
3890 dispc.user_handler = NULL;
3891 dispc.user_data = NULL;
96e2e637
TV		 3892}
3893
fbff010b
JS		 3894/*
3895 * Workaround for errata i734 in DSS dispc
3896 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
3897 *
3898 * For gamma tables to work on LCD1 the GFX plane has to be used at
3899 * least once after DSS HW has come out of reset. The workaround
3900 * sets up a minimal LCD setup with GFX plane and waits for one
3901 * vertical sync irq before disabling the setup and continuing with
3902 * the context restore. The physical outputs are gated during the
3903 * operation. This workaround requires that gamma table's LOADMODE
3904 * is set to 0x2 in DISPC_CONTROL1 register.
3905 *
3906 * For details see:
3907 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata
3908 * Literature Number: SWPZ037E
3909 * Or some other relevant errata document for the DSS IP version.
3910 */
3911
3912static const struct dispc_errata_i734_data {
da11bbbb 3913 struct videomode vm;
fbff010b
JS		 3914 struct omap_overlay_info ovli;
3915 struct omap_overlay_manager_info mgri;
3916 struct dss_lcd_mgr_config lcd_conf;
3917} i734 = {
da11bbbb 3918 .vm = {
fb7f3c43 3919 .hactive = 8, .vactive = 1,
fbff010b 3920 .pixelclock = 16000000,
a85f4a80 3921 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
458540c6 3922 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
6b44cd27 3923
3fa3ab4a 3924 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
d34afb73
PU		 3925 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
3926 DISPLAY_FLAGS_PIXDATA_POSEDGE,
fbff010b
JS		 3927 },
3928 .ovli = {
3929 .screen_width = 1,
3930 .width = 1, .height = 1,
41aff42a 3931 .fourcc = DRM_FORMAT_XRGB8888,
0bd97c42 3932 .rotation = DRM_MODE_ROTATE_0,
517a8a95 3933 .rotation_type = OMAP_DSS_ROT_NONE,
fbff010b
JS		 3934 .pos_x = 0, .pos_y = 0,
3935 .out_width = 0, .out_height = 0,
3936 .global_alpha = 0xff,
3937 .pre_mult_alpha = 0,
3938 .zorder = 0,
3939 },
3940 .mgri = {
3941 .default_color = 0,
3942 .trans_enabled = false,
3943 .partial_alpha_enabled = false,
3944 .cpr_enable = false,
3945 },
3946 .lcd_conf = {
3947 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS,
3948 .stallmode = false,
3949 .fifohandcheck = false,
3950 .clock_info = {
3951 .lck_div = 1,
3952 .pck_div = 2,
3953 },
3954 .video_port_width = 24,
3955 .lcden_sig_polarity = 0,
3956 },
3957};
3958
3959static struct i734_buf {
3960 size_t size;
3961 dma_addr_t paddr;
3962 void *vaddr;
3963} i734_buf;
3964
3965static int dispc_errata_i734_wa_init(void)
3966{
3967 if (!dispc.feat->has_gamma_i734_bug)
3968 return 0;
3969
3970 i734_buf.size = i734.ovli.width * i734.ovli.height *
41aff42a 3971 color_mode_to_bpp(i734.ovli.fourcc) / 8;
fbff010b
JS		 3972
3973 i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size,
3974 &i734_buf.paddr, GFP_KERNEL);
3975 if (!i734_buf.vaddr) {
3976 dev_err(&dispc.pdev->dev, "%s: dma_alloc_writecombine failed",
3977 __func__);
3978 return -ENOMEM;
3979 }
3980
3981 return 0;
3982}
3983
3984static void dispc_errata_i734_wa_fini(void)
3985{
3986 if (!dispc.feat->has_gamma_i734_bug)
3987 return;
3988
3989 dma_free_writecombine(&dispc.pdev->dev, i734_buf.size, i734_buf.vaddr,
3990 i734_buf.paddr);
3991}
3992
3993static void dispc_errata_i734_wa(void)
3994{
3995 u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD);
3996 struct omap_overlay_info ovli;
3997 struct dss_lcd_mgr_config lcd_conf;
3998 u32 gatestate;
3999 unsigned int count;
4000
4001 if (!dispc.feat->has_gamma_i734_bug)
4002 return;
4003
4004 gatestate = REG_GET(DISPC_CONFIG, 8, 4);
4005
4006 ovli = i734.ovli;
4007 ovli.paddr = i734_buf.paddr;
4008 lcd_conf = i734.lcd_conf;
4009
4010 /* Gate all LCD1 outputs */
4011 REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4);
4012
4013 /* Setup and enable GFX plane */
49a3057a
TV		 4014 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false,
4015 OMAP_DSS_CHANNEL_LCD);
fbff010b
JS		 4016 dispc_ovl_enable(OMAP_DSS_GFX, true);
4017
4018 /* Set up and enable display manager for LCD1 */
4019 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD, &i734.mgri);
4020 dispc_calc_clock_rates(dss_get_dispc_clk_rate(),
4021 &lcd_conf.clock_info);
4022 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf);
da11bbbb 4023 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm);
fbff010b
JS		 4024
4025 dispc_clear_irqstatus(framedone_irq);
4026
4027 /* Enable and shut the channel to produce just one frame */
4028 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, true);
4029 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, false);
4030
4031 /* Busy wait for framedone. We can't fiddle with irq handlers
4032 * in PM resume. Typically the loop runs less than 5 times and
4033 * waits less than a micro second.
4034 */
4035 count = 0;
4036 while (!(dispc_read_irqstatus() & framedone_irq)) {
4037 if (count++ > 10000) {
4038 dev_err(&dispc.pdev->dev, "%s: framedone timeout\n",
4039 __func__);
4040 break;
4041 }
4042 }
4043 dispc_ovl_enable(OMAP_DSS_GFX, false);
4044
4045 /* Clear all irq bits before continuing */
4046 dispc_clear_irqstatus(0xffffffff);
4047
4048 /* Restore the original state to LCD1 output gates */
4049 REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4);
4050}
4051
a1a37647
TV		 4052static const struct dispc_ops dispc_ops = {
4053 .read_irqstatus = dispc_read_irqstatus,
4054 .clear_irqstatus = dispc_clear_irqstatus,
a1a37647
TV		 4055 .write_irqenable = dispc_write_irqenable,
4056
4057 .request_irq = dispc_request_irq,
4058 .free_irq = dispc_free_irq,
4059
4060 .runtime_get = dispc_runtime_get,
4061 .runtime_put = dispc_runtime_put,
4062
4063 .get_num_ovls = dispc_get_num_ovls,
4064 .get_num_mgrs = dispc_get_num_mgrs,
4065
4066 .mgr_enable = dispc_mgr_enable,
4067 .mgr_is_enabled = dispc_mgr_is_enabled,
4068 .mgr_get_vsync_irq = dispc_mgr_get_vsync_irq,
4069 .mgr_get_framedone_irq = dispc_mgr_get_framedone_irq,
4070 .mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq,
4071 .mgr_go_busy = dispc_mgr_go_busy,
4072 .mgr_go = dispc_mgr_go,
4073 .mgr_set_lcd_config = dispc_mgr_set_lcd_config,
4074 .mgr_set_timings = dispc_mgr_set_timings,
4075 .mgr_setup = dispc_mgr_setup,
4076 .mgr_get_supported_outputs = dispc_mgr_get_supported_outputs,
4077 .mgr_gamma_size = dispc_mgr_gamma_size,
4078 .mgr_set_gamma = dispc_mgr_set_gamma,
4079
4080 .ovl_enable = dispc_ovl_enable,
a1a37647
TV		 4081 .ovl_setup = dispc_ovl_setup,
4082 .ovl_get_color_modes = dispc_ovl_get_color_modes,
4083};
4084
060b6d9c 4085/* DISPC HW IP initialisation */
736e60dd 4086static int dispc_bind(struct device *dev, struct device *master, void *data)
060b6d9c 4087{
736e60dd 4088 struct platform_device *pdev = to_platform_device(dev);
060b6d9c 4089 u32 rev;
affe360d 4090 int r = 0;
ea9da36a 4091 struct resource *dispc_mem;
0006fd63 4092 struct device_node *np = pdev->dev.of_node;
ea9da36a 4093
060b6d9c
SG		 4094 dispc.pdev = pdev;
4095
d49cd155
TV		 4096 spin_lock_init(&dispc.control_lock);
4097
84b47623 4098 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4099 if (r)
4100 return r;
4101
fbff010b
JS		 4102 r = dispc_errata_i734_wa_init();
4103 if (r)
4104 return r;
4105
ea9da36a 4106 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
b22622f0
LP		 4107 dispc.base = devm_ioremap_resource(&pdev->dev, dispc_mem);
4108 if (IS_ERR(dispc.base))
4109 return PTR_ERR(dispc.base);
cd3b3449 4110
affe360d
AT		 4111 dispc.irq = platform_get_irq(dispc.pdev, 0);
4112 if (dispc.irq < 0) {
4113 DSSERR("platform_get_irq failed\n");
cd3b3449 4114 return -ENODEV;
affe360d
AT		 4115 }
4116
0006fd63
TV		 4117 if (np && of_property_read_bool(np, "syscon-pol")) {
4118 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4119 if (IS_ERR(dispc.syscon_pol)) {
4120 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4121 return PTR_ERR(dispc.syscon_pol);
4122 }
4123
4124 if (of_property_read_u32_index(np, "syscon-pol", 1,
4125 &dispc.syscon_pol_offset)) {
4126 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4127 return -EINVAL;
4128 }
4129 }
4130
acc3a231
JS		 4131 r = dispc_init_gamma_tables();
4132 if (r)
4133 return r;
4134
4fbafaf3
TV		 4135 pm_runtime_enable(&pdev->dev);
4136
4137 r = dispc_runtime_get();
4138 if (r)
4139 goto err_runtime_get;
060b6d9c
SG		 4140
4141 _omap_dispc_initial_config();
4142
060b6d9c 4143 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4144 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4145 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4146
4fbafaf3 4147 dispc_runtime_put();
060b6d9c 4148
a1a37647
TV		 4149 dispc_set_ops(&dispc_ops);
4150
e40402cf
TV		 4151 dss_debugfs_create_file("dispc", dispc_dump_regs);
4152
060b6d9c 4153 return 0;
4fbafaf3
TV		 4154
4155err_runtime_get:
4156 pm_runtime_disable(&pdev->dev);
affe360d 4157 return r;
060b6d9c
SG		 4158}
4159
736e60dd
TV		 4160static void dispc_unbind(struct device *dev, struct device *master,
4161 void *data)
060b6d9c 4162{
a1a37647
TV		 4163 dispc_set_ops(NULL);
4164
736e60dd 4165 pm_runtime_disable(dev);
fbff010b
JS		 4166
4167 dispc_errata_i734_wa_fini();
736e60dd
TV		 4168}
4169
4170static const struct component_ops dispc_component_ops = {
4171 .bind = dispc_bind,
4172 .unbind = dispc_unbind,
4173};
04b1fc02 4174
736e60dd
TV		 4175static int dispc_probe(struct platform_device *pdev)
4176{
4177 return component_add(&pdev->dev, &dispc_component_ops);
4178}
4179
4180static int dispc_remove(struct platform_device *pdev)
4181{
4182 component_del(&pdev->dev, &dispc_component_ops);
060b6d9c
SG		 4183 return 0;
4184}
4185
4fbafaf3
TV		 4186static int dispc_runtime_suspend(struct device *dev)
4187{
0925afc9
TV		 4188 dispc.is_enabled = false;
4189 /* ensure the dispc_irq_handler sees the is_enabled value */
4190 smp_wmb();
4191 /* wait for current handler to finish before turning the DISPC off */
4192 synchronize_irq(dispc.irq);
4193
4fbafaf3 4194 dispc_save_context();
4fbafaf3
TV		 4195
4196 return 0;
4197}
4198
4199static int dispc_runtime_resume(struct device *dev)
4200{
9229b516
TV		 4201 /*
4202 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4203 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4204 * _omap_dispc_initial_config(). We can thus use it to detect if
4205 * we have lost register context.
4206 */
0925afc9
TV		 4207 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4208 _omap_dispc_initial_config();
9229b516 4209
fbff010b
JS		 4210 dispc_errata_i734_wa();
4211
0925afc9 4212 dispc_restore_context();
acc3a231
JS		 4213
4214 dispc_restore_gamma_tables();
0925afc9 4215 }
be07dcd7 4216
0925afc9
TV		 4217 dispc.is_enabled = true;
4218 /* ensure the dispc_irq_handler sees the is_enabled value */
4219 smp_wmb();
4fbafaf3
TV		 4220
4221 return 0;
4222}
4223
4224static const struct dev_pm_ops dispc_pm_ops = {
4225 .runtime_suspend = dispc_runtime_suspend,
4226 .runtime_resume = dispc_runtime_resume,
4227};
4228
d7977f88
TV		 4229static const struct of_device_id dispc_of_match[] = {
4230 { .compatible = "ti,omap2-dispc", },
4231 { .compatible = "ti,omap3-dispc", },
4232 { .compatible = "ti,omap4-dispc", },
2e7e6b68 4233 { .compatible = "ti,omap5-dispc", },
93550927 4234 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 4235 {},
4236};
4237
060b6d9c 4238static struct platform_driver omap_dispchw_driver = {
736e60dd
TV		 4239 .probe = dispc_probe,
4240 .remove = dispc_remove,
060b6d9c
SG		 4241 .driver = {
4242 .name = "omapdss_dispc",
4fbafaf3 4243 .pm = &dispc_pm_ops,
d7977f88 4244 .of_match_table = dispc_of_match,
422ccbd5 4245 .suppress_bind_attrs = true,
060b6d9c
SG		 4246 },
4247};
4248
6e7e8f06 4249int __init dispc_init_platform_driver(void)
060b6d9c 4250{
736e60dd 4251 return platform_driver_register(&omap_dispchw_driver);
060b6d9c
SG		 4252}
4253
ede92695 4254void dispc_uninit_platform_driver(void)
060b6d9c 4255{
04c742c3 4256 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4257}
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