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drm/omap: HDMI5: Use pointer to cfg->v_fc_config.timings in hdmi_core_video_config
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
736e60dd 42#include <linux/component.h>
80c39712 43
32043da7 44#include "omapdss.h"
80c39712 45#include "dss.h"
a0acb557 46#include "dss_features.h"
9b372c2d 47#include "dispc.h"
80c39712
TV		 48
49/* DISPC */
8613b000 50#define DISPC_SZ_REGS SZ_4K
80c39712 51
5ed8cf5b
TV		 52enum omap_burst_size {
53 BURST_SIZE_X2 = 0,
54 BURST_SIZE_X4 = 1,
55 BURST_SIZE_X8 = 2,
56};
57
80c39712
TV		 58#define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
60
61#define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
63
dcbe765b
CM		 64struct dispc_features {
65 u8 sw_start;
66 u8 fp_start;
67 u8 bp_start;
68 u16 sw_max;
69 u16 vp_max;
70 u16 hp_max;
33b89928
AT		 71 u8 mgr_width_start;
72 u8 mgr_height_start;
73 u16 mgr_width_max;
74 u16 mgr_height_max;
ca5ca69c
AT		 75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk;
0c6921de 77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 78 const struct omap_video_timings *mgr_timings,
79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 82 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 83 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 84 u16 width, u16 height, u16 out_width, u16 out_height,
85 bool mem_to_mem);
42a6961c 86 u8 num_fifos;
66a0f9e4
TV		 87
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround:1;
cffa947d
TV		 90
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv:1;
d0df9a2c
AT		 93
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround:1;
8bc65552
AT		 96
97 bool set_max_preload:1;
f2aee319
TV		 98
99 /* PIXEL_INC is not added to the last pixel of a line */
100 bool last_pixel_inc_missing:1;
e5f80917
TV		 101
102 /* POL_FREQ has ALIGN bit */
103 bool supports_sync_align:1;
20efbc35
TV		 104
105 bool has_writeback:1;
3a38ed53
TV		 106
107 bool supports_double_pixel:1;
b7536d67
TV		 108
109 /*
110 * Field order for VENC is different than HDMI. We should handle this in
111 * some intelligent manner, but as the SoCs have either HDMI or VENC,
112 * never both, we can just use this flag for now.
113 */
114 bool reverse_ilace_field_order:1;
acc3a231
JS		 115
116 bool has_gamma_table:1;
fbff010b
JS		 117
118 bool has_gamma_i734_bug:1;
dcbe765b
CM		 119};
120
42a6961c 121#define DISPC_MAX_NR_FIFOS 5
acc3a231 122#define DISPC_MAX_CHANNEL_GAMMA 4
42a6961c 123
80c39712 124static struct {
060b6d9c 125 struct platform_device *pdev;
80c39712 126 void __iomem *base;
4fbafaf3 127
affe360d 128 int irq;
0925afc9
TV		 129 irq_handler_t user_handler;
130 void *user_data;
80c39712 131
7b3926b3 132 unsigned long core_clk_rate;
5391e87d 133 unsigned long tv_pclk_rate;
7b3926b3 134
42a6961c
TV		 135 u32 fifo_size[DISPC_MAX_NR_FIFOS];
136 /* maps which plane is using a fifo. fifo-id -> plane-id */
137 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 138
49ea86f3 139 bool ctx_valid;
80c39712 140 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 141
acc3a231
JS		 142 u32 *gamma_table[DISPC_MAX_CHANNEL_GAMMA];
143
dcbe765b 144 const struct dispc_features *feat;
0925afc9
TV		 145
146 bool is_enabled;
0006fd63
TV		 147
148 struct regmap *syscon_pol;
149 u32 syscon_pol_offset;
d49cd155
TV		 150
151 /* DISPC_CONTROL & DISPC_CONFIG lock*/
152 spinlock_t control_lock;
80c39712
TV		 153} dispc;
154
0d66cbb5
AJ		 155enum omap_color_component {
156 /* used for all color formats for OMAP3 and earlier
157 * and for RGB and Y color component on OMAP4
158 */
159 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
160 /* used for UV component for
161 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
162 * color formats on OMAP4
163 */
164 DISPC_COLOR_COMPONENT_UV = 1 << 1,
165};
166
efa70b3b
CM		 167enum mgr_reg_fields {
168 DISPC_MGR_FLD_ENABLE,
169 DISPC_MGR_FLD_STNTFT,
170 DISPC_MGR_FLD_GO,
171 DISPC_MGR_FLD_TFTDATALINES,
172 DISPC_MGR_FLD_STALLMODE,
173 DISPC_MGR_FLD_TCKENABLE,
174 DISPC_MGR_FLD_TCKSELECTION,
175 DISPC_MGR_FLD_CPR,
176 DISPC_MGR_FLD_FIFOHANDCHECK,
177 /* used to maintain a count of the above fields */
178 DISPC_MGR_FLD_NUM,
179};
180
5c348ba9
JS		 181struct dispc_reg_field {
182 u16 reg;
183 u8 high;
184 u8 low;
185};
186
acc3a231
JS		 187struct dispc_gamma_desc {
188 u32 len;
189 u32 bits;
190 u16 reg;
191 bool has_index;
192};
193
efa70b3b
CM		 194static const struct {
195 const char *name;
196 u32 vsync_irq;
197 u32 framedone_irq;
198 u32 sync_lost_irq;
acc3a231 199 struct dispc_gamma_desc gamma;
5c348ba9 200 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 201} mgr_desc[] = {
202 [OMAP_DSS_CHANNEL_LCD] = {
203 .name = "LCD",
204 .vsync_irq = DISPC_IRQ_VSYNC,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
acc3a231
JS		 207 .gamma = {
208 .len = 256,
209 .bits = 8,
210 .reg = DISPC_GAMMA_TABLE0,
211 .has_index = true,
212 },
efa70b3b
CM		 213 .reg_desc = {
214 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
215 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
216 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
217 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
218 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
219 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
220 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
221 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
222 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
223 },
224 },
225 [OMAP_DSS_CHANNEL_DIGIT] = {
226 .name = "DIGIT",
227 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 228 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b 229 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
acc3a231
JS		 230 .gamma = {
231 .len = 1024,
232 .bits = 10,
233 .reg = DISPC_GAMMA_TABLE2,
234 .has_index = false,
235 },
efa70b3b
CM		 236 .reg_desc = {
237 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
238 [DISPC_MGR_FLD_STNTFT] = { },
239 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
240 [DISPC_MGR_FLD_TFTDATALINES] = { },
241 [DISPC_MGR_FLD_STALLMODE] = { },
242 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
243 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
244 [DISPC_MGR_FLD_CPR] = { },
245 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
246 },
247 },
248 [OMAP_DSS_CHANNEL_LCD2] = {
249 .name = "LCD2",
250 .vsync_irq = DISPC_IRQ_VSYNC2,
251 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
252 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
acc3a231
JS		 253 .gamma = {
254 .len = 256,
255 .bits = 8,
256 .reg = DISPC_GAMMA_TABLE1,
257 .has_index = true,
258 },
efa70b3b
CM		 259 .reg_desc = {
260 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
261 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
262 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
263 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
264 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
265 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
266 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
267 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
268 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
269 },
270 },
e86d456a
CM		 271 [OMAP_DSS_CHANNEL_LCD3] = {
272 .name = "LCD3",
273 .vsync_irq = DISPC_IRQ_VSYNC3,
274 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
275 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
acc3a231
JS		 276 .gamma = {
277 .len = 256,
278 .bits = 8,
279 .reg = DISPC_GAMMA_TABLE3,
280 .has_index = true,
281 },
e86d456a
CM		 282 .reg_desc = {
283 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
284 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
285 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
286 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
287 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
288 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
289 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
290 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
291 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
292 },
293 },
efa70b3b
CM		 294};
295
6e5264b0
AT		 296struct color_conv_coef {
297 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
298 int full_range;
299};
300
65904155
TV		 301static unsigned long dispc_fclk_rate(void);
302static unsigned long dispc_core_clk_rate(void);
303static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
304static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
305
3e8a6ff2
AT		 306static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
307static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 308
55978cc2 309static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 310{
55978cc2 311 __raw_writel(val, dispc.base + idx);
80c39712
TV		 312}
313
55978cc2 314static inline u32 dispc_read_reg(const u16 idx)
80c39712 315{
55978cc2 316 return __raw_readl(dispc.base + idx);
80c39712
TV		 317}
318
efa70b3b
CM		 319static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
320{
5c348ba9 321 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 322 return REG_GET(rfld.reg, rfld.high, rfld.low);
323}
324
325static void mgr_fld_write(enum omap_channel channel,
326 enum mgr_reg_fields regfld, int val) {
5c348ba9 327 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
d49cd155
TV		 328 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
329 unsigned long flags;
330
331 if (need_lock)
332 spin_lock_irqsave(&dispc.control_lock, flags);
333
efa70b3b 334 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
d49cd155
TV		 335
336 if (need_lock)
337 spin_unlock_irqrestore(&dispc.control_lock, flags);
efa70b3b
CM		 338}
339
80c39712 340#define SR(reg) \
55978cc2 341 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 342#define RR(reg) \
55978cc2 343 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 344
4fbafaf3 345static void dispc_save_context(void)
80c39712 346{
c6104b8e 347 int i, j;
80c39712 348
4fbafaf3
TV		 349 DSSDBG("dispc_save_context\n");
350
80c39712
TV		 351 SR(IRQENABLE);
352 SR(CONTROL);
353 SR(CONFIG);
80c39712 354 SR(LINE_NUMBER);
11354dd5
AT		 355 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
356 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 357 SR(GLOBAL_ALPHA);
2a205f34
SS		 358 if (dss_has_feature(FEAT_MGR_LCD2)) {
359 SR(CONTROL2);
2a205f34
SS		 360 SR(CONFIG2);
361 }
e86d456a
CM		 362 if (dss_has_feature(FEAT_MGR_LCD3)) {
363 SR(CONTROL3);
364 SR(CONFIG3);
365 }
80c39712 366
c6104b8e
AT		 367 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
368 SR(DEFAULT_COLOR(i));
369 SR(TRANS_COLOR(i));
370 SR(SIZE_MGR(i));
371 if (i == OMAP_DSS_CHANNEL_DIGIT)
372 continue;
373 SR(TIMING_H(i));
374 SR(TIMING_V(i));
375 SR(POL_FREQ(i));
376 SR(DIVISORo(i));
377
378 SR(DATA_CYCLE1(i));
379 SR(DATA_CYCLE2(i));
380 SR(DATA_CYCLE3(i));
381
332e9d70 382 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 383 SR(CPR_COEF_R(i));
384 SR(CPR_COEF_G(i));
385 SR(CPR_COEF_B(i));
332e9d70 386 }
2a205f34 387 }
80c39712 388
c6104b8e
AT		 389 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
390 SR(OVL_BA0(i));
391 SR(OVL_BA1(i));
392 SR(OVL_POSITION(i));
393 SR(OVL_SIZE(i));
394 SR(OVL_ATTRIBUTES(i));
395 SR(OVL_FIFO_THRESHOLD(i));
396 SR(OVL_ROW_INC(i));
397 SR(OVL_PIXEL_INC(i));
398 if (dss_has_feature(FEAT_PRELOAD))
399 SR(OVL_PRELOAD(i));
400 if (i == OMAP_DSS_GFX) {
401 SR(OVL_WINDOW_SKIP(i));
402 SR(OVL_TABLE_BA(i));
403 continue;
404 }
405 SR(OVL_FIR(i));
406 SR(OVL_PICTURE_SIZE(i));
407 SR(OVL_ACCU0(i));
408 SR(OVL_ACCU1(i));
9b372c2d 409
c6104b8e
AT		 410 for (j = 0; j < 8; j++)
411 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 412
c6104b8e
AT		 413 for (j = 0; j < 8; j++)
414 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 415
c6104b8e
AT		 416 for (j = 0; j < 5; j++)
417 SR(OVL_CONV_COEF(i, j));
ab5ca071 418
c6104b8e
AT		 419 if (dss_has_feature(FEAT_FIR_COEF_V)) {
420 for (j = 0; j < 8; j++)
421 SR(OVL_FIR_COEF_V(i, j));
422 }
9b372c2d 423
c6104b8e
AT		 424 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
425 SR(OVL_BA0_UV(i));
426 SR(OVL_BA1_UV(i));
427 SR(OVL_FIR2(i));
428 SR(OVL_ACCU2_0(i));
429 SR(OVL_ACCU2_1(i));
ab5ca071 430
c6104b8e
AT		 431 for (j = 0; j < 8; j++)
432 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 433
c6104b8e
AT		 434 for (j = 0; j < 8; j++)
435 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 436
c6104b8e
AT		 437 for (j = 0; j < 8; j++)
438 SR(OVL_FIR_COEF_V2(i, j));
439 }
440 if (dss_has_feature(FEAT_ATTR2))
441 SR(OVL_ATTRIBUTES2(i));
ab5ca071 442 }
0cf35df3
MR		 443
444 if (dss_has_feature(FEAT_CORE_CLK_DIV))
445 SR(DIVISOR);
49ea86f3 446
49ea86f3
TV		 447 dispc.ctx_valid = true;
448
9229b516 449 DSSDBG("context saved\n");
80c39712
TV		 450}
451
4fbafaf3 452static void dispc_restore_context(void)
80c39712 453{
9229b516 454 int i, j;
4fbafaf3
TV		 455
456 DSSDBG("dispc_restore_context\n");
457
49ea86f3
TV		 458 if (!dispc.ctx_valid)
459 return;
460
75c7d59d 461 /*RR(IRQENABLE);*/
80c39712
TV		 462 /*RR(CONTROL);*/
463 RR(CONFIG);
80c39712 464 RR(LINE_NUMBER);
11354dd5
AT		 465 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
466 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 467 RR(GLOBAL_ALPHA);
c6104b8e 468 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 469 RR(CONFIG2);
e86d456a
CM		 470 if (dss_has_feature(FEAT_MGR_LCD3))
471 RR(CONFIG3);
80c39712 472
c6104b8e
AT		 473 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
474 RR(DEFAULT_COLOR(i));
475 RR(TRANS_COLOR(i));
476 RR(SIZE_MGR(i));
477 if (i == OMAP_DSS_CHANNEL_DIGIT)
478 continue;
479 RR(TIMING_H(i));
480 RR(TIMING_V(i));
481 RR(POL_FREQ(i));
482 RR(DIVISORo(i));
483
484 RR(DATA_CYCLE1(i));
485 RR(DATA_CYCLE2(i));
486 RR(DATA_CYCLE3(i));
2a205f34 487
332e9d70 488 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 489 RR(CPR_COEF_R(i));
490 RR(CPR_COEF_G(i));
491 RR(CPR_COEF_B(i));
332e9d70 492 }
2a205f34 493 }
80c39712 494
c6104b8e
AT		 495 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
496 RR(OVL_BA0(i));
497 RR(OVL_BA1(i));
498 RR(OVL_POSITION(i));
499 RR(OVL_SIZE(i));
500 RR(OVL_ATTRIBUTES(i));
501 RR(OVL_FIFO_THRESHOLD(i));
502 RR(OVL_ROW_INC(i));
503 RR(OVL_PIXEL_INC(i));
504 if (dss_has_feature(FEAT_PRELOAD))
505 RR(OVL_PRELOAD(i));
506 if (i == OMAP_DSS_GFX) {
507 RR(OVL_WINDOW_SKIP(i));
508 RR(OVL_TABLE_BA(i));
509 continue;
510 }
511 RR(OVL_FIR(i));
512 RR(OVL_PICTURE_SIZE(i));
513 RR(OVL_ACCU0(i));
514 RR(OVL_ACCU1(i));
9b372c2d 515
c6104b8e
AT		 516 for (j = 0; j < 8; j++)
517 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 518
c6104b8e
AT		 519 for (j = 0; j < 8; j++)
520 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 521
c6104b8e
AT		 522 for (j = 0; j < 5; j++)
523 RR(OVL_CONV_COEF(i, j));
ab5ca071 524
c6104b8e
AT		 525 if (dss_has_feature(FEAT_FIR_COEF_V)) {
526 for (j = 0; j < 8; j++)
527 RR(OVL_FIR_COEF_V(i, j));
528 }
9b372c2d 529
c6104b8e
AT		 530 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
531 RR(OVL_BA0_UV(i));
532 RR(OVL_BA1_UV(i));
533 RR(OVL_FIR2(i));
534 RR(OVL_ACCU2_0(i));
535 RR(OVL_ACCU2_1(i));
ab5ca071 536
c6104b8e
AT		 537 for (j = 0; j < 8; j++)
538 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 539
c6104b8e
AT		 540 for (j = 0; j < 8; j++)
541 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 542
c6104b8e
AT		 543 for (j = 0; j < 8; j++)
544 RR(OVL_FIR_COEF_V2(i, j));
545 }
546 if (dss_has_feature(FEAT_ATTR2))
547 RR(OVL_ATTRIBUTES2(i));
ab5ca071 548 }
80c39712 549
0cf35df3
MR		 550 if (dss_has_feature(FEAT_CORE_CLK_DIV))
551 RR(DIVISOR);
552
80c39712
TV		 553 /* enable last, because LCD & DIGIT enable are here */
554 RR(CONTROL);
2a205f34
SS		 555 if (dss_has_feature(FEAT_MGR_LCD2))
556 RR(CONTROL2);
e86d456a
CM		 557 if (dss_has_feature(FEAT_MGR_LCD3))
558 RR(CONTROL3);
75c7d59d 559 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 560 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 561
562 /*
563 * enable last so IRQs won't trigger before
564 * the context is fully restored
565 */
566 RR(IRQENABLE);
49ea86f3
TV		 567
568 DSSDBG("context restored\n");
80c39712
TV		 569}
570
571#undef SR
572#undef RR
573
4fbafaf3
TV		 574int dispc_runtime_get(void)
575{
576 int r;
577
578 DSSDBG("dispc_runtime_get\n");
579
580 r = pm_runtime_get_sync(&dispc.pdev->dev);
581 WARN_ON(r < 0);
582 return r < 0 ? r : 0;
583}
348be69d 584EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 585
586void dispc_runtime_put(void)
587{
588 int r;
589
590 DSSDBG("dispc_runtime_put\n");
591
0eaf9f52 592 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 593 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 594}
348be69d 595EXPORT_SYMBOL(dispc_runtime_put);
80c39712 596
3dcec4d6
TV		 597u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
598{
efa70b3b 599 return mgr_desc[channel].vsync_irq;
3dcec4d6 600}
348be69d 601EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 602
7d1365c9
TV		 603u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
604{
cffa947d
TV		 605 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
606 return 0;
607
efa70b3b 608 return mgr_desc[channel].framedone_irq;
7d1365c9 609}
348be69d 610EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 611
cb699200
TV		 612u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
613{
614 return mgr_desc[channel].sync_lost_irq;
615}
348be69d 616EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 617
0b23e5b8
AT		 618u32 dispc_wb_get_framedone_irq(void)
619{
620 return DISPC_IRQ_FRAMEDONEWB;
621}
622
26d9dd0d 623bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 624{
efa70b3b 625 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 626}
348be69d 627EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 628
26d9dd0d 629void dispc_mgr_go(enum omap_channel channel)
80c39712 630{
0bcfdba6 631 WARN_ON(!dispc_mgr_is_enabled(channel));
3c91ee8c 632 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 633
efa70b3b 634 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 635
efa70b3b 636 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 637}
348be69d 638EXPORT_SYMBOL(dispc_mgr_go);
80c39712 639
0b23e5b8
AT		 640bool dispc_wb_go_busy(void)
641{
642 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
643}
644
645void dispc_wb_go(void)
646{
647 enum omap_plane plane = OMAP_DSS_WB;
648 bool enable, go;
649
650 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
651
652 if (!enable)
653 return;
654
655 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
656 if (go) {
657 DSSERR("GO bit not down for WB\n");
658 return;
659 }
660
661 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
662}
663
f0e5caab 664static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 665{
9b372c2d 666 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 667}
668
f0e5caab 669static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 670{
9b372c2d 671 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 672}
673
f0e5caab 674static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 675{
9b372c2d 676 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 677}
678
f0e5caab 679static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 680{
681 BUG_ON(plane == OMAP_DSS_GFX);
682
683 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
684}
685
f0e5caab
TV		 686static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
687 u32 value)
ab5ca071
AJ		 688{
689 BUG_ON(plane == OMAP_DSS_GFX);
690
691 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
692}
693
f0e5caab 694static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 695{
696 BUG_ON(plane == OMAP_DSS_GFX);
697
698 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
699}
700
debd9074
CM		 701static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
702 int fir_vinc, int five_taps,
703 enum omap_color_component color_comp)
80c39712 704{
debd9074 705 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 706 int i;
707
debd9074
CM		 708 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
709 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 710
711 for (i = 0; i < 8; i++) {
712 u32 h, hv;
713
debd9074
CM		 714 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
715 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
716 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
717 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
718 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
719 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
720 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
721 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 722
0d66cbb5 723 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 724 dispc_ovl_write_firh_reg(plane, i, h);
725 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 726 } else {
f0e5caab
TV		 727 dispc_ovl_write_firh2_reg(plane, i, h);
728 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 729 }
730
80c39712
TV		 731 }
732
66be8f6c
GI		 733 if (five_taps) {
734 for (i = 0; i < 8; i++) {
735 u32 v;
debd9074
CM		 736 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
737 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 738 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 739 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 740 else
f0e5caab 741 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 742 }
80c39712
TV		 743 }
744}
745
80c39712 746
6e5264b0
AT		 747static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
748 const struct color_conv_coef *ct)
749{
80c39712
TV		 750#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
751
6e5264b0
AT		 752 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
753 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
754 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
755 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
756 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 757
6e5264b0 758 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 759
760#undef CVAL
80c39712
TV		 761}
762
6e5264b0
AT		 763static void dispc_setup_color_conv_coef(void)
764{
765 int i;
766 int num_ovl = dss_feat_get_num_ovls();
6e5264b0 767 const struct color_conv_coef ctbl_bt601_5_ovl = {
7d18bbee 768 /* YUV -> RGB */
6e5264b0
AT		 769 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
770 };
771 const struct color_conv_coef ctbl_bt601_5_wb = {
7d18bbee
TV		 772 /* RGB -> YUV */
773 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
6e5264b0
AT		 774 };
775
776 for (i = 1; i < num_ovl; i++)
777 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
778
20efbc35
TV		 779 if (dispc.feat->has_writeback)
780 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
6e5264b0 781}
80c39712 782
f0e5caab 783static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 784{
9b372c2d 785 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 786}
787
f0e5caab 788static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 789{
9b372c2d 790 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 791}
792
f0e5caab 793static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 794{
795 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
796}
797
f0e5caab 798static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 799{
800 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
801}
802
d79db853
AT		 803static void dispc_ovl_set_pos(enum omap_plane plane,
804 enum omap_overlay_caps caps, int x, int y)
80c39712 805{
d79db853
AT		 806 u32 val;
807
808 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
809 return;
810
811 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 812
813 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 814}
815
78b687fc
AT		 816static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
817 int height)
80c39712 818{
80c39712 819 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 820
36d87d95 821 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 822 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
823 else
824 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 825}
826
78b687fc
AT		 827static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
828 int height)
80c39712
TV		 829{
830 u32 val;
80c39712
TV		 831
832 BUG_ON(plane == OMAP_DSS_GFX);
833
834 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 835
36d87d95
AT		 836 if (plane == OMAP_DSS_WB)
837 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
838 else
839 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 840}
841
5b54ed3e
AT		 842static void dispc_ovl_set_zorder(enum omap_plane plane,
843 enum omap_overlay_caps caps, u8 zorder)
54128701 844{
5b54ed3e 845 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 846 return;
847
848 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
849}
850
851static void dispc_ovl_enable_zorder_planes(void)
852{
853 int i;
854
855 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
856 return;
857
858 for (i = 0; i < dss_feat_get_num_ovls(); i++)
859 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
860}
861
5b54ed3e
AT		 862static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
863 enum omap_overlay_caps caps, bool enable)
fd28a390 864{
5b54ed3e 865 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 866 return;
867
9b372c2d 868 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 869}
870
5b54ed3e
AT		 871static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
872 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 873{
b8c095b4 874 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 875 int shift;
876
5b54ed3e 877 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 878 return;
a0acb557 879
fe3cc9d6
TV		 880 shift = shifts[plane];
881 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 882}
883
f0e5caab 884static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 885{
9b372c2d 886 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 887}
888
f0e5caab 889static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 890{
9b372c2d 891 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 892}
893
f0e5caab 894static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 895 enum omap_color_mode color_mode)
896{
897 u32 m = 0;
f20e4220
AJ		 898 if (plane != OMAP_DSS_GFX) {
899 switch (color_mode) {
900 case OMAP_DSS_COLOR_NV12:
901 m = 0x0; break;
08f3267e 902 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 903 m = 0x1; break;
904 case OMAP_DSS_COLOR_RGBA16:
905 m = 0x2; break;
08f3267e 906 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 907 m = 0x4; break;
908 case OMAP_DSS_COLOR_ARGB16:
909 m = 0x5; break;
910 case OMAP_DSS_COLOR_RGB16:
911 m = 0x6; break;
912 case OMAP_DSS_COLOR_ARGB16_1555:
913 m = 0x7; break;
914 case OMAP_DSS_COLOR_RGB24U:
915 m = 0x8; break;
916 case OMAP_DSS_COLOR_RGB24P:
917 m = 0x9; break;
918 case OMAP_DSS_COLOR_YUV2:
919 m = 0xa; break;
920 case OMAP_DSS_COLOR_UYVY:
921 m = 0xb; break;
922 case OMAP_DSS_COLOR_ARGB32:
923 m = 0xc; break;
924 case OMAP_DSS_COLOR_RGBA32:
925 m = 0xd; break;
926 case OMAP_DSS_COLOR_RGBX32:
927 m = 0xe; break;
928 case OMAP_DSS_COLOR_XRGB16_1555:
929 m = 0xf; break;
930 default:
c6eee968 931 BUG(); return;
f20e4220
AJ		 932 }
933 } else {
934 switch (color_mode) {
935 case OMAP_DSS_COLOR_CLUT1:
936 m = 0x0; break;
937 case OMAP_DSS_COLOR_CLUT2:
938 m = 0x1; break;
939 case OMAP_DSS_COLOR_CLUT4:
940 m = 0x2; break;
941 case OMAP_DSS_COLOR_CLUT8:
942 m = 0x3; break;
943 case OMAP_DSS_COLOR_RGB12U:
944 m = 0x4; break;
945 case OMAP_DSS_COLOR_ARGB16:
946 m = 0x5; break;
947 case OMAP_DSS_COLOR_RGB16:
948 m = 0x6; break;
949 case OMAP_DSS_COLOR_ARGB16_1555:
950 m = 0x7; break;
951 case OMAP_DSS_COLOR_RGB24U:
952 m = 0x8; break;
953 case OMAP_DSS_COLOR_RGB24P:
954 m = 0x9; break;
08f3267e 955 case OMAP_DSS_COLOR_RGBX16:
f20e4220 956 m = 0xa; break;
08f3267e 957 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 958 m = 0xb; break;
959 case OMAP_DSS_COLOR_ARGB32:
960 m = 0xc; break;
961 case OMAP_DSS_COLOR_RGBA32:
962 m = 0xd; break;
963 case OMAP_DSS_COLOR_RGBX32:
964 m = 0xe; break;
965 case OMAP_DSS_COLOR_XRGB16_1555:
966 m = 0xf; break;
967 default:
c6eee968 968 BUG(); return;
f20e4220 969 }
80c39712
TV		 970 }
971
9b372c2d 972 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 973}
974
65e006ff
CM		 975static void dispc_ovl_configure_burst_type(enum omap_plane plane,
976 enum omap_dss_rotation_type rotation_type)
977{
978 if (dss_has_feature(FEAT_BURST_2D) == 0)
979 return;
980
981 if (rotation_type == OMAP_DSS_ROT_TILER)
982 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
983 else
984 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
985}
986
f427984e 987void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 988{
989 int shift;
990 u32 val;
2a205f34 991 int chan = 0, chan2 = 0;
80c39712
TV		 992
993 switch (plane) {
994 case OMAP_DSS_GFX:
995 shift = 8;
996 break;
997 case OMAP_DSS_VIDEO1:
998 case OMAP_DSS_VIDEO2:
b8c095b4 999 case OMAP_DSS_VIDEO3:
80c39712
TV		 1000 shift = 16;
1001 break;
1002 default:
1003 BUG();
1004 return;
1005 }
1006
9b372c2d 1007 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 1008 if (dss_has_feature(FEAT_MGR_LCD2)) {
1009 switch (channel) {
1010 case OMAP_DSS_CHANNEL_LCD:
1011 chan = 0;
1012 chan2 = 0;
1013 break;
1014 case OMAP_DSS_CHANNEL_DIGIT:
1015 chan = 1;
1016 chan2 = 0;
1017 break;
1018 case OMAP_DSS_CHANNEL_LCD2:
1019 chan = 0;
1020 chan2 = 1;
1021 break;
e86d456a
CM		 1022 case OMAP_DSS_CHANNEL_LCD3:
1023 if (dss_has_feature(FEAT_MGR_LCD3)) {
1024 chan = 0;
1025 chan2 = 2;
1026 } else {
1027 BUG();
1028 return;
1029 }
1030 break;
c2665c41
TV		 1031 case OMAP_DSS_CHANNEL_WB:
1032 chan = 0;
1033 chan2 = 3;
1034 break;
2a205f34
SS		 1035 default:
1036 BUG();
c6eee968 1037 return;
2a205f34
SS		 1038 }
1039
1040 val = FLD_MOD(val, chan, shift, shift);
1041 val = FLD_MOD(val, chan2, 31, 30);
1042 } else {
1043 val = FLD_MOD(val, channel, shift, shift);
1044 }
9b372c2d 1045 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 1046}
348be69d 1047EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 1048
2cc5d1af
TV		 1049static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1050{
1051 int shift;
1052 u32 val;
2cc5d1af
TV		 1053
1054 switch (plane) {
1055 case OMAP_DSS_GFX:
1056 shift = 8;
1057 break;
1058 case OMAP_DSS_VIDEO1:
1059 case OMAP_DSS_VIDEO2:
1060 case OMAP_DSS_VIDEO3:
1061 shift = 16;
1062 break;
1063 default:
1064 BUG();
c6eee968 1065 return 0;
2cc5d1af
TV		 1066 }
1067
1068 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1069
d7df5ad4
TV		 1070 if (FLD_GET(val, shift, shift) == 1)
1071 return OMAP_DSS_CHANNEL_DIGIT;
2cc5d1af 1072
d7df5ad4
TV		 1073 if (!dss_has_feature(FEAT_MGR_LCD2))
1074 return OMAP_DSS_CHANNEL_LCD;
1075
1076 switch (FLD_GET(val, 31, 30)) {
1077 case 0:
1078 default:
1079 return OMAP_DSS_CHANNEL_LCD;
1080 case 1:
1081 return OMAP_DSS_CHANNEL_LCD2;
1082 case 2:
1083 return OMAP_DSS_CHANNEL_LCD3;
c2665c41
TV		 1084 case 3:
1085 return OMAP_DSS_CHANNEL_WB;
d7df5ad4 1086 }
2cc5d1af
TV		 1087}
1088
d9ac773c
AT		 1089void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1090{
1091 enum omap_plane plane = OMAP_DSS_WB;
1092
1093 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1094}
1095
f0e5caab 1096static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1097 enum omap_burst_size burst_size)
1098{
8bbe09ee 1099 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1100 int shift;
80c39712 1101
fe3cc9d6 1102 shift = shifts[plane];
5ed8cf5b 1103 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1104}
1105
5ed8cf5b
TV		 1106static void dispc_configure_burst_sizes(void)
1107{
1108 int i;
1109 const int burst_size = BURST_SIZE_X8;
1110
1111 /* Configure burst size always to maximum size */
392faa0e 1112 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1113 dispc_ovl_set_burst_size(i, burst_size);
5b354af9
TV		 1114 if (dispc.feat->has_writeback)
1115 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
5ed8cf5b
TV		 1116}
1117
83fa2f2e 1118static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1119{
1120 unsigned unit = dss_feat_get_burst_size_unit();
1121 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1122 return unit * 8;
1123}
1124
c64dca40 1125static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1126{
efa70b3b 1127 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1128 return;
1129
efa70b3b 1130 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1131}
1132
c64dca40 1133static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1134 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1135{
1136 u32 coef_r, coef_g, coef_b;
1137
dd88b7a6 1138 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1139 return;
1140
1141 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1142 FLD_VAL(coefs->rb, 9, 0);
1143 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1144 FLD_VAL(coefs->gb, 9, 0);
1145 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1146 FLD_VAL(coefs->bb, 9, 0);
1147
1148 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1149 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1150 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1151}
1152
f0e5caab 1153static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1154{
1155 u32 val;
1156
1157 BUG_ON(plane == OMAP_DSS_GFX);
1158
9b372c2d 1159 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1160 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1161 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1162}
1163
d79db853
AT		 1164static void dispc_ovl_enable_replication(enum omap_plane plane,
1165 enum omap_overlay_caps caps, bool enable)
80c39712 1166{
b8c095b4 1167 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1168 int shift;
80c39712 1169
d79db853
AT		 1170 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1171 return;
1172
fe3cc9d6
TV		 1173 shift = shifts[plane];
1174 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1175}
1176
8f366162 1177static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1178 u16 height)
80c39712
TV		 1179{
1180 u32 val;
80c39712 1181
33b89928
AT		 1182 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1183 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1184
8f366162 1185 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1186}
1187
42a6961c 1188static void dispc_init_fifos(void)
80c39712 1189{
80c39712 1190 u32 size;
42a6961c 1191 int fifo;
a0acb557 1192 u8 start, end;
5ed8cf5b 1193 u32 unit;
47fc469b 1194 int i;
5ed8cf5b
TV		 1195
1196 unit = dss_feat_get_buffer_size_unit();
80c39712 1197
a0acb557 1198 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1199
42a6961c
TV		 1200 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1201 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1202 size *= unit;
42a6961c
TV		 1203 dispc.fifo_size[fifo] = size;
1204
1205 /*
1206 * By default fifos are mapped directly to overlays, fifo 0 to
1207 * ovl 0, fifo 1 to ovl 1, etc.
1208 */
1209 dispc.fifo_assignment[fifo] = fifo;
80c39712 1210 }
66a0f9e4
TV		 1211
1212 /*
1213 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1214 * causes problems with certain use cases, like using the tiler in 2D
1215 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1216 * giving GFX plane a larger fifo. WB but should work fine with a
1217 * smaller fifo.
1218 */
1219 if (dispc.feat->gfx_fifo_workaround) {
1220 u32 v;
1221
1222 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1223
1224 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1225 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1226 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1227 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1228
1229 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1230
1231 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1232 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1233 }
47fc469b
TV		 1234
1235 /*
1236 * Setup default fifo thresholds.
1237 */
1238 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1239 u32 low, high;
1240 const bool use_fifomerge = false;
1241 const bool manual_update = false;
1242
1243 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1244 use_fifomerge, manual_update);
1245
1246 dispc_ovl_set_fifo_threshold(i, low, high);
1247 }
65e116e1
TV		 1248
1249 if (dispc.feat->has_writeback) {
1250 u32 low, high;
1251 const bool use_fifomerge = false;
1252 const bool manual_update = false;
1253
1254 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1255 use_fifomerge, manual_update);
1256
1257 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1258 }
80c39712
TV		 1259}
1260
83fa2f2e 1261static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1262{
42a6961c
TV		 1263 int fifo;
1264 u32 size = 0;
1265
1266 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1267 if (dispc.fifo_assignment[fifo] == plane)
1268 size += dispc.fifo_size[fifo];
1269 }
1270
1271 return size;
80c39712
TV		 1272}
1273
6f04e1bf 1274void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1275{
a0acb557 1276 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1277 u32 unit;
1278
1279 unit = dss_feat_get_buffer_size_unit();
1280
1281 WARN_ON(low % unit != 0);
1282 WARN_ON(high % unit != 0);
1283
1284 low /= unit;
1285 high /= unit;
a0acb557 1286
9b372c2d
AT		 1287 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1288 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1289
3cb5d966 1290 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1291 plane,
9b372c2d 1292 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1293 lo_start, lo_end) * unit,
9b372c2d 1294 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1295 hi_start, hi_end) * unit,
1296 low * unit, high * unit);
80c39712 1297
9b372c2d 1298 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1299 FLD_VAL(high, hi_start, hi_end) |
1300 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1301
1302 /*
1303 * configure the preload to the pipeline's high threhold, if HT it's too
1304 * large for the preload field, set the threshold to the maximum value
1305 * that can be held by the preload register
1306 */
1307 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1308 plane != OMAP_DSS_WB)
1309 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712
TV		 1310}
1311
1312void dispc_enable_fifomerge(bool enable)
1313{
e6b0f884
TV		 1314 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1315 WARN_ON(enable);
1316 return;
1317 }
1318
80c39712
TV		 1319 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1320 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1321}
1322
83fa2f2e 1323void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1324 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1325 bool manual_update)
83fa2f2e
TV		 1326{
1327 /*
1328 * All sizes are in bytes. Both the buffer and burst are made of
1329 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1330 */
1331
1332 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1333 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1334 int i;
83fa2f2e
TV		 1335
1336 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1337 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1338
e0e405b9
TV		 1339 if (use_fifomerge) {
1340 total_fifo_size = 0;
392faa0e 1341 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1342 total_fifo_size += dispc_ovl_get_fifo_size(i);
1343 } else {
1344 total_fifo_size = ovl_fifo_size;
1345 }
1346
1347 /*
1348 * We use the same low threshold for both fifomerge and non-fifomerge
1349 * cases, but for fifomerge we calculate the high threshold using the
1350 * combined fifo size
1351 */
1352
3568f2a4 1353 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1354 *fifo_low = ovl_fifo_size - burst_size * 2;
1355 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1356 } else if (plane == OMAP_DSS_WB) {
1357 /*
1358 * Most optimal configuration for writeback is to push out data
1359 * to the interconnect the moment writeback pushes enough pixels
1360 * in the FIFO to form a burst
1361 */
1362 *fifo_low = 0;
1363 *fifo_high = burst_size;
e0e405b9
TV		 1364 } else {
1365 *fifo_low = ovl_fifo_size - burst_size;
1366 *fifo_high = total_fifo_size - buf_unit;
1367 }
83fa2f2e
TV		 1368}
1369
c64aa3a6
TV		 1370static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1371{
1372 int bit;
1373
1374 if (plane == OMAP_DSS_GFX)
1375 bit = 14;
1376 else
1377 bit = 23;
1378
1379 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1380}
1381
1382static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1383 int low, int high)
1384{
1385 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1386 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1387}
1388
1389static void dispc_init_mflag(void)
1390{
1391 int i;
1392
fe59e5cf
TV		 1393 /*
1394 * HACK: NV12 color format and MFLAG seem to have problems working
1395 * together: using two displays, and having an NV12 overlay on one of
1396 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1397 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1398 * remove the errors, but there doesn't seem to be a clear logic on
1399 * which values work and which not.
1400 *
1401 * As a work-around, set force MFLAG to always on.
1402 */
c64aa3a6 1403 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
fe59e5cf 1404 (1 << 0) | /* MFLAG_CTRL = force always on */
c64aa3a6
TV		 1405 (0 << 2)); /* MFLAG_START = disable */
1406
1407 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1408 u32 size = dispc_ovl_get_fifo_size(i);
1409 u32 unit = dss_feat_get_buffer_size_unit();
1410 u32 low, high;
1411
1412 dispc_ovl_set_mflag(i, true);
1413
1414 /*
1415 * Simulation team suggests below thesholds:
1416 * HT = fifosize * 5 / 8;
1417 * LT = fifosize * 4 / 8;
1418 */
1419
1420 low = size * 4 / 8 / unit;
1421 high = size * 5 / 8 / unit;
1422
1423 dispc_ovl_set_mflag_threshold(i, low, high);
1424 }
ecb0b366
TV		 1425
1426 if (dispc.feat->has_writeback) {
1427 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1428 u32 unit = dss_feat_get_buffer_size_unit();
1429 u32 low, high;
1430
1431 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1432
1433 /*
1434 * Simulation team suggests below thesholds:
1435 * HT = fifosize * 5 / 8;
1436 * LT = fifosize * 4 / 8;
1437 */
1438
1439 low = size * 4 / 8 / unit;
1440 high = size * 5 / 8 / unit;
1441
1442 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1443 }
c64aa3a6
TV		 1444}
1445
f0e5caab 1446static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1447 int hinc, int vinc,
1448 enum omap_color_component color_comp)
80c39712
TV		 1449{
1450 u32 val;
80c39712 1451
0d66cbb5
AJ		 1452 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1453 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1454
0d66cbb5
AJ		 1455 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1456 &hinc_start, &hinc_end);
1457 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1458 &vinc_start, &vinc_end);
1459 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1460 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1461
0d66cbb5
AJ		 1462 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1463 } else {
1464 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1465 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1466 }
80c39712
TV		 1467}
1468
f0e5caab 1469static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1470{
1471 u32 val;
87a7484b 1472 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1473
87a7484b
AT		 1474 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1475 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1476
1477 val = FLD_VAL(vaccu, vert_start, vert_end) |
1478 FLD_VAL(haccu, hor_start, hor_end);
1479
9b372c2d 1480 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1481}
1482
f0e5caab 1483static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1484{
1485 u32 val;
87a7484b 1486 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1487
87a7484b
AT		 1488 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1489 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1490
1491 val = FLD_VAL(vaccu, vert_start, vert_end) |
1492 FLD_VAL(haccu, hor_start, hor_end);
1493
9b372c2d 1494 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1495}
1496
f0e5caab
TV		 1497static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1498 int vaccu)
ab5ca071
AJ		 1499{
1500 u32 val;
1501
1502 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1503 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1504}
1505
f0e5caab
TV		 1506static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1507 int vaccu)
ab5ca071
AJ		 1508{
1509 u32 val;
1510
1511 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1512 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1513}
80c39712 1514
f0e5caab 1515static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1516 u16 orig_width, u16 orig_height,
1517 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1518 bool five_taps, u8 rotation,
1519 enum omap_color_component color_comp)
80c39712 1520{
0d66cbb5 1521 int fir_hinc, fir_vinc;
80c39712 1522
ed14a3ce
AJ		 1523 fir_hinc = 1024 * orig_width / out_width;
1524 fir_vinc = 1024 * orig_height / out_height;
80c39712 1525
debd9074
CM		 1526 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1527 color_comp);
f0e5caab 1528 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1529}
1530
05dd0f53
CM		 1531static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1532 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1533 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1534{
1535 int h_accu2_0, h_accu2_1;
1536 int v_accu2_0, v_accu2_1;
1537 int chroma_hinc, chroma_vinc;
1538 int idx;
1539
1540 struct accu {
1541 s8 h0_m, h0_n;
1542 s8 h1_m, h1_n;
1543 s8 v0_m, v0_n;
1544 s8 v1_m, v1_n;
1545 };
1546
1547 const struct accu *accu_table;
1548 const struct accu *accu_val;
1549
1550 static const struct accu accu_nv12[4] = {
1551 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1552 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1553 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1554 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1555 };
1556
1557 static const struct accu accu_nv12_ilace[4] = {
1558 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1559 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1560 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1561 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1562 };
1563
1564 static const struct accu accu_yuv[4] = {
1565 { 0, 1, 0, 1, 0, 1, 0, 1 },
1566 { 0, 1, 0, 1, 0, 1, 0, 1 },
1567 { -1, 1, 0, 1, 0, 1, 0, 1 },
1568 { 0, 1, 0, 1, -1, 1, 0, 1 },
1569 };
1570
1571 switch (rotation) {
1572 case OMAP_DSS_ROT_0:
1573 idx = 0;
1574 break;
1575 case OMAP_DSS_ROT_90:
1576 idx = 1;
1577 break;
1578 case OMAP_DSS_ROT_180:
1579 idx = 2;
1580 break;
1581 case OMAP_DSS_ROT_270:
1582 idx = 3;
1583 break;
1584 default:
1585 BUG();
c6eee968 1586 return;
05dd0f53
CM		 1587 }
1588
1589 switch (color_mode) {
1590 case OMAP_DSS_COLOR_NV12:
1591 if (ilace)
1592 accu_table = accu_nv12_ilace;
1593 else
1594 accu_table = accu_nv12;
1595 break;
1596 case OMAP_DSS_COLOR_YUV2:
1597 case OMAP_DSS_COLOR_UYVY:
1598 accu_table = accu_yuv;
1599 break;
1600 default:
1601 BUG();
c6eee968 1602 return;
05dd0f53
CM		 1603 }
1604
1605 accu_val = &accu_table[idx];
1606
1607 chroma_hinc = 1024 * orig_width / out_width;
1608 chroma_vinc = 1024 * orig_height / out_height;
1609
1610 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1611 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1612 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1613 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1614
1615 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1616 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1617}
1618
f0e5caab 1619static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1620 u16 orig_width, u16 orig_height,
1621 u16 out_width, u16 out_height,
1622 bool ilace, bool five_taps,
1623 bool fieldmode, enum omap_color_mode color_mode,
1624 u8 rotation)
1625{
1626 int accu0 = 0;
1627 int accu1 = 0;
1628 u32 l;
80c39712 1629
f0e5caab 1630 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1631 out_width, out_height, five_taps,
1632 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1633 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1634
87a7484b
AT		 1635 /* RESIZEENABLE and VERTICALTAPS */
1636 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1637 l |= (orig_width != out_width) ? (1 << 5) : 0;
1638 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1639 l |= five_taps ? (1 << 21) : 0;
80c39712 1640
87a7484b
AT		 1641 /* VRESIZECONF and HRESIZECONF */
1642 if (dss_has_feature(FEAT_RESIZECONF)) {
1643 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1644 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1645 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1646 }
80c39712 1647
87a7484b
AT		 1648 /* LINEBUFFERSPLIT */
1649 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1650 l &= ~(0x1 << 22);
1651 l |= five_taps ? (1 << 22) : 0;
1652 }
80c39712 1653
9b372c2d 1654 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1655
1656 /*
1657 * field 0 = even field = bottom field
1658 * field 1 = odd field = top field
1659 */
1660 if (ilace && !fieldmode) {
1661 accu1 = 0;
0d66cbb5 1662 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1663 if (accu0 >= 1024/2) {
1664 accu1 = 1024/2;
1665 accu0 -= accu1;
1666 }
1667 }
1668
f0e5caab
TV		 1669 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1670 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1671}
1672
f0e5caab 1673static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1674 u16 orig_width, u16 orig_height,
1675 u16 out_width, u16 out_height,
1676 bool ilace, bool five_taps,
1677 bool fieldmode, enum omap_color_mode color_mode,
1678 u8 rotation)
1679{
1680 int scale_x = out_width != orig_width;
1681 int scale_y = out_height != orig_height;
0cac5b61 1682 bool chroma_upscale = plane != OMAP_DSS_WB;
0d66cbb5
AJ		 1683
1684 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1685 return;
1686 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1687 color_mode != OMAP_DSS_COLOR_UYVY &&
1688 color_mode != OMAP_DSS_COLOR_NV12)) {
1689 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1690 if (plane != OMAP_DSS_WB)
1691 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1692 return;
1693 }
36377357
TV		 1694
1695 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1696 out_height, ilace, color_mode, rotation);
1697
0d66cbb5
AJ		 1698 switch (color_mode) {
1699 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1700 if (chroma_upscale) {
1701 /* UV is subsampled by 2 horizontally and vertically */
1702 orig_height >>= 1;
1703 orig_width >>= 1;
1704 } else {
1705 /* UV is downsampled by 2 horizontally and vertically */
1706 orig_height <<= 1;
1707 orig_width <<= 1;
1708 }
1709
0d66cbb5
AJ		 1710 break;
1711 case OMAP_DSS_COLOR_YUV2:
1712 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1713 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1714 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1715 rotation == OMAP_DSS_ROT_180) {
1716 if (chroma_upscale)
1717 /* UV is subsampled by 2 horizontally */
1718 orig_width >>= 1;
1719 else
1720 /* UV is downsampled by 2 horizontally */
1721 orig_width <<= 1;
1722 }
1723
0d66cbb5
AJ		 1724 /* must use FIR for YUV422 if rotated */
1725 if (rotation != OMAP_DSS_ROT_0)
1726 scale_x = scale_y = true;
20fbb50b 1727
0d66cbb5
AJ		 1728 break;
1729 default:
1730 BUG();
c6eee968 1731 return;
0d66cbb5
AJ		 1732 }
1733
1734 if (out_width != orig_width)
1735 scale_x = true;
1736 if (out_height != orig_height)
1737 scale_y = true;
1738
f0e5caab 1739 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1740 out_width, out_height, five_taps,
1741 rotation, DISPC_COLOR_COMPONENT_UV);
1742
2a5561b1
AT		 1743 if (plane != OMAP_DSS_WB)
1744 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1745 (scale_x || scale_y) ? 1 : 0, 8, 8);
1746
0d66cbb5
AJ		 1747 /* set H scaling */
1748 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1749 /* set V scaling */
1750 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1751}
1752
f0e5caab 1753static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1754 u16 orig_width, u16 orig_height,
1755 u16 out_width, u16 out_height,
1756 bool ilace, bool five_taps,
1757 bool fieldmode, enum omap_color_mode color_mode,
1758 u8 rotation)
1759{
1760 BUG_ON(plane == OMAP_DSS_GFX);
1761
f0e5caab 1762 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1763 orig_width, orig_height,
1764 out_width, out_height,
1765 ilace, five_taps,
1766 fieldmode, color_mode,
1767 rotation);
1768
f0e5caab 1769 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1770 orig_width, orig_height,
1771 out_width, out_height,
1772 ilace, five_taps,
1773 fieldmode, color_mode,
1774 rotation);
1775}
1776
f0e5caab 1777static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1778 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1779 bool mirroring, enum omap_color_mode color_mode)
1780{
87a7484b
AT		 1781 bool row_repeat = false;
1782 int vidrot = 0;
1783
80c39712
TV		 1784 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1785 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1786
1787 if (mirroring) {
1788 switch (rotation) {
1789 case OMAP_DSS_ROT_0:
1790 vidrot = 2;
1791 break;
1792 case OMAP_DSS_ROT_90:
1793 vidrot = 1;
1794 break;
1795 case OMAP_DSS_ROT_180:
1796 vidrot = 0;
1797 break;
1798 case OMAP_DSS_ROT_270:
1799 vidrot = 3;
1800 break;
1801 }
1802 } else {
1803 switch (rotation) {
1804 case OMAP_DSS_ROT_0:
1805 vidrot = 0;
1806 break;
1807 case OMAP_DSS_ROT_90:
1808 vidrot = 1;
1809 break;
1810 case OMAP_DSS_ROT_180:
1811 vidrot = 2;
1812 break;
1813 case OMAP_DSS_ROT_270:
1814 vidrot = 3;
1815 break;
1816 }
1817 }
1818
80c39712 1819 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1820 row_repeat = true;
80c39712 1821 else
87a7484b 1822 row_repeat = false;
80c39712 1823 }
87a7484b 1824
3397cc6a
TV		 1825 /*
1826 * OMAP4/5 Errata i631:
1827 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1828 * rows beyond the framebuffer, which may cause OCP error.
1829 */
1830 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1831 rotation_type != OMAP_DSS_ROT_TILER)
1832 vidrot = 1;
1833
9b372c2d 1834 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1835 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1836 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1837 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1838
1839 if (color_mode == OMAP_DSS_COLOR_NV12) {
1840 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1841 (rotation == OMAP_DSS_ROT_0 ||
1842 rotation == OMAP_DSS_ROT_180);
1843 /* DOUBLESTRIDE */
1844 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1845 }
1846
80c39712
TV		 1847}
1848
1849static int color_mode_to_bpp(enum omap_color_mode color_mode)
1850{
1851 switch (color_mode) {
1852 case OMAP_DSS_COLOR_CLUT1:
1853 return 1;
1854 case OMAP_DSS_COLOR_CLUT2:
1855 return 2;
1856 case OMAP_DSS_COLOR_CLUT4:
1857 return 4;
1858 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1859 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1860 return 8;
1861 case OMAP_DSS_COLOR_RGB12U:
1862 case OMAP_DSS_COLOR_RGB16:
1863 case OMAP_DSS_COLOR_ARGB16:
1864 case OMAP_DSS_COLOR_YUV2:
1865 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1866 case OMAP_DSS_COLOR_RGBA16:
1867 case OMAP_DSS_COLOR_RGBX16:
1868 case OMAP_DSS_COLOR_ARGB16_1555:
1869 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1870 return 16;
1871 case OMAP_DSS_COLOR_RGB24P:
1872 return 24;
1873 case OMAP_DSS_COLOR_RGB24U:
1874 case OMAP_DSS_COLOR_ARGB32:
1875 case OMAP_DSS_COLOR_RGBA32:
1876 case OMAP_DSS_COLOR_RGBX32:
1877 return 32;
1878 default:
1879 BUG();
c6eee968 1880 return 0;
80c39712
TV		 1881 }
1882}
1883
1884static s32 pixinc(int pixels, u8 ps)
1885{
1886 if (pixels == 1)
1887 return 1;
1888 else if (pixels > 1)
1889 return 1 + (pixels - 1) * ps;
1890 else if (pixels < 0)
1891 return 1 - (-pixels + 1) * ps;
1892 else
1893 BUG();
c6eee968 1894 return 0;
80c39712
TV		 1895}
1896
1897static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1898 u16 screen_width,
1899 u16 width, u16 height,
1900 enum omap_color_mode color_mode, bool fieldmode,
1901 unsigned int field_offset,
1902 unsigned *offset0, unsigned *offset1,
aed74b55 1903 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1904{
1905 u8 ps;
1906
1907 /* FIXME CLUT formats */
1908 switch (color_mode) {
1909 case OMAP_DSS_COLOR_CLUT1:
1910 case OMAP_DSS_COLOR_CLUT2:
1911 case OMAP_DSS_COLOR_CLUT4:
1912 case OMAP_DSS_COLOR_CLUT8:
1913 BUG();
1914 return;
1915 case OMAP_DSS_COLOR_YUV2:
1916 case OMAP_DSS_COLOR_UYVY:
1917 ps = 4;
1918 break;
1919 default:
1920 ps = color_mode_to_bpp(color_mode) / 8;
1921 break;
1922 }
1923
1924 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1925 width, height);
1926
1927 /*
1928 * field 0 = even field = bottom field
1929 * field 1 = odd field = top field
1930 */
1931 switch (rotation + mirror * 4) {
1932 case OMAP_DSS_ROT_0:
1933 case OMAP_DSS_ROT_180:
1934 /*
1935 * If the pixel format is YUV or UYVY divide the width
1936 * of the image by 2 for 0 and 180 degree rotation.
1937 */
1938 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1939 color_mode == OMAP_DSS_COLOR_UYVY)
1940 width = width >> 1;
1941 case OMAP_DSS_ROT_90:
1942 case OMAP_DSS_ROT_270:
1943 *offset1 = 0;
1944 if (field_offset)
1945 *offset0 = field_offset * screen_width * ps;
1946 else
1947 *offset0 = 0;
1948
aed74b55
CM		 1949 *row_inc = pixinc(1 +
1950 (y_predecim * screen_width - x_predecim * width) +
1951 (fieldmode ? screen_width : 0), ps);
1952 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1953 break;
1954
1955 case OMAP_DSS_ROT_0 + 4:
1956 case OMAP_DSS_ROT_180 + 4:
1957 /* If the pixel format is YUV or UYVY divide the width
1958 * of the image by 2 for 0 degree and 180 degree
1959 */
1960 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1961 color_mode == OMAP_DSS_COLOR_UYVY)
1962 width = width >> 1;
1963 case OMAP_DSS_ROT_90 + 4:
1964 case OMAP_DSS_ROT_270 + 4:
1965 *offset1 = 0;
1966 if (field_offset)
1967 *offset0 = field_offset * screen_width * ps;
1968 else
1969 *offset0 = 0;
aed74b55
CM		 1970 *row_inc = pixinc(1 -
1971 (y_predecim * screen_width + x_predecim * width) -
1972 (fieldmode ? screen_width : 0), ps);
1973 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1974 break;
1975
1976 default:
1977 BUG();
c6eee968 1978 return;
80c39712
TV		 1979 }
1980}
1981
1982static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1983 u16 screen_width,
1984 u16 width, u16 height,
1985 enum omap_color_mode color_mode, bool fieldmode,
1986 unsigned int field_offset,
1987 unsigned *offset0, unsigned *offset1,
aed74b55 1988 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1989{
1990 u8 ps;
1991 u16 fbw, fbh;
1992
1993 /* FIXME CLUT formats */
1994 switch (color_mode) {
1995 case OMAP_DSS_COLOR_CLUT1:
1996 case OMAP_DSS_COLOR_CLUT2:
1997 case OMAP_DSS_COLOR_CLUT4:
1998 case OMAP_DSS_COLOR_CLUT8:
1999 BUG();
2000 return;
2001 default:
2002 ps = color_mode_to_bpp(color_mode) / 8;
2003 break;
2004 }
2005
2006 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
2007 width, height);
2008
2009 /* width & height are overlay sizes, convert to fb sizes */
2010
2011 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
2012 fbw = width;
2013 fbh = height;
2014 } else {
2015 fbw = height;
2016 fbh = width;
2017 }
2018
2019 /*
2020 * field 0 = even field = bottom field
2021 * field 1 = odd field = top field
2022 */
2023 switch (rotation + mirror * 4) {
2024 case OMAP_DSS_ROT_0:
2025 *offset1 = 0;
2026 if (field_offset)
2027 *offset0 = *offset1 + field_offset * screen_width * ps;
2028 else
2029 *offset0 = *offset1;
aed74b55
CM		 2030 *row_inc = pixinc(1 +
2031 (y_predecim * screen_width - fbw * x_predecim) +
2032 (fieldmode ? screen_width : 0), ps);
2033 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2034 color_mode == OMAP_DSS_COLOR_UYVY)
2035 *pix_inc = pixinc(x_predecim, 2 * ps);
2036 else
2037 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2038 break;
2039 case OMAP_DSS_ROT_90:
2040 *offset1 = screen_width * (fbh - 1) * ps;
2041 if (field_offset)
2042 *offset0 = *offset1 + field_offset * ps;
2043 else
2044 *offset0 = *offset1;
aed74b55
CM		 2045 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2046 y_predecim + (fieldmode ? 1 : 0), ps);
2047 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2048 break;
2049 case OMAP_DSS_ROT_180:
2050 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2051 if (field_offset)
2052 *offset0 = *offset1 - field_offset * screen_width * ps;
2053 else
2054 *offset0 = *offset1;
2055 *row_inc = pixinc(-1 -
aed74b55
CM		 2056 (y_predecim * screen_width - fbw * x_predecim) -
2057 (fieldmode ? screen_width : 0), ps);
2058 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2059 color_mode == OMAP_DSS_COLOR_UYVY)
2060 *pix_inc = pixinc(-x_predecim, 2 * ps);
2061 else
2062 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2063 break;
2064 case OMAP_DSS_ROT_270:
2065 *offset1 = (fbw - 1) * ps;
2066 if (field_offset)
2067 *offset0 = *offset1 - field_offset * ps;
2068 else
2069 *offset0 = *offset1;
aed74b55
CM		 2070 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2071 y_predecim - (fieldmode ? 1 : 0), ps);
2072 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2073 break;
2074
2075 /* mirroring */
2076 case OMAP_DSS_ROT_0 + 4:
2077 *offset1 = (fbw - 1) * ps;
2078 if (field_offset)
2079 *offset0 = *offset1 + field_offset * screen_width * ps;
2080 else
2081 *offset0 = *offset1;
aed74b55 2082 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 2083 (fieldmode ? screen_width : 0),
2084 ps);
aed74b55
CM		 2085 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2086 color_mode == OMAP_DSS_COLOR_UYVY)
2087 *pix_inc = pixinc(-x_predecim, 2 * ps);
2088 else
2089 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 2090 break;
2091
2092 case OMAP_DSS_ROT_90 + 4:
2093 *offset1 = 0;
2094 if (field_offset)
2095 *offset0 = *offset1 + field_offset * ps;
2096 else
2097 *offset0 = *offset1;
aed74b55
CM		 2098 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2099 y_predecim + (fieldmode ? 1 : 0),
80c39712 2100 ps);
aed74b55 2101 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 2102 break;
2103
2104 case OMAP_DSS_ROT_180 + 4:
2105 *offset1 = screen_width * (fbh - 1) * ps;
2106 if (field_offset)
2107 *offset0 = *offset1 - field_offset * screen_width * ps;
2108 else
2109 *offset0 = *offset1;
aed74b55 2110 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 2111 (fieldmode ? screen_width : 0),
2112 ps);
aed74b55
CM		 2113 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2114 color_mode == OMAP_DSS_COLOR_UYVY)
2115 *pix_inc = pixinc(x_predecim, 2 * ps);
2116 else
2117 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 2118 break;
2119
2120 case OMAP_DSS_ROT_270 + 4:
2121 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2122 if (field_offset)
2123 *offset0 = *offset1 - field_offset * ps;
2124 else
2125 *offset0 = *offset1;
aed74b55
CM		 2126 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2127 y_predecim - (fieldmode ? 1 : 0),
80c39712 2128 ps);
aed74b55 2129 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 2130 break;
2131
2132 default:
2133 BUG();
c6eee968 2134 return;
80c39712
TV		 2135 }
2136}
2137
65e006ff
CM		 2138static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2139 enum omap_color_mode color_mode, bool fieldmode,
2140 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2141 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2142{
2143 u8 ps;
2144
2145 switch (color_mode) {
2146 case OMAP_DSS_COLOR_CLUT1:
2147 case OMAP_DSS_COLOR_CLUT2:
2148 case OMAP_DSS_COLOR_CLUT4:
2149 case OMAP_DSS_COLOR_CLUT8:
2150 BUG();
2151 return;
2152 default:
2153 ps = color_mode_to_bpp(color_mode) / 8;
2154 break;
2155 }
2156
2157 DSSDBG("scrw %d, width %d\n", screen_width, width);
2158
2159 /*
2160 * field 0 = even field = bottom field
2161 * field 1 = odd field = top field
2162 */
2163 *offset1 = 0;
2164 if (field_offset)
2165 *offset0 = *offset1 + field_offset * screen_width * ps;
2166 else
2167 *offset0 = *offset1;
2168 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2169 (fieldmode ? screen_width : 0), ps);
2170 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2171 color_mode == OMAP_DSS_COLOR_UYVY)
2172 *pix_inc = pixinc(x_predecim, 2 * ps);
2173 else
2174 *pix_inc = pixinc(x_predecim, ps);
2175}
2176
7faa9233
CM		 2177/*
2178 * This function is used to avoid synclosts in OMAP3, because of some
2179 * undocumented horizontal position and timing related limitations.
2180 */
465ec13f 2181static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2182 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2183 u16 width, u16 height, u16 out_width, u16 out_height,
2184 bool five_taps)
7faa9233 2185{
230edc03 2186 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2187 unsigned long nonactive;
7faa9233
CM		 2188 static const u8 limits[3] = { 8, 10, 20 };
2189 u64 val, blank;
2190 int i;
2191
0a30e150 2192 nonactive = t->hactive + t->hfront_porch + t->hsync_len +
a85f4a80 2193 t->hback_porch - out_width;
7faa9233
CM		 2194
2195 i = 0;
2196 if (out_height < height)
2197 i++;
2198 if (out_width < width)
2199 i++;
a85f4a80 2200 blank = div_u64((u64)(t->hback_porch + t->hsync_len + t->hfront_porch) *
0a30e150 2201 lclk, pclk);
7faa9233
CM		 2202 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2203 if (blank <= limits[i])
2204 return -EINVAL;
2205
e4998634
ID		 2206 /* FIXME add checks for 3-tap filter once the limitations are known */
2207 if (!five_taps)
2208 return 0;
2209
7faa9233
CM		 2210 /*
2211 * Pixel data should be prepared before visible display point starts.
2212 * So, atleast DS-2 lines must have already been fetched by DISPC
2213 * during nonactive - pos_x period.
2214 */
2215 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2216 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2217 val, max(0, ds - 2) * width);
2218 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2219 return -EINVAL;
2220
2221 /*
2222 * All lines need to be refilled during the nonactive period of which
2223 * only one line can be loaded during the active period. So, atleast
2224 * DS - 1 lines should be loaded during nonactive period.
2225 */
2226 val = div_u64((u64)nonactive * lclk, pclk);
2227 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2228 val, max(0, ds - 1) * width);
2229 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2230 return -EINVAL;
2231
2232 return 0;
2233}
2234
8702ee50 2235static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2236 const struct omap_video_timings *mgr_timings, u16 width,
2237 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2238 enum omap_color_mode color_mode)
80c39712 2239{
8b53d991 2240 u32 core_clk = 0;
3e8a6ff2 2241 u64 tmp;
80c39712 2242
7282f1b7
CM		 2243 if (height <= out_height && width <= out_width)
2244 return (unsigned long) pclk;
2245
80c39712 2246 if (height > out_height) {
81899060 2247 unsigned int ppl = mgr_timings->hactive;
80c39712 2248
c582935c 2249 tmp = (u64)pclk * height * out_width;
80c39712 2250 do_div(tmp, 2 * out_height * ppl);
8b53d991 2251 core_clk = tmp;
80c39712 2252
2d9c5597
VS		 2253 if (height > 2 * out_height) {
2254 if (ppl == out_width)
2255 return 0;
2256
c582935c 2257 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
80c39712 2258 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2259 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2260 }
2261 }
2262
2263 if (width > out_width) {
c582935c 2264 tmp = (u64)pclk * width;
80c39712 2265 do_div(tmp, out_width);
8b53d991 2266 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2267
2268 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2269 core_clk <<= 1;
80c39712
TV		 2270 }
2271
8b53d991 2272 return core_clk;
80c39712
TV		 2273}
2274
8702ee50 2275static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2276 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2277{
dcbe765b
CM		 2278 if (height > out_height && width > out_width)
2279 return pclk * 4;
2280 else
2281 return pclk * 2;
2282}
2283
8702ee50 2284static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2285 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2286{
2287 unsigned int hf, vf;
2288
2289 /*
2290 * FIXME how to determine the 'A' factor
2291 * for the no downscaling case ?
2292 */
2293
2294 if (width > 3 * out_width)
2295 hf = 4;
2296 else if (width > 2 * out_width)
2297 hf = 3;
2298 else if (width > out_width)
2299 hf = 2;
2300 else
2301 hf = 1;
80c39712
TV		 2302 if (height > out_height)
2303 vf = 2;
2304 else
2305 vf = 1;
2306
dcbe765b
CM		 2307 return pclk * vf * hf;
2308}
2309
8702ee50 2310static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2311 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2312{
8ba85306
AT		 2313 /*
2314 * If the overlay/writeback is in mem to mem mode, there are no
2315 * downscaling limitations with respect to pixel clock, return 1 as
2316 * required core clock to represent that we have sufficient enough
2317 * core clock to do maximum downscaling
2318 */
2319 if (mem_to_mem)
2320 return 1;
2321
dcbe765b
CM		 2322 if (width > out_width)
2323 return DIV_ROUND_UP(pclk, out_width) * width;
2324 else
2325 return pclk;
2326}
2327
0c6921de 2328static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2329 const struct omap_video_timings *mgr_timings,
2330 u16 width, u16 height, u16 out_width, u16 out_height,
2331 enum omap_color_mode color_mode, bool *five_taps,
2332 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2333 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2334{
2335 int error;
2336 u16 in_width, in_height;
2337 int min_factor = min(*decim_x, *decim_y);
2338 const int maxsinglelinewidth =
2339 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2340
dcbe765b
CM		 2341 *five_taps = false;
2342
2343 do {
eec77da2
TV		 2344 in_height = height / *decim_y;
2345 in_width = width / *decim_x;
8702ee50 2346 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2347 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2348 error = (in_width > maxsinglelinewidth || !*core_clk ||
2349 *core_clk > dispc_core_clk_rate());
2350 if (error) {
2351 if (*decim_x == *decim_y) {
2352 *decim_x = min_factor;
2353 ++*decim_y;
2354 } else {
2355 swap(*decim_x, *decim_y);
2356 if (*decim_x < *decim_y)
2357 ++*decim_x;
2358 }
2359 }
2360 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2361
3ce17b48
TV		 2362 if (error) {
2363 DSSERR("failed to find scaling settings\n");
2364 return -EINVAL;
2365 }
2366
dcbe765b
CM		 2367 if (in_width > maxsinglelinewidth) {
2368 DSSERR("Cannot scale max input width exceeded");
2369 return -EINVAL;
2370 }
2371 return 0;
2372}
2373
0c6921de 2374static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2375 const struct omap_video_timings *mgr_timings,
2376 u16 width, u16 height, u16 out_width, u16 out_height,
2377 enum omap_color_mode color_mode, bool *five_taps,
2378 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2379 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2380{
2381 int error;
2382 u16 in_width, in_height;
dcbe765b
CM		 2383 const int maxsinglelinewidth =
2384 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2385
2386 do {
eec77da2
TV		 2387 in_height = height / *decim_y;
2388 in_width = width / *decim_x;
e4998634 2389 *five_taps = in_height > out_height;
dcbe765b
CM		 2390
2391 if (in_width > maxsinglelinewidth)
2392 if (in_height > out_height &&
2393 in_height < out_height * 2)
2394 *five_taps = false;
e4998634
ID		 2395again:
2396 if (*five_taps)
2397 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2398 in_width, in_height, out_width,
2399 out_height, color_mode);
2400 else
8702ee50 2401 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2402 in_height, out_width, out_height,
2403 mem_to_mem);
dcbe765b 2404
e4998634
ID		 2405 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2406 pos_x, in_width, in_height, out_width,
2407 out_height, *five_taps);
2408 if (error && *five_taps) {
2409 *five_taps = false;
2410 goto again;
2411 }
2412
dcbe765b
CM		 2413 error = (error || in_width > maxsinglelinewidth * 2 ||
2414 (in_width > maxsinglelinewidth && *five_taps) ||
2415 !*core_clk || *core_clk > dispc_core_clk_rate());
ab6b2582
TV		 2416
2417 if (!error) {
2418 /* verify that we're inside the limits of scaler */
2419 if (in_width / 4 > out_width)
2420 error = 1;
2421
2422 if (*five_taps) {
2423 if (in_height / 4 > out_height)
2424 error = 1;
dcbe765b 2425 } else {
ab6b2582
TV		 2426 if (in_height / 2 > out_height)
2427 error = 1;
dcbe765b
CM		 2428 }
2429 }
ab6b2582 2430
7059e3d8
TV		 2431 if (error)
2432 ++*decim_y;
dcbe765b
CM		 2433 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2434
3ce17b48
TV		 2435 if (error) {
2436 DSSERR("failed to find scaling settings\n");
2437 return -EINVAL;
2438 }
2439
f5a73482
TV		 2440 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2441 in_height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2442 DSSERR("horizontal timing too tight\n");
2443 return -EINVAL;
7282f1b7 2444 }
dcbe765b
CM		 2445
2446 if (in_width > (maxsinglelinewidth * 2)) {
2447 DSSERR("Cannot setup scaling");
2448 DSSERR("width exceeds maximum width possible");
2449 return -EINVAL;
2450 }
2451
2452 if (in_width > maxsinglelinewidth && *five_taps) {
2453 DSSERR("cannot setup scaling with five taps");
2454 return -EINVAL;
2455 }
2456 return 0;
2457}
2458
0c6921de 2459static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2460 const struct omap_video_timings *mgr_timings,
2461 u16 width, u16 height, u16 out_width, u16 out_height,
2462 enum omap_color_mode color_mode, bool *five_taps,
2463 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2464 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2465{
2466 u16 in_width, in_width_max;
2467 int decim_x_min = *decim_x;
eec77da2 2468 u16 in_height = height / *decim_y;
dcbe765b
CM		 2469 const int maxsinglelinewidth =
2470 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2471 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2472
5d501085
AT		 2473 if (mem_to_mem) {
2474 in_width_max = out_width * maxdownscale;
2475 } else {
8ba85306
AT		 2476 in_width_max = dispc_core_clk_rate() /
2477 DIV_ROUND_UP(pclk, out_width);
5d501085 2478 }
dcbe765b 2479
dcbe765b
CM		 2480 *decim_x = DIV_ROUND_UP(width, in_width_max);
2481
2482 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2483 if (*decim_x > *x_predecim)
2484 return -EINVAL;
2485
2486 do {
eec77da2 2487 in_width = width / *decim_x;
dcbe765b
CM		 2488 } while (*decim_x <= *x_predecim &&
2489 in_width > maxsinglelinewidth && ++*decim_x);
2490
2491 if (in_width > maxsinglelinewidth) {
2492 DSSERR("Cannot scale width exceeds max line width");
2493 return -EINVAL;
2494 }
2495
8702ee50 2496 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2497 out_width, out_height, mem_to_mem);
dcbe765b 2498 return 0;
80c39712
TV		 2499}
2500
e4c5ae7f
TV		 2501#define DIV_FRAC(dividend, divisor) \
2502 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2503
74e16458 2504static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2505 enum omap_overlay_caps caps,
81ab95b7
AT		 2506 const struct omap_video_timings *mgr_timings,
2507 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2508 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2509 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2510 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2511{
0373cac6 2512 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2513 const int max_decim_limit = 16;
8b53d991 2514 unsigned long core_clk = 0;
dcbe765b 2515 int decim_x, decim_y, ret;
79ad75f2 2516
f95cb5eb
TV		 2517 if (width == out_width && height == out_height)
2518 return 0;
2519
fd2eac5a 2520 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
4e1d3ca0
TV		 2521 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2522 return -EINVAL;
2523 }
2524
5b54ed3e 2525 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2526 return -EINVAL;
79ad75f2 2527
74e16458 2528 if (mem_to_mem) {
1c031441
AT		 2529 *x_predecim = *y_predecim = 1;
2530 } else {
2531 *x_predecim = max_decim_limit;
2532 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2533 dss_has_feature(FEAT_BURST_2D)) ?
2534 2 : max_decim_limit;
2535 }
aed74b55
CM		 2536
2537 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2538 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2539 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2540 color_mode == OMAP_DSS_COLOR_CLUT8) {
2541 *x_predecim = 1;
2542 *y_predecim = 1;
2543 *five_taps = false;
2544 return 0;
2545 }
2546
2547 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2548 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2549
aed74b55 2550 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2551 return -EINVAL;
2552
aed74b55 2553 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2554 return -EINVAL;
2555
0c6921de 2556 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2557 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2558 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2559 mem_to_mem);
dcbe765b
CM		 2560 if (ret)
2561 return ret;
79ad75f2 2562
e4c5ae7f
TV		 2563 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2564 width, height,
2565 out_width, out_height,
2566 out_width / width, DIV_FRAC(out_width, width),
2567 out_height / height, DIV_FRAC(out_height, height),
2568
2569 decim_x, decim_y,
2570 width / decim_x, height / decim_y,
2571 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2572 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2573
2574 *five_taps ? 5 : 3,
2575 core_clk, dispc_core_clk_rate());
79ad75f2 2576
8b53d991 2577 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2578 DSSERR("failed to set up scaling, "
8b53d991
CM		 2579 "required core clk rate = %lu Hz, "
2580 "current core clk rate = %lu Hz\n",
2581 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2582 return -EINVAL;
2583 }
2584
aed74b55
CM		 2585 *x_predecim = decim_x;
2586 *y_predecim = decim_y;
79ad75f2
AT		 2587 return 0;
2588}
2589
84a880fd 2590static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2591 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2592 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2593 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2594 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2595 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2596 bool replication, const struct omap_video_timings *mgr_timings,
2597 bool mem_to_mem)
80c39712 2598{
7282f1b7 2599 bool five_taps = true;
62a83183 2600 bool fieldmode = false;
79ad75f2 2601 int r, cconv = 0;
80c39712
TV		 2602 unsigned offset0, offset1;
2603 s32 row_inc;
2604 s32 pix_inc;
6be0d73e 2605 u16 frame_width, frame_height;
80c39712 2606 unsigned int field_offset = 0;
84a880fd
AT		 2607 u16 in_height = height;
2608 u16 in_width = width;
aed74b55 2609 int x_predecim = 1, y_predecim = 1;
8050cbe4 2610 bool ilace = mgr_timings->interlace;
74e16458
TV		 2611 unsigned long pclk = dispc_plane_pclk_rate(plane);
2612 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2613
e566658f 2614 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2615 return -EINVAL;
2616
c4661b33
TV		 2617 switch (color_mode) {
2618 case OMAP_DSS_COLOR_YUV2:
2619 case OMAP_DSS_COLOR_UYVY:
2620 case OMAP_DSS_COLOR_NV12:
2621 if (in_width & 1) {
2622 DSSERR("input width %d is not even for YUV format\n",
2623 in_width);
2624 return -EINVAL;
2625 }
2626 break;
2627
2628 default:
2629 break;
2630 }
2631
84a880fd
AT		 2632 out_width = out_width == 0 ? width : out_width;
2633 out_height = out_height == 0 ? height : out_height;
cf073668 2634
84a880fd 2635 if (ilace && height == out_height)
62a83183 2636 fieldmode = true;
80c39712
TV		 2637
2638 if (ilace) {
2639 if (fieldmode)
aed74b55 2640 in_height /= 2;
8eeb7019 2641 pos_y /= 2;
aed74b55 2642 out_height /= 2;
80c39712
TV		 2643
2644 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2645 "out_height %d\n", in_height, pos_y,
2646 out_height);
80c39712
TV		 2647 }
2648
84a880fd 2649 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2650 return -EINVAL;
2651
74e16458 2652 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2653 in_height, out_width, out_height, color_mode,
2654 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2655 rotation_type, mem_to_mem);
79ad75f2
AT		 2656 if (r)
2657 return r;
80c39712 2658
eec77da2
TV		 2659 in_width = in_width / x_predecim;
2660 in_height = in_height / y_predecim;
aed74b55 2661
c4661b33
TV		 2662 if (x_predecim > 1 || y_predecim > 1)
2663 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2664 x_predecim, y_predecim, in_width, in_height);
2665
2666 switch (color_mode) {
2667 case OMAP_DSS_COLOR_YUV2:
2668 case OMAP_DSS_COLOR_UYVY:
2669 case OMAP_DSS_COLOR_NV12:
2670 if (in_width & 1) {
2671 DSSDBG("predecimated input width is not even for YUV format\n");
2672 DSSDBG("adjusting input width %d -> %d\n",
2673 in_width, in_width & ~1);
2674
2675 in_width &= ~1;
2676 }
2677 break;
2678
2679 default:
2680 break;
2681 }
2682
84a880fd
AT		 2683 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2684 color_mode == OMAP_DSS_COLOR_UYVY ||
2685 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2686 cconv = 1;
80c39712
TV		 2687
2688 if (ilace && !fieldmode) {
2689 /*
2690 * when downscaling the bottom field may have to start several
2691 * source lines below the top field. Unfortunately ACCUI
2692 * registers will only hold the fractional part of the offset
2693 * so the integer part must be added to the base address of the
2694 * bottom field.
2695 */
aed74b55 2696 if (!in_height || in_height == out_height)
80c39712
TV		 2697 field_offset = 0;
2698 else
aed74b55 2699 field_offset = in_height / out_height / 2;
80c39712
TV		 2700 }
2701
2702 /* Fields are independent but interleaved in memory. */
2703 if (fieldmode)
2704 field_offset = 1;
2705
c6eee968
TV		 2706 offset0 = 0;
2707 offset1 = 0;
2708 row_inc = 0;
2709 pix_inc = 0;
2710
6be0d73e
AT		 2711 if (plane == OMAP_DSS_WB) {
2712 frame_width = out_width;
2713 frame_height = out_height;
2714 } else {
2715 frame_width = in_width;
2716 frame_height = height;
2717 }
2718
84a880fd 2719 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2720 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2721 color_mode, fieldmode, field_offset,
65e006ff
CM		 2722 &offset0, &offset1, &row_inc, &pix_inc,
2723 x_predecim, y_predecim);
84a880fd 2724 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2725 calc_dma_rotation_offset(rotation, mirror, screen_width,
2726 frame_width, frame_height,
84a880fd 2727 color_mode, fieldmode, field_offset,
aed74b55
CM		 2728 &offset0, &offset1, &row_inc, &pix_inc,
2729 x_predecim, y_predecim);
80c39712 2730 else
84a880fd 2731 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2732 screen_width, frame_width, frame_height,
84a880fd 2733 color_mode, fieldmode, field_offset,
aed74b55
CM		 2734 &offset0, &offset1, &row_inc, &pix_inc,
2735 x_predecim, y_predecim);
80c39712
TV		 2736
2737 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2738 offset0, offset1, row_inc, pix_inc);
2739
84a880fd 2740 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2741
84a880fd 2742 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2743
b7536d67
TV		 2744 if (dispc.feat->reverse_ilace_field_order)
2745 swap(offset0, offset1);
2746
84a880fd
AT		 2747 dispc_ovl_set_ba0(plane, paddr + offset0);
2748 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2749
84a880fd
AT		 2750 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2751 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2752 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2753 }
2754
f2aee319
TV		 2755 if (dispc.feat->last_pixel_inc_missing)
2756 row_inc += pix_inc - 1;
2757
f0e5caab
TV		 2758 dispc_ovl_set_row_inc(plane, row_inc);
2759 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2760
84a880fd 2761 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2762 in_height, out_width, out_height);
80c39712 2763
84a880fd 2764 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2765
78b687fc 2766 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2767
5b54ed3e 2768 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2769 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2770 out_height, ilace, five_taps, fieldmode,
84a880fd 2771 color_mode, rotation);
78b687fc 2772 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2773 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2774 }
2775
c35eeb2e
AT		 2776 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2777 color_mode);
80c39712 2778
84a880fd
AT		 2779 dispc_ovl_set_zorder(plane, caps, zorder);
2780 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2781 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2782
d79db853 2783 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2784
80c39712
TV		 2785 return 0;
2786}
2787
84a880fd 2788int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2789 bool replication, const struct omap_video_timings *mgr_timings,
2790 bool mem_to_mem)
84a880fd
AT		 2791{
2792 int r;
16bf20c7 2793 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2794 enum omap_channel channel;
2795
2796 channel = dispc_ovl_get_channel_out(plane);
2797
24f13a66
AB		 2798 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2799 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2800 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd
AT		 2801 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2802 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2803
16bf20c7 2804 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2805 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2806 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2807 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2808 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2809
2810 return r;
2811}
348be69d 2812EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2813
749feffa 2814int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2815 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2816{
2817 int r;
9e4a0fc7 2818 u32 l;
749feffa
AT		 2819 enum omap_plane plane = OMAP_DSS_WB;
2820 const int pos_x = 0, pos_y = 0;
2821 const u8 zorder = 0, global_alpha = 0;
2822 const bool replication = false;
9e4a0fc7 2823 bool truncation;
81899060 2824 int in_width = mgr_timings->hactive;
fb7f3c43 2825 int in_height = mgr_timings->vactive;
749feffa
AT		 2826 enum omap_overlay_caps caps =
2827 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2828
2829 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2830 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2831 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2832 wi->mirror);
2833
2834 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2835 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2836 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2837 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2838 replication, mgr_timings, mem_to_mem);
2839
2840 switch (wi->color_mode) {
2841 case OMAP_DSS_COLOR_RGB16:
2842 case OMAP_DSS_COLOR_RGB24P:
2843 case OMAP_DSS_COLOR_ARGB16:
2844 case OMAP_DSS_COLOR_RGBA16:
2845 case OMAP_DSS_COLOR_RGB12U:
2846 case OMAP_DSS_COLOR_ARGB16_1555:
2847 case OMAP_DSS_COLOR_XRGB16_1555:
2848 case OMAP_DSS_COLOR_RGBX16:
2849 truncation = true;
2850 break;
2851 default:
2852 truncation = false;
2853 break;
2854 }
2855
2856 /* setup extra DISPC_WB_ATTRIBUTES */
2857 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2858 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2859 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
4c055ce0
TV		 2860 if (mem_to_mem)
2861 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
98cd5796
TV		 2862 else
2863 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
9e4a0fc7 2864 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa 2865
98cd5796
TV		 2866 if (mem_to_mem) {
2867 /* WBDELAYCOUNT */
2868 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2869 } else {
2870 int wbdelay;
2871
0996c68e 2872 wbdelay = min(mgr_timings->vfront_porch +
458540c6 2873 mgr_timings->vsync_len + mgr_timings->vback_porch, 255);
98cd5796
TV		 2874
2875 /* WBDELAYCOUNT */
2876 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2877 }
2878
749feffa
AT		 2879 return r;
2880}
2881
f0e5caab 2882int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2883{
e6d80f95
TV		 2884 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2885
9b372c2d 2886 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2887
2888 return 0;
80c39712 2889}
348be69d 2890EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2891
04bd8ac1
TV		 2892bool dispc_ovl_enabled(enum omap_plane plane)
2893{
2894 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2895}
348be69d 2896EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2897
7b9cb5ee
TV		 2898enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2899{
2900 return dss_feat_get_supported_outputs(channel);
2901}
2902EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);
2903
f1a813d3 2904void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2905{
efa70b3b
CM		 2906 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2907 /* flush posted write */
2908 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2909}
348be69d 2910EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2911
65398511
TV		 2912bool dispc_mgr_is_enabled(enum omap_channel channel)
2913{
2914 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2915}
348be69d 2916EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2917
0b23e5b8
AT		 2918void dispc_wb_enable(bool enable)
2919{
916188a4 2920 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2921}
2922
2923bool dispc_wb_is_enabled(void)
2924{
916188a4 2925 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2926}
2927
fb2cec1f 2928static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2929{
6ced40bf
AT		 2930 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2931 return;
2932
80c39712 2933 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2934}
2935
2936void dispc_lcd_enable_signal(bool enable)
2937{
6ced40bf
AT		 2938 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2939 return;
2940
80c39712 2941 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2942}
2943
2944void dispc_pck_free_enable(bool enable)
2945{
6ced40bf
AT		 2946 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2947 return;
2948
80c39712 2949 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2950}
2951
fb2cec1f 2952static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2953{
efa70b3b 2954 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2955}
2956
2957
fb2cec1f 2958static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2959{
d21f43bc 2960 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2961}
2962
65904155 2963static void dispc_set_loadmode(enum omap_dss_load_mode mode)
80c39712 2964{
80c39712 2965 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2966}
2967
2968
c64dca40 2969static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2970{
8613b000 2971 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2972}
2973
c64dca40 2974static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2975 enum omap_dss_trans_key_type type,
2976 u32 trans_key)
2977{
efa70b3b 2978 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2979
8613b000 2980 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2981}
2982
c64dca40 2983static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2984{
efa70b3b 2985 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2986}
11354dd5 2987
c64dca40
TV		 2988static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2989 bool enable)
80c39712 2990{
11354dd5 2991 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2992 return;
2993
80c39712
TV		 2994 if (ch == OMAP_DSS_CHANNEL_LCD)
2995 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2996 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2997 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2998}
11354dd5 2999
c64dca40 3000void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 3001 const struct omap_overlay_manager_info *info)
c64dca40
TV		 3002{
3003 dispc_mgr_set_default_color(channel, info->default_color);
3004 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3005 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3006 dispc_mgr_enable_alpha_fixed_zorder(channel,
3007 info->partial_alpha_enabled);
3008 if (dss_has_feature(FEAT_CPR)) {
3009 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3010 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3011 }
3012}
348be69d 3013EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 3014
fb2cec1f 3015static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 3016{
3017 int code;
3018
3019 switch (data_lines) {
3020 case 12:
3021 code = 0;
3022 break;
3023 case 16:
3024 code = 1;
3025 break;
3026 case 18:
3027 code = 2;
3028 break;
3029 case 24:
3030 code = 3;
3031 break;
3032 default:
3033 BUG();
3034 return;
3035 }
3036
efa70b3b 3037 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 3038}
3039
fb2cec1f 3040static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 3041{
3042 u32 l;
569969d6 3043 int gpout0, gpout1;
80c39712
TV		 3044
3045 switch (mode) {
569969d6
AT		 3046 case DSS_IO_PAD_MODE_RESET:
3047 gpout0 = 0;
3048 gpout1 = 0;
80c39712 3049 break;
569969d6
AT		 3050 case DSS_IO_PAD_MODE_RFBI:
3051 gpout0 = 1;
80c39712
TV		 3052 gpout1 = 0;
3053 break;
569969d6
AT		 3054 case DSS_IO_PAD_MODE_BYPASS:
3055 gpout0 = 1;
80c39712
TV		 3056 gpout1 = 1;
3057 break;
80c39712
TV		 3058 default:
3059 BUG();
3060 return;
3061 }
3062
569969d6
AT		 3063 l = dispc_read_reg(DISPC_CONTROL);
3064 l = FLD_MOD(l, gpout0, 15, 15);
3065 l = FLD_MOD(l, gpout1, 16, 16);
3066 dispc_write_reg(DISPC_CONTROL, l);
3067}
3068
fb2cec1f 3069static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 3070{
efa70b3b 3071 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 3072}
3073
fb2cec1f
TV		 3074void dispc_mgr_set_lcd_config(enum omap_channel channel,
3075 const struct dss_lcd_mgr_config *config)
3076{
3077 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3078
3079 dispc_mgr_enable_stallmode(channel, config->stallmode);
3080 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3081
3082 dispc_mgr_set_clock_div(channel, &config->clock_info);
3083
3084 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3085
3086 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3087
3088 dispc_mgr_set_lcd_type_tft(channel);
3089}
348be69d 3090EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 3091
8f366162
AT		 3092static bool _dispc_mgr_size_ok(u16 width, u16 height)
3093{
33b89928
AT		 3094 return width <= dispc.feat->mgr_width_max &&
3095 height <= dispc.feat->mgr_height_max;
8f366162
AT		 3096}
3097
4dc2250d 3098static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp,
80c39712
TV		 3099 int vsw, int vfp, int vbp)
3100{
4dc2250d 3101 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max ||
dcbe765b
CM		 3102 hfp < 1 || hfp > dispc.feat->hp_max ||
3103 hbp < 1 || hbp > dispc.feat->hp_max ||
3104 vsw < 1 || vsw > dispc.feat->sw_max ||
3105 vfp < 0 || vfp > dispc.feat->vp_max ||
3106 vbp < 0 || vbp > dispc.feat->vp_max)
3107 return false;
80c39712
TV		 3108 return true;
3109}
3110
ca5ca69c
AT		 3111static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3112 unsigned long pclk)
3113{
3114 if (dss_mgr_is_lcd(channel))
0cac5b61 3115 return pclk <= dispc.feat->max_lcd_pclk;
ca5ca69c 3116 else
0cac5b61 3117 return pclk <= dispc.feat->max_tv_pclk;
ca5ca69c
AT		 3118}
3119
8f366162 3120bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 3121 const struct omap_video_timings *timings)
80c39712 3122{
fb7f3c43 3123 if (!_dispc_mgr_size_ok(timings->hactive, timings->vactive))
eadd33bb 3124 return false;
8f366162 3125
eadd33bb
TV		 3126 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3127 return false;
ca5ca69c
AT		 3128
3129 if (dss_mgr_is_lcd(channel)) {
beb8384d 3130 /* TODO: OMAP4+ supports interlace for LCD outputs */
eadd33bb
TV		 3131 if (timings->interlace)
3132 return false;
beb8384d 3133
0a30e150 3134 if (!_dispc_lcd_timings_ok(timings->hsync_len,
a85f4a80 3135 timings->hfront_porch, timings->hback_porch,
0996c68e 3136 timings->vsync_len, timings->vfront_porch,
458540c6 3137 timings->vback_porch))
eadd33bb 3138 return false;
ca5ca69c 3139 }
8f366162 3140
eadd33bb 3141 return true;
80c39712
TV		 3142}
3143
4dc2250d 3144static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len,
655e2941
AT		 3145 int hfp, int hbp, int vsw, int vfp, int vbp,
3146 enum omap_dss_signal_level vsync_level,
3147 enum omap_dss_signal_level hsync_level,
3148 enum omap_dss_signal_edge data_pclk_edge,
3149 enum omap_dss_signal_level de_level,
3150 enum omap_dss_signal_edge sync_pclk_edge)
3151
80c39712 3152{
655e2941 3153 u32 timing_h, timing_v, l;
ed351881 3154 bool onoff, rf, ipc, vs, hs, de;
80c39712 3155
4dc2250d 3156 timing_h = FLD_VAL(hsync_len-1, dispc.feat->sw_start, 0) |
dcbe765b
CM		 3157 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3158 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3159 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3160 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3161 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3162
64ba4f74
SS		 3163 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3164 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 3165
ed351881
TV		 3166 switch (vsync_level) {
3167 case OMAPDSS_SIG_ACTIVE_LOW:
3168 vs = true;
3169 break;
3170 case OMAPDSS_SIG_ACTIVE_HIGH:
3171 vs = false;
3172 break;
3173 default:
3174 BUG();
3175 }
3176
3177 switch (hsync_level) {
3178 case OMAPDSS_SIG_ACTIVE_LOW:
3179 hs = true;
3180 break;
3181 case OMAPDSS_SIG_ACTIVE_HIGH:
3182 hs = false;
3183 break;
3184 default:
3185 BUG();
3186 }
3187
3188 switch (de_level) {
3189 case OMAPDSS_SIG_ACTIVE_LOW:
3190 de = true;
3191 break;
3192 case OMAPDSS_SIG_ACTIVE_HIGH:
3193 de = false;
3194 break;
3195 default:
3196 BUG();
3197 }
3198
655e2941
AT		 3199 switch (data_pclk_edge) {
3200 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3201 ipc = false;
3202 break;
3203 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3204 ipc = true;
3205 break;
655e2941
AT		 3206 default:
3207 BUG();
3208 }
3209
7a16360d
TV		 3210 /* always use the 'rf' setting */
3211 onoff = true;
3212
655e2941 3213 switch (sync_pclk_edge) {
655e2941 3214 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
655e2941
AT		 3215 rf = false;
3216 break;
3217 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
655e2941
AT		 3218 rf = true;
3219 break;
3220 default:
3221 BUG();
cf6ac4ce 3222 }
655e2941 3223
d80e02ef
TV		 3224 l = FLD_VAL(onoff, 17, 17) |
3225 FLD_VAL(rf, 16, 16) |
ed351881 3226 FLD_VAL(de, 15, 15) |
d80e02ef 3227 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 3228 FLD_VAL(hs, 13, 13) |
3229 FLD_VAL(vs, 12, 12);
d80e02ef 3230
e5f80917
TV		 3231 /* always set ALIGN bit when available */
3232 if (dispc.feat->supports_sync_align)
3233 l |= (1 << 18);
3234
655e2941 3235 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 3236
3237 if (dispc.syscon_pol) {
3238 const int shifts[] = {
3239 [OMAP_DSS_CHANNEL_LCD] = 0,
3240 [OMAP_DSS_CHANNEL_LCD2] = 1,
3241 [OMAP_DSS_CHANNEL_LCD3] = 2,
3242 };
3243
3244 u32 mask, val;
3245
3246 mask = (1 << 0) | (1 << 3) | (1 << 6);
3247 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3248
3249 mask <<= 16 + shifts[channel];
3250 val <<= 16 + shifts[channel];
3251
3252 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3253 mask, val);
3254 }
80c39712
TV		 3255}
3256
3257/* change name to mode? */
c51d921a 3258void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3259 const struct omap_video_timings *timings)
80c39712
TV		 3260{
3261 unsigned xtot, ytot;
3262 unsigned long ht, vt;
2aefad49 3263 struct omap_video_timings t = *timings;
80c39712 3264
fb7f3c43 3265 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
80c39712 3266
2aefad49 3267 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3268 BUG();
c6eee968
TV		 3269 return;
3270 }
80c39712 3271
dd88b7a6 3272 if (dss_mgr_is_lcd(channel)) {
458540c6
PU		 3273 _dispc_mgr_set_lcd_timings(channel,
3274 t.hsync_len, t.hfront_porch, t.hback_porch,
3275 t.vsync_len, t.vfront_porch, t.vback_porch,
a85f4a80
PU		 3276 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3277 t.de_level, t.sync_pclk_edge);
80c39712 3278
a85f4a80 3279 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
458540c6 3280 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
80c39712 3281
d8d78941
TV		 3282 ht = timings->pixelclock / xtot;
3283 vt = timings->pixelclock / xtot / ytot;
c51d921a 3284
d8d78941 3285 DSSDBG("pck %u\n", timings->pixelclock);
4dc2250d 3286 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
a85f4a80 3287 t.hsync_len, t.hfront_porch, t.hback_porch,
458540c6 3288 t.vsync_len, t.vfront_porch, t.vback_porch);
655e2941
AT		 3289 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3290 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3291 t.de_level, t.sync_pclk_edge);
80c39712 3292
c51d921a 3293 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3294 } else {
0bcfdba6 3295 if (t.interlace)
fb7f3c43 3296 t.vactive /= 2;
3a38ed53
TV		 3297
3298 if (dispc.feat->supports_double_pixel)
3299 REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0,
3300 19, 17);
c51d921a 3301 }
8f366162 3302
fb7f3c43 3303 dispc_mgr_set_size(channel, t.hactive, t.vactive);
80c39712 3304}
348be69d 3305EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3306
26d9dd0d 3307static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3308 u16 pck_div)
80c39712
TV		 3309{
3310 BUG_ON(lck_div < 1);
9eaaf207 3311 BUG_ON(pck_div < 1);
80c39712 3312
ce7fa5eb 3313 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3314 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3 3315
0bcfdba6 3316 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
7b3926b3
TV		 3317 channel == OMAP_DSS_CHANNEL_LCD)
3318 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3319}
3320
26d9dd0d 3321static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3322 int *pck_div)
80c39712
TV		 3323{
3324 u32 l;
ce7fa5eb 3325 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3326 *lck_div = FLD_GET(l, 23, 16);
3327 *pck_div = FLD_GET(l, 7, 0);
3328}
3329
65904155 3330static unsigned long dispc_fclk_rate(void)
80c39712 3331{
ef03b401
TV		 3332 unsigned long r;
3333 enum dss_clk_source src;
80c39712 3334
ef03b401
TV		 3335 src = dss_get_dispc_clk_source();
3336
3337 if (src == DSS_CLK_SRC_FCK) {
5aaee69d 3338 r = dss_get_dispc_clk_rate();
ef03b401
TV		 3339 } else {
3340 struct dss_pll *pll;
3341 unsigned clkout_idx;
93550927 3342
ef03b401
TV		 3343 pll = dss_pll_find_by_src(src);
3344 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
93550927 3345
ef03b401 3346 r = pll->cinfo.clkout[clkout_idx];
66534e8e
AT		 3347 }
3348
80c39712
TV		 3349 return r;
3350}
3351
65904155 3352static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712
TV		 3353{
3354 int lcd;
3355 unsigned long r;
01575776 3356 enum dss_clk_source src;
80c39712 3357
01575776
TV		 3358 /* for TV, LCLK rate is the FCLK rate */
3359 if (!dss_mgr_is_lcd(channel))
3360 return dispc_fclk_rate();
80c39712 3361
01575776 3362 src = dss_get_lcd_clk_source(channel);
93550927 3363
01575776
TV		 3364 if (src == DSS_CLK_SRC_FCK) {
3365 r = dss_get_dispc_clk_rate();
3366 } else {
3367 struct dss_pll *pll;
3368 unsigned clkout_idx;
93550927 3369
01575776
TV		 3370 pll = dss_pll_find_by_src(src);
3371 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
80c39712 3372
01575776 3373 r = pll->cinfo.clkout[clkout_idx];
c31cba8a 3374 }
01575776
TV		 3375
3376 lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3377
3378 return r / lcd;
80c39712
TV		 3379}
3380
65904155 3381static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3382{
80c39712 3383 unsigned long r;
80c39712 3384
dd88b7a6 3385 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3386 int pcd;
3387 u32 l;
80c39712 3388
c3dc6a7a 3389 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3390
c3dc6a7a 3391 pcd = FLD_GET(l, 7, 0);
80c39712 3392
c3dc6a7a
AT		 3393 r = dispc_mgr_lclk_rate(channel);
3394
3395 return r / pcd;
3396 } else {
5391e87d 3397 return dispc.tv_pclk_rate;
c3dc6a7a 3398 }
80c39712
TV		 3399}
3400
5391e87d
TV		 3401void dispc_set_tv_pclk(unsigned long pclk)
3402{
3403 dispc.tv_pclk_rate = pclk;
3404}
3405
65904155 3406static unsigned long dispc_core_clk_rate(void)
8b53d991 3407{
7b3926b3 3408 return dispc.core_clk_rate;
8b53d991
CM		 3409}
3410
3e8a6ff2
AT		 3411static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3412{
251886d8
TV		 3413 enum omap_channel channel;
3414
3415 if (plane == OMAP_DSS_WB)
3416 return 0;
3417
3418 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3419
3420 return dispc_mgr_pclk_rate(channel);
3421}
3422
3423static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3424{
251886d8
TV		 3425 enum omap_channel channel;
3426
3427 if (plane == OMAP_DSS_WB)
3428 return 0;
3429
3430 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3431
c31cba8a 3432 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3433}
c31cba8a 3434
6f1891fc 3435static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3436{
3437 int lcd, pcd;
dc0352d1 3438 enum dss_clk_source lcd_clk_src;
6f1891fc
CM		 3439
3440 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3441
3442 lcd_clk_src = dss_get_lcd_clk_source(channel);
3443
557a1544 3444 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
407bd564 3445 dss_get_clk_source_name(lcd_clk_src));
6f1891fc
CM		 3446
3447 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3448
3449 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3450 dispc_mgr_lclk_rate(channel), lcd);
3451 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3452 dispc_mgr_pclk_rate(channel), pcd);
3453}
3454
3455void dispc_dump_clocks(struct seq_file *s)
3456{
3457 int lcd;
0cf35df3 3458 u32 l;
dc0352d1 3459 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3460
4fbafaf3
TV		 3461 if (dispc_runtime_get())
3462 return;
80c39712 3463
80c39712
TV		 3464 seq_printf(s, "- DISPC -\n");
3465
557a1544 3466 seq_printf(s, "dispc fclk source = %s\n",
407bd564 3467 dss_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3468
3469 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3470
0cf35df3
MR		 3471 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3472 seq_printf(s, "- DISPC-CORE-CLK -\n");
3473 l = dispc_read_reg(DISPC_DIVISOR);
3474 lcd = FLD_GET(l, 23, 16);
3475
3476 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3477 (dispc_fclk_rate()/lcd), lcd);
3478 }
2a205f34 3479
6f1891fc 3480 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3481
6f1891fc
CM		 3482 if (dss_has_feature(FEAT_MGR_LCD2))
3483 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3484 if (dss_has_feature(FEAT_MGR_LCD3))
3485 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3486
3487 dispc_runtime_put();
80c39712
TV		 3488}
3489
e40402cf 3490static void dispc_dump_regs(struct seq_file *s)
80c39712 3491{
4dd2da15
AT		 3492 int i, j;
3493 const char *mgr_names[] = {
3494 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3495 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3496 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3497 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3498 };
3499 const char *ovl_names[] = {
3500 [OMAP_DSS_GFX] = "GFX",
3501 [OMAP_DSS_VIDEO1] = "VID1",
3502 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3503 [OMAP_DSS_VIDEO3] = "VID3",
06c525fe 3504 [OMAP_DSS_WB] = "WB",
4dd2da15
AT		 3505 };
3506 const char **p_names;
3507
9b372c2d 3508#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3509
4fbafaf3
TV		 3510 if (dispc_runtime_get())
3511 return;
80c39712 3512
5010be80 3513 /* DISPC common registers */
80c39712
TV		 3514 DUMPREG(DISPC_REVISION);
3515 DUMPREG(DISPC_SYSCONFIG);
3516 DUMPREG(DISPC_SYSSTATUS);
3517 DUMPREG(DISPC_IRQSTATUS);
3518 DUMPREG(DISPC_IRQENABLE);
3519 DUMPREG(DISPC_CONTROL);
3520 DUMPREG(DISPC_CONFIG);
3521 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3522 DUMPREG(DISPC_LINE_STATUS);
3523 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3524 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3525 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3526 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3527 if (dss_has_feature(FEAT_MGR_LCD2)) {
3528 DUMPREG(DISPC_CONTROL2);
3529 DUMPREG(DISPC_CONFIG2);
5010be80 3530 }
6f1891fc
CM		 3531 if (dss_has_feature(FEAT_MGR_LCD3)) {
3532 DUMPREG(DISPC_CONTROL3);
3533 DUMPREG(DISPC_CONFIG3);
3534 }
29fceeeb
TV		 3535 if (dss_has_feature(FEAT_MFLAG))
3536 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3537
3538#undef DUMPREG
3539
3540#define DISPC_REG(i, name) name(i)
4dd2da15 3541#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3542 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3543 dispc_read_reg(DISPC_REG(i, r)))
3544
4dd2da15 3545 p_names = mgr_names;
5010be80 3546
4dd2da15
AT		 3547 /* DISPC channel specific registers */
3548 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3549 DUMPREG(i, DISPC_DEFAULT_COLOR);
3550 DUMPREG(i, DISPC_TRANS_COLOR);
3551 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3552
4dd2da15
AT		 3553 if (i == OMAP_DSS_CHANNEL_DIGIT)
3554 continue;
5010be80 3555
4dd2da15
AT		 3556 DUMPREG(i, DISPC_TIMING_H);
3557 DUMPREG(i, DISPC_TIMING_V);
3558 DUMPREG(i, DISPC_POL_FREQ);
3559 DUMPREG(i, DISPC_DIVISORo);
5010be80 3560
4dd2da15
AT		 3561 DUMPREG(i, DISPC_DATA_CYCLE1);
3562 DUMPREG(i, DISPC_DATA_CYCLE2);
3563 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3564
332e9d70 3565 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3566 DUMPREG(i, DISPC_CPR_COEF_R);
3567 DUMPREG(i, DISPC_CPR_COEF_G);
3568 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3569 }
2a205f34 3570 }
80c39712 3571
4dd2da15
AT		 3572 p_names = ovl_names;
3573
3574 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3575 DUMPREG(i, DISPC_OVL_BA0);
3576 DUMPREG(i, DISPC_OVL_BA1);
3577 DUMPREG(i, DISPC_OVL_POSITION);
3578 DUMPREG(i, DISPC_OVL_SIZE);
3579 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3580 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3581 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3582 DUMPREG(i, DISPC_OVL_ROW_INC);
3583 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3584
4dd2da15
AT		 3585 if (dss_has_feature(FEAT_PRELOAD))
3586 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3587 if (dss_has_feature(FEAT_MFLAG))
3588 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3589
3590 if (i == OMAP_DSS_GFX) {
3591 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3592 DUMPREG(i, DISPC_OVL_TABLE_BA);
3593 continue;
3594 }
3595
3596 DUMPREG(i, DISPC_OVL_FIR);
3597 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3598 DUMPREG(i, DISPC_OVL_ACCU0);
3599 DUMPREG(i, DISPC_OVL_ACCU1);
3600 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3601 DUMPREG(i, DISPC_OVL_BA0_UV);
3602 DUMPREG(i, DISPC_OVL_BA1_UV);
3603 DUMPREG(i, DISPC_OVL_FIR2);
3604 DUMPREG(i, DISPC_OVL_ACCU2_0);
3605 DUMPREG(i, DISPC_OVL_ACCU2_1);
3606 }
3607 if (dss_has_feature(FEAT_ATTR2))
3608 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3609 }
5010be80 3610
20efbc35 3611 if (dispc.feat->has_writeback) {
06c525fe
TV		 3612 i = OMAP_DSS_WB;
3613 DUMPREG(i, DISPC_OVL_BA0);
3614 DUMPREG(i, DISPC_OVL_BA1);
3615 DUMPREG(i, DISPC_OVL_SIZE);
3616 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3617 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3618 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3619 DUMPREG(i, DISPC_OVL_ROW_INC);
3620 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3621
3622 if (dss_has_feature(FEAT_MFLAG))
3623 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3624
3625 DUMPREG(i, DISPC_OVL_FIR);
3626 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3627 DUMPREG(i, DISPC_OVL_ACCU0);
3628 DUMPREG(i, DISPC_OVL_ACCU1);
3629 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3630 DUMPREG(i, DISPC_OVL_BA0_UV);
3631 DUMPREG(i, DISPC_OVL_BA1_UV);
3632 DUMPREG(i, DISPC_OVL_FIR2);
3633 DUMPREG(i, DISPC_OVL_ACCU2_0);
3634 DUMPREG(i, DISPC_OVL_ACCU2_1);
3635 }
3636 if (dss_has_feature(FEAT_ATTR2))
3637 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3638 }
3639
5010be80
AT		 3640#undef DISPC_REG
3641#undef DUMPREG
3642
3643#define DISPC_REG(plane, name, i) name(plane, i)
3644#define DUMPREG(plane, name, i) \
4dd2da15 3645 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3646 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3647 dispc_read_reg(DISPC_REG(plane, name, i)))
3648
4dd2da15 3649 /* Video pipeline coefficient registers */
332e9d70 3650
4dd2da15
AT		 3651 /* start from OMAP_DSS_VIDEO1 */
3652 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3653 for (j = 0; j < 8; j++)
3654 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3655
4dd2da15
AT		 3656 for (j = 0; j < 8; j++)
3657 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3658
4dd2da15
AT		 3659 for (j = 0; j < 5; j++)
3660 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3661
4dd2da15
AT		 3662 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3663 for (j = 0; j < 8; j++)
3664 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3665 }
3666
3667 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3668 for (j = 0; j < 8; j++)
3669 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3670
3671 for (j = 0; j < 8; j++)
3672 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3673
3674 for (j = 0; j < 8; j++)
3675 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3676 }
332e9d70 3677 }
80c39712 3678
4fbafaf3 3679 dispc_runtime_put();
5010be80
AT		 3680
3681#undef DISPC_REG
80c39712
TV		 3682#undef DUMPREG
3683}
3684
80c39712
TV		 3685/* calculate clock rates using dividers in cinfo */
3686int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3687 struct dispc_clock_info *cinfo)
3688{
80c39712
TV		 3689 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3690 return -EINVAL;
9eaaf207 3691 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3692 return -EINVAL;
80c39712 3693
80c39712
TV		 3694 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3695 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3696
80c39712
TV		 3697 return 0;
3698}
80c39712 3699
7c284e6e
TV		 3700bool dispc_div_calc(unsigned long dispc,
3701 unsigned long pck_min, unsigned long pck_max,
3702 dispc_div_calc_func func, void *data)
3703{
3704 int lckd, lckd_start, lckd_stop;
3705 int pckd, pckd_start, pckd_stop;
3706 unsigned long pck, lck;
3707 unsigned long lck_max;
3708 unsigned long pckd_hw_min, pckd_hw_max;
3709 unsigned min_fck_per_pck;
3710 unsigned long fck;
80c39712 3711
7c284e6e
TV		 3712#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3713 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3714#else
3715 min_fck_per_pck = 0;
3716#endif
80c39712 3717
7c284e6e
TV		 3718 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3719 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3720
7c284e6e 3721 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3722
7c284e6e
TV		 3723 pck_min = pck_min ? pck_min : 1;
3724 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3725
7c284e6e
TV		 3726 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3727 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3728
7c284e6e
TV		 3729 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3730 lck = dispc / lckd;
80c39712 3731
7c284e6e
TV		 3732 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3733 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3734
7c284e6e
TV		 3735 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3736 pck = lck / pckd;
80c39712 3737
7c284e6e
TV		 3738 /*
3739 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3740 * clock, which means we're configuring DISPC fclk here
3741 * also. Thus we need to use the calculated lck. For
3742 * OMAP4+ the DISPC fclk is a separate clock.
3743 */
3744 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3745 fck = dispc_core_clk_rate();
3746 else
3747 fck = lck;
3748
3749 if (fck < pck * min_fck_per_pck)
3750 continue;
3751
3752 if (func(lckd, pckd, lck, pck, data))
3753 return true;
3754 }
3755 }
3756
3757 return false;
80c39712
TV		 3758}
3759
f0d08f89 3760void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3761 const struct dispc_clock_info *cinfo)
80c39712
TV		 3762{
3763 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3764 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3765
26d9dd0d 3766 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3767}
3768
26d9dd0d 3769int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3770 struct dispc_clock_info *cinfo)
80c39712
TV		 3771{
3772 unsigned long fck;
3773
3774 fck = dispc_fclk_rate();
3775
ce7fa5eb
MR		 3776 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3777 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3778
3779 cinfo->lck = fck / cinfo->lck_div;
3780 cinfo->pck = cinfo->lck / cinfo->pck_div;
3781
3782 return 0;
3783}
3784
4e0397cf
TV		 3785u32 dispc_read_irqstatus(void)
3786{
3787 return dispc_read_reg(DISPC_IRQSTATUS);
3788}
348be69d 3789EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3790
3791void dispc_clear_irqstatus(u32 mask)
3792{
3793 dispc_write_reg(DISPC_IRQSTATUS, mask);
3794}
348be69d 3795EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3796
3797u32 dispc_read_irqenable(void)
3798{
3799 return dispc_read_reg(DISPC_IRQENABLE);
3800}
348be69d 3801EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3802
3803void dispc_write_irqenable(u32 mask)
3804{
3805 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3806
3807 /* clear the irqstatus for newly enabled irqs */
3808 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3809
3810 dispc_write_reg(DISPC_IRQENABLE, mask);
3811}
348be69d 3812EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3813
80c39712
TV		 3814void dispc_enable_sidle(void)
3815{
3816 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3817}
3818
3819void dispc_disable_sidle(void)
3820{
3821 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3822}
3823
acc3a231
JS		 3824u32 dispc_mgr_gamma_size(enum omap_channel channel)
3825{
3826 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3827
3828 if (!dispc.feat->has_gamma_table)
3829 return 0;
3830
3831 return gdesc->len;
3832}
3833EXPORT_SYMBOL(dispc_mgr_gamma_size);
3834
3835static void dispc_mgr_write_gamma_table(enum omap_channel channel)
3836{
3837 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3838 u32 *table = dispc.gamma_table[channel];
3839 unsigned int i;
3840
3841 DSSDBG("%s: channel %d\n", __func__, channel);
3842
3843 for (i = 0; i < gdesc->len; ++i) {
3844 u32 v = table[i];
3845
3846 if (gdesc->has_index)
3847 v |= i << 24;
3848 else if (i == 0)
3849 v |= 1 << 31;
3850
3851 dispc_write_reg(gdesc->reg, v);
3852 }
3853}
3854
3855static void dispc_restore_gamma_tables(void)
3856{
3857 DSSDBG("%s()\n", __func__);
3858
3859 if (!dispc.feat->has_gamma_table)
3860 return;
3861
3862 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD);
3863
3864 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT);
3865
3866 if (dss_has_feature(FEAT_MGR_LCD2))
3867 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2);
3868
3869 if (dss_has_feature(FEAT_MGR_LCD3))
3870 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3);
3871}
3872
3873static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3874 { .red = 0, .green = 0, .blue = 0, },
3875 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3876};
3877
3878void dispc_mgr_set_gamma(enum omap_channel channel,
3879 const struct drm_color_lut *lut,
3880 unsigned int length)
3881{
3882 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3883 u32 *table = dispc.gamma_table[channel];
3884 uint i;
3885
3886 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3887 channel, length, gdesc->len);
3888
3889 if (!dispc.feat->has_gamma_table)
3890 return;
3891
3892 if (lut == NULL || length < 2) {
3893 lut = dispc_mgr_gamma_default_lut;
3894 length = ARRAY_SIZE(dispc_mgr_gamma_default_lut);
3895 }
3896
3897 for (i = 0; i < length - 1; ++i) {
3898 uint first = i * (gdesc->len - 1) / (length - 1);
3899 uint last = (i + 1) * (gdesc->len - 1) / (length - 1);
3900 uint w = last - first;
3901 u16 r, g, b;
3902 uint j;
3903
3904 if (w == 0)
3905 continue;
3906
3907 for (j = 0; j <= w; j++) {
3908 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3909 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3910 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w;
3911
3912 r >>= 16 - gdesc->bits;
3913 g >>= 16 - gdesc->bits;
3914 b >>= 16 - gdesc->bits;
3915
3916 table[first + j] = (r << (gdesc->bits * 2)) |
3917 (g << gdesc->bits) | b;
3918 }
3919 }
3920
3921 if (dispc.is_enabled)
3922 dispc_mgr_write_gamma_table(channel);
3923}
3924EXPORT_SYMBOL(dispc_mgr_set_gamma);
3925
3926static int dispc_init_gamma_tables(void)
3927{
3928 int channel;
3929
3930 if (!dispc.feat->has_gamma_table)
3931 return 0;
3932
3933 for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) {
3934 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3935 u32 *gt;
3936
3937 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3938 !dss_has_feature(FEAT_MGR_LCD2))
3939 continue;
3940
3941 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3942 !dss_has_feature(FEAT_MGR_LCD3))
3943 continue;
3944
3945 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len,
3946 sizeof(u32), GFP_KERNEL);
3947 if (!gt)
3948 return -ENOMEM;
3949
3950 dispc.gamma_table[channel] = gt;
3951
3952 dispc_mgr_set_gamma(channel, NULL, 0);
3953 }
3954 return 0;
3955}
3956
80c39712
TV		 3957static void _omap_dispc_initial_config(void)
3958{
3959 u32 l;
3960
0cf35df3
MR		 3961 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3962 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3963 l = dispc_read_reg(DISPC_DIVISOR);
3964 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3965 l = FLD_MOD(l, 1, 0, 0);
3966 l = FLD_MOD(l, 1, 23, 16);
3967 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3968
3969 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3970 }
3971
acc3a231
JS		 3972 /* Use gamma table mode, instead of palette mode */
3973 if (dispc.feat->has_gamma_table)
3974 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3);
3975
3976 /* For older DSS versions (FEAT_FUNCGATED) this enables
3977 * func-clock auto-gating. For newer versions
3978 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables.
3979 */
3980 if (dss_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table)
6ced40bf 3981 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3982
6e5264b0 3983 dispc_setup_color_conv_coef();
80c39712
TV		 3984
3985 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3986
42a6961c 3987 dispc_init_fifos();
5ed8cf5b
TV		 3988
3989 dispc_configure_burst_sizes();
54128701
AT		 3990
3991 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3992
3993 if (dispc.feat->mstandby_workaround)
3994 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
c64aa3a6
TV		 3995
3996 if (dss_has_feature(FEAT_MFLAG))
3997 dispc_init_mflag();
80c39712
TV		 3998}
3999
ede92695 4000static const struct dispc_features omap24xx_dispc_feats = {
dcbe765b
CM		 4001 .sw_start = 5,
4002 .fp_start = 15,
4003 .bp_start = 27,
4004 .sw_max = 64,
4005 .vp_max = 255,
4006 .hp_max = 256,
33b89928
AT		 4007 .mgr_width_start = 10,
4008 .mgr_height_start = 26,
4009 .mgr_width_max = 2048,
4010 .mgr_height_max = 2048,
ca5ca69c 4011 .max_lcd_pclk = 66500000,
dcbe765b
CM		 4012 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4013 .calc_core_clk = calc_core_clk_24xx,
42a6961c 4014 .num_fifos = 3,
cffa947d 4015 .no_framedone_tv = true,
8bc65552 4016 .set_max_preload = false,
f2aee319 4017 .last_pixel_inc_missing = true,
dcbe765b
CM		 4018};
4019
ede92695 4020static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
dcbe765b
CM		 4021 .sw_start = 5,
4022 .fp_start = 15,
4023 .bp_start = 27,
4024 .sw_max = 64,
4025 .vp_max = 255,
4026 .hp_max = 256,
33b89928
AT		 4027 .mgr_width_start = 10,
4028 .mgr_height_start = 26,
4029 .mgr_width_max = 2048,
4030 .mgr_height_max = 2048,
ca5ca69c
AT		 4031 .max_lcd_pclk = 173000000,
4032 .max_tv_pclk = 59000000,
dcbe765b
CM		 4033 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4034 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4035 .num_fifos = 3,
cffa947d 4036 .no_framedone_tv = true,
8bc65552 4037 .set_max_preload = false,
f2aee319 4038 .last_pixel_inc_missing = true,
dcbe765b
CM		 4039};
4040
ede92695 4041static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
dcbe765b
CM		 4042 .sw_start = 7,
4043 .fp_start = 19,
4044 .bp_start = 31,
4045 .sw_max = 256,
4046 .vp_max = 4095,
4047 .hp_max = 4096,
33b89928
AT		 4048 .mgr_width_start = 10,
4049 .mgr_height_start = 26,
4050 .mgr_width_max = 2048,
4051 .mgr_height_max = 2048,
ca5ca69c
AT		 4052 .max_lcd_pclk = 173000000,
4053 .max_tv_pclk = 59000000,
dcbe765b
CM		 4054 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4055 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4056 .num_fifos = 3,
cffa947d 4057 .no_framedone_tv = true,
8bc65552 4058 .set_max_preload = false,
f2aee319 4059 .last_pixel_inc_missing = true,
dcbe765b
CM		 4060};
4061
ede92695 4062static const struct dispc_features omap44xx_dispc_feats = {
dcbe765b
CM		 4063 .sw_start = 7,
4064 .fp_start = 19,
4065 .bp_start = 31,
4066 .sw_max = 256,
4067 .vp_max = 4095,
4068 .hp_max = 4096,
33b89928
AT		 4069 .mgr_width_start = 10,
4070 .mgr_height_start = 26,
4071 .mgr_width_max = 2048,
4072 .mgr_height_max = 2048,
ca5ca69c
AT		 4073 .max_lcd_pclk = 170000000,
4074 .max_tv_pclk = 185625000,
dcbe765b
CM		 4075 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4076 .calc_core_clk = calc_core_clk_44xx,
42a6961c 4077 .num_fifos = 5,
66a0f9e4 4078 .gfx_fifo_workaround = true,
8bc65552 4079 .set_max_preload = true,
e5f80917 4080 .supports_sync_align = true,
20efbc35 4081 .has_writeback = true,
3a38ed53 4082 .supports_double_pixel = true,
b7536d67 4083 .reverse_ilace_field_order = true,
acc3a231 4084 .has_gamma_table = true,
fbff010b 4085 .has_gamma_i734_bug = true,
dcbe765b
CM		 4086};
4087
ede92695 4088static const struct dispc_features omap54xx_dispc_feats = {
264236f8
AT		 4089 .sw_start = 7,
4090 .fp_start = 19,
4091 .bp_start = 31,
4092 .sw_max = 256,
4093 .vp_max = 4095,
4094 .hp_max = 4096,
4095 .mgr_width_start = 11,
4096 .mgr_height_start = 27,
4097 .mgr_width_max = 4096,
4098 .mgr_height_max = 4096,
ca5ca69c
AT		 4099 .max_lcd_pclk = 170000000,
4100 .max_tv_pclk = 186000000,
264236f8
AT		 4101 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4102 .calc_core_clk = calc_core_clk_44xx,
4103 .num_fifos = 5,
4104 .gfx_fifo_workaround = true,
d0df9a2c 4105 .mstandby_workaround = true,
8bc65552 4106 .set_max_preload = true,
e5f80917 4107 .supports_sync_align = true,
20efbc35 4108 .has_writeback = true,
3a38ed53 4109 .supports_double_pixel = true,
b7536d67 4110 .reverse_ilace_field_order = true,
acc3a231 4111 .has_gamma_table = true,
fbff010b 4112 .has_gamma_i734_bug = true,
264236f8
AT		 4113};
4114
ede92695 4115static int dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 4116{
4117 const struct dispc_features *src;
4118 struct dispc_features *dst;
4119
84b47623 4120 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 4121 if (!dst) {
84b47623 4122 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 4123 return -ENOMEM;
4124 }
4125
b2c7d54f 4126 switch (omapdss_get_version()) {
84b47623 4127 case OMAPDSS_VER_OMAP24xx:
dcbe765b 4128 src = &omap24xx_dispc_feats;
84b47623
TV		 4129 break;
4130
4131 case OMAPDSS_VER_OMAP34xx_ES1:
4132 src = &omap34xx_rev1_0_dispc_feats;
4133 break;
4134
4135 case OMAPDSS_VER_OMAP34xx_ES3:
4136 case OMAPDSS_VER_OMAP3630:
4137 case OMAPDSS_VER_AM35xx:
d6279d4a 4138 case OMAPDSS_VER_AM43xx:
84b47623
TV		 4139 src = &omap34xx_rev3_0_dispc_feats;
4140 break;
4141
4142 case OMAPDSS_VER_OMAP4430_ES1:
4143 case OMAPDSS_VER_OMAP4430_ES2:
4144 case OMAPDSS_VER_OMAP4:
dcbe765b 4145 src = &omap44xx_dispc_feats;
84b47623
TV		 4146 break;
4147
4148 case OMAPDSS_VER_OMAP5:
93550927 4149 case OMAPDSS_VER_DRA7xx:
264236f8 4150 src = &omap54xx_dispc_feats;
84b47623
TV		 4151 break;
4152
4153 default:
dcbe765b
CM		 4154 return -ENODEV;
4155 }
4156
4157 memcpy(dst, src, sizeof(*dst));
4158 dispc.feat = dst;
4159
4160 return 0;
4161}
4162
0925afc9
TV		 4163static irqreturn_t dispc_irq_handler(int irq, void *arg)
4164{
4165 if (!dispc.is_enabled)
4166 return IRQ_NONE;
4167
4168 return dispc.user_handler(irq, dispc.user_data);
4169}
4170
96e2e637
TV		 4171int dispc_request_irq(irq_handler_t handler, void *dev_id)
4172{
0925afc9
TV		 4173 int r;
4174
4175 if (dispc.user_handler != NULL)
4176 return -EBUSY;
4177
4178 dispc.user_handler = handler;
4179 dispc.user_data = dev_id;
4180
4181 /* ensure the dispc_irq_handler sees the values above */
4182 smp_wmb();
4183
4184 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4185 IRQF_SHARED, "OMAP DISPC", &dispc);
4186 if (r) {
4187 dispc.user_handler = NULL;
4188 dispc.user_data = NULL;
4189 }
4190
4191 return r;
96e2e637 4192}
348be69d 4193EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 4194
4195void dispc_free_irq(void *dev_id)
4196{
0925afc9
TV		 4197 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4198
4199 dispc.user_handler = NULL;
4200 dispc.user_data = NULL;
96e2e637 4201}
348be69d 4202EXPORT_SYMBOL(dispc_free_irq);
96e2e637 4203
fbff010b
JS		 4204/*
4205 * Workaround for errata i734 in DSS dispc
4206 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4207 *
4208 * For gamma tables to work on LCD1 the GFX plane has to be used at
4209 * least once after DSS HW has come out of reset. The workaround
4210 * sets up a minimal LCD setup with GFX plane and waits for one
4211 * vertical sync irq before disabling the setup and continuing with
4212 * the context restore. The physical outputs are gated during the
4213 * operation. This workaround requires that gamma table's LOADMODE
4214 * is set to 0x2 in DISPC_CONTROL1 register.
4215 *
4216 * For details see:
4217 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata
4218 * Literature Number: SWPZ037E
4219 * Or some other relevant errata document for the DSS IP version.
4220 */
4221
4222static const struct dispc_errata_i734_data {
4223 struct omap_video_timings timings;
4224 struct omap_overlay_info ovli;
4225 struct omap_overlay_manager_info mgri;
4226 struct dss_lcd_mgr_config lcd_conf;
4227} i734 = {
4228 .timings = {
fb7f3c43 4229 .hactive = 8, .vactive = 1,
fbff010b 4230 .pixelclock = 16000000,
a85f4a80 4231 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
458540c6 4232 .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
fbff010b
JS		 4233 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
4234 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
4235 .interlace = false,
4236 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
4237 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
4238 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
4239 .double_pixel = false,
4240 },
4241 .ovli = {
4242 .screen_width = 1,
4243 .width = 1, .height = 1,
4244 .color_mode = OMAP_DSS_COLOR_RGB24U,
4245 .rotation = OMAP_DSS_ROT_0,
4246 .rotation_type = OMAP_DSS_ROT_DMA,
4247 .mirror = 0,
4248 .pos_x = 0, .pos_y = 0,
4249 .out_width = 0, .out_height = 0,
4250 .global_alpha = 0xff,
4251 .pre_mult_alpha = 0,
4252 .zorder = 0,
4253 },
4254 .mgri = {
4255 .default_color = 0,
4256 .trans_enabled = false,
4257 .partial_alpha_enabled = false,
4258 .cpr_enable = false,
4259 },
4260 .lcd_conf = {
4261 .io_pad_mode = DSS_IO_PAD_MODE_BYPASS,
4262 .stallmode = false,
4263 .fifohandcheck = false,
4264 .clock_info = {
4265 .lck_div = 1,
4266 .pck_div = 2,
4267 },
4268 .video_port_width = 24,
4269 .lcden_sig_polarity = 0,
4270 },
4271};
4272
4273static struct i734_buf {
4274 size_t size;
4275 dma_addr_t paddr;
4276 void *vaddr;
4277} i734_buf;
4278
4279static int dispc_errata_i734_wa_init(void)
4280{
4281 if (!dispc.feat->has_gamma_i734_bug)
4282 return 0;
4283
4284 i734_buf.size = i734.ovli.width * i734.ovli.height *
4285 color_mode_to_bpp(i734.ovli.color_mode) / 8;
4286
4287 i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size,
4288 &i734_buf.paddr, GFP_KERNEL);
4289 if (!i734_buf.vaddr) {
4290 dev_err(&dispc.pdev->dev, "%s: dma_alloc_writecombine failed",
4291 __func__);
4292 return -ENOMEM;
4293 }
4294
4295 return 0;
4296}
4297
4298static void dispc_errata_i734_wa_fini(void)
4299{
4300 if (!dispc.feat->has_gamma_i734_bug)
4301 return;
4302
4303 dma_free_writecombine(&dispc.pdev->dev, i734_buf.size, i734_buf.vaddr,
4304 i734_buf.paddr);
4305}
4306
4307static void dispc_errata_i734_wa(void)
4308{
4309 u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD);
4310 struct omap_overlay_info ovli;
4311 struct dss_lcd_mgr_config lcd_conf;
4312 u32 gatestate;
4313 unsigned int count;
4314
4315 if (!dispc.feat->has_gamma_i734_bug)
4316 return;
4317
4318 gatestate = REG_GET(DISPC_CONFIG, 8, 4);
4319
4320 ovli = i734.ovli;
4321 ovli.paddr = i734_buf.paddr;
4322 lcd_conf = i734.lcd_conf;
4323
4324 /* Gate all LCD1 outputs */
4325 REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4);
4326
4327 /* Setup and enable GFX plane */
4328 dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD);
4329 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, false, &i734.timings, false);
4330 dispc_ovl_enable(OMAP_DSS_GFX, true);
4331
4332 /* Set up and enable display manager for LCD1 */
4333 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD, &i734.mgri);
4334 dispc_calc_clock_rates(dss_get_dispc_clk_rate(),
4335 &lcd_conf.clock_info);
4336 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4337 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.timings);
4338
4339 dispc_clear_irqstatus(framedone_irq);
4340
4341 /* Enable and shut the channel to produce just one frame */
4342 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, true);
4343 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, false);
4344
4345 /* Busy wait for framedone. We can't fiddle with irq handlers
4346 * in PM resume. Typically the loop runs less than 5 times and
4347 * waits less than a micro second.
4348 */
4349 count = 0;
4350 while (!(dispc_read_irqstatus() & framedone_irq)) {
4351 if (count++ > 10000) {
4352 dev_err(&dispc.pdev->dev, "%s: framedone timeout\n",
4353 __func__);
4354 break;
4355 }
4356 }
4357 dispc_ovl_enable(OMAP_DSS_GFX, false);
4358
4359 /* Clear all irq bits before continuing */
4360 dispc_clear_irqstatus(0xffffffff);
4361
4362 /* Restore the original state to LCD1 output gates */
4363 REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4);
4364}
4365
060b6d9c 4366/* DISPC HW IP initialisation */
736e60dd 4367static int dispc_bind(struct device *dev, struct device *master, void *data)
060b6d9c 4368{
736e60dd 4369 struct platform_device *pdev = to_platform_device(dev);
060b6d9c 4370 u32 rev;
affe360d 4371 int r = 0;
ea9da36a 4372 struct resource *dispc_mem;
0006fd63 4373 struct device_node *np = pdev->dev.of_node;
ea9da36a 4374
060b6d9c
SG		 4375 dispc.pdev = pdev;
4376
d49cd155
TV		 4377 spin_lock_init(&dispc.control_lock);
4378
84b47623 4379 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4380 if (r)
4381 return r;
4382
fbff010b
JS		 4383 r = dispc_errata_i734_wa_init();
4384 if (r)
4385 return r;
4386
ea9da36a
SG		 4387 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4388 if (!dispc_mem) {
4389 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4390 return -EINVAL;
ea9da36a 4391 }
cd3b3449 4392
6e2a14d2
JL		 4393 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4394 resource_size(dispc_mem));
060b6d9c
SG		 4395 if (!dispc.base) {
4396 DSSERR("can't ioremap DISPC\n");
cd3b3449 4397 return -ENOMEM;
affe360d 4398 }
cd3b3449 4399
affe360d
AT		 4400 dispc.irq = platform_get_irq(dispc.pdev, 0);
4401 if (dispc.irq < 0) {
4402 DSSERR("platform_get_irq failed\n");
cd3b3449 4403 return -ENODEV;
affe360d
AT		 4404 }
4405
0006fd63
TV		 4406 if (np && of_property_read_bool(np, "syscon-pol")) {
4407 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4408 if (IS_ERR(dispc.syscon_pol)) {
4409 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4410 return PTR_ERR(dispc.syscon_pol);
4411 }
4412
4413 if (of_property_read_u32_index(np, "syscon-pol", 1,
4414 &dispc.syscon_pol_offset)) {
4415 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4416 return -EINVAL;
4417 }
4418 }
4419
acc3a231
JS		 4420 r = dispc_init_gamma_tables();
4421 if (r)
4422 return r;
4423
4fbafaf3
TV		 4424 pm_runtime_enable(&pdev->dev);
4425
4426 r = dispc_runtime_get();
4427 if (r)
4428 goto err_runtime_get;
060b6d9c
SG		 4429
4430 _omap_dispc_initial_config();
4431
060b6d9c 4432 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4433 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4434 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4435
4fbafaf3 4436 dispc_runtime_put();
060b6d9c 4437
e40402cf
TV		 4438 dss_debugfs_create_file("dispc", dispc_dump_regs);
4439
060b6d9c 4440 return 0;
4fbafaf3
TV		 4441
4442err_runtime_get:
4443 pm_runtime_disable(&pdev->dev);
affe360d 4444 return r;
060b6d9c
SG		 4445}
4446
736e60dd
TV		 4447static void dispc_unbind(struct device *dev, struct device *master,
4448 void *data)
060b6d9c 4449{
736e60dd 4450 pm_runtime_disable(dev);
fbff010b
JS		 4451
4452 dispc_errata_i734_wa_fini();
736e60dd
TV		 4453}
4454
4455static const struct component_ops dispc_component_ops = {
4456 .bind = dispc_bind,
4457 .unbind = dispc_unbind,
4458};
04b1fc02 4459
736e60dd
TV		 4460static int dispc_probe(struct platform_device *pdev)
4461{
4462 return component_add(&pdev->dev, &dispc_component_ops);
4463}
4464
4465static int dispc_remove(struct platform_device *pdev)
4466{
4467 component_del(&pdev->dev, &dispc_component_ops);
060b6d9c
SG		 4468 return 0;
4469}
4470
4fbafaf3
TV		 4471static int dispc_runtime_suspend(struct device *dev)
4472{
0925afc9
TV		 4473 dispc.is_enabled = false;
4474 /* ensure the dispc_irq_handler sees the is_enabled value */
4475 smp_wmb();
4476 /* wait for current handler to finish before turning the DISPC off */
4477 synchronize_irq(dispc.irq);
4478
4fbafaf3 4479 dispc_save_context();
4fbafaf3
TV		 4480
4481 return 0;
4482}
4483
4484static int dispc_runtime_resume(struct device *dev)
4485{
9229b516
TV		 4486 /*
4487 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4488 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4489 * _omap_dispc_initial_config(). We can thus use it to detect if
4490 * we have lost register context.
4491 */
0925afc9
TV		 4492 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4493 _omap_dispc_initial_config();
9229b516 4494
fbff010b
JS		 4495 dispc_errata_i734_wa();
4496
0925afc9 4497 dispc_restore_context();
acc3a231
JS		 4498
4499 dispc_restore_gamma_tables();
0925afc9 4500 }
be07dcd7 4501
0925afc9
TV		 4502 dispc.is_enabled = true;
4503 /* ensure the dispc_irq_handler sees the is_enabled value */
4504 smp_wmb();
4fbafaf3
TV		 4505
4506 return 0;
4507}
4508
4509static const struct dev_pm_ops dispc_pm_ops = {
4510 .runtime_suspend = dispc_runtime_suspend,
4511 .runtime_resume = dispc_runtime_resume,
4512};
4513
d7977f88
TV		 4514static const struct of_device_id dispc_of_match[] = {
4515 { .compatible = "ti,omap2-dispc", },
4516 { .compatible = "ti,omap3-dispc", },
4517 { .compatible = "ti,omap4-dispc", },
2e7e6b68 4518 { .compatible = "ti,omap5-dispc", },
93550927 4519 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 4520 {},
4521};
4522
060b6d9c 4523static struct platform_driver omap_dispchw_driver = {
736e60dd
TV		 4524 .probe = dispc_probe,
4525 .remove = dispc_remove,
060b6d9c
SG		 4526 .driver = {
4527 .name = "omapdss_dispc",
4fbafaf3 4528 .pm = &dispc_pm_ops,
d7977f88 4529 .of_match_table = dispc_of_match,
422ccbd5 4530 .suppress_bind_attrs = true,
060b6d9c
SG		 4531 },
4532};
4533
6e7e8f06 4534int __init dispc_init_platform_driver(void)
060b6d9c 4535{
736e60dd 4536 return platform_driver_register(&omap_dispchw_driver);
060b6d9c
SG		 4537}
4538
ede92695 4539void dispc_uninit_platform_driver(void)
060b6d9c 4540{
04c742c3 4541 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4542}
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