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Commit | Line | Data |
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553c48cf TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dpi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DPI" | |
24 | ||
25 | #include <linux/kernel.h> | |
553c48cf | 26 | #include <linux/delay.h> |
a8a35931 | 27 | #include <linux/export.h> |
8a2cfea8 | 28 | #include <linux/err.h> |
553c48cf | 29 | #include <linux/errno.h> |
8a2cfea8 TV |
30 | #include <linux/platform_device.h> |
31 | #include <linux/regulator/consumer.h> | |
13b1ba7d | 32 | #include <linux/string.h> |
2ecef246 | 33 | #include <linux/of.h> |
2daea7af | 34 | #include <linux/clk.h> |
d178e034 | 35 | #include <linux/sys_soc.h> |
553c48cf | 36 | |
32043da7 | 37 | #include "omapdss.h" |
553c48cf TV |
38 | #include "dss.h" |
39 | ||
630d2d0d | 40 | struct dpi_data { |
00df43b8 | 41 | struct platform_device *pdev; |
b8dab2bd | 42 | enum dss_model dss_model; |
00df43b8 | 43 | |
8a2cfea8 | 44 | struct regulator *vdds_dsi_reg; |
331e6078 | 45 | enum dss_clk_source clk_src; |
2daea7af | 46 | struct dss_pll *pll; |
5cf9a264 | 47 | |
c8a5e4e8 AT |
48 | struct mutex lock; |
49 | ||
da11bbbb | 50 | struct videomode vm; |
5cf9a264 | 51 | struct dss_lcd_mgr_config mgr_config; |
c6b393d4 | 52 | int data_lines; |
81b87f51 | 53 | |
1f68d9c4 | 54 | struct omap_dss_device output; |
2ecef246 TV |
55 | |
56 | bool port_initialized; | |
630d2d0d AT |
57 | }; |
58 | ||
2ac6a1aa AT |
59 | static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev) |
60 | { | |
61 | return container_of(dssdev, struct dpi_data, output); | |
62 | } | |
63 | ||
7bbdef2b TV |
64 | static enum dss_clk_source dpi_get_clk_src_dra7xx(enum omap_channel channel) |
65 | { | |
66 | /* | |
67 | * Possible clock sources: | |
68 | * LCD1: FCK/PLL1_1/HDMI_PLL | |
69 | * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3) | |
70 | * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1) | |
71 | */ | |
72 | ||
73 | switch (channel) { | |
74 | case OMAP_DSS_CHANNEL_LCD: | |
75 | { | |
76 | if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_1)) | |
77 | return DSS_CLK_SRC_PLL1_1; | |
78 | break; | |
79 | } | |
80 | case OMAP_DSS_CHANNEL_LCD2: | |
81 | { | |
82 | if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3)) | |
83 | return DSS_CLK_SRC_PLL1_3; | |
84 | if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_3)) | |
85 | return DSS_CLK_SRC_PLL2_3; | |
86 | break; | |
87 | } | |
88 | case OMAP_DSS_CHANNEL_LCD3: | |
89 | { | |
90 | if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_1)) | |
91 | return DSS_CLK_SRC_PLL2_1; | |
92 | if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3)) | |
93 | return DSS_CLK_SRC_PLL1_3; | |
94 | break; | |
95 | } | |
96 | default: | |
97 | break; | |
98 | } | |
99 | ||
100 | return DSS_CLK_SRC_FCK; | |
101 | } | |
102 | ||
b8dab2bd | 103 | static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi) |
a72b64b9 | 104 | { |
b8dab2bd LP |
105 | enum omap_channel channel = dpi->output.dispc_channel; |
106 | ||
bd0f5cc3 TV |
107 | /* |
108 | * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL | |
109 | * would also be used for DISPC fclk. Meaning, when the DPI output is | |
110 | * disabled, DISPC clock will be disabled, and TV out will stop. | |
111 | */ | |
b8dab2bd LP |
112 | switch (dpi->dss_model) { |
113 | case DSS_MODEL_OMAP2: | |
114 | case DSS_MODEL_OMAP3: | |
331e6078 | 115 | return DSS_CLK_SRC_FCK; |
bd0f5cc3 | 116 | |
b8dab2bd | 117 | case DSS_MODEL_OMAP4: |
f8ad984c TV |
118 | switch (channel) { |
119 | case OMAP_DSS_CHANNEL_LCD: | |
331e6078 | 120 | return DSS_CLK_SRC_PLL1_1; |
f8ad984c | 121 | case OMAP_DSS_CHANNEL_LCD2: |
331e6078 | 122 | return DSS_CLK_SRC_PLL2_1; |
f8ad984c | 123 | default: |
331e6078 | 124 | return DSS_CLK_SRC_FCK; |
f8ad984c TV |
125 | } |
126 | ||
b8dab2bd | 127 | case DSS_MODEL_OMAP5: |
f8ad984c TV |
128 | switch (channel) { |
129 | case OMAP_DSS_CHANNEL_LCD: | |
331e6078 | 130 | return DSS_CLK_SRC_PLL1_1; |
f8ad984c | 131 | case OMAP_DSS_CHANNEL_LCD3: |
331e6078 TV |
132 | return DSS_CLK_SRC_PLL2_1; |
133 | case OMAP_DSS_CHANNEL_LCD2: | |
f8ad984c | 134 | default: |
331e6078 | 135 | return DSS_CLK_SRC_FCK; |
f8ad984c TV |
136 | } |
137 | ||
b8dab2bd | 138 | case DSS_MODEL_DRA7: |
7bbdef2b | 139 | return dpi_get_clk_src_dra7xx(channel); |
a2408154 | 140 | |
0e8276ef | 141 | default: |
3b63ca75 | 142 | return DSS_CLK_SRC_FCK; |
0e8276ef | 143 | } |
7636b3b4 AT |
144 | } |
145 | ||
100c8262 | 146 | struct dpi_clk_calc_ctx { |
2daea7af | 147 | struct dss_pll *pll; |
13ece4d3 | 148 | unsigned clkout_idx; |
100c8262 TV |
149 | |
150 | /* inputs */ | |
151 | ||
152 | unsigned long pck_min, pck_max; | |
153 | ||
154 | /* outputs */ | |
155 | ||
31dca077 | 156 | struct dss_pll_clock_info pll_cinfo; |
c56812fc | 157 | unsigned long fck; |
100c8262 TV |
158 | struct dispc_clock_info dispc_cinfo; |
159 | }; | |
160 | ||
161 | static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
162 | unsigned long pck, void *data) | |
163 | { | |
164 | struct dpi_clk_calc_ctx *ctx = data; | |
165 | ||
166 | /* | |
167 | * Odd dividers give us uneven duty cycle, causing problem when level | |
168 | * shifted. So skip all odd dividers when the pixel clock is on the | |
169 | * higher side. | |
170 | */ | |
72e5512a | 171 | if (ctx->pck_min >= 100000000) { |
100c8262 TV |
172 | if (lckd > 1 && lckd % 2 != 0) |
173 | return false; | |
174 | ||
175 | if (pckd > 1 && pckd % 2 != 0) | |
176 | return false; | |
177 | } | |
178 | ||
179 | ctx->dispc_cinfo.lck_div = lckd; | |
180 | ctx->dispc_cinfo.pck_div = pckd; | |
181 | ctx->dispc_cinfo.lck = lck; | |
182 | ctx->dispc_cinfo.pck = pck; | |
183 | ||
184 | return true; | |
185 | } | |
186 | ||
187 | ||
2daea7af | 188 | static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, |
100c8262 TV |
189 | void *data) |
190 | { | |
191 | struct dpi_clk_calc_ctx *ctx = data; | |
192 | ||
31dca077 TV |
193 | ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; |
194 | ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; | |
100c8262 TV |
195 | |
196 | return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, | |
197 | dpi_calc_dispc_cb, ctx); | |
198 | } | |
199 | ||
200 | ||
2daea7af TV |
201 | static bool dpi_calc_pll_cb(int n, int m, unsigned long fint, |
202 | unsigned long clkdco, | |
100c8262 TV |
203 | void *data) |
204 | { | |
205 | struct dpi_clk_calc_ctx *ctx = data; | |
206 | ||
31dca077 TV |
207 | ctx->pll_cinfo.n = n; |
208 | ctx->pll_cinfo.m = m; | |
209 | ctx->pll_cinfo.fint = fint; | |
210 | ctx->pll_cinfo.clkdco = clkdco; | |
100c8262 | 211 | |
cd0715ff | 212 | return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, |
9f0fbaea | 213 | ctx->pck_min, dss_get_max_fck_rate(), |
2daea7af | 214 | dpi_calc_hsdiv_cb, ctx); |
100c8262 TV |
215 | } |
216 | ||
d0f58bd3 | 217 | static bool dpi_calc_dss_cb(unsigned long fck, void *data) |
100c8262 TV |
218 | { |
219 | struct dpi_clk_calc_ctx *ctx = data; | |
220 | ||
d0f58bd3 | 221 | ctx->fck = fck; |
100c8262 TV |
222 | |
223 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, | |
224 | dpi_calc_dispc_cb, ctx); | |
225 | } | |
226 | ||
31dca077 | 227 | static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck, |
630d2d0d | 228 | struct dpi_clk_calc_ctx *ctx) |
100c8262 TV |
229 | { |
230 | unsigned long clkin; | |
100c8262 | 231 | |
100c8262 | 232 | memset(ctx, 0, sizeof(*ctx)); |
2daea7af | 233 | ctx->pll = dpi->pll; |
13ece4d3 | 234 | ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src); |
100c8262 | 235 | |
683cd866 | 236 | clkin = clk_get_rate(dpi->pll->clkin); |
100c8262 | 237 | |
683cd866 TV |
238 | if (dpi->pll->hw->type == DSS_PLL_TYPE_A) { |
239 | unsigned long pll_min, pll_max; | |
2daea7af | 240 | |
683cd866 TV |
241 | ctx->pck_min = pck - 1000; |
242 | ctx->pck_max = pck + 1000; | |
243 | ||
244 | pll_min = 0; | |
245 | pll_max = 0; | |
246 | ||
247 | return dss_pll_calc_a(ctx->pll, clkin, | |
248 | pll_min, pll_max, | |
249 | dpi_calc_pll_cb, ctx); | |
250 | } else { /* DSS_PLL_TYPE_B */ | |
31dca077 | 251 | dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo); |
683cd866 TV |
252 | |
253 | ctx->dispc_cinfo.lck_div = 1; | |
254 | ctx->dispc_cinfo.pck_div = 1; | |
31dca077 | 255 | ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0]; |
683cd866 TV |
256 | ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck; |
257 | ||
258 | return true; | |
259 | } | |
100c8262 TV |
260 | } |
261 | ||
262 | static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) | |
263 | { | |
264 | int i; | |
265 | ||
266 | /* | |
267 | * DSS fck gives us very few possibilities, so finding a good pixel | |
268 | * clock may not be possible. We try multiple times to find the clock, | |
269 | * each time widening the pixel clock range we look for, up to | |
2c6360fb | 270 | * +/- ~15MHz. |
100c8262 TV |
271 | */ |
272 | ||
2c6360fb | 273 | for (i = 0; i < 25; ++i) { |
100c8262 TV |
274 | bool ok; |
275 | ||
276 | memset(ctx, 0, sizeof(*ctx)); | |
277 | if (pck > 1000 * i * i * i) | |
278 | ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); | |
279 | else | |
280 | ctx->pck_min = 0; | |
281 | ctx->pck_max = pck + 1000 * i * i * i; | |
282 | ||
688af02d | 283 | ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx); |
100c8262 TV |
284 | if (ok) |
285 | return ok; | |
286 | } | |
287 | ||
288 | return false; | |
289 | } | |
290 | ||
291 | ||
292 | ||
31dca077 | 293 | static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel, |
ff1b2cde SS |
294 | unsigned long pck_req, unsigned long *fck, int *lck_div, |
295 | int *pck_div) | |
553c48cf | 296 | { |
100c8262 | 297 | struct dpi_clk_calc_ctx ctx; |
553c48cf | 298 | int r; |
100c8262 | 299 | bool ok; |
553c48cf | 300 | |
31dca077 | 301 | ok = dpi_pll_clk_calc(dpi, pck_req, &ctx); |
100c8262 TV |
302 | if (!ok) |
303 | return -EINVAL; | |
553c48cf | 304 | |
31dca077 | 305 | r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); |
553c48cf TV |
306 | if (r) |
307 | return r; | |
308 | ||
331e6078 | 309 | dss_select_lcd_clk_source(channel, dpi->clk_src); |
553c48cf | 310 | |
630d2d0d | 311 | dpi->mgr_config.clock_info = ctx.dispc_cinfo; |
553c48cf | 312 | |
31dca077 | 313 | *fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; |
100c8262 TV |
314 | *lck_div = ctx.dispc_cinfo.lck_div; |
315 | *pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf TV |
316 | |
317 | return 0; | |
318 | } | |
7636b3b4 | 319 | |
630d2d0d AT |
320 | static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req, |
321 | unsigned long *fck, int *lck_div, int *pck_div) | |
553c48cf | 322 | { |
100c8262 | 323 | struct dpi_clk_calc_ctx ctx; |
553c48cf | 324 | int r; |
100c8262 | 325 | bool ok; |
553c48cf | 326 | |
100c8262 TV |
327 | ok = dpi_dss_clk_calc(pck_req, &ctx); |
328 | if (!ok) | |
329 | return -EINVAL; | |
553c48cf | 330 | |
d0f58bd3 | 331 | r = dss_set_fck_rate(ctx.fck); |
553c48cf TV |
332 | if (r) |
333 | return r; | |
334 | ||
630d2d0d | 335 | dpi->mgr_config.clock_info = ctx.dispc_cinfo; |
553c48cf | 336 | |
d0f58bd3 | 337 | *fck = ctx.fck; |
100c8262 TV |
338 | *lck_div = ctx.dispc_cinfo.lck_div; |
339 | *pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf TV |
340 | |
341 | return 0; | |
342 | } | |
553c48cf | 343 | |
630d2d0d | 344 | static int dpi_set_mode(struct dpi_data *dpi) |
553c48cf | 345 | { |
630d2d0d | 346 | struct omap_dss_device *out = &dpi->output; |
a070ba6c | 347 | enum omap_channel channel = out->dispc_channel; |
da11bbbb | 348 | struct videomode *vm = &dpi->vm; |
7636b3b4 AT |
349 | int lck_div = 0, pck_div = 0; |
350 | unsigned long fck = 0; | |
553c48cf | 351 | unsigned long pck; |
553c48cf TV |
352 | int r = 0; |
353 | ||
2daea7af | 354 | if (dpi->pll) |
da11bbbb | 355 | r = dpi_set_pll_clk(dpi, channel, vm->pixelclock, &fck, |
6d523e7b | 356 | &lck_div, &pck_div); |
7636b3b4 | 357 | else |
da11bbbb | 358 | r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck, |
6d523e7b | 359 | &lck_div, &pck_div); |
553c48cf | 360 | if (r) |
4fbafaf3 | 361 | return r; |
553c48cf | 362 | |
d8d78941 | 363 | pck = fck / lck_div / pck_div; |
553c48cf | 364 | |
da11bbbb | 365 | if (pck != vm->pixelclock) { |
7aa91e76 | 366 | DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", |
da11bbbb | 367 | vm->pixelclock, pck); |
553c48cf | 368 | |
da11bbbb | 369 | vm->pixelclock = pck; |
553c48cf TV |
370 | } |
371 | ||
da11bbbb | 372 | dss_mgr_set_timings(channel, vm); |
553c48cf | 373 | |
4fbafaf3 | 374 | return 0; |
553c48cf TV |
375 | } |
376 | ||
630d2d0d | 377 | static void dpi_config_lcd_manager(struct dpi_data *dpi) |
553c48cf | 378 | { |
630d2d0d | 379 | struct omap_dss_device *out = &dpi->output; |
a070ba6c | 380 | enum omap_channel channel = out->dispc_channel; |
630d2d0d AT |
381 | |
382 | dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; | |
569969d6 | 383 | |
630d2d0d AT |
384 | dpi->mgr_config.stallmode = false; |
385 | dpi->mgr_config.fifohandcheck = false; | |
5cf9a264 | 386 | |
630d2d0d | 387 | dpi->mgr_config.video_port_width = dpi->data_lines; |
5cf9a264 | 388 | |
630d2d0d | 389 | dpi->mgr_config.lcden_sig_polarity = 0; |
5cf9a264 | 390 | |
a070ba6c | 391 | dss_mgr_set_lcd_config(channel, &dpi->mgr_config); |
553c48cf TV |
392 | } |
393 | ||
86a3efe1 | 394 | static int dpi_display_enable(struct omap_dss_device *dssdev) |
553c48cf | 395 | { |
2ac6a1aa | 396 | struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); |
630d2d0d | 397 | struct omap_dss_device *out = &dpi->output; |
a070ba6c | 398 | enum omap_channel channel = out->dispc_channel; |
553c48cf TV |
399 | int r; |
400 | ||
630d2d0d | 401 | mutex_lock(&dpi->lock); |
c8a5e4e8 | 402 | |
f1504ad0 | 403 | if (!out->dispc_channel_connected) { |
5d512fcd | 404 | DSSERR("failed to enable display: no output/manager\n"); |
c8a5e4e8 | 405 | r = -ENODEV; |
5d512fcd | 406 | goto err_no_out_mgr; |
05e1d606 TV |
407 | } |
408 | ||
e65837b5 | 409 | if (dpi->vdds_dsi_reg) { |
630d2d0d | 410 | r = regulator_enable(dpi->vdds_dsi_reg); |
8a2cfea8 | 411 | if (r) |
4fbafaf3 | 412 | goto err_reg_enable; |
8a2cfea8 TV |
413 | } |
414 | ||
4fbafaf3 | 415 | r = dispc_runtime_get(); |
553c48cf | 416 | if (r) |
4fbafaf3 TV |
417 | goto err_get_dispc; |
418 | ||
a070ba6c | 419 | r = dss_dpi_select_source(out->port_num, channel); |
de09e455 TV |
420 | if (r) |
421 | goto err_src_sel; | |
422 | ||
2daea7af TV |
423 | if (dpi->pll) { |
424 | r = dss_pll_enable(dpi->pll); | |
7636b3b4 | 425 | if (r) |
31dca077 | 426 | goto err_pll_init; |
7636b3b4 AT |
427 | } |
428 | ||
630d2d0d | 429 | r = dpi_set_mode(dpi); |
553c48cf | 430 | if (r) |
4fbafaf3 | 431 | goto err_set_mode; |
553c48cf | 432 | |
630d2d0d | 433 | dpi_config_lcd_manager(dpi); |
5cf9a264 | 434 | |
553c48cf TV |
435 | mdelay(2); |
436 | ||
a070ba6c | 437 | r = dss_mgr_enable(channel); |
33ca237f TV |
438 | if (r) |
439 | goto err_mgr_enable; | |
553c48cf | 440 | |
630d2d0d | 441 | mutex_unlock(&dpi->lock); |
c8a5e4e8 | 442 | |
553c48cf TV |
443 | return 0; |
444 | ||
33ca237f | 445 | err_mgr_enable: |
4fbafaf3 | 446 | err_set_mode: |
2daea7af TV |
447 | if (dpi->pll) |
448 | dss_pll_disable(dpi->pll); | |
31dca077 | 449 | err_pll_init: |
de09e455 | 450 | err_src_sel: |
4fbafaf3 TV |
451 | dispc_runtime_put(); |
452 | err_get_dispc: | |
e65837b5 | 453 | if (dpi->vdds_dsi_reg) |
630d2d0d | 454 | regulator_disable(dpi->vdds_dsi_reg); |
4fbafaf3 | 455 | err_reg_enable: |
5d512fcd | 456 | err_no_out_mgr: |
630d2d0d | 457 | mutex_unlock(&dpi->lock); |
553c48cf TV |
458 | return r; |
459 | } | |
460 | ||
86a3efe1 | 461 | static void dpi_display_disable(struct omap_dss_device *dssdev) |
553c48cf | 462 | { |
2ac6a1aa | 463 | struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); |
a070ba6c | 464 | enum omap_channel channel = dpi->output.dispc_channel; |
5d512fcd | 465 | |
630d2d0d | 466 | mutex_lock(&dpi->lock); |
c8a5e4e8 | 467 | |
a070ba6c | 468 | dss_mgr_disable(channel); |
553c48cf | 469 | |
2daea7af | 470 | if (dpi->pll) { |
3b63ca75 | 471 | dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); |
2daea7af | 472 | dss_pll_disable(dpi->pll); |
7636b3b4 | 473 | } |
553c48cf | 474 | |
4fbafaf3 | 475 | dispc_runtime_put(); |
553c48cf | 476 | |
e65837b5 | 477 | if (dpi->vdds_dsi_reg) |
630d2d0d | 478 | regulator_disable(dpi->vdds_dsi_reg); |
8a2cfea8 | 479 | |
630d2d0d | 480 | mutex_unlock(&dpi->lock); |
553c48cf | 481 | } |
553c48cf | 482 | |
86a3efe1 | 483 | static void dpi_set_timings(struct omap_dss_device *dssdev, |
da11bbbb | 484 | struct videomode *vm) |
553c48cf | 485 | { |
2ac6a1aa | 486 | struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); |
630d2d0d | 487 | |
553c48cf | 488 | DSSDBG("dpi_set_timings\n"); |
c8a5e4e8 | 489 | |
630d2d0d | 490 | mutex_lock(&dpi->lock); |
c8a5e4e8 | 491 | |
da11bbbb | 492 | dpi->vm = *vm; |
c499144c | 493 | |
630d2d0d | 494 | mutex_unlock(&dpi->lock); |
553c48cf TV |
495 | } |
496 | ||
0b24edb1 | 497 | static void dpi_get_timings(struct omap_dss_device *dssdev, |
da11bbbb | 498 | struct videomode *vm) |
0b24edb1 | 499 | { |
2ac6a1aa | 500 | struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); |
630d2d0d AT |
501 | |
502 | mutex_lock(&dpi->lock); | |
0b24edb1 | 503 | |
da11bbbb | 504 | *vm = dpi->vm; |
0b24edb1 | 505 | |
630d2d0d | 506 | mutex_unlock(&dpi->lock); |
0b24edb1 TV |
507 | } |
508 | ||
86a3efe1 | 509 | static int dpi_check_timings(struct omap_dss_device *dssdev, |
da11bbbb | 510 | struct videomode *vm) |
553c48cf | 511 | { |
2ac6a1aa | 512 | struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); |
a070ba6c | 513 | enum omap_channel channel = dpi->output.dispc_channel; |
553c48cf TV |
514 | int lck_div, pck_div; |
515 | unsigned long fck; | |
516 | unsigned long pck; | |
100c8262 TV |
517 | struct dpi_clk_calc_ctx ctx; |
518 | bool ok; | |
553c48cf | 519 | |
da11bbbb | 520 | if (vm->hactive % 8 != 0) |
2158f2c7 TV |
521 | return -EINVAL; |
522 | ||
da11bbbb | 523 | if (!dispc_mgr_timings_ok(channel, vm)) |
553c48cf TV |
524 | return -EINVAL; |
525 | ||
da11bbbb | 526 | if (vm->pixelclock == 0) |
553c48cf TV |
527 | return -EINVAL; |
528 | ||
2daea7af | 529 | if (dpi->pll) { |
da11bbbb | 530 | ok = dpi_pll_clk_calc(dpi, vm->pixelclock, &ctx); |
100c8262 TV |
531 | if (!ok) |
532 | return -EINVAL; | |
553c48cf | 533 | |
31dca077 | 534 | fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; |
7636b3b4 | 535 | } else { |
da11bbbb | 536 | ok = dpi_dss_clk_calc(vm->pixelclock, &ctx); |
100c8262 TV |
537 | if (!ok) |
538 | return -EINVAL; | |
553c48cf | 539 | |
d0f58bd3 | 540 | fck = ctx.fck; |
553c48cf | 541 | } |
7636b3b4 | 542 | |
100c8262 TV |
543 | lck_div = ctx.dispc_cinfo.lck_div; |
544 | pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf | 545 | |
d8d78941 | 546 | pck = fck / lck_div / pck_div; |
553c48cf | 547 | |
da11bbbb | 548 | vm->pixelclock = pck; |
553c48cf TV |
549 | |
550 | return 0; | |
551 | } | |
553c48cf | 552 | |
31dca077 | 553 | static int dpi_verify_pll(struct dss_pll *pll) |
6061675b TV |
554 | { |
555 | int r; | |
556 | ||
557 | /* do initial setup with the PLL to see if it is operational */ | |
558 | ||
2daea7af | 559 | r = dss_pll_enable(pll); |
f76b178a | 560 | if (r) |
6061675b | 561 | return r; |
6061675b | 562 | |
2daea7af | 563 | dss_pll_disable(pll); |
6061675b TV |
564 | |
565 | return 0; | |
566 | } | |
567 | ||
d178e034 | 568 | static const struct soc_device_attribute dpi_soc_devices[] = { |
bf25dac3 LP |
569 | { .machine = "OMAP3[456]*" }, |
570 | { .machine = "[AD]M37*" }, | |
d178e034 LP |
571 | { /* sentinel */ } |
572 | }; | |
573 | ||
630d2d0d | 574 | static int dpi_init_regulator(struct dpi_data *dpi) |
2795f646 TV |
575 | { |
576 | struct regulator *vdds_dsi; | |
577 | ||
d178e034 LP |
578 | /* |
579 | * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and | |
580 | * DM37xx only. | |
581 | */ | |
582 | if (!soc_device_match(dpi_soc_devices)) | |
2795f646 TV |
583 | return 0; |
584 | ||
630d2d0d | 585 | if (dpi->vdds_dsi_reg) |
2795f646 TV |
586 | return 0; |
587 | ||
630d2d0d | 588 | vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi"); |
2795f646 | 589 | if (IS_ERR(vdds_dsi)) { |
40359a9b TV |
590 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) |
591 | DSSERR("can't get VDDS_DSI regulator\n"); | |
4123de21 | 592 | return PTR_ERR(vdds_dsi); |
2795f646 TV |
593 | } |
594 | ||
630d2d0d | 595 | dpi->vdds_dsi_reg = vdds_dsi; |
2795f646 TV |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
630d2d0d | 600 | static void dpi_init_pll(struct dpi_data *dpi) |
2795f646 | 601 | { |
2daea7af | 602 | struct dss_pll *pll; |
2795f646 | 603 | |
2daea7af | 604 | if (dpi->pll) |
2795f646 TV |
605 | return; |
606 | ||
b8dab2bd | 607 | dpi->clk_src = dpi_get_clk_src(dpi); |
331e6078 TV |
608 | |
609 | pll = dss_pll_find_by_src(dpi->clk_src); | |
2daea7af | 610 | if (!pll) |
2795f646 TV |
611 | return; |
612 | ||
31dca077 TV |
613 | if (dpi_verify_pll(pll)) { |
614 | DSSWARN("PLL not operational\n"); | |
2795f646 TV |
615 | return; |
616 | } | |
617 | ||
2daea7af | 618 | dpi->pll = pll; |
2795f646 TV |
619 | } |
620 | ||
2eea5ae6 TV |
621 | /* |
622 | * Return a hardcoded channel for the DPI output. This should work for | |
623 | * current use cases, but this can be later expanded to either resolve | |
624 | * the channel in some more dynamic manner, or get the channel as a user | |
625 | * parameter. | |
626 | */ | |
b8dab2bd | 627 | static enum omap_channel dpi_get_channel(struct dpi_data *dpi, int port_num) |
2eea5ae6 | 628 | { |
b8dab2bd LP |
629 | switch (dpi->dss_model) { |
630 | case DSS_MODEL_OMAP2: | |
631 | case DSS_MODEL_OMAP3: | |
2eea5ae6 TV |
632 | return OMAP_DSS_CHANNEL_LCD; |
633 | ||
b8dab2bd | 634 | case DSS_MODEL_DRA7: |
a2408154 TV |
635 | switch (port_num) { |
636 | case 2: | |
637 | return OMAP_DSS_CHANNEL_LCD3; | |
638 | case 1: | |
639 | return OMAP_DSS_CHANNEL_LCD2; | |
640 | case 0: | |
641 | default: | |
642 | return OMAP_DSS_CHANNEL_LCD; | |
643 | } | |
644 | ||
b8dab2bd | 645 | case DSS_MODEL_OMAP4: |
2eea5ae6 TV |
646 | return OMAP_DSS_CHANNEL_LCD2; |
647 | ||
b8dab2bd | 648 | case DSS_MODEL_OMAP5: |
2eea5ae6 TV |
649 | return OMAP_DSS_CHANNEL_LCD3; |
650 | ||
651 | default: | |
652 | DSSWARN("unsupported DSS version\n"); | |
653 | return OMAP_DSS_CHANNEL_LCD; | |
654 | } | |
655 | } | |
656 | ||
0b24edb1 TV |
657 | static int dpi_connect(struct omap_dss_device *dssdev, |
658 | struct omap_dss_device *dst) | |
659 | { | |
2ac6a1aa | 660 | struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); |
a070ba6c | 661 | enum omap_channel channel = dpi->output.dispc_channel; |
0b24edb1 TV |
662 | int r; |
663 | ||
630d2d0d | 664 | r = dpi_init_regulator(dpi); |
0b24edb1 TV |
665 | if (r) |
666 | return r; | |
667 | ||
630d2d0d | 668 | dpi_init_pll(dpi); |
0b24edb1 | 669 | |
a070ba6c | 670 | r = dss_mgr_connect(channel, dssdev); |
0b24edb1 TV |
671 | if (r) |
672 | return r; | |
673 | ||
674 | r = omapdss_output_set_device(dssdev, dst); | |
675 | if (r) { | |
676 | DSSERR("failed to connect output to new device: %s\n", | |
677 | dst->name); | |
a070ba6c | 678 | dss_mgr_disconnect(channel, dssdev); |
0b24edb1 TV |
679 | return r; |
680 | } | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
685 | static void dpi_disconnect(struct omap_dss_device *dssdev, | |
686 | struct omap_dss_device *dst) | |
687 | { | |
a070ba6c TV |
688 | struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); |
689 | enum omap_channel channel = dpi->output.dispc_channel; | |
690 | ||
9560dc10 | 691 | WARN_ON(dst != dssdev->dst); |
0b24edb1 | 692 | |
9560dc10 | 693 | if (dst != dssdev->dst) |
0b24edb1 TV |
694 | return; |
695 | ||
696 | omapdss_output_unset_device(dssdev); | |
697 | ||
a070ba6c | 698 | dss_mgr_disconnect(channel, dssdev); |
0b24edb1 TV |
699 | } |
700 | ||
701 | static const struct omapdss_dpi_ops dpi_ops = { | |
702 | .connect = dpi_connect, | |
703 | .disconnect = dpi_disconnect, | |
704 | ||
86a3efe1 TV |
705 | .enable = dpi_display_enable, |
706 | .disable = dpi_display_disable, | |
0b24edb1 TV |
707 | |
708 | .check_timings = dpi_check_timings, | |
86a3efe1 | 709 | .set_timings = dpi_set_timings, |
0b24edb1 | 710 | .get_timings = dpi_get_timings, |
0b24edb1 TV |
711 | }; |
712 | ||
b8dab2bd | 713 | static void dpi_init_output_port(struct dpi_data *dpi, struct device_node *port) |
80eb6751 | 714 | { |
80eb6751 | 715 | struct omap_dss_device *out = &dpi->output; |
f7e38fe9 AT |
716 | int r; |
717 | u32 port_num; | |
718 | ||
719 | r = of_property_read_u32(port, "reg", &port_num); | |
720 | if (r) | |
721 | port_num = 0; | |
722 | ||
723 | switch (port_num) { | |
724 | case 2: | |
725 | out->name = "dpi.2"; | |
726 | break; | |
727 | case 1: | |
728 | out->name = "dpi.1"; | |
729 | break; | |
730 | case 0: | |
731 | default: | |
732 | out->name = "dpi.0"; | |
733 | break; | |
734 | } | |
80eb6751 | 735 | |
b8dab2bd | 736 | out->dev = &dpi->pdev->dev; |
80eb6751 AT |
737 | out->id = OMAP_DSS_OUTPUT_DPI; |
738 | out->output_type = OMAP_DISPLAY_TYPE_DPI; | |
b8dab2bd | 739 | out->dispc_channel = dpi_get_channel(dpi, port_num); |
f7e38fe9 | 740 | out->port_num = port_num; |
80eb6751 AT |
741 | out->ops.dpi = &dpi_ops; |
742 | out->owner = THIS_MODULE; | |
743 | ||
744 | omapdss_register_output(out); | |
745 | } | |
746 | ||
ede92695 | 747 | static void dpi_uninit_output_port(struct device_node *port) |
80eb6751 AT |
748 | { |
749 | struct dpi_data *dpi = port->data; | |
750 | struct omap_dss_device *out = &dpi->output; | |
751 | ||
752 | omapdss_unregister_output(out); | |
753 | } | |
754 | ||
b8dab2bd LP |
755 | int dpi_init_port(struct platform_device *pdev, struct device_node *port, |
756 | enum dss_model dss_model) | |
2ecef246 | 757 | { |
2ac6a1aa | 758 | struct dpi_data *dpi; |
2ecef246 TV |
759 | struct device_node *ep; |
760 | u32 datalines; | |
761 | int r; | |
762 | ||
2ac6a1aa AT |
763 | dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); |
764 | if (!dpi) | |
765 | return -ENOMEM; | |
766 | ||
09bffa6e | 767 | ep = of_get_next_child(port, NULL); |
2ecef246 TV |
768 | if (!ep) |
769 | return 0; | |
770 | ||
771 | r = of_property_read_u32(ep, "data-lines", &datalines); | |
772 | if (r) { | |
773 | DSSERR("failed to parse datalines\n"); | |
774 | goto err_datalines; | |
775 | } | |
776 | ||
630d2d0d | 777 | dpi->data_lines = datalines; |
2ecef246 TV |
778 | |
779 | of_node_put(ep); | |
780 | ||
630d2d0d | 781 | dpi->pdev = pdev; |
b8dab2bd | 782 | dpi->dss_model = dss_model; |
80eb6751 | 783 | port->data = dpi; |
2ecef246 | 784 | |
630d2d0d | 785 | mutex_init(&dpi->lock); |
2ecef246 | 786 | |
b8dab2bd | 787 | dpi_init_output_port(dpi, port); |
2ecef246 | 788 | |
630d2d0d | 789 | dpi->port_initialized = true; |
2ecef246 TV |
790 | |
791 | return 0; | |
792 | ||
793 | err_datalines: | |
794 | of_node_put(ep); | |
795 | ||
796 | return r; | |
797 | } | |
798 | ||
ede92695 | 799 | void dpi_uninit_port(struct device_node *port) |
2ecef246 | 800 | { |
80eb6751 | 801 | struct dpi_data *dpi = port->data; |
630d2d0d AT |
802 | |
803 | if (!dpi->port_initialized) | |
2ecef246 TV |
804 | return; |
805 | ||
80eb6751 | 806 | dpi_uninit_output_port(port); |
2ecef246 | 807 | } |