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3de7a1dc | 1 | /* |
3de7a1dc | 2 | * Copyright (C) 2009 Nokia Corporation |
6505d75c | 3 | * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> |
3de7a1dc TV |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #define DSS_SUBSYS_NAME "DSI" | |
19 | ||
20 | #include <linux/kernel.h> | |
9e1305d0 LP |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/regmap.h> | |
3de7a1dc TV |
23 | #include <linux/io.h> |
24 | #include <linux/clk.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/mutex.h> | |
355b200b | 30 | #include <linux/module.h> |
b9eb5d7d | 31 | #include <linux/semaphore.h> |
3de7a1dc TV |
32 | #include <linux/seq_file.h> |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/regulator/consumer.h> | |
3de7a1dc | 35 | #include <linux/wait.h> |
18946f62 | 36 | #include <linux/workqueue.h> |
40885ab3 | 37 | #include <linux/sched.h> |
f1da39d9 | 38 | #include <linux/slab.h> |
5a8b572d | 39 | #include <linux/debugfs.h> |
4fbafaf3 | 40 | #include <linux/pm_runtime.h> |
6274a619 | 41 | #include <linux/of.h> |
09bffa6e | 42 | #include <linux/of_graph.h> |
6274a619 | 43 | #include <linux/of_platform.h> |
736e60dd | 44 | #include <linux/component.h> |
44d8ca10 | 45 | #include <linux/sys_soc.h> |
3de7a1dc | 46 | |
7a7c48f9 | 47 | #include <video/mipi_display.h> |
3de7a1dc | 48 | |
32043da7 | 49 | #include "omapdss.h" |
3de7a1dc TV |
50 | #include "dss.h" |
51 | ||
3de7a1dc TV |
52 | #define DSI_CATCH_MISSING_TE |
53 | ||
68104467 | 54 | struct dsi_reg { u16 module; u16 idx; }; |
3de7a1dc | 55 | |
68104467 | 56 | #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) |
3de7a1dc | 57 | |
3de7a1dc TV |
58 | /* DSI Protocol Engine */ |
59 | ||
68104467 TV |
60 | #define DSI_PROTO 0 |
61 | #define DSI_PROTO_SZ 0x200 | |
62 | ||
63 | #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) | |
64 | #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) | |
65 | #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) | |
66 | #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) | |
67 | #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) | |
68 | #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) | |
69 | #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) | |
70 | #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) | |
71 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) | |
72 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) | |
73 | #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) | |
74 | #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) | |
75 | #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) | |
76 | #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) | |
77 | #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) | |
78 | #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) | |
79 | #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) | |
80 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) | |
81 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) | |
82 | #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) | |
83 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) | |
84 | #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) | |
85 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) | |
86 | #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) | |
87 | #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) | |
88 | #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) | |
89 | #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) | |
90 | #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) | |
91 | #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) | |
92 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) | |
93 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) | |
94 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) | |
95 | #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) | |
96 | #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) | |
3de7a1dc TV |
97 | |
98 | /* DSIPHY_SCP */ | |
99 | ||
68104467 TV |
100 | #define DSI_PHY 1 |
101 | #define DSI_PHY_OFFSET 0x200 | |
102 | #define DSI_PHY_SZ 0x40 | |
103 | ||
104 | #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) | |
105 | #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) | |
106 | #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) | |
107 | #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) | |
108 | #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) | |
3de7a1dc TV |
109 | |
110 | /* DSI_PLL_CTRL_SCP */ | |
111 | ||
68104467 TV |
112 | #define DSI_PLL 2 |
113 | #define DSI_PLL_OFFSET 0x300 | |
114 | #define DSI_PLL_SZ 0x20 | |
115 | ||
116 | #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) | |
117 | #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) | |
118 | #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) | |
119 | #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) | |
120 | #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) | |
3de7a1dc | 121 | |
7093d6cd LP |
122 | #define REG_GET(dsi, idx, start, end) \ |
123 | FLD_GET(dsi_read_reg(dsi, idx), start, end) | |
3de7a1dc | 124 | |
7093d6cd LP |
125 | #define REG_FLD_MOD(dsi, idx, val, start, end) \ |
126 | dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end)) | |
3de7a1dc TV |
127 | |
128 | /* Global interrupts */ | |
129 | #define DSI_IRQ_VC0 (1 << 0) | |
130 | #define DSI_IRQ_VC1 (1 << 1) | |
131 | #define DSI_IRQ_VC2 (1 << 2) | |
132 | #define DSI_IRQ_VC3 (1 << 3) | |
133 | #define DSI_IRQ_WAKEUP (1 << 4) | |
134 | #define DSI_IRQ_RESYNC (1 << 5) | |
135 | #define DSI_IRQ_PLL_LOCK (1 << 7) | |
136 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) | |
137 | #define DSI_IRQ_PLL_RECALL (1 << 9) | |
138 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) | |
139 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) | |
140 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) | |
141 | #define DSI_IRQ_TE_TRIGGER (1 << 16) | |
142 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) | |
143 | #define DSI_IRQ_SYNC_LOST (1 << 18) | |
144 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) | |
145 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) | |
146 | #define DSI_IRQ_ERROR_MASK \ | |
147 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ | |
00355412 | 148 | DSI_IRQ_TA_TIMEOUT) |
3de7a1dc TV |
149 | #define DSI_IRQ_CHANNEL_MASK 0xf |
150 | ||
151 | /* Virtual channel interrupts */ | |
152 | #define DSI_VC_IRQ_CS (1 << 0) | |
153 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) | |
154 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) | |
155 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) | |
156 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) | |
157 | #define DSI_VC_IRQ_BTA (1 << 5) | |
158 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) | |
159 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) | |
160 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) | |
161 | #define DSI_VC_IRQ_ERROR_MASK \ | |
162 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ | |
163 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ | |
164 | DSI_VC_IRQ_FIFO_TX_UDF) | |
165 | ||
166 | /* ComplexIO interrupts */ | |
167 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) | |
168 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) | |
169 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) | |
6705615e TV |
170 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
171 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) | |
3de7a1dc TV |
172 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
173 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) | |
174 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) | |
6705615e TV |
175 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
176 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) | |
3de7a1dc TV |
177 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
178 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) | |
179 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) | |
6705615e TV |
180 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
181 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) | |
3de7a1dc TV |
182 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
183 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) | |
184 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) | |
6705615e TV |
185 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
186 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) | |
3de7a1dc TV |
187 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
188 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) | |
189 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) | |
190 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) | |
191 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) | |
192 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) | |
6705615e TV |
193 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
194 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) | |
195 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) | |
196 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) | |
3de7a1dc TV |
197 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
198 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) | |
bbecb50b TV |
199 | #define DSI_CIO_IRQ_ERROR_MASK \ |
200 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ | |
6705615e TV |
201 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
202 | DSI_CIO_IRQ_ERRSYNCESC5 | \ | |
203 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ | |
204 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ | |
205 | DSI_CIO_IRQ_ERRESC5 | \ | |
206 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ | |
207 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ | |
208 | DSI_CIO_IRQ_ERRCONTROL5 | \ | |
bbecb50b TV |
209 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
210 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ | |
6705615e TV |
211 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
212 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ | |
213 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) | |
3de7a1dc | 214 | |
4ae2dddd | 215 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
7093d6cd | 216 | struct dsi_data; |
4ae2dddd | 217 | |
f81b0fd4 LP |
218 | static int dsi_display_init_dispc(struct dsi_data *dsi); |
219 | static void dsi_display_uninit_dispc(struct dsi_data *dsi); | |
b7dec9b6 | 220 | |
7093d6cd | 221 | static int dsi_vc_send_null(struct dsi_data *dsi, int channel); |
5cfc1c3c | 222 | |
acf604b7 TV |
223 | /* DSI PLL HSDIV indices */ |
224 | #define HSDIV_DISPC 0 | |
225 | #define HSDIV_DSI 1 | |
226 | ||
4ae2dddd | 227 | #define DSI_MAX_NR_ISRS 2 |
739a7f46 TV |
228 | #define DSI_MAX_NR_LANES 5 |
229 | ||
742e693b LP |
230 | enum dsi_model { |
231 | DSI_MODEL_OMAP3, | |
232 | DSI_MODEL_OMAP4, | |
233 | DSI_MODEL_OMAP5, | |
234 | }; | |
235 | ||
739a7f46 TV |
236 | enum dsi_lane_function { |
237 | DSI_LANE_UNUSED = 0, | |
238 | DSI_LANE_CLK, | |
239 | DSI_LANE_DATA1, | |
240 | DSI_LANE_DATA2, | |
241 | DSI_LANE_DATA3, | |
242 | DSI_LANE_DATA4, | |
243 | }; | |
244 | ||
245 | struct dsi_lane_config { | |
246 | enum dsi_lane_function function; | |
247 | u8 polarity; | |
248 | }; | |
4ae2dddd TV |
249 | |
250 | struct dsi_isr_data { | |
251 | omap_dsi_isr_t isr; | |
252 | void *arg; | |
253 | u32 mask; | |
254 | }; | |
255 | ||
3de7a1dc TV |
256 | enum fifo_size { |
257 | DSI_FIFO_SIZE_0 = 0, | |
258 | DSI_FIFO_SIZE_32 = 1, | |
259 | DSI_FIFO_SIZE_64 = 2, | |
260 | DSI_FIFO_SIZE_96 = 3, | |
261 | DSI_FIFO_SIZE_128 = 4, | |
262 | }; | |
263 | ||
d6049144 AT |
264 | enum dsi_vc_source { |
265 | DSI_VC_SOURCE_L4 = 0, | |
266 | DSI_VC_SOURCE_VP, | |
3de7a1dc TV |
267 | }; |
268 | ||
dfc0fd8d TV |
269 | struct dsi_irq_stats { |
270 | unsigned long last_reset; | |
d11e5c82 LP |
271 | unsigned int irq_count; |
272 | unsigned int dsi_irqs[32]; | |
273 | unsigned int vc_irqs[4][32]; | |
274 | unsigned int cio_irqs[32]; | |
dfc0fd8d TV |
275 | }; |
276 | ||
4ae2dddd TV |
277 | struct dsi_isr_tables { |
278 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; | |
279 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; | |
280 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; | |
281 | }; | |
282 | ||
f1e0001f | 283 | struct dsi_clk_calc_ctx { |
7093d6cd | 284 | struct dsi_data *dsi; |
2daea7af | 285 | struct dss_pll *pll; |
f1e0001f TV |
286 | |
287 | /* inputs */ | |
288 | ||
289 | const struct omap_dss_dsi_config *config; | |
290 | ||
291 | unsigned long req_pck_min, req_pck_nom, req_pck_max; | |
292 | ||
293 | /* outputs */ | |
294 | ||
2daea7af | 295 | struct dss_pll_clock_info dsi_cinfo; |
f1e0001f TV |
296 | struct dispc_clock_info dispc_cinfo; |
297 | ||
da11bbbb | 298 | struct videomode vm; |
f1e0001f TV |
299 | struct omap_dss_dsi_videomode_timings dsi_vm; |
300 | }; | |
301 | ||
7b71c410 TV |
302 | struct dsi_lp_clock_info { |
303 | unsigned long lp_clk; | |
304 | u16 lp_clk_div; | |
305 | }; | |
306 | ||
742e693b LP |
307 | struct dsi_module_id_data { |
308 | u32 address; | |
309 | int id; | |
310 | }; | |
311 | ||
44d8ca10 LP |
312 | enum dsi_quirks { |
313 | DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */ | |
314 | DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1), | |
315 | DSI_QUIRK_VC_OCP_WIDTH = (1 << 2), | |
316 | DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3), | |
317 | DSI_QUIRK_GNQ = (1 << 4), | |
318 | DSI_QUIRK_PHY_DCC = (1 << 5), | |
319 | }; | |
320 | ||
742e693b LP |
321 | struct dsi_of_data { |
322 | enum dsi_model model; | |
323 | const struct dss_pll_hw *pll_hw; | |
324 | const struct dsi_module_id_data *modules; | |
fe9964cb LP |
325 | unsigned int max_fck_freq; |
326 | unsigned int max_pll_lpdiv; | |
44d8ca10 | 327 | enum dsi_quirks quirks; |
742e693b LP |
328 | }; |
329 | ||
f1da39d9 | 330 | struct dsi_data { |
4600ea9c | 331 | struct device *dev; |
68104467 TV |
332 | void __iomem *proto_base; |
333 | void __iomem *phy_base; | |
334 | void __iomem *pll_base; | |
4fbafaf3 | 335 | |
742e693b | 336 | const struct dsi_of_data *data; |
11ee9606 TV |
337 | int module_id; |
338 | ||
affe360d | 339 | int irq; |
3de7a1dc | 340 | |
0925afc9 TV |
341 | bool is_enabled; |
342 | ||
4fbafaf3 | 343 | struct clk *dss_clk; |
9e1305d0 | 344 | struct regmap *syscon; |
8aea8e6a | 345 | struct dss_device *dss; |
4fbafaf3 | 346 | |
a0d269ec | 347 | struct dispc_clock_info user_dispc_cinfo; |
2daea7af | 348 | struct dss_pll_clock_info user_dsi_cinfo; |
3de7a1dc | 349 | |
7b71c410 TV |
350 | struct dsi_lp_clock_info user_lp_cinfo; |
351 | struct dsi_lp_clock_info current_lp_cinfo; | |
352 | ||
2daea7af TV |
353 | struct dss_pll pll; |
354 | ||
2a89dc15 | 355 | bool vdds_dsi_enabled; |
3de7a1dc TV |
356 | struct regulator *vdds_dsi_reg; |
357 | ||
358 | struct { | |
d6049144 | 359 | enum dsi_vc_source source; |
3de7a1dc | 360 | struct omap_dss_device *dssdev; |
558c73e2 TV |
361 | enum fifo_size tx_fifo_size; |
362 | enum fifo_size rx_fifo_size; | |
5ee3c144 | 363 | int vc_id; |
3de7a1dc TV |
364 | } vc[4]; |
365 | ||
366 | struct mutex lock; | |
b9eb5d7d | 367 | struct semaphore bus_lock; |
3de7a1dc | 368 | |
4ae2dddd TV |
369 | spinlock_t irq_lock; |
370 | struct dsi_isr_tables isr_tables; | |
371 | /* space for a copy used by the interrupt handler */ | |
372 | struct dsi_isr_tables isr_tables_copy; | |
373 | ||
18946f62 | 374 | int update_channel; |
477fed70 | 375 | #ifdef DSI_PERF_MEASURE |
d11e5c82 | 376 | unsigned int update_bytes; |
5476e74a | 377 | #endif |
3de7a1dc | 378 | |
3de7a1dc | 379 | bool te_enabled; |
40885ab3 | 380 | bool ulps_enabled; |
3de7a1dc | 381 | |
18946f62 TV |
382 | void (*framedone_callback)(int, void *); |
383 | void *framedone_data; | |
384 | ||
385 | struct delayed_work framedone_timeout_work; | |
386 | ||
3de7a1dc TV |
387 | #ifdef DSI_CATCH_MISSING_TE |
388 | struct timer_list te_timer; | |
389 | #endif | |
390 | ||
391 | unsigned long cache_req_pck; | |
392 | unsigned long cache_clk_freq; | |
2daea7af | 393 | struct dss_pll_clock_info cache_cinfo; |
3de7a1dc TV |
394 | |
395 | u32 errors; | |
396 | spinlock_t errors_lock; | |
477fed70 | 397 | #ifdef DSI_PERF_MEASURE |
3de7a1dc TV |
398 | ktime_t perf_setup_time; |
399 | ktime_t perf_start_time; | |
3de7a1dc TV |
400 | #endif |
401 | int debug_read; | |
402 | int debug_write; | |
f33656e1 LP |
403 | struct { |
404 | struct dss_debugfs_entry *irqs; | |
405 | struct dss_debugfs_entry *regs; | |
3ce75d67 | 406 | struct dss_debugfs_entry *clks; |
f33656e1 | 407 | } debugfs; |
dfc0fd8d TV |
408 | |
409 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
410 | spinlock_t irq_stats_lock; | |
411 | struct dsi_irq_stats irq_stats; | |
412 | #endif | |
24c1ae41 | 413 | |
d11e5c82 LP |
414 | unsigned int num_lanes_supported; |
415 | unsigned int line_buffer_size; | |
75d7247c | 416 | |
739a7f46 | 417 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; |
d11e5c82 | 418 | unsigned int num_lanes_used; |
75d7247c | 419 | |
d11e5c82 | 420 | unsigned int scp_clk_refcount; |
7d2572f8 AT |
421 | |
422 | struct dss_lcd_mgr_config mgr_config; | |
da11bbbb | 423 | struct videomode vm; |
02c3960b | 424 | enum omap_dss_dsi_pixel_format pix_fmt; |
dca2b152 | 425 | enum omap_dss_dsi_mode mode; |
0b3ffe39 | 426 | struct omap_dss_dsi_videomode_timings vm_timings; |
81b87f51 | 427 | |
1f68d9c4 | 428 | struct omap_dss_device output; |
f1da39d9 | 429 | }; |
3de7a1dc | 430 | |
2e868dbe | 431 | struct dsi_packet_sent_handler_data { |
7093d6cd | 432 | struct dsi_data *dsi; |
2e868dbe AT |
433 | struct completion *completion; |
434 | }; | |
435 | ||
477fed70 | 436 | #ifdef DSI_PERF_MEASURE |
90ab5ee9 RR |
437 | static bool dsi_perf; |
438 | module_param(dsi_perf, bool, 0644); | |
3de7a1dc TV |
439 | #endif |
440 | ||
c068408e | 441 | static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev) |
f1da39d9 | 442 | { |
c068408e | 443 | return dev_get_drvdata(dssdev->dev); |
a72b64b9 AT |
444 | } |
445 | ||
7093d6cd LP |
446 | static inline void dsi_write_reg(struct dsi_data *dsi, |
447 | const struct dsi_reg idx, u32 val) | |
3de7a1dc | 448 | { |
68104467 TV |
449 | void __iomem *base; |
450 | ||
451 | switch(idx.module) { | |
452 | case DSI_PROTO: base = dsi->proto_base; break; | |
453 | case DSI_PHY: base = dsi->phy_base; break; | |
454 | case DSI_PLL: base = dsi->pll_base; break; | |
455 | default: return; | |
456 | } | |
f1da39d9 | 457 | |
68104467 | 458 | __raw_writel(val, base + idx.idx); |
3de7a1dc TV |
459 | } |
460 | ||
7093d6cd | 461 | static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx) |
3de7a1dc | 462 | { |
68104467 | 463 | void __iomem *base; |
f1da39d9 | 464 | |
68104467 TV |
465 | switch(idx.module) { |
466 | case DSI_PROTO: base = dsi->proto_base; break; | |
467 | case DSI_PHY: base = dsi->phy_base; break; | |
468 | case DSI_PLL: base = dsi->pll_base; break; | |
469 | default: return 0; | |
470 | } | |
471 | ||
472 | return __raw_readl(base + idx.idx); | |
3de7a1dc TV |
473 | } |
474 | ||
5cfc1c3c | 475 | static void dsi_bus_lock(struct omap_dss_device *dssdev) |
3de7a1dc | 476 | { |
c068408e | 477 | struct dsi_data *dsi = to_dsi_data(dssdev); |
f1da39d9 AT |
478 | |
479 | down(&dsi->bus_lock); | |
3de7a1dc | 480 | } |
3de7a1dc | 481 | |
5cfc1c3c | 482 | static void dsi_bus_unlock(struct omap_dss_device *dssdev) |
3de7a1dc | 483 | { |
c068408e | 484 | struct dsi_data *dsi = to_dsi_data(dssdev); |
f1da39d9 AT |
485 | |
486 | up(&dsi->bus_lock); | |
3de7a1dc | 487 | } |
3de7a1dc | 488 | |
7093d6cd | 489 | static bool dsi_bus_is_locked(struct dsi_data *dsi) |
4f765023 | 490 | { |
f1da39d9 | 491 | return dsi->bus_lock.count == 0; |
4f765023 TV |
492 | } |
493 | ||
f36a06e7 TV |
494 | static void dsi_completion_handler(void *data, u32 mask) |
495 | { | |
496 | complete((struct completion *)data); | |
497 | } | |
498 | ||
7093d6cd LP |
499 | static inline bool wait_for_bit_change(struct dsi_data *dsi, |
500 | const struct dsi_reg idx, | |
501 | int bitnum, int value) | |
3de7a1dc | 502 | { |
3b98409e TV |
503 | unsigned long timeout; |
504 | ktime_t wait; | |
505 | int t; | |
3de7a1dc | 506 | |
3b98409e TV |
507 | /* first busyloop to see if the bit changes right away */ |
508 | t = 100; | |
509 | while (t-- > 0) { | |
7093d6cd | 510 | if (REG_GET(dsi, idx, bitnum, bitnum) == value) |
bafa89fc | 511 | return true; |
3de7a1dc TV |
512 | } |
513 | ||
3b98409e TV |
514 | /* then loop for 500ms, sleeping for 1ms in between */ |
515 | timeout = jiffies + msecs_to_jiffies(500); | |
516 | while (time_before(jiffies, timeout)) { | |
7093d6cd | 517 | if (REG_GET(dsi, idx, bitnum, bitnum) == value) |
bafa89fc | 518 | return true; |
3de7a1dc | 519 | |
3b98409e TV |
520 | wait = ns_to_ktime(1000 * 1000); |
521 | set_current_state(TASK_UNINTERRUPTIBLE); | |
522 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
3de7a1dc TV |
523 | } |
524 | ||
bafa89fc | 525 | return false; |
3de7a1dc TV |
526 | } |
527 | ||
892fdcb0 | 528 | static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
a3b3cc2b AT |
529 | { |
530 | switch (fmt) { | |
531 | case OMAP_DSS_DSI_FMT_RGB888: | |
532 | case OMAP_DSS_DSI_FMT_RGB666: | |
533 | return 24; | |
534 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
535 | return 18; | |
536 | case OMAP_DSS_DSI_FMT_RGB565: | |
537 | return 16; | |
538 | default: | |
539 | BUG(); | |
c6eee968 | 540 | return 0; |
a3b3cc2b AT |
541 | } |
542 | } | |
543 | ||
477fed70 | 544 | #ifdef DSI_PERF_MEASURE |
7093d6cd | 545 | static void dsi_perf_mark_setup(struct dsi_data *dsi) |
3de7a1dc | 546 | { |
f1da39d9 | 547 | dsi->perf_setup_time = ktime_get(); |
3de7a1dc TV |
548 | } |
549 | ||
7093d6cd | 550 | static void dsi_perf_mark_start(struct dsi_data *dsi) |
3de7a1dc | 551 | { |
f1da39d9 | 552 | dsi->perf_start_time = ktime_get(); |
3de7a1dc TV |
553 | } |
554 | ||
7093d6cd | 555 | static void dsi_perf_show(struct dsi_data *dsi, const char *name) |
3de7a1dc TV |
556 | { |
557 | ktime_t t, setup_time, trans_time; | |
558 | u32 total_bytes; | |
559 | u32 setup_us, trans_us, total_us; | |
560 | ||
561 | if (!dsi_perf) | |
562 | return; | |
563 | ||
3de7a1dc TV |
564 | t = ktime_get(); |
565 | ||
f1da39d9 | 566 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
3de7a1dc TV |
567 | setup_us = (u32)ktime_to_us(setup_time); |
568 | if (setup_us == 0) | |
569 | setup_us = 1; | |
570 | ||
f1da39d9 | 571 | trans_time = ktime_sub(t, dsi->perf_start_time); |
3de7a1dc TV |
572 | trans_us = (u32)ktime_to_us(trans_time); |
573 | if (trans_us == 0) | |
574 | trans_us = 1; | |
575 | ||
576 | total_us = setup_us + trans_us; | |
577 | ||
5476e74a | 578 | total_bytes = dsi->update_bytes; |
3de7a1dc | 579 | |
8dfe162a JP |
580 | pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n", |
581 | name, | |
582 | setup_us, | |
583 | trans_us, | |
584 | total_us, | |
585 | 1000 * 1000 / total_us, | |
586 | total_bytes, | |
587 | total_bytes * 1000 / total_us); | |
3de7a1dc TV |
588 | } |
589 | #else | |
7093d6cd | 590 | static inline void dsi_perf_mark_setup(struct dsi_data *dsi) |
4a9a5e39 TV |
591 | { |
592 | } | |
593 | ||
7093d6cd | 594 | static inline void dsi_perf_mark_start(struct dsi_data *dsi) |
4a9a5e39 TV |
595 | { |
596 | } | |
597 | ||
7093d6cd | 598 | static inline void dsi_perf_show(struct dsi_data *dsi, const char *name) |
4a9a5e39 TV |
599 | { |
600 | } | |
3de7a1dc TV |
601 | #endif |
602 | ||
f30be7d3 CM |
603 | static int verbose_irq; |
604 | ||
3de7a1dc TV |
605 | static void print_irq_status(u32 status) |
606 | { | |
d80d499e TV |
607 | if (status == 0) |
608 | return; | |
609 | ||
f30be7d3 | 610 | if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
3de7a1dc | 611 | return; |
3de7a1dc | 612 | |
f30be7d3 CM |
613 | #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" |
614 | ||
615 | pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", | |
616 | status, | |
617 | verbose_irq ? PIS(VC0) : "", | |
618 | verbose_irq ? PIS(VC1) : "", | |
619 | verbose_irq ? PIS(VC2) : "", | |
620 | verbose_irq ? PIS(VC3) : "", | |
621 | PIS(WAKEUP), | |
622 | PIS(RESYNC), | |
623 | PIS(PLL_LOCK), | |
624 | PIS(PLL_UNLOCK), | |
625 | PIS(PLL_RECALL), | |
626 | PIS(COMPLEXIO_ERR), | |
627 | PIS(HS_TX_TIMEOUT), | |
628 | PIS(LP_RX_TIMEOUT), | |
629 | PIS(TE_TRIGGER), | |
630 | PIS(ACK_TRIGGER), | |
631 | PIS(SYNC_LOST), | |
632 | PIS(LDO_POWER_GOOD), | |
633 | PIS(TA_TIMEOUT)); | |
634 | #undef PIS | |
3de7a1dc TV |
635 | } |
636 | ||
637 | static void print_irq_status_vc(int channel, u32 status) | |
638 | { | |
d80d499e TV |
639 | if (status == 0) |
640 | return; | |
641 | ||
f30be7d3 | 642 | if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
3de7a1dc | 643 | return; |
f30be7d3 CM |
644 | |
645 | #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" | |
646 | ||
647 | pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", | |
648 | channel, | |
649 | status, | |
650 | PIS(CS), | |
651 | PIS(ECC_CORR), | |
652 | PIS(ECC_NO_CORR), | |
653 | verbose_irq ? PIS(PACKET_SENT) : "", | |
654 | PIS(BTA), | |
655 | PIS(FIFO_TX_OVF), | |
656 | PIS(FIFO_RX_OVF), | |
657 | PIS(FIFO_TX_UDF), | |
658 | PIS(PP_BUSY_CHANGE)); | |
3de7a1dc | 659 | #undef PIS |
3de7a1dc TV |
660 | } |
661 | ||
662 | static void print_irq_status_cio(u32 status) | |
663 | { | |
d80d499e TV |
664 | if (status == 0) |
665 | return; | |
666 | ||
f30be7d3 CM |
667 | #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" |
668 | ||
669 | pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", | |
670 | status, | |
671 | PIS(ERRSYNCESC1), | |
672 | PIS(ERRSYNCESC2), | |
673 | PIS(ERRSYNCESC3), | |
674 | PIS(ERRESC1), | |
675 | PIS(ERRESC2), | |
676 | PIS(ERRESC3), | |
677 | PIS(ERRCONTROL1), | |
678 | PIS(ERRCONTROL2), | |
679 | PIS(ERRCONTROL3), | |
680 | PIS(STATEULPS1), | |
681 | PIS(STATEULPS2), | |
682 | PIS(STATEULPS3), | |
683 | PIS(ERRCONTENTIONLP0_1), | |
684 | PIS(ERRCONTENTIONLP1_1), | |
685 | PIS(ERRCONTENTIONLP0_2), | |
686 | PIS(ERRCONTENTIONLP1_2), | |
687 | PIS(ERRCONTENTIONLP0_3), | |
688 | PIS(ERRCONTENTIONLP1_3), | |
689 | PIS(ULPSACTIVENOT_ALL0), | |
690 | PIS(ULPSACTIVENOT_ALL1)); | |
3de7a1dc | 691 | #undef PIS |
3de7a1dc TV |
692 | } |
693 | ||
69b281a6 | 694 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
7093d6cd LP |
695 | static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus, |
696 | u32 *vcstatus, u32 ciostatus) | |
3de7a1dc | 697 | { |
3de7a1dc TV |
698 | int i; |
699 | ||
f1da39d9 | 700 | spin_lock(&dsi->irq_stats_lock); |
69b281a6 | 701 | |
f1da39d9 AT |
702 | dsi->irq_stats.irq_count++; |
703 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); | |
69b281a6 TV |
704 | |
705 | for (i = 0; i < 4; ++i) | |
f1da39d9 | 706 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
69b281a6 | 707 | |
f1da39d9 | 708 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
69b281a6 | 709 | |
f1da39d9 | 710 | spin_unlock(&dsi->irq_stats_lock); |
69b281a6 TV |
711 | } |
712 | #else | |
7093d6cd | 713 | #define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus) |
dfc0fd8d TV |
714 | #endif |
715 | ||
69b281a6 TV |
716 | static int debug_irq; |
717 | ||
7093d6cd LP |
718 | static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus, |
719 | u32 *vcstatus, u32 ciostatus) | |
69b281a6 TV |
720 | { |
721 | int i; | |
722 | ||
3de7a1dc TV |
723 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
724 | DSSERR("DSI error, irqstatus %x\n", irqstatus); | |
725 | print_irq_status(irqstatus); | |
f1da39d9 AT |
726 | spin_lock(&dsi->errors_lock); |
727 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; | |
728 | spin_unlock(&dsi->errors_lock); | |
3de7a1dc TV |
729 | } else if (debug_irq) { |
730 | print_irq_status(irqstatus); | |
731 | } | |
732 | ||
3de7a1dc | 733 | for (i = 0; i < 4; ++i) { |
69b281a6 TV |
734 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
735 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", | |
736 | i, vcstatus[i]); | |
737 | print_irq_status_vc(i, vcstatus[i]); | |
738 | } else if (debug_irq) { | |
739 | print_irq_status_vc(i, vcstatus[i]); | |
740 | } | |
741 | } | |
3de7a1dc | 742 | |
69b281a6 TV |
743 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
744 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); | |
745 | print_irq_status_cio(ciostatus); | |
746 | } else if (debug_irq) { | |
747 | print_irq_status_cio(ciostatus); | |
748 | } | |
749 | } | |
3de7a1dc | 750 | |
4ae2dddd | 751 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
d11e5c82 | 752 | unsigned int isr_array_size, u32 irqstatus) |
4ae2dddd TV |
753 | { |
754 | struct dsi_isr_data *isr_data; | |
755 | int i; | |
756 | ||
757 | for (i = 0; i < isr_array_size; i++) { | |
758 | isr_data = &isr_array[i]; | |
759 | if (isr_data->isr && isr_data->mask & irqstatus) | |
760 | isr_data->isr(isr_data->arg, irqstatus); | |
761 | } | |
762 | } | |
763 | ||
764 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, | |
765 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
766 | { | |
767 | int i; | |
768 | ||
769 | dsi_call_isrs(isr_tables->isr_table, | |
770 | ARRAY_SIZE(isr_tables->isr_table), | |
771 | irqstatus); | |
772 | ||
773 | for (i = 0; i < 4; ++i) { | |
774 | if (vcstatus[i] == 0) | |
775 | continue; | |
776 | dsi_call_isrs(isr_tables->isr_table_vc[i], | |
777 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), | |
778 | vcstatus[i]); | |
779 | } | |
780 | ||
781 | if (ciostatus != 0) | |
782 | dsi_call_isrs(isr_tables->isr_table_cio, | |
783 | ARRAY_SIZE(isr_tables->isr_table_cio), | |
784 | ciostatus); | |
785 | } | |
786 | ||
69b281a6 TV |
787 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
788 | { | |
7093d6cd | 789 | struct dsi_data *dsi = arg; |
69b281a6 TV |
790 | u32 irqstatus, vcstatus[4], ciostatus; |
791 | int i; | |
dfc0fd8d | 792 | |
0925afc9 TV |
793 | if (!dsi->is_enabled) |
794 | return IRQ_NONE; | |
795 | ||
f1da39d9 | 796 | spin_lock(&dsi->irq_lock); |
4ae2dddd | 797 | |
7093d6cd | 798 | irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS); |
3de7a1dc | 799 | |
69b281a6 | 800 | /* IRQ is not for us */ |
4ae2dddd | 801 | if (!irqstatus) { |
f1da39d9 | 802 | spin_unlock(&dsi->irq_lock); |
69b281a6 | 803 | return IRQ_NONE; |
4ae2dddd | 804 | } |
ab83b14c | 805 | |
7093d6cd | 806 | dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
69b281a6 | 807 | /* flush posted write */ |
7093d6cd | 808 | dsi_read_reg(dsi, DSI_IRQSTATUS); |
69b281a6 TV |
809 | |
810 | for (i = 0; i < 4; ++i) { | |
811 | if ((irqstatus & (1 << i)) == 0) { | |
812 | vcstatus[i] = 0; | |
813 | continue; | |
3de7a1dc TV |
814 | } |
815 | ||
7093d6cd | 816 | vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); |
69b281a6 | 817 | |
7093d6cd | 818 | dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
3de7a1dc | 819 | /* flush posted write */ |
7093d6cd | 820 | dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); |
3de7a1dc TV |
821 | } |
822 | ||
823 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { | |
7093d6cd | 824 | ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); |
3de7a1dc | 825 | |
7093d6cd | 826 | dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
3de7a1dc | 827 | /* flush posted write */ |
7093d6cd | 828 | dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); |
69b281a6 TV |
829 | } else { |
830 | ciostatus = 0; | |
831 | } | |
3de7a1dc | 832 | |
69b281a6 TV |
833 | #ifdef DSI_CATCH_MISSING_TE |
834 | if (irqstatus & DSI_IRQ_TE_TRIGGER) | |
f1da39d9 | 835 | del_timer(&dsi->te_timer); |
69b281a6 TV |
836 | #endif |
837 | ||
4ae2dddd TV |
838 | /* make a copy and unlock, so that isrs can unregister |
839 | * themselves */ | |
f1da39d9 AT |
840 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
841 | sizeof(dsi->isr_tables)); | |
4ae2dddd | 842 | |
f1da39d9 | 843 | spin_unlock(&dsi->irq_lock); |
4ae2dddd | 844 | |
f1da39d9 | 845 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
4ae2dddd | 846 | |
7093d6cd | 847 | dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus); |
69b281a6 | 848 | |
7093d6cd | 849 | dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus); |
dfc0fd8d | 850 | |
affe360d | 851 | return IRQ_HANDLED; |
3de7a1dc TV |
852 | } |
853 | ||
f1da39d9 | 854 | /* dsi->irq_lock has to be locked by the caller */ |
7093d6cd LP |
855 | static void _omap_dsi_configure_irqs(struct dsi_data *dsi, |
856 | struct dsi_isr_data *isr_array, | |
857 | unsigned int isr_array_size, | |
858 | u32 default_mask, | |
859 | const struct dsi_reg enable_reg, | |
860 | const struct dsi_reg status_reg) | |
3de7a1dc | 861 | { |
4ae2dddd TV |
862 | struct dsi_isr_data *isr_data; |
863 | u32 mask; | |
864 | u32 old_mask; | |
3de7a1dc TV |
865 | int i; |
866 | ||
4ae2dddd | 867 | mask = default_mask; |
3de7a1dc | 868 | |
4ae2dddd TV |
869 | for (i = 0; i < isr_array_size; i++) { |
870 | isr_data = &isr_array[i]; | |
3de7a1dc | 871 | |
4ae2dddd TV |
872 | if (isr_data->isr == NULL) |
873 | continue; | |
874 | ||
875 | mask |= isr_data->mask; | |
3de7a1dc TV |
876 | } |
877 | ||
7093d6cd | 878 | old_mask = dsi_read_reg(dsi, enable_reg); |
4ae2dddd | 879 | /* clear the irqstatus for newly enabled irqs */ |
7093d6cd LP |
880 | dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask); |
881 | dsi_write_reg(dsi, enable_reg, mask); | |
4ae2dddd TV |
882 | |
883 | /* flush posted writes */ | |
7093d6cd LP |
884 | dsi_read_reg(dsi, enable_reg); |
885 | dsi_read_reg(dsi, status_reg); | |
4ae2dddd | 886 | } |
3de7a1dc | 887 | |
f1da39d9 | 888 | /* dsi->irq_lock has to be locked by the caller */ |
7093d6cd | 889 | static void _omap_dsi_set_irqs(struct dsi_data *dsi) |
4ae2dddd TV |
890 | { |
891 | u32 mask = DSI_IRQ_ERROR_MASK; | |
3de7a1dc | 892 | #ifdef DSI_CATCH_MISSING_TE |
4ae2dddd | 893 | mask |= DSI_IRQ_TE_TRIGGER; |
3de7a1dc | 894 | #endif |
7093d6cd | 895 | _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table, |
f1da39d9 | 896 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, |
4ae2dddd TV |
897 | DSI_IRQENABLE, DSI_IRQSTATUS); |
898 | } | |
3de7a1dc | 899 | |
f1da39d9 | 900 | /* dsi->irq_lock has to be locked by the caller */ |
7093d6cd | 901 | static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc) |
4ae2dddd | 902 | { |
7093d6cd | 903 | _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc], |
f1da39d9 | 904 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), |
4ae2dddd TV |
905 | DSI_VC_IRQ_ERROR_MASK, |
906 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); | |
907 | } | |
908 | ||
f1da39d9 | 909 | /* dsi->irq_lock has to be locked by the caller */ |
7093d6cd | 910 | static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi) |
4ae2dddd | 911 | { |
7093d6cd | 912 | _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio, |
f1da39d9 | 913 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), |
4ae2dddd TV |
914 | DSI_CIO_IRQ_ERROR_MASK, |
915 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); | |
916 | } | |
917 | ||
7093d6cd | 918 | static void _dsi_initialize_irq(struct dsi_data *dsi) |
4ae2dddd TV |
919 | { |
920 | unsigned long flags; | |
921 | int vc; | |
922 | ||
f1da39d9 | 923 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 924 | |
f1da39d9 | 925 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
4ae2dddd | 926 | |
7093d6cd | 927 | _omap_dsi_set_irqs(dsi); |
4ae2dddd | 928 | for (vc = 0; vc < 4; ++vc) |
7093d6cd LP |
929 | _omap_dsi_set_irqs_vc(dsi, vc); |
930 | _omap_dsi_set_irqs_cio(dsi); | |
4ae2dddd | 931 | |
f1da39d9 | 932 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd | 933 | } |
3de7a1dc | 934 | |
4ae2dddd | 935 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
d11e5c82 | 936 | struct dsi_isr_data *isr_array, unsigned int isr_array_size) |
4ae2dddd TV |
937 | { |
938 | struct dsi_isr_data *isr_data; | |
939 | int free_idx; | |
940 | int i; | |
941 | ||
942 | BUG_ON(isr == NULL); | |
943 | ||
944 | /* check for duplicate entry and find a free slot */ | |
945 | free_idx = -1; | |
946 | for (i = 0; i < isr_array_size; i++) { | |
947 | isr_data = &isr_array[i]; | |
948 | ||
949 | if (isr_data->isr == isr && isr_data->arg == arg && | |
950 | isr_data->mask == mask) { | |
951 | return -EINVAL; | |
952 | } | |
953 | ||
954 | if (isr_data->isr == NULL && free_idx == -1) | |
955 | free_idx = i; | |
956 | } | |
957 | ||
958 | if (free_idx == -1) | |
959 | return -EBUSY; | |
960 | ||
961 | isr_data = &isr_array[free_idx]; | |
962 | isr_data->isr = isr; | |
963 | isr_data->arg = arg; | |
964 | isr_data->mask = mask; | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
969 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
d11e5c82 | 970 | struct dsi_isr_data *isr_array, unsigned int isr_array_size) |
4ae2dddd TV |
971 | { |
972 | struct dsi_isr_data *isr_data; | |
973 | int i; | |
974 | ||
975 | for (i = 0; i < isr_array_size; i++) { | |
976 | isr_data = &isr_array[i]; | |
977 | if (isr_data->isr != isr || isr_data->arg != arg || | |
978 | isr_data->mask != mask) | |
979 | continue; | |
980 | ||
981 | isr_data->isr = NULL; | |
982 | isr_data->arg = NULL; | |
983 | isr_data->mask = 0; | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | return -EINVAL; | |
989 | } | |
990 | ||
7093d6cd LP |
991 | static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, |
992 | void *arg, u32 mask) | |
4ae2dddd TV |
993 | { |
994 | unsigned long flags; | |
995 | int r; | |
996 | ||
f1da39d9 | 997 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 998 | |
f1da39d9 AT |
999 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
1000 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
1001 | |
1002 | if (r == 0) | |
7093d6cd | 1003 | _omap_dsi_set_irqs(dsi); |
4ae2dddd | 1004 | |
f1da39d9 | 1005 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1006 | |
1007 | return r; | |
1008 | } | |
1009 | ||
7093d6cd LP |
1010 | static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, |
1011 | void *arg, u32 mask) | |
4ae2dddd TV |
1012 | { |
1013 | unsigned long flags; | |
1014 | int r; | |
1015 | ||
f1da39d9 | 1016 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1017 | |
f1da39d9 AT |
1018 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
1019 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
1020 | |
1021 | if (r == 0) | |
7093d6cd | 1022 | _omap_dsi_set_irqs(dsi); |
4ae2dddd | 1023 | |
f1da39d9 | 1024 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1025 | |
1026 | return r; | |
1027 | } | |
1028 | ||
7093d6cd LP |
1029 | static int dsi_register_isr_vc(struct dsi_data *dsi, int channel, |
1030 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd TV |
1031 | { |
1032 | unsigned long flags; | |
1033 | int r; | |
1034 | ||
f1da39d9 | 1035 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
1036 | |
1037 | r = _dsi_register_isr(isr, arg, mask, | |
f1da39d9 AT |
1038 | dsi->isr_tables.isr_table_vc[channel], |
1039 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
1040 | |
1041 | if (r == 0) | |
7093d6cd | 1042 | _omap_dsi_set_irqs_vc(dsi, channel); |
4ae2dddd | 1043 | |
f1da39d9 | 1044 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1045 | |
1046 | return r; | |
1047 | } | |
1048 | ||
7093d6cd LP |
1049 | static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel, |
1050 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd TV |
1051 | { |
1052 | unsigned long flags; | |
1053 | int r; | |
1054 | ||
f1da39d9 | 1055 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
1056 | |
1057 | r = _dsi_unregister_isr(isr, arg, mask, | |
f1da39d9 AT |
1058 | dsi->isr_tables.isr_table_vc[channel], |
1059 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
1060 | |
1061 | if (r == 0) | |
7093d6cd | 1062 | _omap_dsi_set_irqs_vc(dsi, channel); |
4ae2dddd | 1063 | |
f1da39d9 | 1064 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1065 | |
1066 | return r; | |
1067 | } | |
1068 | ||
7093d6cd LP |
1069 | static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr, |
1070 | void *arg, u32 mask) | |
4ae2dddd TV |
1071 | { |
1072 | unsigned long flags; | |
1073 | int r; | |
1074 | ||
f1da39d9 | 1075 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1076 | |
f1da39d9 AT |
1077 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1078 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1079 | |
1080 | if (r == 0) | |
7093d6cd | 1081 | _omap_dsi_set_irqs_cio(dsi); |
4ae2dddd | 1082 | |
f1da39d9 | 1083 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1084 | |
1085 | return r; | |
1086 | } | |
1087 | ||
7093d6cd LP |
1088 | static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr, |
1089 | void *arg, u32 mask) | |
4ae2dddd TV |
1090 | { |
1091 | unsigned long flags; | |
1092 | int r; | |
1093 | ||
f1da39d9 | 1094 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1095 | |
f1da39d9 AT |
1096 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1097 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1098 | |
1099 | if (r == 0) | |
7093d6cd | 1100 | _omap_dsi_set_irqs_cio(dsi); |
4ae2dddd | 1101 | |
f1da39d9 | 1102 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1103 | |
1104 | return r; | |
3de7a1dc TV |
1105 | } |
1106 | ||
7093d6cd | 1107 | static u32 dsi_get_errors(struct dsi_data *dsi) |
3de7a1dc TV |
1108 | { |
1109 | unsigned long flags; | |
1110 | u32 e; | |
7093d6cd | 1111 | |
f1da39d9 AT |
1112 | spin_lock_irqsave(&dsi->errors_lock, flags); |
1113 | e = dsi->errors; | |
1114 | dsi->errors = 0; | |
1115 | spin_unlock_irqrestore(&dsi->errors_lock, flags); | |
3de7a1dc TV |
1116 | return e; |
1117 | } | |
1118 | ||
7093d6cd | 1119 | static int dsi_runtime_get(struct dsi_data *dsi) |
3de7a1dc | 1120 | { |
4fbafaf3 | 1121 | int r; |
4fbafaf3 TV |
1122 | |
1123 | DSSDBG("dsi_runtime_get\n"); | |
1124 | ||
4600ea9c | 1125 | r = pm_runtime_get_sync(dsi->dev); |
4fbafaf3 TV |
1126 | WARN_ON(r < 0); |
1127 | return r < 0 ? r : 0; | |
1128 | } | |
1129 | ||
7093d6cd | 1130 | static void dsi_runtime_put(struct dsi_data *dsi) |
4fbafaf3 | 1131 | { |
4fbafaf3 TV |
1132 | int r; |
1133 | ||
1134 | DSSDBG("dsi_runtime_put\n"); | |
1135 | ||
4600ea9c | 1136 | r = pm_runtime_put_sync(dsi->dev); |
5be3aebd | 1137 | WARN_ON(r < 0 && r != -ENOSYS); |
3de7a1dc TV |
1138 | } |
1139 | ||
7093d6cd | 1140 | static void _dsi_print_reset_status(struct dsi_data *dsi) |
3de7a1dc TV |
1141 | { |
1142 | u32 l; | |
c335cbf9 | 1143 | int b0, b1, b2; |
3de7a1dc | 1144 | |
3de7a1dc TV |
1145 | /* A dummy read using the SCP interface to any DSIPHY register is |
1146 | * required after DSIPHY reset to complete the reset of the DSI complex | |
1147 | * I/O. */ | |
7093d6cd | 1148 | l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); |
3de7a1dc | 1149 | |
44d8ca10 | 1150 | if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { |
c335cbf9 TV |
1151 | b0 = 28; |
1152 | b1 = 27; | |
1153 | b2 = 26; | |
1154 | } else { | |
1155 | b0 = 24; | |
1156 | b1 = 25; | |
1157 | b2 = 26; | |
1158 | } | |
1159 | ||
f30be7d3 | 1160 | #define DSI_FLD_GET(fld, start, end)\ |
7093d6cd | 1161 | FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end) |
f30be7d3 CM |
1162 | |
1163 | pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", | |
1164 | DSI_FLD_GET(PLL_STATUS, 0, 0), | |
1165 | DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), | |
1166 | DSI_FLD_GET(DSIPHY_CFG5, b0, b0), | |
1167 | DSI_FLD_GET(DSIPHY_CFG5, b1, b1), | |
1168 | DSI_FLD_GET(DSIPHY_CFG5, b2, b2), | |
1169 | DSI_FLD_GET(DSIPHY_CFG5, 29, 29), | |
1170 | DSI_FLD_GET(DSIPHY_CFG5, 30, 30), | |
1171 | DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); | |
1172 | ||
1173 | #undef DSI_FLD_GET | |
3de7a1dc | 1174 | } |
3de7a1dc | 1175 | |
7093d6cd | 1176 | static inline int dsi_if_enable(struct dsi_data *dsi, bool enable) |
3de7a1dc TV |
1177 | { |
1178 | DSSDBG("dsi_if_enable(%d)\n", enable); | |
1179 | ||
1180 | enable = enable ? 1 : 0; | |
7093d6cd | 1181 | REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
3de7a1dc | 1182 | |
7093d6cd | 1183 | if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) { |
bafa89fc LP |
1184 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
1185 | return -EIO; | |
3de7a1dc TV |
1186 | } |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
7093d6cd | 1191 | static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi) |
3de7a1dc | 1192 | { |
2daea7af | 1193 | return dsi->pll.cinfo.clkout[HSDIV_DISPC]; |
3de7a1dc TV |
1194 | } |
1195 | ||
7093d6cd | 1196 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi) |
3de7a1dc | 1197 | { |
2daea7af | 1198 | return dsi->pll.cinfo.clkout[HSDIV_DSI]; |
3de7a1dc TV |
1199 | } |
1200 | ||
7093d6cd | 1201 | static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi) |
3de7a1dc | 1202 | { |
2daea7af | 1203 | return dsi->pll.cinfo.clkdco / 16; |
3de7a1dc TV |
1204 | } |
1205 | ||
7093d6cd | 1206 | static unsigned long dsi_fclk_rate(struct dsi_data *dsi) |
3de7a1dc TV |
1207 | { |
1208 | unsigned long r; | |
3cc62aad | 1209 | enum dss_clk_source source; |
3de7a1dc | 1210 | |
3cc62aad LP |
1211 | source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id); |
1212 | if (source == DSS_CLK_SRC_FCK) { | |
1bb47835 | 1213 | /* DSI FCLK source is DSS_CLK_FCK */ |
4fbafaf3 | 1214 | r = clk_get_rate(dsi->dss_clk); |
3de7a1dc | 1215 | } else { |
1bb47835 | 1216 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
7093d6cd | 1217 | r = dsi_get_pll_hsdiv_dsi_rate(dsi); |
3de7a1dc TV |
1218 | } |
1219 | ||
1220 | return r; | |
1221 | } | |
1222 | ||
7b71c410 TV |
1223 | static int dsi_lp_clock_calc(unsigned long dsi_fclk, |
1224 | unsigned long lp_clk_min, unsigned long lp_clk_max, | |
1225 | struct dsi_lp_clock_info *lp_cinfo) | |
f1e0001f | 1226 | { |
d11e5c82 | 1227 | unsigned int lp_clk_div; |
f1e0001f TV |
1228 | unsigned long lp_clk; |
1229 | ||
1230 | lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); | |
1231 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1232 | ||
1233 | if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) | |
1234 | return -EINVAL; | |
1235 | ||
7b71c410 TV |
1236 | lp_cinfo->lp_clk_div = lp_clk_div; |
1237 | lp_cinfo->lp_clk = lp_clk; | |
f1e0001f TV |
1238 | |
1239 | return 0; | |
1240 | } | |
1241 | ||
7093d6cd | 1242 | static int dsi_set_lp_clk_divisor(struct dsi_data *dsi) |
3de7a1dc TV |
1243 | { |
1244 | unsigned long dsi_fclk; | |
d11e5c82 | 1245 | unsigned int lp_clk_div; |
3de7a1dc | 1246 | unsigned long lp_clk; |
d11e5c82 | 1247 | unsigned int lpdiv_max = dsi->data->max_pll_lpdiv; |
2daea7af | 1248 | |
3de7a1dc | 1249 | |
7b71c410 | 1250 | lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; |
3de7a1dc | 1251 | |
2daea7af | 1252 | if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) |
3de7a1dc TV |
1253 | return -EINVAL; |
1254 | ||
7093d6cd | 1255 | dsi_fclk = dsi_fclk_rate(dsi); |
3de7a1dc TV |
1256 | |
1257 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1258 | ||
1259 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); | |
7b71c410 TV |
1260 | dsi->current_lp_cinfo.lp_clk = lp_clk; |
1261 | dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; | |
3de7a1dc | 1262 | |
a72b64b9 | 1263 | /* LP_CLK_DIVISOR */ |
7093d6cd | 1264 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); |
3de7a1dc | 1265 | |
a72b64b9 | 1266 | /* LP_RX_SYNCHRO_ENABLE */ |
7093d6cd | 1267 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); |
3de7a1dc TV |
1268 | |
1269 | return 0; | |
1270 | } | |
1271 | ||
7093d6cd | 1272 | static void dsi_enable_scp_clk(struct dsi_data *dsi) |
24c1ae41 | 1273 | { |
f1da39d9 | 1274 | if (dsi->scp_clk_refcount++ == 0) |
7093d6cd | 1275 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 TV |
1276 | } |
1277 | ||
7093d6cd | 1278 | static void dsi_disable_scp_clk(struct dsi_data *dsi) |
24c1ae41 | 1279 | { |
f1da39d9 AT |
1280 | WARN_ON(dsi->scp_clk_refcount == 0); |
1281 | if (--dsi->scp_clk_refcount == 0) | |
7093d6cd | 1282 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 | 1283 | } |
3de7a1dc TV |
1284 | |
1285 | enum dsi_pll_power_state { | |
1286 | DSI_PLL_POWER_OFF = 0x0, | |
1287 | DSI_PLL_POWER_ON_HSCLK = 0x1, | |
1288 | DSI_PLL_POWER_ON_ALL = 0x2, | |
1289 | DSI_PLL_POWER_ON_DIV = 0x3, | |
1290 | }; | |
1291 | ||
7093d6cd | 1292 | static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state) |
3de7a1dc TV |
1293 | { |
1294 | int t = 0; | |
1295 | ||
c94dfe05 | 1296 | /* DSI-PLL power command 0x3 is not working */ |
44d8ca10 LP |
1297 | if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && |
1298 | state == DSI_PLL_POWER_ON_DIV) | |
c94dfe05 TV |
1299 | state = DSI_PLL_POWER_ON_ALL; |
1300 | ||
a72b64b9 | 1301 | /* PLL_PWR_CMD */ |
7093d6cd | 1302 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); |
3de7a1dc TV |
1303 | |
1304 | /* PLL_PWR_STATUS */ | |
7093d6cd | 1305 | while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) { |
24be78b3 | 1306 | if (++t > 1000) { |
3de7a1dc TV |
1307 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
1308 | state); | |
1309 | return -ENODEV; | |
1310 | } | |
24be78b3 | 1311 | udelay(1); |
3de7a1dc TV |
1312 | } |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
3de7a1dc | 1317 | |
fe9964cb LP |
1318 | static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi, |
1319 | struct dss_pll_clock_info *cinfo) | |
d66b1581 TV |
1320 | { |
1321 | unsigned long max_dsi_fck; | |
1322 | ||
fe9964cb | 1323 | max_dsi_fck = dsi->data->max_fck_freq; |
d66b1581 | 1324 | |
2daea7af TV |
1325 | cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); |
1326 | cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; | |
d66b1581 TV |
1327 | } |
1328 | ||
2daea7af | 1329 | static int dsi_pll_enable(struct dss_pll *pll) |
544bfb68 | 1330 | { |
2daea7af | 1331 | struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); |
3de7a1dc | 1332 | int r = 0; |
3de7a1dc TV |
1333 | |
1334 | DSSDBG("PLL init\n"); | |
1335 | ||
7093d6cd | 1336 | r = dsi_runtime_get(dsi); |
f76b178a TV |
1337 | if (r) |
1338 | return r; | |
1339 | ||
24c1ae41 TV |
1340 | /* |
1341 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. | |
1342 | */ | |
7093d6cd | 1343 | dsi_enable_scp_clk(dsi); |
3de7a1dc | 1344 | |
f1da39d9 AT |
1345 | if (!dsi->vdds_dsi_enabled) { |
1346 | r = regulator_enable(dsi->vdds_dsi_reg); | |
2a89dc15 TV |
1347 | if (r) |
1348 | goto err0; | |
f1da39d9 | 1349 | dsi->vdds_dsi_enabled = true; |
2a89dc15 | 1350 | } |
3de7a1dc TV |
1351 | |
1352 | /* XXX PLL does not come out of reset without this... */ | |
8a7eda76 | 1353 | dispc_pck_free_enable(dsi->dss->dispc, 1); |
3de7a1dc | 1354 | |
7093d6cd | 1355 | if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) { |
3de7a1dc TV |
1356 | DSSERR("PLL not coming out of reset.\n"); |
1357 | r = -ENODEV; | |
8a7eda76 | 1358 | dispc_pck_free_enable(dsi->dss->dispc, 0); |
3de7a1dc TV |
1359 | goto err1; |
1360 | } | |
1361 | ||
1362 | /* XXX ... but if left on, we get problems when planes do not | |
1363 | * fill the whole display. No idea about this */ | |
8a7eda76 | 1364 | dispc_pck_free_enable(dsi->dss->dispc, 0); |
3de7a1dc | 1365 | |
7093d6cd | 1366 | r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL); |
3de7a1dc TV |
1367 | |
1368 | if (r) | |
1369 | goto err1; | |
1370 | ||
1371 | DSSDBG("PLL init done\n"); | |
1372 | ||
1373 | return 0; | |
1374 | err1: | |
f1da39d9 AT |
1375 | if (dsi->vdds_dsi_enabled) { |
1376 | regulator_disable(dsi->vdds_dsi_reg); | |
1377 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1378 | } |
3de7a1dc | 1379 | err0: |
7093d6cd LP |
1380 | dsi_disable_scp_clk(dsi); |
1381 | dsi_runtime_put(dsi); | |
3de7a1dc TV |
1382 | return r; |
1383 | } | |
1384 | ||
7093d6cd | 1385 | static void dsi_pll_uninit(struct dsi_data *dsi, bool disconnect_lanes) |
3de7a1dc | 1386 | { |
7093d6cd | 1387 | dsi_pll_power(dsi, DSI_PLL_POWER_OFF); |
2a89dc15 | 1388 | if (disconnect_lanes) { |
f1da39d9 AT |
1389 | WARN_ON(!dsi->vdds_dsi_enabled); |
1390 | regulator_disable(dsi->vdds_dsi_reg); | |
1391 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1392 | } |
24c1ae41 | 1393 | |
7093d6cd LP |
1394 | dsi_disable_scp_clk(dsi); |
1395 | dsi_runtime_put(dsi); | |
24c1ae41 | 1396 | |
3de7a1dc TV |
1397 | DSSDBG("PLL uninit done\n"); |
1398 | } | |
1399 | ||
2daea7af TV |
1400 | static void dsi_pll_disable(struct dss_pll *pll) |
1401 | { | |
1402 | struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); | |
2daea7af | 1403 | |
7093d6cd | 1404 | dsi_pll_uninit(dsi, true); |
2daea7af TV |
1405 | } |
1406 | ||
3ce75d67 | 1407 | static int dsi_dump_dsi_clocks(struct seq_file *s, void *p) |
3de7a1dc | 1408 | { |
4df04ac9 | 1409 | struct dsi_data *dsi = s->private; |
2daea7af | 1410 | struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; |
dc0352d1 | 1411 | enum dss_clk_source dispc_clk_src, dsi_clk_src; |
11ee9606 | 1412 | int dsi_module = dsi->module_id; |
2daea7af | 1413 | struct dss_pll *pll = &dsi->pll; |
067a57e4 | 1414 | |
3cc62aad LP |
1415 | dispc_clk_src = dss_get_dispc_clk_source(dsi->dss); |
1416 | dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module); | |
3de7a1dc | 1417 | |
7093d6cd | 1418 | if (dsi_runtime_get(dsi)) |
3ce75d67 | 1419 | return 0; |
3de7a1dc | 1420 | |
5a8b572d | 1421 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); |
3de7a1dc | 1422 | |
2daea7af | 1423 | seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); |
3de7a1dc | 1424 | |
2daea7af | 1425 | seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); |
3de7a1dc | 1426 | |
2daea7af TV |
1427 | seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", |
1428 | cinfo->clkdco, cinfo->m); | |
3de7a1dc | 1429 | |
2daea7af | 1430 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", |
407bd564 | 1431 | dss_get_clk_source_name(dsi_module == 0 ? |
3b63ca75 TV |
1432 | DSS_CLK_SRC_PLL1_1 : |
1433 | DSS_CLK_SRC_PLL2_1), | |
acf604b7 | 1434 | cinfo->clkout[HSDIV_DISPC], |
2daea7af | 1435 | cinfo->mX[HSDIV_DISPC], |
3b63ca75 | 1436 | dispc_clk_src == DSS_CLK_SRC_FCK ? |
63cf28ac | 1437 | "off" : "on"); |
3de7a1dc | 1438 | |
2daea7af | 1439 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", |
407bd564 | 1440 | dss_get_clk_source_name(dsi_module == 0 ? |
3b63ca75 TV |
1441 | DSS_CLK_SRC_PLL1_2 : |
1442 | DSS_CLK_SRC_PLL2_2), | |
acf604b7 | 1443 | cinfo->clkout[HSDIV_DSI], |
2daea7af | 1444 | cinfo->mX[HSDIV_DSI], |
3b63ca75 | 1445 | dsi_clk_src == DSS_CLK_SRC_FCK ? |
63cf28ac | 1446 | "off" : "on"); |
3de7a1dc | 1447 | |
5a8b572d | 1448 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
3de7a1dc | 1449 | |
557a1544 | 1450 | seq_printf(s, "dsi fclk source = %s\n", |
407bd564 | 1451 | dss_get_clk_source_name(dsi_clk_src)); |
3de7a1dc | 1452 | |
7093d6cd | 1453 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi)); |
3de7a1dc TV |
1454 | |
1455 | seq_printf(s, "DDR_CLK\t\t%lu\n", | |
4a38aede | 1456 | cinfo->clkdco / 4); |
3de7a1dc | 1457 | |
7093d6cd | 1458 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi)); |
3de7a1dc | 1459 | |
7b71c410 | 1460 | seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); |
3de7a1dc | 1461 | |
7093d6cd | 1462 | dsi_runtime_put(dsi); |
5a8b572d | 1463 | |
3ce75d67 | 1464 | return 0; |
5a8b572d AT |
1465 | } |
1466 | ||
dfc0fd8d | 1467 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
f3ed97f9 | 1468 | static int dsi_dump_dsi_irqs(struct seq_file *s, void *p) |
dfc0fd8d | 1469 | { |
4df04ac9 | 1470 | struct dsi_data *dsi = s->private; |
dfc0fd8d TV |
1471 | unsigned long flags; |
1472 | struct dsi_irq_stats stats; | |
1473 | ||
f1da39d9 | 1474 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
dfc0fd8d | 1475 | |
f1da39d9 AT |
1476 | stats = dsi->irq_stats; |
1477 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); | |
1478 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d | 1479 | |
f1da39d9 | 1480 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
dfc0fd8d TV |
1481 | |
1482 | seq_printf(s, "period %u ms\n", | |
1483 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
1484 | ||
1485 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
1486 | #define PIS(x) \ | |
1487 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); | |
1488 | ||
11ee9606 | 1489 | seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); |
dfc0fd8d TV |
1490 | PIS(VC0); |
1491 | PIS(VC1); | |
1492 | PIS(VC2); | |
1493 | PIS(VC3); | |
1494 | PIS(WAKEUP); | |
1495 | PIS(RESYNC); | |
1496 | PIS(PLL_LOCK); | |
1497 | PIS(PLL_UNLOCK); | |
1498 | PIS(PLL_RECALL); | |
1499 | PIS(COMPLEXIO_ERR); | |
1500 | PIS(HS_TX_TIMEOUT); | |
1501 | PIS(LP_RX_TIMEOUT); | |
1502 | PIS(TE_TRIGGER); | |
1503 | PIS(ACK_TRIGGER); | |
1504 | PIS(SYNC_LOST); | |
1505 | PIS(LDO_POWER_GOOD); | |
1506 | PIS(TA_TIMEOUT); | |
1507 | #undef PIS | |
1508 | ||
1509 | #define PIS(x) \ | |
1510 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ | |
1511 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ | |
1512 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ | |
1513 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ | |
1514 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); | |
1515 | ||
1516 | seq_printf(s, "-- VC interrupts --\n"); | |
1517 | PIS(CS); | |
1518 | PIS(ECC_CORR); | |
1519 | PIS(PACKET_SENT); | |
1520 | PIS(FIFO_TX_OVF); | |
1521 | PIS(FIFO_RX_OVF); | |
1522 | PIS(BTA); | |
1523 | PIS(ECC_NO_CORR); | |
1524 | PIS(FIFO_TX_UDF); | |
1525 | PIS(PP_BUSY_CHANGE); | |
1526 | #undef PIS | |
1527 | ||
1528 | #define PIS(x) \ | |
1529 | seq_printf(s, "%-20s %10d\n", #x, \ | |
1530 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); | |
1531 | ||
1532 | seq_printf(s, "-- CIO interrupts --\n"); | |
1533 | PIS(ERRSYNCESC1); | |
1534 | PIS(ERRSYNCESC2); | |
1535 | PIS(ERRSYNCESC3); | |
1536 | PIS(ERRESC1); | |
1537 | PIS(ERRESC2); | |
1538 | PIS(ERRESC3); | |
1539 | PIS(ERRCONTROL1); | |
1540 | PIS(ERRCONTROL2); | |
1541 | PIS(ERRCONTROL3); | |
1542 | PIS(STATEULPS1); | |
1543 | PIS(STATEULPS2); | |
1544 | PIS(STATEULPS3); | |
1545 | PIS(ERRCONTENTIONLP0_1); | |
1546 | PIS(ERRCONTENTIONLP1_1); | |
1547 | PIS(ERRCONTENTIONLP0_2); | |
1548 | PIS(ERRCONTENTIONLP1_2); | |
1549 | PIS(ERRCONTENTIONLP0_3); | |
1550 | PIS(ERRCONTENTIONLP1_3); | |
1551 | PIS(ULPSACTIVENOT_ALL0); | |
1552 | PIS(ULPSACTIVENOT_ALL1); | |
1553 | #undef PIS | |
a72b64b9 | 1554 | |
f33656e1 | 1555 | return 0; |
5a8b572d | 1556 | } |
5a8b572d AT |
1557 | #endif |
1558 | ||
f3ed97f9 | 1559 | static int dsi_dump_dsi_regs(struct seq_file *s, void *p) |
5a8b572d | 1560 | { |
4df04ac9 | 1561 | struct dsi_data *dsi = s->private; |
3de7a1dc | 1562 | |
7093d6cd | 1563 | if (dsi_runtime_get(dsi)) |
f3ed97f9 | 1564 | return 0; |
7093d6cd | 1565 | dsi_enable_scp_clk(dsi); |
3de7a1dc | 1566 | |
f3ed97f9 | 1567 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r)) |
3de7a1dc TV |
1568 | DUMPREG(DSI_REVISION); |
1569 | DUMPREG(DSI_SYSCONFIG); | |
1570 | DUMPREG(DSI_SYSSTATUS); | |
1571 | DUMPREG(DSI_IRQSTATUS); | |
1572 | DUMPREG(DSI_IRQENABLE); | |
1573 | DUMPREG(DSI_CTRL); | |
1574 | DUMPREG(DSI_COMPLEXIO_CFG1); | |
1575 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); | |
1576 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); | |
1577 | DUMPREG(DSI_CLK_CTRL); | |
1578 | DUMPREG(DSI_TIMING1); | |
1579 | DUMPREG(DSI_TIMING2); | |
1580 | DUMPREG(DSI_VM_TIMING1); | |
1581 | DUMPREG(DSI_VM_TIMING2); | |
1582 | DUMPREG(DSI_VM_TIMING3); | |
1583 | DUMPREG(DSI_CLK_TIMING); | |
1584 | DUMPREG(DSI_TX_FIFO_VC_SIZE); | |
1585 | DUMPREG(DSI_RX_FIFO_VC_SIZE); | |
1586 | DUMPREG(DSI_COMPLEXIO_CFG2); | |
1587 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); | |
1588 | DUMPREG(DSI_VM_TIMING4); | |
1589 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); | |
1590 | DUMPREG(DSI_VM_TIMING5); | |
1591 | DUMPREG(DSI_VM_TIMING6); | |
1592 | DUMPREG(DSI_VM_TIMING7); | |
1593 | DUMPREG(DSI_STOPCLK_TIMING); | |
1594 | ||
1595 | DUMPREG(DSI_VC_CTRL(0)); | |
1596 | DUMPREG(DSI_VC_TE(0)); | |
1597 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); | |
1598 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); | |
1599 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); | |
1600 | DUMPREG(DSI_VC_IRQSTATUS(0)); | |
1601 | DUMPREG(DSI_VC_IRQENABLE(0)); | |
1602 | ||
1603 | DUMPREG(DSI_VC_CTRL(1)); | |
1604 | DUMPREG(DSI_VC_TE(1)); | |
1605 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); | |
1606 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); | |
1607 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); | |
1608 | DUMPREG(DSI_VC_IRQSTATUS(1)); | |
1609 | DUMPREG(DSI_VC_IRQENABLE(1)); | |
1610 | ||
1611 | DUMPREG(DSI_VC_CTRL(2)); | |
1612 | DUMPREG(DSI_VC_TE(2)); | |
1613 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); | |
1614 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); | |
1615 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); | |
1616 | DUMPREG(DSI_VC_IRQSTATUS(2)); | |
1617 | DUMPREG(DSI_VC_IRQENABLE(2)); | |
1618 | ||
1619 | DUMPREG(DSI_VC_CTRL(3)); | |
1620 | DUMPREG(DSI_VC_TE(3)); | |
1621 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); | |
1622 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); | |
1623 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); | |
1624 | DUMPREG(DSI_VC_IRQSTATUS(3)); | |
1625 | DUMPREG(DSI_VC_IRQENABLE(3)); | |
1626 | ||
1627 | DUMPREG(DSI_DSIPHY_CFG0); | |
1628 | DUMPREG(DSI_DSIPHY_CFG1); | |
1629 | DUMPREG(DSI_DSIPHY_CFG2); | |
1630 | DUMPREG(DSI_DSIPHY_CFG5); | |
1631 | ||
1632 | DUMPREG(DSI_PLL_CONTROL); | |
1633 | DUMPREG(DSI_PLL_STATUS); | |
1634 | DUMPREG(DSI_PLL_GO); | |
1635 | DUMPREG(DSI_PLL_CONFIGURATION1); | |
1636 | DUMPREG(DSI_PLL_CONFIGURATION2); | |
f3ed97f9 | 1637 | #undef DUMPREG |
3de7a1dc | 1638 | |
7093d6cd LP |
1639 | dsi_disable_scp_clk(dsi); |
1640 | dsi_runtime_put(dsi); | |
5a8b572d | 1641 | |
f33656e1 | 1642 | return 0; |
5a8b572d AT |
1643 | } |
1644 | ||
cc5c1850 | 1645 | enum dsi_cio_power_state { |
3de7a1dc TV |
1646 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
1647 | DSI_COMPLEXIO_POWER_ON = 0x1, | |
1648 | DSI_COMPLEXIO_POWER_ULPS = 0x2, | |
1649 | }; | |
1650 | ||
7093d6cd | 1651 | static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state) |
3de7a1dc TV |
1652 | { |
1653 | int t = 0; | |
1654 | ||
1655 | /* PWR_CMD */ | |
7093d6cd | 1656 | REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); |
3de7a1dc TV |
1657 | |
1658 | /* PWR_STATUS */ | |
7093d6cd | 1659 | while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1), |
a72b64b9 | 1660 | 26, 25) != state) { |
24be78b3 | 1661 | if (++t > 1000) { |
3de7a1dc TV |
1662 | DSSERR("failed to set complexio power state to " |
1663 | "%d\n", state); | |
1664 | return -ENODEV; | |
1665 | } | |
24be78b3 | 1666 | udelay(1); |
3de7a1dc TV |
1667 | } |
1668 | ||
1669 | return 0; | |
1670 | } | |
1671 | ||
7093d6cd | 1672 | static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi) |
0c65622b AT |
1673 | { |
1674 | int val; | |
1675 | ||
1676 | /* line buffer on OMAP3 is 1024 x 24bits */ | |
1677 | /* XXX: for some reason using full buffer size causes | |
1678 | * considerable TX slowdown with update sizes that fill the | |
1679 | * whole buffer */ | |
44d8ca10 | 1680 | if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) |
0c65622b AT |
1681 | return 1023 * 3; |
1682 | ||
7093d6cd | 1683 | val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ |
0c65622b AT |
1684 | |
1685 | switch (val) { | |
1686 | case 1: | |
1687 | return 512 * 3; /* 512x24 bits */ | |
1688 | case 2: | |
1689 | return 682 * 3; /* 682x24 bits */ | |
1690 | case 3: | |
1691 | return 853 * 3; /* 853x24 bits */ | |
1692 | case 4: | |
1693 | return 1024 * 3; /* 1024x24 bits */ | |
1694 | case 5: | |
1695 | return 1194 * 3; /* 1194x24 bits */ | |
1696 | case 6: | |
1697 | return 1365 * 3; /* 1365x24 bits */ | |
2ac80fbe TV |
1698 | case 7: |
1699 | return 1920 * 3; /* 1920x24 bits */ | |
0c65622b AT |
1700 | default: |
1701 | BUG(); | |
c6eee968 | 1702 | return 0; |
0c65622b AT |
1703 | } |
1704 | } | |
1705 | ||
7093d6cd | 1706 | static int dsi_set_lane_config(struct dsi_data *dsi) |
3de7a1dc | 1707 | { |
48368395 TV |
1708 | static const u8 offsets[] = { 0, 4, 8, 12, 16 }; |
1709 | static const enum dsi_lane_function functions[] = { | |
1710 | DSI_LANE_CLK, | |
1711 | DSI_LANE_DATA1, | |
1712 | DSI_LANE_DATA2, | |
1713 | DSI_LANE_DATA3, | |
1714 | DSI_LANE_DATA4, | |
1715 | }; | |
3de7a1dc | 1716 | u32 r; |
48368395 | 1717 | int i; |
3de7a1dc | 1718 | |
7093d6cd | 1719 | r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1); |
48368395 TV |
1720 | |
1721 | for (i = 0; i < dsi->num_lanes_used; ++i) { | |
d11e5c82 LP |
1722 | unsigned int offset = offsets[i]; |
1723 | unsigned int polarity, lane_number; | |
1724 | unsigned int t; | |
48368395 TV |
1725 | |
1726 | for (t = 0; t < dsi->num_lanes_supported; ++t) | |
1727 | if (dsi->lanes[t].function == functions[i]) | |
1728 | break; | |
1729 | ||
1730 | if (t == dsi->num_lanes_supported) | |
1731 | return -EINVAL; | |
1732 | ||
1733 | lane_number = t; | |
1734 | polarity = dsi->lanes[t].polarity; | |
1735 | ||
1736 | r = FLD_MOD(r, lane_number + 1, offset + 2, offset); | |
1737 | r = FLD_MOD(r, polarity, offset + 3, offset + 3); | |
75d7247c | 1738 | } |
75d7247c | 1739 | |
48368395 TV |
1740 | /* clear the unused lanes */ |
1741 | for (; i < dsi->num_lanes_supported; ++i) { | |
d11e5c82 | 1742 | unsigned int offset = offsets[i]; |
48368395 TV |
1743 | |
1744 | r = FLD_MOD(r, 0, offset + 2, offset); | |
1745 | r = FLD_MOD(r, 0, offset + 3, offset + 3); | |
75d7247c | 1746 | } |
3de7a1dc | 1747 | |
7093d6cd | 1748 | dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r); |
3de7a1dc | 1749 | |
48368395 | 1750 | return 0; |
3de7a1dc TV |
1751 | } |
1752 | ||
7093d6cd | 1753 | static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns) |
3de7a1dc TV |
1754 | { |
1755 | /* convert time in ns to ddr ticks, rounding up */ | |
2daea7af | 1756 | unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; |
7093d6cd | 1757 | |
3de7a1dc TV |
1758 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
1759 | } | |
1760 | ||
7093d6cd | 1761 | static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr) |
3de7a1dc | 1762 | { |
2daea7af | 1763 | unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; |
7093d6cd | 1764 | |
3de7a1dc TV |
1765 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
1766 | } | |
1767 | ||
7093d6cd | 1768 | static void dsi_cio_timings(struct dsi_data *dsi) |
3de7a1dc TV |
1769 | { |
1770 | u32 r; | |
1771 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; | |
1772 | u32 tlpx_half, tclk_trail, tclk_zero; | |
1773 | u32 tclk_prepare; | |
1774 | ||
1775 | /* calculate timings */ | |
1776 | ||
1777 | /* 1 * DDR_CLK = 2 * UI */ | |
1778 | ||
1779 | /* min 40ns + 4*UI max 85ns + 6*UI */ | |
7093d6cd | 1780 | ths_prepare = ns2ddr(dsi, 70) + 2; |
3de7a1dc TV |
1781 | |
1782 | /* min 145ns + 10*UI */ | |
7093d6cd | 1783 | ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2; |
3de7a1dc TV |
1784 | |
1785 | /* min max(8*UI, 60ns+4*UI) */ | |
7093d6cd | 1786 | ths_trail = ns2ddr(dsi, 60) + 5; |
3de7a1dc TV |
1787 | |
1788 | /* min 100ns */ | |
7093d6cd | 1789 | ths_exit = ns2ddr(dsi, 145); |
3de7a1dc TV |
1790 | |
1791 | /* tlpx min 50n */ | |
7093d6cd | 1792 | tlpx_half = ns2ddr(dsi, 25); |
3de7a1dc TV |
1793 | |
1794 | /* min 60ns */ | |
7093d6cd | 1795 | tclk_trail = ns2ddr(dsi, 60) + 2; |
3de7a1dc TV |
1796 | |
1797 | /* min 38ns, max 95ns */ | |
7093d6cd | 1798 | tclk_prepare = ns2ddr(dsi, 65); |
3de7a1dc TV |
1799 | |
1800 | /* min tclk-prepare + tclk-zero = 300ns */ | |
7093d6cd | 1801 | tclk_zero = ns2ddr(dsi, 260); |
3de7a1dc TV |
1802 | |
1803 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", | |
7093d6cd LP |
1804 | ths_prepare, ddr2ns(dsi, ths_prepare), |
1805 | ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero)); | |
3de7a1dc | 1806 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
7093d6cd LP |
1807 | ths_trail, ddr2ns(dsi, ths_trail), |
1808 | ths_exit, ddr2ns(dsi, ths_exit)); | |
3de7a1dc TV |
1809 | |
1810 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " | |
1811 | "tclk_zero %u (%uns)\n", | |
7093d6cd LP |
1812 | tlpx_half, ddr2ns(dsi, tlpx_half), |
1813 | tclk_trail, ddr2ns(dsi, tclk_trail), | |
1814 | tclk_zero, ddr2ns(dsi, tclk_zero)); | |
3de7a1dc | 1815 | DSSDBG("tclk_prepare %u (%uns)\n", |
7093d6cd | 1816 | tclk_prepare, ddr2ns(dsi, tclk_prepare)); |
3de7a1dc TV |
1817 | |
1818 | /* program timings */ | |
1819 | ||
7093d6cd | 1820 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
1821 | r = FLD_MOD(r, ths_prepare, 31, 24); |
1822 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); | |
1823 | r = FLD_MOD(r, ths_trail, 15, 8); | |
1824 | r = FLD_MOD(r, ths_exit, 7, 0); | |
7093d6cd | 1825 | dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r); |
3de7a1dc | 1826 | |
7093d6cd | 1827 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); |
e84dc1cc | 1828 | r = FLD_MOD(r, tlpx_half, 20, 16); |
3de7a1dc TV |
1829 | r = FLD_MOD(r, tclk_trail, 15, 8); |
1830 | r = FLD_MOD(r, tclk_zero, 7, 0); | |
77ccbfbb | 1831 | |
44d8ca10 | 1832 | if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { |
77ccbfbb TV |
1833 | r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ |
1834 | r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ | |
1835 | r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ | |
1836 | } | |
1837 | ||
7093d6cd | 1838 | dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r); |
3de7a1dc | 1839 | |
7093d6cd | 1840 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); |
3de7a1dc | 1841 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
7093d6cd | 1842 | dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r); |
3de7a1dc TV |
1843 | } |
1844 | ||
9b4362f2 | 1845 | /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ |
7093d6cd LP |
1846 | static void dsi_cio_enable_lane_override(struct dsi_data *dsi, |
1847 | unsigned int mask_p, | |
1848 | unsigned int mask_n) | |
0a0ee46b | 1849 | { |
9b4362f2 TV |
1850 | int i; |
1851 | u32 l; | |
d9820850 | 1852 | u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; |
0a0ee46b | 1853 | |
9b4362f2 TV |
1854 | l = 0; |
1855 | ||
1856 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
d11e5c82 | 1857 | unsigned int p = dsi->lanes[i].polarity; |
9b4362f2 TV |
1858 | |
1859 | if (mask_p & (1 << i)) | |
1860 | l |= 1 << (i * 2 + (p ? 0 : 1)); | |
1861 | ||
1862 | if (mask_n & (1 << i)) | |
1863 | l |= 1 << (i * 2 + (p ? 1 : 0)); | |
1864 | } | |
1865 | ||
0a0ee46b TV |
1866 | /* |
1867 | * Bits in REGLPTXSCPDAT4TO0DXDY: | |
1868 | * 17: DY0 18: DX0 | |
1869 | * 19: DY1 20: DX1 | |
1870 | * 21: DY2 22: DX2 | |
75d7247c AT |
1871 | * 23: DY3 24: DX3 |
1872 | * 25: DY4 26: DX4 | |
0a0ee46b TV |
1873 | */ |
1874 | ||
1875 | /* Set the lane override configuration */ | |
a72b64b9 AT |
1876 | |
1877 | /* REGLPTXSCPDAT4TO0DXDY */ | |
7093d6cd | 1878 | REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); |
0a0ee46b TV |
1879 | |
1880 | /* Enable lane override */ | |
a72b64b9 AT |
1881 | |
1882 | /* ENLPTXSCPDAT */ | |
7093d6cd | 1883 | REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27); |
0a0ee46b TV |
1884 | } |
1885 | ||
7093d6cd | 1886 | static void dsi_cio_disable_lane_override(struct dsi_data *dsi) |
0a0ee46b TV |
1887 | { |
1888 | /* Disable lane override */ | |
7093d6cd | 1889 | REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
0a0ee46b | 1890 | /* Reset the lane override configuration */ |
a72b64b9 | 1891 | /* REGLPTXSCPDAT4TO0DXDY */ |
7093d6cd | 1892 | REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17); |
0a0ee46b | 1893 | } |
3de7a1dc | 1894 | |
7093d6cd | 1895 | static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi) |
03329ace | 1896 | { |
8dc0766f TV |
1897 | int t, i; |
1898 | bool in_use[DSI_MAX_NR_LANES]; | |
1899 | static const u8 offsets_old[] = { 28, 27, 26 }; | |
1900 | static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; | |
1901 | const u8 *offsets; | |
1902 | ||
44d8ca10 | 1903 | if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) |
8dc0766f TV |
1904 | offsets = offsets_old; |
1905 | else | |
1906 | offsets = offsets_new; | |
03329ace | 1907 | |
8dc0766f TV |
1908 | for (i = 0; i < dsi->num_lanes_supported; ++i) |
1909 | in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; | |
03329ace TV |
1910 | |
1911 | t = 100000; | |
1912 | while (true) { | |
1913 | u32 l; | |
03329ace TV |
1914 | int ok; |
1915 | ||
7093d6cd | 1916 | l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); |
03329ace TV |
1917 | |
1918 | ok = 0; | |
8dc0766f TV |
1919 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
1920 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
03329ace TV |
1921 | ok++; |
1922 | } | |
1923 | ||
8dc0766f | 1924 | if (ok == dsi->num_lanes_supported) |
03329ace TV |
1925 | break; |
1926 | ||
1927 | if (--t == 0) { | |
8dc0766f TV |
1928 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
1929 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
03329ace TV |
1930 | continue; |
1931 | ||
1932 | DSSERR("CIO TXCLKESC%d domain not coming " \ | |
1933 | "out of reset\n", i); | |
1934 | } | |
1935 | return -EIO; | |
1936 | } | |
1937 | } | |
1938 | ||
1939 | return 0; | |
1940 | } | |
1941 | ||
85f17e8e | 1942 | /* return bitmask of enabled lanes, lane0 being the lsb */ |
7093d6cd | 1943 | static unsigned int dsi_get_lane_mask(struct dsi_data *dsi) |
5bc416cb | 1944 | { |
d11e5c82 | 1945 | unsigned int mask = 0; |
85f17e8e | 1946 | int i; |
5bc416cb | 1947 | |
85f17e8e TV |
1948 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
1949 | if (dsi->lanes[i].function != DSI_LANE_UNUSED) | |
1950 | mask |= 1 << i; | |
1951 | } | |
5bc416cb | 1952 | |
85f17e8e | 1953 | return mask; |
5bc416cb TV |
1954 | } |
1955 | ||
9e1305d0 LP |
1956 | /* OMAP4 CONTROL_DSIPHY */ |
1957 | #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 | |
1958 | ||
1959 | #define OMAP4_DSI2_LANEENABLE_SHIFT 29 | |
1960 | #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) | |
1961 | #define OMAP4_DSI1_LANEENABLE_SHIFT 24 | |
1962 | #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) | |
1963 | #define OMAP4_DSI1_PIPD_SHIFT 19 | |
1964 | #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) | |
1965 | #define OMAP4_DSI2_PIPD_SHIFT 14 | |
1966 | #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) | |
1967 | ||
1968 | static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes) | |
1969 | { | |
1970 | u32 enable_mask, enable_shift; | |
1971 | u32 pipd_mask, pipd_shift; | |
9e1305d0 | 1972 | |
9e1305d0 LP |
1973 | if (dsi->module_id == 0) { |
1974 | enable_mask = OMAP4_DSI1_LANEENABLE_MASK; | |
1975 | enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; | |
1976 | pipd_mask = OMAP4_DSI1_PIPD_MASK; | |
1977 | pipd_shift = OMAP4_DSI1_PIPD_SHIFT; | |
1978 | } else if (dsi->module_id == 1) { | |
1979 | enable_mask = OMAP4_DSI2_LANEENABLE_MASK; | |
1980 | enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; | |
1981 | pipd_mask = OMAP4_DSI2_PIPD_MASK; | |
1982 | pipd_shift = OMAP4_DSI2_PIPD_SHIFT; | |
1983 | } else { | |
1984 | return -ENODEV; | |
1985 | } | |
1986 | ||
5cdc8dbb TV |
1987 | return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, |
1988 | enable_mask | pipd_mask, | |
1989 | (lanes << enable_shift) | (lanes << pipd_shift)); | |
9e1305d0 LP |
1990 | } |
1991 | ||
eeb45f85 TV |
1992 | /* OMAP5 CONTROL_DSIPHY */ |
1993 | ||
1994 | #define OMAP5_DSIPHY_SYSCON_OFFSET 0x74 | |
1995 | ||
1996 | #define OMAP5_DSI1_LANEENABLE_SHIFT 24 | |
1997 | #define OMAP5_DSI2_LANEENABLE_SHIFT 19 | |
1998 | #define OMAP5_DSI_LANEENABLE_MASK 0x1f | |
1999 | ||
2000 | static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes) | |
2001 | { | |
2002 | u32 enable_shift; | |
2003 | ||
2004 | if (dsi->module_id == 0) | |
2005 | enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT; | |
2006 | else if (dsi->module_id == 1) | |
2007 | enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT; | |
2008 | else | |
2009 | return -ENODEV; | |
2010 | ||
2011 | return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, | |
2012 | OMAP5_DSI_LANEENABLE_MASK << enable_shift, | |
2013 | lanes << enable_shift); | |
2014 | } | |
2015 | ||
9e1305d0 LP |
2016 | static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) |
2017 | { | |
eeb45f85 TV |
2018 | if (dsi->data->model == DSI_MODEL_OMAP4) |
2019 | return dsi_omap4_mux_pads(dsi, lane_mask); | |
2020 | if (dsi->data->model == DSI_MODEL_OMAP5) | |
2021 | return dsi_omap5_mux_pads(dsi, lane_mask); | |
2022 | return 0; | |
9e1305d0 LP |
2023 | } |
2024 | ||
2025 | static void dsi_disable_pads(struct dsi_data *dsi) | |
2026 | { | |
eeb45f85 TV |
2027 | if (dsi->data->model == DSI_MODEL_OMAP4) |
2028 | dsi_omap4_mux_pads(dsi, 0); | |
2029 | else if (dsi->data->model == DSI_MODEL_OMAP5) | |
2030 | dsi_omap5_mux_pads(dsi, 0); | |
9e1305d0 LP |
2031 | } |
2032 | ||
7093d6cd | 2033 | static int dsi_cio_init(struct dsi_data *dsi) |
3de7a1dc | 2034 | { |
65c62bb9 | 2035 | int r; |
40885ab3 | 2036 | u32 l; |
3de7a1dc | 2037 | |
702d267e | 2038 | DSSDBG("DSI CIO init starts"); |
3de7a1dc | 2039 | |
7093d6cd | 2040 | r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi)); |
5bc416cb TV |
2041 | if (r) |
2042 | return r; | |
d1f5857e | 2043 | |
7093d6cd | 2044 | dsi_enable_scp_clk(dsi); |
40885ab3 | 2045 | |
3de7a1dc TV |
2046 | /* A dummy read using the SCP interface to any DSIPHY register is |
2047 | * required after DSIPHY reset to complete the reset of the DSI complex | |
2048 | * I/O. */ | |
7093d6cd | 2049 | dsi_read_reg(dsi, DSI_DSIPHY_CFG5); |
3de7a1dc | 2050 | |
7093d6cd | 2051 | if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) { |
65c62bb9 TV |
2052 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
2053 | r = -EIO; | |
2054 | goto err_scp_clk_dom; | |
3de7a1dc TV |
2055 | } |
2056 | ||
7093d6cd | 2057 | r = dsi_set_lane_config(dsi); |
48368395 TV |
2058 | if (r) |
2059 | goto err_scp_clk_dom; | |
3de7a1dc | 2060 | |
40885ab3 | 2061 | /* set TX STOP MODE timer to maximum for this operation */ |
7093d6cd | 2062 | l = dsi_read_reg(dsi, DSI_TIMING1); |
40885ab3 TV |
2063 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
2064 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ | |
2065 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ | |
2066 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ | |
7093d6cd | 2067 | dsi_write_reg(dsi, DSI_TIMING1, l); |
40885ab3 | 2068 | |
f1da39d9 | 2069 | if (dsi->ulps_enabled) { |
d11e5c82 | 2070 | unsigned int mask_p; |
9b4362f2 | 2071 | int i; |
75d7247c | 2072 | |
65c62bb9 TV |
2073 | DSSDBG("manual ulps exit\n"); |
2074 | ||
40885ab3 TV |
2075 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
2076 | * stop state. DSS HW cannot do this via the normal | |
2077 | * ULPS exit sequence, as after reset the DSS HW thinks | |
2078 | * that we are not in ULPS mode, and refuses to send the | |
2079 | * sequence. So we need to send the ULPS exit sequence | |
9b4362f2 TV |
2080 | * manually by setting positive lines high and negative lines |
2081 | * low for 1ms. | |
40885ab3 TV |
2082 | */ |
2083 | ||
9b4362f2 | 2084 | mask_p = 0; |
75d7247c | 2085 | |
9b4362f2 TV |
2086 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2087 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
2088 | continue; | |
2089 | mask_p |= 1 << i; | |
2090 | } | |
75d7247c | 2091 | |
7093d6cd | 2092 | dsi_cio_enable_lane_override(dsi, mask_p, 0); |
40885ab3 | 2093 | } |
3de7a1dc | 2094 | |
7093d6cd | 2095 | r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON); |
3de7a1dc | 2096 | if (r) |
65c62bb9 TV |
2097 | goto err_cio_pwr; |
2098 | ||
7093d6cd | 2099 | if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) { |
65c62bb9 TV |
2100 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
2101 | r = -ENODEV; | |
2102 | goto err_cio_pwr_dom; | |
2103 | } | |
2104 | ||
7093d6cd LP |
2105 | dsi_if_enable(dsi, true); |
2106 | dsi_if_enable(dsi, false); | |
2107 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ | |
3de7a1dc | 2108 | |
7093d6cd | 2109 | r = dsi_cio_wait_tx_clk_esc_reset(dsi); |
03329ace TV |
2110 | if (r) |
2111 | goto err_tx_clk_esc_rst; | |
2112 | ||
f1da39d9 | 2113 | if (dsi->ulps_enabled) { |
40885ab3 TV |
2114 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
2115 | ktime_t wait = ns_to_ktime(1000 * 1000); | |
2116 | set_current_state(TASK_UNINTERRUPTIBLE); | |
2117 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
2118 | ||
2119 | /* Disable the override. The lanes should be set to Mark-11 | |
2120 | * state by the HW */ | |
7093d6cd | 2121 | dsi_cio_disable_lane_override(dsi); |
40885ab3 TV |
2122 | } |
2123 | ||
2124 | /* FORCE_TX_STOP_MODE_IO */ | |
7093d6cd | 2125 | REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); |
40885ab3 | 2126 | |
7093d6cd | 2127 | dsi_cio_timings(dsi); |
3de7a1dc | 2128 | |
dca2b152 | 2129 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
8af6ff01 | 2130 | /* DDR_CLK_ALWAYS_ON */ |
7093d6cd | 2131 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, |
0b3ffe39 | 2132 | dsi->vm_timings.ddr_clk_always_on, 13, 13); |
8af6ff01 AT |
2133 | } |
2134 | ||
f1da39d9 | 2135 | dsi->ulps_enabled = false; |
3de7a1dc TV |
2136 | |
2137 | DSSDBG("CIO init done\n"); | |
65c62bb9 TV |
2138 | |
2139 | return 0; | |
2140 | ||
03329ace | 2141 | err_tx_clk_esc_rst: |
7093d6cd | 2142 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
65c62bb9 | 2143 | err_cio_pwr_dom: |
7093d6cd | 2144 | dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); |
65c62bb9 | 2145 | err_cio_pwr: |
f1da39d9 | 2146 | if (dsi->ulps_enabled) |
7093d6cd | 2147 | dsi_cio_disable_lane_override(dsi); |
65c62bb9 | 2148 | err_scp_clk_dom: |
7093d6cd | 2149 | dsi_disable_scp_clk(dsi); |
9e1305d0 | 2150 | dsi_disable_pads(dsi); |
3de7a1dc TV |
2151 | return r; |
2152 | } | |
2153 | ||
7093d6cd | 2154 | static void dsi_cio_uninit(struct dsi_data *dsi) |
3de7a1dc | 2155 | { |
8af6ff01 | 2156 | /* DDR_CLK_ALWAYS_ON */ |
7093d6cd | 2157 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); |
8af6ff01 | 2158 | |
7093d6cd LP |
2159 | dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); |
2160 | dsi_disable_scp_clk(dsi); | |
9e1305d0 | 2161 | dsi_disable_pads(dsi); |
3de7a1dc TV |
2162 | } |
2163 | ||
7093d6cd LP |
2164 | static void dsi_config_tx_fifo(struct dsi_data *dsi, |
2165 | enum fifo_size size1, enum fifo_size size2, | |
2166 | enum fifo_size size3, enum fifo_size size4) | |
3de7a1dc TV |
2167 | { |
2168 | u32 r = 0; | |
2169 | int add = 0; | |
2170 | int i; | |
2171 | ||
558c73e2 TV |
2172 | dsi->vc[0].tx_fifo_size = size1; |
2173 | dsi->vc[1].tx_fifo_size = size2; | |
2174 | dsi->vc[2].tx_fifo_size = size3; | |
2175 | dsi->vc[3].tx_fifo_size = size4; | |
3de7a1dc TV |
2176 | |
2177 | for (i = 0; i < 4; i++) { | |
2178 | u8 v; | |
558c73e2 | 2179 | int size = dsi->vc[i].tx_fifo_size; |
3de7a1dc TV |
2180 | |
2181 | if (add + size > 4) { | |
2182 | DSSERR("Illegal FIFO configuration\n"); | |
2183 | BUG(); | |
c6eee968 | 2184 | return; |
3de7a1dc TV |
2185 | } |
2186 | ||
2187 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2188 | r |= v << (8 * i); | |
2189 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2190 | add += size; | |
2191 | } | |
2192 | ||
7093d6cd | 2193 | dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2194 | } |
2195 | ||
7093d6cd | 2196 | static void dsi_config_rx_fifo(struct dsi_data *dsi, |
a72b64b9 | 2197 | enum fifo_size size1, enum fifo_size size2, |
3de7a1dc TV |
2198 | enum fifo_size size3, enum fifo_size size4) |
2199 | { | |
2200 | u32 r = 0; | |
2201 | int add = 0; | |
2202 | int i; | |
2203 | ||
558c73e2 TV |
2204 | dsi->vc[0].rx_fifo_size = size1; |
2205 | dsi->vc[1].rx_fifo_size = size2; | |
2206 | dsi->vc[2].rx_fifo_size = size3; | |
2207 | dsi->vc[3].rx_fifo_size = size4; | |
3de7a1dc TV |
2208 | |
2209 | for (i = 0; i < 4; i++) { | |
2210 | u8 v; | |
558c73e2 | 2211 | int size = dsi->vc[i].rx_fifo_size; |
3de7a1dc TV |
2212 | |
2213 | if (add + size > 4) { | |
2214 | DSSERR("Illegal FIFO configuration\n"); | |
2215 | BUG(); | |
c6eee968 | 2216 | return; |
3de7a1dc TV |
2217 | } |
2218 | ||
2219 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2220 | r |= v << (8 * i); | |
2221 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2222 | add += size; | |
2223 | } | |
2224 | ||
7093d6cd | 2225 | dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2226 | } |
2227 | ||
7093d6cd | 2228 | static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi) |
3de7a1dc TV |
2229 | { |
2230 | u32 r; | |
2231 | ||
7093d6cd | 2232 | r = dsi_read_reg(dsi, DSI_TIMING1); |
3de7a1dc | 2233 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
7093d6cd | 2234 | dsi_write_reg(dsi, DSI_TIMING1, r); |
3de7a1dc | 2235 | |
7093d6cd | 2236 | if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) { |
3de7a1dc TV |
2237 | DSSERR("TX_STOP bit not going down\n"); |
2238 | return -EIO; | |
2239 | } | |
2240 | ||
2241 | return 0; | |
2242 | } | |
2243 | ||
7093d6cd | 2244 | static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel) |
cf398fb3 | 2245 | { |
7093d6cd | 2246 | return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0); |
cf398fb3 AT |
2247 | } |
2248 | ||
2249 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) | |
2250 | { | |
2e868dbe AT |
2251 | struct dsi_packet_sent_handler_data *vp_data = |
2252 | (struct dsi_packet_sent_handler_data *) data; | |
7093d6cd | 2253 | struct dsi_data *dsi = vp_data->dsi; |
f1da39d9 AT |
2254 | const int channel = dsi->update_channel; |
2255 | u8 bit = dsi->te_enabled ? 30 : 31; | |
cf398fb3 | 2256 | |
7093d6cd | 2257 | if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0) |
2e868dbe | 2258 | complete(vp_data->completion); |
cf398fb3 AT |
2259 | } |
2260 | ||
7093d6cd | 2261 | static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel) |
cf398fb3 | 2262 | { |
2e868dbe | 2263 | DECLARE_COMPLETION_ONSTACK(completion); |
39917f08 | 2264 | struct dsi_packet_sent_handler_data vp_data = { |
7093d6cd | 2265 | .dsi = dsi, |
39917f08 JL |
2266 | .completion = &completion |
2267 | }; | |
cf398fb3 AT |
2268 | int r = 0; |
2269 | u8 bit; | |
2270 | ||
f1da39d9 | 2271 | bit = dsi->te_enabled ? 30 : 31; |
cf398fb3 | 2272 | |
7093d6cd | 2273 | r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2274 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2275 | if (r) |
2276 | goto err0; | |
2277 | ||
2278 | /* Wait for completion only if TE_EN/TE_START is still set */ | |
7093d6cd | 2279 | if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) { |
cf398fb3 AT |
2280 | if (wait_for_completion_timeout(&completion, |
2281 | msecs_to_jiffies(10)) == 0) { | |
2282 | DSSERR("Failed to complete previous frame transfer\n"); | |
2283 | r = -EIO; | |
2284 | goto err1; | |
2285 | } | |
2286 | } | |
2287 | ||
7093d6cd | 2288 | dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2289 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2290 | |
2291 | return 0; | |
2292 | err1: | |
7093d6cd | 2293 | dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2294 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2295 | err0: |
2296 | return r; | |
2297 | } | |
2298 | ||
2299 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) | |
2300 | { | |
2e868dbe AT |
2301 | struct dsi_packet_sent_handler_data *l4_data = |
2302 | (struct dsi_packet_sent_handler_data *) data; | |
7093d6cd | 2303 | struct dsi_data *dsi = l4_data->dsi; |
f1da39d9 | 2304 | const int channel = dsi->update_channel; |
cf398fb3 | 2305 | |
7093d6cd | 2306 | if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0) |
2e868dbe | 2307 | complete(l4_data->completion); |
cf398fb3 AT |
2308 | } |
2309 | ||
7093d6cd | 2310 | static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel) |
cf398fb3 | 2311 | { |
cf398fb3 | 2312 | DECLARE_COMPLETION_ONSTACK(completion); |
39917f08 | 2313 | struct dsi_packet_sent_handler_data l4_data = { |
7093d6cd | 2314 | .dsi = dsi, |
39917f08 JL |
2315 | .completion = &completion |
2316 | }; | |
2e868dbe | 2317 | int r = 0; |
cf398fb3 | 2318 | |
7093d6cd | 2319 | r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2320 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2321 | if (r) |
2322 | goto err0; | |
2323 | ||
2324 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ | |
7093d6cd | 2325 | if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) { |
cf398fb3 AT |
2326 | if (wait_for_completion_timeout(&completion, |
2327 | msecs_to_jiffies(10)) == 0) { | |
2328 | DSSERR("Failed to complete previous l4 transfer\n"); | |
2329 | r = -EIO; | |
2330 | goto err1; | |
2331 | } | |
2332 | } | |
2333 | ||
7093d6cd | 2334 | dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2335 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2336 | |
2337 | return 0; | |
2338 | err1: | |
7093d6cd | 2339 | dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2340 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2341 | err0: |
2342 | return r; | |
2343 | } | |
2344 | ||
7093d6cd | 2345 | static int dsi_sync_vc(struct dsi_data *dsi, int channel) |
cf398fb3 | 2346 | { |
7093d6cd | 2347 | WARN_ON(!dsi_bus_is_locked(dsi)); |
cf398fb3 AT |
2348 | |
2349 | WARN_ON(in_interrupt()); | |
2350 | ||
7093d6cd | 2351 | if (!dsi_vc_is_enabled(dsi, channel)) |
cf398fb3 AT |
2352 | return 0; |
2353 | ||
d6049144 AT |
2354 | switch (dsi->vc[channel].source) { |
2355 | case DSI_VC_SOURCE_VP: | |
7093d6cd | 2356 | return dsi_sync_vc_vp(dsi, channel); |
d6049144 | 2357 | case DSI_VC_SOURCE_L4: |
7093d6cd | 2358 | return dsi_sync_vc_l4(dsi, channel); |
cf398fb3 AT |
2359 | default: |
2360 | BUG(); | |
c6eee968 | 2361 | return -EINVAL; |
cf398fb3 AT |
2362 | } |
2363 | } | |
2364 | ||
7093d6cd | 2365 | static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable) |
3de7a1dc | 2366 | { |
446f7bff TV |
2367 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
2368 | channel, enable); | |
3de7a1dc TV |
2369 | |
2370 | enable = enable ? 1 : 0; | |
2371 | ||
7093d6cd | 2372 | REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0); |
3de7a1dc | 2373 | |
7093d6cd | 2374 | if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) { |
bafa89fc LP |
2375 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
2376 | return -EIO; | |
3de7a1dc TV |
2377 | } |
2378 | ||
2379 | return 0; | |
2380 | } | |
2381 | ||
7093d6cd | 2382 | static void dsi_vc_initial_config(struct dsi_data *dsi, int channel) |
3de7a1dc TV |
2383 | { |
2384 | u32 r; | |
2385 | ||
702d267e | 2386 | DSSDBG("Initial config of virtual channel %d", channel); |
3de7a1dc | 2387 | |
7093d6cd | 2388 | r = dsi_read_reg(dsi, DSI_VC_CTRL(channel)); |
3de7a1dc TV |
2389 | |
2390 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ | |
2391 | DSSERR("VC(%d) busy when trying to configure it!\n", | |
2392 | channel); | |
2393 | ||
2394 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2395 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ | |
2396 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ | |
2397 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ | |
2398 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ | |
2399 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ | |
2400 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ | |
44d8ca10 | 2401 | if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) |
9613c02b | 2402 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ |
3de7a1dc TV |
2403 | |
2404 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ | |
2405 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ | |
2406 | ||
7093d6cd | 2407 | dsi_write_reg(dsi, DSI_VC_CTRL(channel), r); |
2c1a3ea0 TV |
2408 | |
2409 | dsi->vc[channel].source = DSI_VC_SOURCE_L4; | |
3de7a1dc TV |
2410 | } |
2411 | ||
7093d6cd LP |
2412 | static int dsi_vc_config_source(struct dsi_data *dsi, int channel, |
2413 | enum dsi_vc_source source) | |
3de7a1dc | 2414 | { |
d6049144 | 2415 | if (dsi->vc[channel].source == source) |
9ecd9684 | 2416 | return 0; |
3de7a1dc | 2417 | |
702d267e | 2418 | DSSDBG("Source config of virtual channel %d", channel); |
3de7a1dc | 2419 | |
7093d6cd | 2420 | dsi_sync_vc(dsi, channel); |
cf398fb3 | 2421 | |
7093d6cd | 2422 | dsi_vc_enable(dsi, channel, 0); |
3de7a1dc | 2423 | |
9ecd9684 | 2424 | /* VC_BUSY */ |
7093d6cd | 2425 | if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) { |
3de7a1dc | 2426 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
9ecd9684 TV |
2427 | return -EIO; |
2428 | } | |
3de7a1dc | 2429 | |
d6049144 | 2430 | /* SOURCE, 0 = L4, 1 = video port */ |
7093d6cd | 2431 | REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1); |
3de7a1dc | 2432 | |
9613c02b | 2433 | /* DCS_CMD_ENABLE */ |
44d8ca10 | 2434 | if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) { |
d6049144 | 2435 | bool enable = source == DSI_VC_SOURCE_VP; |
7093d6cd | 2436 | REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30); |
d6049144 | 2437 | } |
9613c02b | 2438 | |
7093d6cd | 2439 | dsi_vc_enable(dsi, channel, 1); |
3de7a1dc | 2440 | |
d6049144 | 2441 | dsi->vc[channel].source = source; |
9ecd9684 TV |
2442 | |
2443 | return 0; | |
3de7a1dc TV |
2444 | } |
2445 | ||
5cfc1c3c | 2446 | static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
1ffefe75 | 2447 | bool enable) |
3de7a1dc | 2448 | { |
c068408e | 2449 | struct dsi_data *dsi = to_dsi_data(dssdev); |
a72b64b9 | 2450 | |
3de7a1dc TV |
2451 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
2452 | ||
7093d6cd | 2453 | WARN_ON(!dsi_bus_is_locked(dsi)); |
61140c9a | 2454 | |
7093d6cd LP |
2455 | dsi_vc_enable(dsi, channel, 0); |
2456 | dsi_if_enable(dsi, 0); | |
3de7a1dc | 2457 | |
7093d6cd | 2458 | REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9); |
3de7a1dc | 2459 | |
7093d6cd LP |
2460 | dsi_vc_enable(dsi, channel, 1); |
2461 | dsi_if_enable(dsi, 1); | |
3de7a1dc | 2462 | |
7093d6cd | 2463 | dsi_force_tx_stop_mode_io(dsi); |
8af6ff01 AT |
2464 | |
2465 | /* start the DDR clock by sending a NULL packet */ | |
0b3ffe39 | 2466 | if (dsi->vm_timings.ddr_clk_always_on && enable) |
7093d6cd | 2467 | dsi_vc_send_null(dsi, channel); |
3de7a1dc TV |
2468 | } |
2469 | ||
7093d6cd | 2470 | static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel) |
3de7a1dc | 2471 | { |
7093d6cd | 2472 | while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc | 2473 | u32 val; |
7093d6cd | 2474 | val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); |
3de7a1dc TV |
2475 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
2476 | (val >> 0) & 0xff, | |
2477 | (val >> 8) & 0xff, | |
2478 | (val >> 16) & 0xff, | |
2479 | (val >> 24) & 0xff); | |
2480 | } | |
2481 | } | |
2482 | ||
2483 | static void dsi_show_rx_ack_with_err(u16 err) | |
2484 | { | |
2485 | DSSERR("\tACK with ERROR (%#x):\n", err); | |
2486 | if (err & (1 << 0)) | |
2487 | DSSERR("\t\tSoT Error\n"); | |
2488 | if (err & (1 << 1)) | |
2489 | DSSERR("\t\tSoT Sync Error\n"); | |
2490 | if (err & (1 << 2)) | |
2491 | DSSERR("\t\tEoT Sync Error\n"); | |
2492 | if (err & (1 << 3)) | |
2493 | DSSERR("\t\tEscape Mode Entry Command Error\n"); | |
2494 | if (err & (1 << 4)) | |
2495 | DSSERR("\t\tLP Transmit Sync Error\n"); | |
2496 | if (err & (1 << 5)) | |
2497 | DSSERR("\t\tHS Receive Timeout Error\n"); | |
2498 | if (err & (1 << 6)) | |
2499 | DSSERR("\t\tFalse Control Error\n"); | |
2500 | if (err & (1 << 7)) | |
2501 | DSSERR("\t\t(reserved7)\n"); | |
2502 | if (err & (1 << 8)) | |
2503 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); | |
2504 | if (err & (1 << 9)) | |
2505 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); | |
2506 | if (err & (1 << 10)) | |
2507 | DSSERR("\t\tChecksum Error\n"); | |
2508 | if (err & (1 << 11)) | |
2509 | DSSERR("\t\tData type not recognized\n"); | |
2510 | if (err & (1 << 12)) | |
2511 | DSSERR("\t\tInvalid VC ID\n"); | |
2512 | if (err & (1 << 13)) | |
2513 | DSSERR("\t\tInvalid Transmission Length\n"); | |
2514 | if (err & (1 << 14)) | |
2515 | DSSERR("\t\t(reserved14)\n"); | |
2516 | if (err & (1 << 15)) | |
2517 | DSSERR("\t\tDSI Protocol Violation\n"); | |
2518 | } | |
2519 | ||
7093d6cd | 2520 | static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel) |
3de7a1dc TV |
2521 | { |
2522 | /* RX_FIFO_NOT_EMPTY */ | |
7093d6cd | 2523 | while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc TV |
2524 | u32 val; |
2525 | u8 dt; | |
7093d6cd | 2526 | val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); |
86a7867e | 2527 | DSSERR("\trawval %#08x\n", val); |
3de7a1dc | 2528 | dt = FLD_GET(val, 5, 0); |
7a7c48f9 | 2529 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
2530 | u16 err = FLD_GET(val, 23, 8); |
2531 | dsi_show_rx_ack_with_err(err); | |
7a7c48f9 | 2532 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { |
86a7867e | 2533 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
3de7a1dc | 2534 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2535 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { |
86a7867e | 2536 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
3de7a1dc | 2537 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2538 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { |
86a7867e | 2539 | DSSERR("\tDCS long response, len %d\n", |
3de7a1dc | 2540 | FLD_GET(val, 23, 8)); |
7093d6cd | 2541 | dsi_vc_flush_long_data(dsi, channel); |
3de7a1dc TV |
2542 | } else { |
2543 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
2544 | } | |
2545 | } | |
2546 | return 0; | |
2547 | } | |
2548 | ||
7093d6cd | 2549 | static int dsi_vc_send_bta(struct dsi_data *dsi, int channel) |
3de7a1dc | 2550 | { |
f1da39d9 | 2551 | if (dsi->debug_write || dsi->debug_read) |
3de7a1dc TV |
2552 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
2553 | ||
7093d6cd | 2554 | WARN_ON(!dsi_bus_is_locked(dsi)); |
3de7a1dc | 2555 | |
a72b64b9 | 2556 | /* RX_FIFO_NOT_EMPTY */ |
7093d6cd | 2557 | if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc | 2558 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
7093d6cd | 2559 | dsi_vc_flush_receive_data(dsi, channel); |
3de7a1dc TV |
2560 | } |
2561 | ||
7093d6cd | 2562 | REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
3de7a1dc | 2563 | |
968f8e97 | 2564 | /* flush posted write */ |
7093d6cd | 2565 | dsi_read_reg(dsi, DSI_VC_CTRL(channel)); |
968f8e97 | 2566 | |
3de7a1dc TV |
2567 | return 0; |
2568 | } | |
2569 | ||
5cfc1c3c | 2570 | static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 2571 | { |
c068408e | 2572 | struct dsi_data *dsi = to_dsi_data(dssdev); |
f36a06e7 | 2573 | DECLARE_COMPLETION_ONSTACK(completion); |
3de7a1dc TV |
2574 | int r = 0; |
2575 | u32 err; | |
2576 | ||
7093d6cd | 2577 | r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler, |
f36a06e7 TV |
2578 | &completion, DSI_VC_IRQ_BTA); |
2579 | if (r) | |
2580 | goto err0; | |
3de7a1dc | 2581 | |
7093d6cd | 2582 | r = dsi_register_isr(dsi, dsi_completion_handler, &completion, |
773b30b2 | 2583 | DSI_IRQ_ERROR_MASK); |
3de7a1dc | 2584 | if (r) |
f36a06e7 | 2585 | goto err1; |
3de7a1dc | 2586 | |
7093d6cd | 2587 | r = dsi_vc_send_bta(dsi, channel); |
773b30b2 TV |
2588 | if (r) |
2589 | goto err2; | |
2590 | ||
f36a06e7 | 2591 | if (wait_for_completion_timeout(&completion, |
3de7a1dc TV |
2592 | msecs_to_jiffies(500)) == 0) { |
2593 | DSSERR("Failed to receive BTA\n"); | |
2594 | r = -EIO; | |
773b30b2 | 2595 | goto err2; |
3de7a1dc TV |
2596 | } |
2597 | ||
7093d6cd | 2598 | err = dsi_get_errors(dsi); |
3de7a1dc TV |
2599 | if (err) { |
2600 | DSSERR("Error while sending BTA: %x\n", err); | |
2601 | r = -EIO; | |
773b30b2 | 2602 | goto err2; |
3de7a1dc | 2603 | } |
773b30b2 | 2604 | err2: |
7093d6cd | 2605 | dsi_unregister_isr(dsi, dsi_completion_handler, &completion, |
773b30b2 | 2606 | DSI_IRQ_ERROR_MASK); |
f36a06e7 | 2607 | err1: |
7093d6cd | 2608 | dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler, |
f36a06e7 TV |
2609 | &completion, DSI_VC_IRQ_BTA); |
2610 | err0: | |
3de7a1dc TV |
2611 | return r; |
2612 | } | |
3de7a1dc | 2613 | |
7093d6cd LP |
2614 | static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel, |
2615 | u8 data_type, u16 len, u8 ecc) | |
3de7a1dc TV |
2616 | { |
2617 | u32 val; | |
2618 | u8 data_id; | |
2619 | ||
7093d6cd | 2620 | WARN_ON(!dsi_bus_is_locked(dsi)); |
3de7a1dc | 2621 | |
f1da39d9 | 2622 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
2623 | |
2624 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | | |
2625 | FLD_VAL(ecc, 31, 24); | |
2626 | ||
7093d6cd | 2627 | dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val); |
3de7a1dc TV |
2628 | } |
2629 | ||
7093d6cd LP |
2630 | static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel, |
2631 | u8 b1, u8 b2, u8 b3, u8 b4) | |
3de7a1dc TV |
2632 | { |
2633 | u32 val; | |
2634 | ||
2635 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; | |
2636 | ||
2637 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", | |
2638 | b1, b2, b3, b4, val); */ | |
2639 | ||
7093d6cd | 2640 | dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
3de7a1dc TV |
2641 | } |
2642 | ||
7093d6cd LP |
2643 | static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type, |
2644 | u8 *data, u16 len, u8 ecc) | |
3de7a1dc TV |
2645 | { |
2646 | /*u32 val; */ | |
2647 | int i; | |
2648 | u8 *p; | |
2649 | int r = 0; | |
2650 | u8 b1, b2, b3, b4; | |
2651 | ||
f1da39d9 | 2652 | if (dsi->debug_write) |
3de7a1dc TV |
2653 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
2654 | ||
2655 | /* len + header */ | |
558c73e2 | 2656 | if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { |
3de7a1dc TV |
2657 | DSSERR("unable to send long packet: packet too long.\n"); |
2658 | return -EINVAL; | |
2659 | } | |
2660 | ||
7093d6cd | 2661 | dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 2662 | |
7093d6cd | 2663 | dsi_vc_write_long_header(dsi, channel, data_type, len, ecc); |
3de7a1dc | 2664 | |
3de7a1dc TV |
2665 | p = data; |
2666 | for (i = 0; i < len >> 2; i++) { | |
f1da39d9 | 2667 | if (dsi->debug_write) |
3de7a1dc | 2668 | DSSDBG("\tsending full packet %d\n", i); |
3de7a1dc TV |
2669 | |
2670 | b1 = *p++; | |
2671 | b2 = *p++; | |
2672 | b3 = *p++; | |
2673 | b4 = *p++; | |
2674 | ||
7093d6cd | 2675 | dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4); |
3de7a1dc TV |
2676 | } |
2677 | ||
2678 | i = len % 4; | |
2679 | if (i) { | |
2680 | b1 = 0; b2 = 0; b3 = 0; | |
2681 | ||
f1da39d9 | 2682 | if (dsi->debug_write) |
3de7a1dc TV |
2683 | DSSDBG("\tsending remainder bytes %d\n", i); |
2684 | ||
2685 | switch (i) { | |
2686 | case 3: | |
2687 | b1 = *p++; | |
2688 | b2 = *p++; | |
2689 | b3 = *p++; | |
2690 | break; | |
2691 | case 2: | |
2692 | b1 = *p++; | |
2693 | b2 = *p++; | |
2694 | break; | |
2695 | case 1: | |
2696 | b1 = *p++; | |
2697 | break; | |
2698 | } | |
2699 | ||
7093d6cd | 2700 | dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0); |
3de7a1dc TV |
2701 | } |
2702 | ||
2703 | return r; | |
2704 | } | |
2705 | ||
7093d6cd LP |
2706 | static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type, |
2707 | u16 data, u8 ecc) | |
3de7a1dc TV |
2708 | { |
2709 | u32 r; | |
2710 | u8 data_id; | |
2711 | ||
7093d6cd | 2712 | WARN_ON(!dsi_bus_is_locked(dsi)); |
3de7a1dc | 2713 | |
f1da39d9 | 2714 | if (dsi->debug_write) |
3de7a1dc TV |
2715 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
2716 | channel, | |
2717 | data_type, data & 0xff, (data >> 8) & 0xff); | |
2718 | ||
7093d6cd | 2719 | dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 2720 | |
7093d6cd | 2721 | if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) { |
3de7a1dc TV |
2722 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
2723 | return -EINVAL; | |
2724 | } | |
2725 | ||
f1da39d9 | 2726 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
2727 | |
2728 | r = (data_id << 0) | (data << 8) | (ecc << 24); | |
2729 | ||
7093d6cd | 2730 | dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
3de7a1dc TV |
2731 | |
2732 | return 0; | |
2733 | } | |
2734 | ||
7093d6cd | 2735 | static int dsi_vc_send_null(struct dsi_data *dsi, int channel) |
3de7a1dc | 2736 | { |
7093d6cd | 2737 | return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0); |
3de7a1dc | 2738 | } |
3de7a1dc | 2739 | |
7093d6cd LP |
2740 | static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel, |
2741 | u8 *data, int len, | |
2742 | enum dss_dsi_content_type type) | |
3de7a1dc TV |
2743 | { |
2744 | int r; | |
2745 | ||
6ff8aa31 AT |
2746 | if (len == 0) { |
2747 | BUG_ON(type == DSS_DSI_CONTENT_DCS); | |
7093d6cd | 2748 | r = dsi_vc_send_short(dsi, channel, |
6ff8aa31 AT |
2749 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); |
2750 | } else if (len == 1) { | |
7093d6cd | 2751 | r = dsi_vc_send_short(dsi, channel, |
6ff8aa31 AT |
2752 | type == DSS_DSI_CONTENT_GENERIC ? |
2753 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : | |
7a7c48f9 | 2754 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); |
3de7a1dc | 2755 | } else if (len == 2) { |
7093d6cd | 2756 | r = dsi_vc_send_short(dsi, channel, |
6ff8aa31 AT |
2757 | type == DSS_DSI_CONTENT_GENERIC ? |
2758 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : | |
7a7c48f9 | 2759 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
3de7a1dc TV |
2760 | data[0] | (data[1] << 8), 0); |
2761 | } else { | |
7093d6cd | 2762 | r = dsi_vc_send_long(dsi, channel, |
6ff8aa31 AT |
2763 | type == DSS_DSI_CONTENT_GENERIC ? |
2764 | MIPI_DSI_GENERIC_LONG_WRITE : | |
2765 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); | |
3de7a1dc TV |
2766 | } |
2767 | ||
2768 | return r; | |
2769 | } | |
6ff8aa31 | 2770 | |
5cfc1c3c | 2771 | static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
6ff8aa31 AT |
2772 | u8 *data, int len) |
2773 | { | |
c068408e | 2774 | struct dsi_data *dsi = to_dsi_data(dssdev); |
9e7e9372 | 2775 | |
7093d6cd | 2776 | return dsi_vc_write_nosync_common(dsi, channel, data, len, |
6ff8aa31 AT |
2777 | DSS_DSI_CONTENT_DCS); |
2778 | } | |
3de7a1dc | 2779 | |
5cfc1c3c | 2780 | static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
6ff8aa31 AT |
2781 | u8 *data, int len) |
2782 | { | |
c068408e | 2783 | struct dsi_data *dsi = to_dsi_data(dssdev); |
9e7e9372 | 2784 | |
7093d6cd | 2785 | return dsi_vc_write_nosync_common(dsi, channel, data, len, |
6ff8aa31 AT |
2786 | DSS_DSI_CONTENT_GENERIC); |
2787 | } | |
6ff8aa31 | 2788 | |
7093d6cd LP |
2789 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, |
2790 | int channel, u8 *data, int len, | |
2791 | enum dss_dsi_content_type type) | |
3de7a1dc | 2792 | { |
c068408e | 2793 | struct dsi_data *dsi = to_dsi_data(dssdev); |
3de7a1dc TV |
2794 | int r; |
2795 | ||
7093d6cd | 2796 | r = dsi_vc_write_nosync_common(dsi, channel, data, len, type); |
3de7a1dc | 2797 | if (r) |
5d68e032 | 2798 | goto err; |
3de7a1dc | 2799 | |
1ffefe75 | 2800 | r = dsi_vc_send_bta_sync(dssdev, channel); |
5d68e032 TV |
2801 | if (r) |
2802 | goto err; | |
3de7a1dc | 2803 | |
a72b64b9 | 2804 | /* RX_FIFO_NOT_EMPTY */ |
7093d6cd | 2805 | if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { |
b63ac1e3 | 2806 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
7093d6cd | 2807 | dsi_vc_flush_receive_data(dsi, channel); |
b63ac1e3 TV |
2808 | r = -EIO; |
2809 | goto err; | |
2810 | } | |
2811 | ||
5d68e032 TV |
2812 | return 0; |
2813 | err: | |
6ff8aa31 | 2814 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", |
5d68e032 | 2815 | channel, data[0], len); |
3de7a1dc TV |
2816 | return r; |
2817 | } | |
6ff8aa31 | 2818 | |
5cfc1c3c | 2819 | static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
6ff8aa31 AT |
2820 | int len) |
2821 | { | |
2822 | return dsi_vc_write_common(dssdev, channel, data, len, | |
2823 | DSS_DSI_CONTENT_DCS); | |
2824 | } | |
3de7a1dc | 2825 | |
5cfc1c3c | 2826 | static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
6ff8aa31 AT |
2827 | int len) |
2828 | { | |
2829 | return dsi_vc_write_common(dssdev, channel, data, len, | |
2830 | DSS_DSI_CONTENT_GENERIC); | |
2831 | } | |
6ff8aa31 | 2832 | |
7093d6cd LP |
2833 | static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel, |
2834 | u8 dcs_cmd) | |
3de7a1dc | 2835 | { |
3de7a1dc TV |
2836 | int r; |
2837 | ||
f1da39d9 | 2838 | if (dsi->debug_read) |
b850975c AT |
2839 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", |
2840 | channel, dcs_cmd); | |
3de7a1dc | 2841 | |
7093d6cd | 2842 | r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); |
b850975c AT |
2843 | if (r) { |
2844 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" | |
2845 | " failed\n", channel, dcs_cmd); | |
2846 | return r; | |
2847 | } | |
3de7a1dc | 2848 | |
b850975c AT |
2849 | return 0; |
2850 | } | |
2851 | ||
7093d6cd LP |
2852 | static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel, |
2853 | u8 *reqdata, int reqlen) | |
b3b89c05 | 2854 | { |
b3b89c05 AT |
2855 | u16 data; |
2856 | u8 data_type; | |
2857 | int r; | |
2858 | ||
2859 | if (dsi->debug_read) | |
2860 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", | |
2861 | channel, reqlen); | |
2862 | ||
2863 | if (reqlen == 0) { | |
2864 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; | |
2865 | data = 0; | |
2866 | } else if (reqlen == 1) { | |
2867 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; | |
2868 | data = reqdata[0]; | |
2869 | } else if (reqlen == 2) { | |
2870 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; | |
2871 | data = reqdata[0] | (reqdata[1] << 8); | |
2872 | } else { | |
2873 | BUG(); | |
c6eee968 | 2874 | return -EINVAL; |
b3b89c05 AT |
2875 | } |
2876 | ||
7093d6cd | 2877 | r = dsi_vc_send_short(dsi, channel, data_type, data, 0); |
b3b89c05 AT |
2878 | if (r) { |
2879 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" | |
2880 | " failed\n", channel, reqlen); | |
2881 | return r; | |
2882 | } | |
2883 | ||
2884 | return 0; | |
2885 | } | |
2886 | ||
7093d6cd LP |
2887 | static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf, |
2888 | int buflen, enum dss_dsi_content_type type) | |
b850975c | 2889 | { |
b850975c AT |
2890 | u32 val; |
2891 | u8 dt; | |
2892 | int r; | |
3de7a1dc TV |
2893 | |
2894 | /* RX_FIFO_NOT_EMPTY */ | |
7093d6cd | 2895 | if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) { |
3de7a1dc | 2896 | DSSERR("RX fifo empty when trying to read.\n"); |
5d68e032 TV |
2897 | r = -EIO; |
2898 | goto err; | |
3de7a1dc TV |
2899 | } |
2900 | ||
7093d6cd | 2901 | val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); |
f1da39d9 | 2902 | if (dsi->debug_read) |
3de7a1dc TV |
2903 | DSSDBG("\theader: %08x\n", val); |
2904 | dt = FLD_GET(val, 5, 0); | |
7a7c48f9 | 2905 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
2906 | u16 err = FLD_GET(val, 23, 8); |
2907 | dsi_show_rx_ack_with_err(err); | |
5d68e032 TV |
2908 | r = -EIO; |
2909 | goto err; | |
3de7a1dc | 2910 | |
b3b89c05 AT |
2911 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
2912 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : | |
2913 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { | |
3de7a1dc | 2914 | u8 data = FLD_GET(val, 15, 8); |
f1da39d9 | 2915 | if (dsi->debug_read) |
b3b89c05 AT |
2916 | DSSDBG("\t%s short response, 1 byte: %02x\n", |
2917 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
2918 | "DCS", data); | |
3de7a1dc | 2919 | |
5d68e032 TV |
2920 | if (buflen < 1) { |
2921 | r = -EIO; | |
2922 | goto err; | |
2923 | } | |
3de7a1dc TV |
2924 | |
2925 | buf[0] = data; | |
2926 | ||
2927 | return 1; | |
b3b89c05 AT |
2928 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
2929 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : | |
2930 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { | |
3de7a1dc | 2931 | u16 data = FLD_GET(val, 23, 8); |
f1da39d9 | 2932 | if (dsi->debug_read) |
b3b89c05 AT |
2933 | DSSDBG("\t%s short response, 2 byte: %04x\n", |
2934 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
2935 | "DCS", data); | |
3de7a1dc | 2936 | |
5d68e032 TV |
2937 | if (buflen < 2) { |
2938 | r = -EIO; | |
2939 | goto err; | |
2940 | } | |
3de7a1dc TV |
2941 | |
2942 | buf[0] = data & 0xff; | |
2943 | buf[1] = (data >> 8) & 0xff; | |
2944 | ||
2945 | return 2; | |
b3b89c05 AT |
2946 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
2947 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : | |
2948 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { | |
3de7a1dc TV |
2949 | int w; |
2950 | int len = FLD_GET(val, 23, 8); | |
f1da39d9 | 2951 | if (dsi->debug_read) |
b3b89c05 AT |
2952 | DSSDBG("\t%s long response, len %d\n", |
2953 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
2954 | "DCS", len); | |
3de7a1dc | 2955 | |
5d68e032 TV |
2956 | if (len > buflen) { |
2957 | r = -EIO; | |
2958 | goto err; | |
2959 | } | |
3de7a1dc TV |
2960 | |
2961 | /* two byte checksum ends the packet, not included in len */ | |
2962 | for (w = 0; w < len + 2;) { | |
2963 | int b; | |
7093d6cd | 2964 | val = dsi_read_reg(dsi, |
a72b64b9 | 2965 | DSI_VC_SHORT_PACKET_HEADER(channel)); |
f1da39d9 | 2966 | if (dsi->debug_read) |
3de7a1dc TV |
2967 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
2968 | (val >> 0) & 0xff, | |
2969 | (val >> 8) & 0xff, | |
2970 | (val >> 16) & 0xff, | |
2971 | (val >> 24) & 0xff); | |
2972 | ||
2973 | for (b = 0; b < 4; ++b) { | |
2974 | if (w < len) | |
2975 | buf[w] = (val >> (b * 8)) & 0xff; | |
2976 | /* we discard the 2 byte checksum */ | |
2977 | ++w; | |
2978 | } | |
2979 | } | |
2980 | ||
2981 | return len; | |
3de7a1dc TV |
2982 | } else { |
2983 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
5d68e032 TV |
2984 | r = -EIO; |
2985 | goto err; | |
3de7a1dc | 2986 | } |
5d68e032 | 2987 | |
5d68e032 | 2988 | err: |
b3b89c05 AT |
2989 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, |
2990 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); | |
b850975c | 2991 | |
5d68e032 | 2992 | return r; |
b850975c AT |
2993 | } |
2994 | ||
5cfc1c3c | 2995 | static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
b850975c AT |
2996 | u8 *buf, int buflen) |
2997 | { | |
c068408e | 2998 | struct dsi_data *dsi = to_dsi_data(dssdev); |
b850975c AT |
2999 | int r; |
3000 | ||
7093d6cd | 3001 | r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd); |
b850975c AT |
3002 | if (r) |
3003 | goto err; | |
5d68e032 | 3004 | |
b850975c AT |
3005 | r = dsi_vc_send_bta_sync(dssdev, channel); |
3006 | if (r) | |
3007 | goto err; | |
3008 | ||
7093d6cd | 3009 | r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen, |
b3b89c05 | 3010 | DSS_DSI_CONTENT_DCS); |
b850975c AT |
3011 | if (r < 0) |
3012 | goto err; | |
3013 | ||
3014 | if (r != buflen) { | |
3015 | r = -EIO; | |
3016 | goto err; | |
3017 | } | |
3018 | ||
3019 | return 0; | |
3020 | err: | |
3021 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); | |
3022 | return r; | |
3de7a1dc | 3023 | } |
3de7a1dc | 3024 | |
b3b89c05 AT |
3025 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, |
3026 | u8 *reqdata, int reqlen, u8 *buf, int buflen) | |
3027 | { | |
c068408e | 3028 | struct dsi_data *dsi = to_dsi_data(dssdev); |
b3b89c05 AT |
3029 | int r; |
3030 | ||
7093d6cd | 3031 | r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen); |
b3b89c05 AT |
3032 | if (r) |
3033 | return r; | |
3034 | ||
3035 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
3036 | if (r) | |
3037 | return r; | |
3038 | ||
7093d6cd | 3039 | r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen, |
b3b89c05 AT |
3040 | DSS_DSI_CONTENT_GENERIC); |
3041 | if (r < 0) | |
3042 | return r; | |
3043 | ||
3044 | if (r != buflen) { | |
3045 | r = -EIO; | |
3046 | return r; | |
3047 | } | |
3048 | ||
3049 | return 0; | |
3050 | } | |
3051 | ||
5cfc1c3c | 3052 | static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
1ffefe75 | 3053 | u16 len) |
3de7a1dc | 3054 | { |
c068408e | 3055 | struct dsi_data *dsi = to_dsi_data(dssdev); |
a72b64b9 | 3056 | |
7093d6cd | 3057 | return dsi_vc_send_short(dsi, channel, |
7a7c48f9 | 3058 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); |
3de7a1dc | 3059 | } |
3de7a1dc | 3060 | |
7093d6cd | 3061 | static int dsi_enter_ulps(struct dsi_data *dsi) |
40885ab3 TV |
3062 | { |
3063 | DECLARE_COMPLETION_ONSTACK(completion); | |
522a0c2f | 3064 | int r, i; |
d11e5c82 | 3065 | unsigned int mask; |
40885ab3 | 3066 | |
702d267e | 3067 | DSSDBG("Entering ULPS"); |
40885ab3 | 3068 | |
7093d6cd | 3069 | WARN_ON(!dsi_bus_is_locked(dsi)); |
40885ab3 | 3070 | |
f1da39d9 | 3071 | WARN_ON(dsi->ulps_enabled); |
40885ab3 | 3072 | |
f1da39d9 | 3073 | if (dsi->ulps_enabled) |
40885ab3 TV |
3074 | return 0; |
3075 | ||
6cc78aa9 | 3076 | /* DDR_CLK_ALWAYS_ON */ |
7093d6cd LP |
3077 | if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) { |
3078 | dsi_if_enable(dsi, 0); | |
3079 | REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); | |
3080 | dsi_if_enable(dsi, 1); | |
40885ab3 TV |
3081 | } |
3082 | ||
7093d6cd LP |
3083 | dsi_sync_vc(dsi, 0); |
3084 | dsi_sync_vc(dsi, 1); | |
3085 | dsi_sync_vc(dsi, 2); | |
3086 | dsi_sync_vc(dsi, 3); | |
40885ab3 | 3087 | |
7093d6cd | 3088 | dsi_force_tx_stop_mode_io(dsi); |
40885ab3 | 3089 | |
7093d6cd LP |
3090 | dsi_vc_enable(dsi, 0, false); |
3091 | dsi_vc_enable(dsi, 1, false); | |
3092 | dsi_vc_enable(dsi, 2, false); | |
3093 | dsi_vc_enable(dsi, 3, false); | |
40885ab3 | 3094 | |
7093d6cd | 3095 | if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
40885ab3 TV |
3096 | DSSERR("HS busy when enabling ULPS\n"); |
3097 | return -EIO; | |
3098 | } | |
3099 | ||
7093d6cd | 3100 | if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
40885ab3 TV |
3101 | DSSERR("LP busy when enabling ULPS\n"); |
3102 | return -EIO; | |
3103 | } | |
3104 | ||
7093d6cd | 3105 | r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion, |
40885ab3 TV |
3106 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3107 | if (r) | |
3108 | return r; | |
3109 | ||
522a0c2f TV |
3110 | mask = 0; |
3111 | ||
3112 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
3113 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
3114 | continue; | |
3115 | mask |= 1 << i; | |
3116 | } | |
40885ab3 TV |
3117 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ |
3118 | /* LANEx_ULPS_SIG2 */ | |
7093d6cd | 3119 | REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5); |
40885ab3 | 3120 | |
a702c859 | 3121 | /* flush posted write and wait for SCP interface to finish the write */ |
7093d6cd | 3122 | dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2); |
40885ab3 TV |
3123 | |
3124 | if (wait_for_completion_timeout(&completion, | |
3125 | msecs_to_jiffies(1000)) == 0) { | |
3126 | DSSERR("ULPS enable timeout\n"); | |
3127 | r = -EIO; | |
3128 | goto err; | |
3129 | } | |
3130 | ||
7093d6cd | 3131 | dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion, |
40885ab3 TV |
3132 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3133 | ||
8ef0e614 | 3134 | /* Reset LANEx_ULPS_SIG2 */ |
7093d6cd | 3135 | REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5); |
8ef0e614 | 3136 | |
a702c859 | 3137 | /* flush posted write and wait for SCP interface to finish the write */ |
7093d6cd | 3138 | dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2); |
8ef0e614 | 3139 | |
7093d6cd | 3140 | dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS); |
40885ab3 | 3141 | |
7093d6cd | 3142 | dsi_if_enable(dsi, false); |
40885ab3 | 3143 | |
f1da39d9 | 3144 | dsi->ulps_enabled = true; |
40885ab3 TV |
3145 | |
3146 | return 0; | |
3147 | ||
3148 | err: | |
7093d6cd | 3149 | dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion, |
40885ab3 TV |
3150 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3151 | return r; | |
3152 | } | |
3153 | ||
7093d6cd LP |
3154 | static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks, |
3155 | bool x4, bool x16) | |
3de7a1dc | 3156 | { |
3de7a1dc | 3157 | unsigned long fck; |
4ffa3571 TV |
3158 | unsigned long total_ticks; |
3159 | u32 r; | |
3de7a1dc | 3160 | |
4ffa3571 | 3161 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3162 | |
4ffa3571 | 3163 | /* ticks in DSI_FCK */ |
7093d6cd | 3164 | fck = dsi_fclk_rate(dsi); |
3de7a1dc | 3165 | |
7093d6cd | 3166 | r = dsi_read_reg(dsi, DSI_TIMING2); |
3de7a1dc | 3167 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
4ffa3571 TV |
3168 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
3169 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ | |
3de7a1dc | 3170 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
7093d6cd | 3171 | dsi_write_reg(dsi, DSI_TIMING2, r); |
3de7a1dc | 3172 | |
4ffa3571 TV |
3173 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3174 | ||
3175 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3176 | total_ticks, | |
3177 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3178 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3179 | } |
3180 | ||
7093d6cd LP |
3181 | static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks, |
3182 | bool x8, bool x16) | |
3de7a1dc | 3183 | { |
3de7a1dc | 3184 | unsigned long fck; |
4ffa3571 TV |
3185 | unsigned long total_ticks; |
3186 | u32 r; | |
3187 | ||
3188 | BUG_ON(ticks > 0x1fff); | |
3de7a1dc TV |
3189 | |
3190 | /* ticks in DSI_FCK */ | |
7093d6cd | 3191 | fck = dsi_fclk_rate(dsi); |
3de7a1dc | 3192 | |
7093d6cd | 3193 | r = dsi_read_reg(dsi, DSI_TIMING1); |
3de7a1dc | 3194 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
4ffa3571 TV |
3195 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
3196 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ | |
3de7a1dc | 3197 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
7093d6cd | 3198 | dsi_write_reg(dsi, DSI_TIMING1, r); |
3de7a1dc | 3199 | |
4ffa3571 TV |
3200 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
3201 | ||
3202 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3203 | total_ticks, | |
3204 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", | |
3205 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3206 | } |
3207 | ||
7093d6cd LP |
3208 | static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks, |
3209 | bool x4, bool x16) | |
3de7a1dc | 3210 | { |
3de7a1dc | 3211 | unsigned long fck; |
4ffa3571 TV |
3212 | unsigned long total_ticks; |
3213 | u32 r; | |
3de7a1dc | 3214 | |
4ffa3571 | 3215 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3216 | |
4ffa3571 | 3217 | /* ticks in DSI_FCK */ |
7093d6cd | 3218 | fck = dsi_fclk_rate(dsi); |
3de7a1dc | 3219 | |
7093d6cd | 3220 | r = dsi_read_reg(dsi, DSI_TIMING1); |
3de7a1dc | 3221 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
4ffa3571 TV |
3222 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
3223 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ | |
3de7a1dc | 3224 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
7093d6cd | 3225 | dsi_write_reg(dsi, DSI_TIMING1, r); |
3de7a1dc | 3226 | |
4ffa3571 TV |
3227 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3228 | ||
3229 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", | |
3230 | total_ticks, | |
3231 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3232 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3233 | } |
3234 | ||
7093d6cd LP |
3235 | static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks, |
3236 | bool x4, bool x16) | |
3de7a1dc | 3237 | { |
3de7a1dc | 3238 | unsigned long fck; |
4ffa3571 TV |
3239 | unsigned long total_ticks; |
3240 | u32 r; | |
3de7a1dc | 3241 | |
4ffa3571 | 3242 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3243 | |
4ffa3571 | 3244 | /* ticks in TxByteClkHS */ |
7093d6cd | 3245 | fck = dsi_get_txbyteclkhs(dsi); |
3de7a1dc | 3246 | |
7093d6cd | 3247 | r = dsi_read_reg(dsi, DSI_TIMING2); |
3de7a1dc | 3248 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
4ffa3571 TV |
3249 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
3250 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ | |
3de7a1dc | 3251 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
7093d6cd | 3252 | dsi_write_reg(dsi, DSI_TIMING2, r); |
3de7a1dc | 3253 | |
4ffa3571 TV |
3254 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3255 | ||
3256 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3257 | total_ticks, | |
3258 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3259 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc | 3260 | } |
8af6ff01 | 3261 | |
7093d6cd | 3262 | static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi) |
8af6ff01 | 3263 | { |
8af6ff01 AT |
3264 | int num_line_buffers; |
3265 | ||
dca2b152 | 3266 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
02c3960b | 3267 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
7d39e59b | 3268 | const struct videomode *vm = &dsi->vm; |
8af6ff01 AT |
3269 | /* |
3270 | * Don't use line buffers if width is greater than the video | |
3271 | * port's line buffer size | |
3272 | */ | |
da11bbbb | 3273 | if (dsi->line_buffer_size <= vm->hactive * bpp / 8) |
8af6ff01 AT |
3274 | num_line_buffers = 0; |
3275 | else | |
3276 | num_line_buffers = 2; | |
3277 | } else { | |
3278 | /* Use maximum number of line buffers in command mode */ | |
3279 | num_line_buffers = 2; | |
3280 | } | |
3281 | ||
3282 | /* LINE_BUFFER */ | |
7093d6cd | 3283 | REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12); |
8af6ff01 AT |
3284 | } |
3285 | ||
7093d6cd | 3286 | static void dsi_config_vp_sync_events(struct dsi_data *dsi) |
8af6ff01 | 3287 | { |
478d7df8 | 3288 | bool sync_end; |
8af6ff01 AT |
3289 | u32 r; |
3290 | ||
478d7df8 TV |
3291 | if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) |
3292 | sync_end = true; | |
3293 | else | |
3294 | sync_end = false; | |
3295 | ||
7093d6cd | 3296 | r = dsi_read_reg(dsi, DSI_CTRL); |
bd5a7b11 AT |
3297 | r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ |
3298 | r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ | |
3299 | r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ | |
8af6ff01 | 3300 | r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ |
478d7df8 | 3301 | r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ |
8af6ff01 | 3302 | r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ |
478d7df8 | 3303 | r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ |
7093d6cd | 3304 | dsi_write_reg(dsi, DSI_CTRL, r); |
8af6ff01 AT |
3305 | } |
3306 | ||
7093d6cd | 3307 | static void dsi_config_blanking_modes(struct dsi_data *dsi) |
8af6ff01 | 3308 | { |
0b3ffe39 AT |
3309 | int blanking_mode = dsi->vm_timings.blanking_mode; |
3310 | int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; | |
3311 | int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; | |
3312 | int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; | |
8af6ff01 AT |
3313 | u32 r; |
3314 | ||
3315 | /* | |
3316 | * 0 = TX FIFO packets sent or LPS in corresponding blanking periods | |
3317 | * 1 = Long blanking packets are sent in corresponding blanking periods | |
3318 | */ | |
7093d6cd | 3319 | r = dsi_read_reg(dsi, DSI_CTRL); |
8af6ff01 AT |
3320 | r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ |
3321 | r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ | |
3322 | r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ | |
3323 | r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ | |
7093d6cd | 3324 | dsi_write_reg(dsi, DSI_CTRL, r); |
8af6ff01 AT |
3325 | } |
3326 | ||
6f28c296 AT |
3327 | /* |
3328 | * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 | |
3329 | * results in maximum transition time for data and clock lanes to enter and | |
3330 | * exit HS mode. Hence, this is the scenario where the least amount of command | |
3331 | * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS | |
3332 | * clock cycles that can be used to interleave command mode data in HS so that | |
3333 | * all scenarios are satisfied. | |
3334 | */ | |
3335 | static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, | |
3336 | int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) | |
3337 | { | |
3338 | int transition; | |
3339 | ||
3340 | /* | |
3341 | * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition | |
3342 | * time of data lanes only, if it isn't set, we need to consider HS | |
3343 | * transition time of both data and clock lanes. HS transition time | |
3344 | * of Scenario 3 is considered. | |
3345 | */ | |
3346 | if (ddr_alwon) { | |
3347 | transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3348 | } else { | |
3349 | int trans1, trans2; | |
3350 | trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3351 | trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + | |
3352 | enter_hs + 1; | |
3353 | transition = max(trans1, trans2); | |
3354 | } | |
3355 | ||
3356 | return blank > transition ? blank - transition : 0; | |
3357 | } | |
3358 | ||
3359 | /* | |
3360 | * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 | |
3361 | * results in maximum transition time for data lanes to enter and exit LP mode. | |
3362 | * Hence, this is the scenario where the least amount of command mode data can | |
3363 | * be interleaved. We program the minimum amount of bytes that can be | |
3364 | * interleaved in LP so that all scenarios are satisfied. | |
3365 | */ | |
3366 | static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, | |
3367 | int lp_clk_div, int tdsi_fclk) | |
3368 | { | |
3369 | int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ | |
3370 | int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ | |
3371 | int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ | |
3372 | int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ | |
3373 | int lp_inter; /* cmd mode data that can be interleaved, in bytes */ | |
3374 | ||
3375 | /* maximum LP transition time according to Scenario 1 */ | |
3376 | trans_lp = exit_hs + max(enter_hs, 2) + 1; | |
3377 | ||
3378 | /* CLKIN4DDR = 16 * TXBYTECLKHS */ | |
3379 | tlp_avail = thsbyte_clk * (blank - trans_lp); | |
3380 | ||
2e063c30 | 3381 | ttxclkesc = tdsi_fclk * lp_clk_div; |
6f28c296 AT |
3382 | |
3383 | lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - | |
3384 | 26) / 16; | |
3385 | ||
3386 | return max(lp_inter, 0); | |
3387 | } | |
3388 | ||
7093d6cd | 3389 | static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi) |
6f28c296 | 3390 | { |
6f28c296 AT |
3391 | int blanking_mode; |
3392 | int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; | |
3393 | int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; | |
3394 | int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; | |
3395 | int tclk_trail, ths_exit, exiths_clk; | |
3396 | bool ddr_alwon; | |
7d39e59b | 3397 | const struct videomode *vm = &dsi->vm; |
02c3960b | 3398 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
6f28c296 | 3399 | int ndl = dsi->num_lanes_used - 1; |
2daea7af | 3400 | int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; |
6f28c296 AT |
3401 | int hsa_interleave_hs = 0, hsa_interleave_lp = 0; |
3402 | int hfp_interleave_hs = 0, hfp_interleave_lp = 0; | |
3403 | int hbp_interleave_hs = 0, hbp_interleave_lp = 0; | |
3404 | int bl_interleave_hs = 0, bl_interleave_lp = 0; | |
3405 | u32 r; | |
3406 | ||
7093d6cd | 3407 | r = dsi_read_reg(dsi, DSI_CTRL); |
6f28c296 AT |
3408 | blanking_mode = FLD_GET(r, 20, 20); |
3409 | hfp_blanking_mode = FLD_GET(r, 21, 21); | |
3410 | hbp_blanking_mode = FLD_GET(r, 22, 22); | |
3411 | hsa_blanking_mode = FLD_GET(r, 23, 23); | |
3412 | ||
7093d6cd | 3413 | r = dsi_read_reg(dsi, DSI_VM_TIMING1); |
6f28c296 AT |
3414 | hbp = FLD_GET(r, 11, 0); |
3415 | hfp = FLD_GET(r, 23, 12); | |
3416 | hsa = FLD_GET(r, 31, 24); | |
3417 | ||
7093d6cd | 3418 | r = dsi_read_reg(dsi, DSI_CLK_TIMING); |
6f28c296 AT |
3419 | ddr_clk_post = FLD_GET(r, 7, 0); |
3420 | ddr_clk_pre = FLD_GET(r, 15, 8); | |
3421 | ||
7093d6cd | 3422 | r = dsi_read_reg(dsi, DSI_VM_TIMING7); |
6f28c296 AT |
3423 | exit_hs_mode_lat = FLD_GET(r, 15, 0); |
3424 | enter_hs_mode_lat = FLD_GET(r, 31, 16); | |
3425 | ||
7093d6cd | 3426 | r = dsi_read_reg(dsi, DSI_CLK_CTRL); |
6f28c296 AT |
3427 | lp_clk_div = FLD_GET(r, 12, 0); |
3428 | ddr_alwon = FLD_GET(r, 13, 13); | |
3429 | ||
7093d6cd | 3430 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); |
6f28c296 AT |
3431 | ths_exit = FLD_GET(r, 7, 0); |
3432 | ||
7093d6cd | 3433 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); |
6f28c296 AT |
3434 | tclk_trail = FLD_GET(r, 15, 8); |
3435 | ||
3436 | exiths_clk = ths_exit + tclk_trail; | |
3437 | ||
da11bbbb | 3438 | width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); |
6f28c296 AT |
3439 | bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); |
3440 | ||
3441 | if (!hsa_blanking_mode) { | |
3442 | hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, | |
3443 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3444 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3445 | hsa_interleave_lp = dsi_compute_interleave_lp(hsa, | |
3446 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3447 | lp_clk_div, dsi_fclk_hsdiv); | |
3448 | } | |
3449 | ||
3450 | if (!hfp_blanking_mode) { | |
3451 | hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, | |
3452 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3453 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3454 | hfp_interleave_lp = dsi_compute_interleave_lp(hfp, | |
3455 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3456 | lp_clk_div, dsi_fclk_hsdiv); | |
3457 | } | |
3458 | ||
3459 | if (!hbp_blanking_mode) { | |
3460 | hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, | |
3461 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3462 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3463 | ||
3464 | hbp_interleave_lp = dsi_compute_interleave_lp(hbp, | |
3465 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3466 | lp_clk_div, dsi_fclk_hsdiv); | |
3467 | } | |
3468 | ||
3469 | if (!blanking_mode) { | |
3470 | bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, | |
3471 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3472 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3473 | ||
3474 | bl_interleave_lp = dsi_compute_interleave_lp(bllp, | |
3475 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3476 | lp_clk_div, dsi_fclk_hsdiv); | |
3477 | } | |
3478 | ||
3479 | DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3480 | hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, | |
3481 | bl_interleave_hs); | |
3482 | ||
3483 | DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3484 | hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, | |
3485 | bl_interleave_lp); | |
3486 | ||
7093d6cd | 3487 | r = dsi_read_reg(dsi, DSI_VM_TIMING4); |
6f28c296 AT |
3488 | r = FLD_MOD(r, hsa_interleave_hs, 23, 16); |
3489 | r = FLD_MOD(r, hfp_interleave_hs, 15, 8); | |
3490 | r = FLD_MOD(r, hbp_interleave_hs, 7, 0); | |
7093d6cd | 3491 | dsi_write_reg(dsi, DSI_VM_TIMING4, r); |
6f28c296 | 3492 | |
7093d6cd | 3493 | r = dsi_read_reg(dsi, DSI_VM_TIMING5); |
6f28c296 AT |
3494 | r = FLD_MOD(r, hsa_interleave_lp, 23, 16); |
3495 | r = FLD_MOD(r, hfp_interleave_lp, 15, 8); | |
3496 | r = FLD_MOD(r, hbp_interleave_lp, 7, 0); | |
7093d6cd | 3497 | dsi_write_reg(dsi, DSI_VM_TIMING5, r); |
6f28c296 | 3498 | |
7093d6cd | 3499 | r = dsi_read_reg(dsi, DSI_VM_TIMING6); |
6f28c296 AT |
3500 | r = FLD_MOD(r, bl_interleave_hs, 31, 15); |
3501 | r = FLD_MOD(r, bl_interleave_lp, 16, 0); | |
7093d6cd | 3502 | dsi_write_reg(dsi, DSI_VM_TIMING6, r); |
6f28c296 AT |
3503 | } |
3504 | ||
7093d6cd | 3505 | static int dsi_proto_config(struct dsi_data *dsi) |
3de7a1dc TV |
3506 | { |
3507 | u32 r; | |
3508 | int buswidth = 0; | |
3509 | ||
7093d6cd | 3510 | dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3511 | DSI_FIFO_SIZE_32, |
3512 | DSI_FIFO_SIZE_32, | |
3513 | DSI_FIFO_SIZE_32); | |
3de7a1dc | 3514 | |
7093d6cd | 3515 | dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3516 | DSI_FIFO_SIZE_32, |
3517 | DSI_FIFO_SIZE_32, | |
3518 | DSI_FIFO_SIZE_32); | |
3de7a1dc TV |
3519 | |
3520 | /* XXX what values for the timeouts? */ | |
7093d6cd LP |
3521 | dsi_set_stop_state_counter(dsi, 0x1000, false, false); |
3522 | dsi_set_ta_timeout(dsi, 0x1fff, true, true); | |
3523 | dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true); | |
3524 | dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true); | |
3de7a1dc | 3525 | |
02c3960b | 3526 | switch (dsi_get_pixel_size(dsi->pix_fmt)) { |
3de7a1dc TV |
3527 | case 16: |
3528 | buswidth = 0; | |
3529 | break; | |
3530 | case 18: | |
3531 | buswidth = 1; | |
3532 | break; | |
3533 | case 24: | |
3534 | buswidth = 2; | |
3535 | break; | |
3536 | default: | |
3537 | BUG(); | |
c6eee968 | 3538 | return -EINVAL; |
3de7a1dc TV |
3539 | } |
3540 | ||
7093d6cd | 3541 | r = dsi_read_reg(dsi, DSI_CTRL); |
3de7a1dc TV |
3542 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
3543 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | |
3544 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | |
3545 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ | |
3546 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | |
3547 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | |
3de7a1dc TV |
3548 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
3549 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ | |
44d8ca10 | 3550 | if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { |
9613c02b AT |
3551 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ |
3552 | /* DCS_CMD_CODE, 1=start, 0=continue */ | |
3553 | r = FLD_MOD(r, 0, 25, 25); | |
3554 | } | |
3de7a1dc | 3555 | |
7093d6cd | 3556 | dsi_write_reg(dsi, DSI_CTRL, r); |
3de7a1dc | 3557 | |
7093d6cd | 3558 | dsi_config_vp_num_line_buffers(dsi); |
8af6ff01 | 3559 | |
dca2b152 | 3560 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
7093d6cd LP |
3561 | dsi_config_vp_sync_events(dsi); |
3562 | dsi_config_blanking_modes(dsi); | |
3563 | dsi_config_cmd_mode_interleaving(dsi); | |
8af6ff01 AT |
3564 | } |
3565 | ||
7093d6cd LP |
3566 | dsi_vc_initial_config(dsi, 0); |
3567 | dsi_vc_initial_config(dsi, 1); | |
3568 | dsi_vc_initial_config(dsi, 2); | |
3569 | dsi_vc_initial_config(dsi, 3); | |
3de7a1dc TV |
3570 | |
3571 | return 0; | |
3572 | } | |
3573 | ||
7093d6cd | 3574 | static void dsi_proto_timings(struct dsi_data *dsi) |
3de7a1dc | 3575 | { |
d11e5c82 LP |
3576 | unsigned int tlpx, tclk_zero, tclk_prepare, tclk_trail; |
3577 | unsigned int tclk_pre, tclk_post; | |
3578 | unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero; | |
3579 | unsigned int ths_trail, ths_exit; | |
3580 | unsigned int ddr_clk_pre, ddr_clk_post; | |
3581 | unsigned int enter_hs_mode_lat, exit_hs_mode_lat; | |
3582 | unsigned int ths_eot; | |
db18644f | 3583 | int ndl = dsi->num_lanes_used - 1; |
3de7a1dc TV |
3584 | u32 r; |
3585 | ||
7093d6cd | 3586 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
3587 | ths_prepare = FLD_GET(r, 31, 24); |
3588 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); | |
3589 | ths_zero = ths_prepare_ths_zero - ths_prepare; | |
3590 | ths_trail = FLD_GET(r, 15, 8); | |
3591 | ths_exit = FLD_GET(r, 7, 0); | |
3592 | ||
7093d6cd | 3593 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); |
e84dc1cc | 3594 | tlpx = FLD_GET(r, 20, 16) * 2; |
3de7a1dc TV |
3595 | tclk_trail = FLD_GET(r, 15, 8); |
3596 | tclk_zero = FLD_GET(r, 7, 0); | |
3597 | ||
7093d6cd | 3598 | r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); |
3de7a1dc TV |
3599 | tclk_prepare = FLD_GET(r, 7, 0); |
3600 | ||
3601 | /* min 8*UI */ | |
3602 | tclk_pre = 20; | |
3603 | /* min 60ns + 52*UI */ | |
7093d6cd | 3604 | tclk_post = ns2ddr(dsi, 60) + 26; |
3de7a1dc | 3605 | |
8af6ff01 | 3606 | ths_eot = DIV_ROUND_UP(4, ndl); |
3de7a1dc TV |
3607 | |
3608 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, | |
3609 | 4); | |
3610 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; | |
3611 | ||
3612 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); | |
3613 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); | |
3614 | ||
7093d6cd | 3615 | r = dsi_read_reg(dsi, DSI_CLK_TIMING); |
3de7a1dc TV |
3616 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
3617 | r = FLD_MOD(r, ddr_clk_post, 7, 0); | |
7093d6cd | 3618 | dsi_write_reg(dsi, DSI_CLK_TIMING, r); |
3de7a1dc TV |
3619 | |
3620 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", | |
3621 | ddr_clk_pre, | |
3622 | ddr_clk_post); | |
3623 | ||
3624 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + | |
3625 | DIV_ROUND_UP(ths_prepare, 4) + | |
3626 | DIV_ROUND_UP(ths_zero + 3, 4); | |
3627 | ||
3628 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; | |
3629 | ||
3630 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | | |
3631 | FLD_VAL(exit_hs_mode_lat, 15, 0); | |
7093d6cd | 3632 | dsi_write_reg(dsi, DSI_VM_TIMING7, r); |
3de7a1dc TV |
3633 | |
3634 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", | |
3635 | enter_hs_mode_lat, exit_hs_mode_lat); | |
8af6ff01 | 3636 | |
dca2b152 | 3637 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
8af6ff01 | 3638 | /* TODO: Implement a video mode check_timings function */ |
0b3ffe39 AT |
3639 | int hsa = dsi->vm_timings.hsa; |
3640 | int hfp = dsi->vm_timings.hfp; | |
3641 | int hbp = dsi->vm_timings.hbp; | |
3642 | int vsa = dsi->vm_timings.vsa; | |
3643 | int vfp = dsi->vm_timings.vfp; | |
3644 | int vbp = dsi->vm_timings.vbp; | |
3645 | int window_sync = dsi->vm_timings.window_sync; | |
478d7df8 | 3646 | bool hsync_end; |
7d39e59b | 3647 | const struct videomode *vm = &dsi->vm; |
02c3960b | 3648 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
8af6ff01 AT |
3649 | int tl, t_he, width_bytes; |
3650 | ||
478d7df8 | 3651 | hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; |
8af6ff01 AT |
3652 | t_he = hsync_end ? |
3653 | ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; | |
3654 | ||
da11bbbb | 3655 | width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); |
8af6ff01 AT |
3656 | |
3657 | /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ | |
3658 | tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + | |
3659 | DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; | |
3660 | ||
3661 | DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, | |
3662 | hfp, hsync_end ? hsa : 0, tl); | |
3663 | DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, | |
da11bbbb | 3664 | vsa, vm->vactive); |
8af6ff01 | 3665 | |
7093d6cd | 3666 | r = dsi_read_reg(dsi, DSI_VM_TIMING1); |
8af6ff01 AT |
3667 | r = FLD_MOD(r, hbp, 11, 0); /* HBP */ |
3668 | r = FLD_MOD(r, hfp, 23, 12); /* HFP */ | |
3669 | r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ | |
7093d6cd | 3670 | dsi_write_reg(dsi, DSI_VM_TIMING1, r); |
8af6ff01 | 3671 | |
7093d6cd | 3672 | r = dsi_read_reg(dsi, DSI_VM_TIMING2); |
8af6ff01 AT |
3673 | r = FLD_MOD(r, vbp, 7, 0); /* VBP */ |
3674 | r = FLD_MOD(r, vfp, 15, 8); /* VFP */ | |
3675 | r = FLD_MOD(r, vsa, 23, 16); /* VSA */ | |
3676 | r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ | |
7093d6cd | 3677 | dsi_write_reg(dsi, DSI_VM_TIMING2, r); |
8af6ff01 | 3678 | |
7093d6cd | 3679 | r = dsi_read_reg(dsi, DSI_VM_TIMING3); |
da11bbbb | 3680 | r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ |
8af6ff01 | 3681 | r = FLD_MOD(r, tl, 31, 16); /* TL */ |
7093d6cd | 3682 | dsi_write_reg(dsi, DSI_VM_TIMING3, r); |
8af6ff01 AT |
3683 | } |
3684 | } | |
3685 | ||
5cfc1c3c | 3686 | static int dsi_configure_pins(struct omap_dss_device *dssdev, |
e4a9e94c TV |
3687 | const struct omap_dsi_pin_config *pin_cfg) |
3688 | { | |
c068408e | 3689 | struct dsi_data *dsi = to_dsi_data(dssdev); |
e4a9e94c TV |
3690 | int num_pins; |
3691 | const int *pins; | |
3692 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; | |
3693 | int num_lanes; | |
3694 | int i; | |
3695 | ||
3696 | static const enum dsi_lane_function functions[] = { | |
3697 | DSI_LANE_CLK, | |
3698 | DSI_LANE_DATA1, | |
3699 | DSI_LANE_DATA2, | |
3700 | DSI_LANE_DATA3, | |
3701 | DSI_LANE_DATA4, | |
3702 | }; | |
3703 | ||
3704 | num_pins = pin_cfg->num_pins; | |
3705 | pins = pin_cfg->pins; | |
3706 | ||
3707 | if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 | |
3708 | || num_pins % 2 != 0) | |
3709 | return -EINVAL; | |
3710 | ||
3711 | for (i = 0; i < DSI_MAX_NR_LANES; ++i) | |
3712 | lanes[i].function = DSI_LANE_UNUSED; | |
3713 | ||
3714 | num_lanes = 0; | |
3715 | ||
3716 | for (i = 0; i < num_pins; i += 2) { | |
3717 | u8 lane, pol; | |
3718 | int dx, dy; | |
3719 | ||
3720 | dx = pins[i]; | |
3721 | dy = pins[i + 1]; | |
3722 | ||
3723 | if (dx < 0 || dx >= dsi->num_lanes_supported * 2) | |
3724 | return -EINVAL; | |
3725 | ||
3726 | if (dy < 0 || dy >= dsi->num_lanes_supported * 2) | |
3727 | return -EINVAL; | |
3728 | ||
3729 | if (dx & 1) { | |
3730 | if (dy != dx - 1) | |
3731 | return -EINVAL; | |
3732 | pol = 1; | |
3733 | } else { | |
3734 | if (dy != dx + 1) | |
3735 | return -EINVAL; | |
3736 | pol = 0; | |
3737 | } | |
3738 | ||
3739 | lane = dx / 2; | |
3740 | ||
3741 | lanes[lane].function = functions[i / 2]; | |
3742 | lanes[lane].polarity = pol; | |
3743 | num_lanes++; | |
3744 | } | |
3745 | ||
3746 | memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); | |
3747 | dsi->num_lanes_used = num_lanes; | |
3748 | ||
3749 | return 0; | |
3750 | } | |
e4a9e94c | 3751 | |
5cfc1c3c | 3752 | static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) |
8af6ff01 | 3753 | { |
c068408e | 3754 | struct dsi_data *dsi = to_dsi_data(dssdev); |
02c3960b | 3755 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
1f68d9c4 | 3756 | struct omap_dss_device *out = &dsi->output; |
8af6ff01 AT |
3757 | u8 data_type; |
3758 | u16 word_count; | |
33ca237f | 3759 | int r; |
8af6ff01 | 3760 | |
f1504ad0 | 3761 | if (!out->dispc_channel_connected) { |
b7dec9b6 TV |
3762 | DSSERR("failed to enable display: no output/manager\n"); |
3763 | return -ENODEV; | |
3764 | } | |
3765 | ||
f81b0fd4 | 3766 | r = dsi_display_init_dispc(dsi); |
b7dec9b6 TV |
3767 | if (r) |
3768 | goto err_init_dispc; | |
3769 | ||
dca2b152 | 3770 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
02c3960b | 3771 | switch (dsi->pix_fmt) { |
9a147a65 TV |
3772 | case OMAP_DSS_DSI_FMT_RGB888: |
3773 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
3774 | break; | |
3775 | case OMAP_DSS_DSI_FMT_RGB666: | |
3776 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
3777 | break; | |
3778 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
3779 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
3780 | break; | |
3781 | case OMAP_DSS_DSI_FMT_RGB565: | |
3782 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
3783 | break; | |
3784 | default: | |
b7dec9b6 TV |
3785 | r = -EINVAL; |
3786 | goto err_pix_fmt; | |
cf6ac4ce | 3787 | } |
8af6ff01 | 3788 | |
7093d6cd LP |
3789 | dsi_if_enable(dsi, false); |
3790 | dsi_vc_enable(dsi, channel, false); | |
8af6ff01 | 3791 | |
9a147a65 | 3792 | /* MODE, 1 = video mode */ |
7093d6cd | 3793 | REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4); |
8af6ff01 | 3794 | |
da11bbbb | 3795 | word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); |
8af6ff01 | 3796 | |
7093d6cd | 3797 | dsi_vc_write_long_header(dsi, channel, data_type, |
9a147a65 | 3798 | word_count, 0); |
8af6ff01 | 3799 | |
7093d6cd LP |
3800 | dsi_vc_enable(dsi, channel, true); |
3801 | dsi_if_enable(dsi, true); | |
9a147a65 | 3802 | } |
8af6ff01 | 3803 | |
28d79f3e | 3804 | r = dss_mgr_enable(&dsi->output); |
b7dec9b6 TV |
3805 | if (r) |
3806 | goto err_mgr_enable; | |
8af6ff01 AT |
3807 | |
3808 | return 0; | |
b7dec9b6 TV |
3809 | |
3810 | err_mgr_enable: | |
3811 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
7093d6cd LP |
3812 | dsi_if_enable(dsi, false); |
3813 | dsi_vc_enable(dsi, channel, false); | |
b7dec9b6 TV |
3814 | } |
3815 | err_pix_fmt: | |
f81b0fd4 | 3816 | dsi_display_uninit_dispc(dsi); |
b7dec9b6 TV |
3817 | err_init_dispc: |
3818 | return r; | |
8af6ff01 | 3819 | } |
8af6ff01 | 3820 | |
5cfc1c3c | 3821 | static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) |
8af6ff01 | 3822 | { |
c068408e | 3823 | struct dsi_data *dsi = to_dsi_data(dssdev); |
8af6ff01 | 3824 | |
dca2b152 | 3825 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { |
7093d6cd LP |
3826 | dsi_if_enable(dsi, false); |
3827 | dsi_vc_enable(dsi, channel, false); | |
8af6ff01 | 3828 | |
9a147a65 | 3829 | /* MODE, 0 = command mode */ |
7093d6cd | 3830 | REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4); |
8af6ff01 | 3831 | |
7093d6cd LP |
3832 | dsi_vc_enable(dsi, channel, true); |
3833 | dsi_if_enable(dsi, true); | |
9a147a65 | 3834 | } |
8af6ff01 | 3835 | |
28d79f3e | 3836 | dss_mgr_disable(&dsi->output); |
b7dec9b6 | 3837 | |
f81b0fd4 | 3838 | dsi_display_uninit_dispc(dsi); |
3de7a1dc TV |
3839 | } |
3840 | ||
7093d6cd | 3841 | static void dsi_update_screen_dispc(struct dsi_data *dsi) |
3de7a1dc | 3842 | { |
d11e5c82 LP |
3843 | unsigned int bytespp; |
3844 | unsigned int bytespl; | |
3845 | unsigned int bytespf; | |
3846 | unsigned int total_len; | |
3847 | unsigned int packet_payload; | |
3848 | unsigned int packet_len; | |
3de7a1dc | 3849 | u32 l; |
0f16aa0a | 3850 | int r; |
f1da39d9 | 3851 | const unsigned channel = dsi->update_channel; |
d11e5c82 | 3852 | const unsigned int line_buf_size = dsi->line_buffer_size; |
da11bbbb PU |
3853 | u16 w = dsi->vm.hactive; |
3854 | u16 h = dsi->vm.vactive; | |
3de7a1dc | 3855 | |
5476e74a | 3856 | DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); |
3de7a1dc | 3857 | |
7093d6cd | 3858 | dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP); |
18946f62 | 3859 | |
02c3960b | 3860 | bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; |
3de7a1dc TV |
3861 | bytespl = w * bytespp; |
3862 | bytespf = bytespl * h; | |
3863 | ||
3864 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is | |
3865 | * number of lines in a packet. See errata about VP_CLK_RATIO */ | |
3866 | ||
3867 | if (bytespf < line_buf_size) | |
3868 | packet_payload = bytespf; | |
3869 | else | |
3870 | packet_payload = (line_buf_size) / bytespl * bytespl; | |
3871 | ||
3872 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ | |
3873 | total_len = (bytespf / packet_payload) * packet_len; | |
3874 | ||
3875 | if (bytespf % packet_payload) | |
3876 | total_len += (bytespf % packet_payload) + 1; | |
3877 | ||
3de7a1dc | 3878 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
7093d6cd | 3879 | dsi_write_reg(dsi, DSI_VC_TE(channel), l); |
3de7a1dc | 3880 | |
7093d6cd | 3881 | dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE, |
a72b64b9 | 3882 | packet_len, 0); |
3de7a1dc | 3883 | |
f1da39d9 | 3884 | if (dsi->te_enabled) |
3de7a1dc TV |
3885 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
3886 | else | |
3887 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ | |
7093d6cd | 3888 | dsi_write_reg(dsi, DSI_VC_TE(channel), l); |
3de7a1dc TV |
3889 | |
3890 | /* We put SIDLEMODE to no-idle for the duration of the transfer, | |
3891 | * because DSS interrupts are not capable of waking up the CPU and the | |
3892 | * framedone interrupt could be delayed for quite a long time. I think | |
3893 | * the same goes for any DSS interrupts, but for some reason I have not | |
3894 | * seen the problem anywhere else than here. | |
3895 | */ | |
8a7eda76 | 3896 | dispc_disable_sidle(dsi->dss->dispc); |
3de7a1dc | 3897 | |
7093d6cd | 3898 | dsi_perf_mark_start(dsi); |
18946f62 | 3899 | |
49dbf589 AT |
3900 | r = schedule_delayed_work(&dsi->framedone_timeout_work, |
3901 | msecs_to_jiffies(250)); | |
0f16aa0a | 3902 | BUG_ON(r == 0); |
18946f62 | 3903 | |
28d79f3e | 3904 | dss_mgr_start_update(&dsi->output); |
3de7a1dc | 3905 | |
f1da39d9 | 3906 | if (dsi->te_enabled) { |
3de7a1dc TV |
3907 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
3908 | * for TE is longer than the timer allows */ | |
7093d6cd | 3909 | REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
3de7a1dc | 3910 | |
7093d6cd | 3911 | dsi_vc_send_bta(dsi, channel); |
3de7a1dc TV |
3912 | |
3913 | #ifdef DSI_CATCH_MISSING_TE | |
f1da39d9 | 3914 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
3de7a1dc TV |
3915 | #endif |
3916 | } | |
3917 | } | |
3918 | ||
3919 | #ifdef DSI_CATCH_MISSING_TE | |
e99e88a9 | 3920 | static void dsi_te_timeout(struct timer_list *unused) |
3de7a1dc TV |
3921 | { |
3922 | DSSERR("TE not received for 250ms!\n"); | |
3923 | } | |
3924 | #endif | |
3925 | ||
7093d6cd | 3926 | static void dsi_handle_framedone(struct dsi_data *dsi, int error) |
3de7a1dc | 3927 | { |
3de7a1dc | 3928 | /* SIDLEMODE back to smart-idle */ |
8a7eda76 | 3929 | dispc_enable_sidle(dsi->dss->dispc); |
3de7a1dc | 3930 | |
f1da39d9 | 3931 | if (dsi->te_enabled) { |
18946f62 | 3932 | /* enable LP_RX_TO again after the TE */ |
7093d6cd | 3933 | REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
3de7a1dc TV |
3934 | } |
3935 | ||
f1da39d9 | 3936 | dsi->framedone_callback(error, dsi->framedone_data); |
ab83b14c TV |
3937 | |
3938 | if (!error) | |
7093d6cd | 3939 | dsi_perf_show(dsi, "DISPC"); |
18946f62 | 3940 | } |
3de7a1dc | 3941 | |
ab83b14c | 3942 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
18946f62 | 3943 | { |
f1da39d9 AT |
3944 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
3945 | framedone_timeout_work.work); | |
ab83b14c TV |
3946 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
3947 | * 250ms which would conflict with this timeout work. What should be | |
3948 | * done is first cancel the transfer on the HW, and then cancel the | |
3949 | * possibly scheduled framedone work. However, cancelling the transfer | |
3950 | * on the HW is buggy, and would probably require resetting the whole | |
3951 | * DSI */ | |
18946f62 | 3952 | |
ab83b14c | 3953 | DSSERR("Framedone not received for 250ms!\n"); |
3de7a1dc | 3954 | |
7093d6cd | 3955 | dsi_handle_framedone(dsi, -ETIMEDOUT); |
3de7a1dc TV |
3956 | } |
3957 | ||
1550202d | 3958 | static void dsi_framedone_irq_callback(void *data) |
3de7a1dc | 3959 | { |
7093d6cd | 3960 | struct dsi_data *dsi = data; |
f1da39d9 | 3961 | |
ab83b14c TV |
3962 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
3963 | * turns itself off. However, DSI still has the pixels in its buffers, | |
3964 | * and is sending the data. | |
3965 | */ | |
3de7a1dc | 3966 | |
136b5721 | 3967 | cancel_delayed_work(&dsi->framedone_timeout_work); |
3de7a1dc | 3968 | |
7093d6cd | 3969 | dsi_handle_framedone(dsi, 0); |
18946f62 | 3970 | } |
3de7a1dc | 3971 | |
5cfc1c3c | 3972 | static int dsi_update(struct omap_dss_device *dssdev, int channel, |
5476e74a | 3973 | void (*callback)(int, void *), void *data) |
18946f62 | 3974 | { |
c068408e | 3975 | struct dsi_data *dsi = to_dsi_data(dssdev); |
18946f62 | 3976 | u16 dw, dh; |
3de7a1dc | 3977 | |
7093d6cd | 3978 | dsi_perf_mark_setup(dsi); |
3de7a1dc | 3979 | |
f1da39d9 | 3980 | dsi->update_channel = channel; |
3de7a1dc | 3981 | |
4a9e78ab TV |
3982 | dsi->framedone_callback = callback; |
3983 | dsi->framedone_data = data; | |
e9c31afc | 3984 | |
da11bbbb PU |
3985 | dw = dsi->vm.hactive; |
3986 | dh = dsi->vm.vactive; | |
e9c31afc | 3987 | |
477fed70 | 3988 | #ifdef DSI_PERF_MEASURE |
5476e74a | 3989 | dsi->update_bytes = dw * dh * |
02c3960b | 3990 | dsi_get_pixel_size(dsi->pix_fmt) / 8; |
5476e74a | 3991 | #endif |
7093d6cd | 3992 | dsi_update_screen_dispc(dsi); |
3de7a1dc | 3993 | |
3de7a1dc TV |
3994 | return 0; |
3995 | } | |
3de7a1dc TV |
3996 | |
3997 | /* Display funcs */ | |
3998 | ||
7093d6cd | 3999 | static int dsi_configure_dispc_clocks(struct dsi_data *dsi) |
3de7a1dc | 4000 | { |
7d2572f8 | 4001 | struct dispc_clock_info dispc_cinfo; |
3de7a1dc | 4002 | int r; |
17518189 | 4003 | unsigned long fck; |
7d2572f8 | 4004 | |
7093d6cd | 4005 | fck = dsi_get_pll_hsdiv_dispc_rate(dsi); |
7d2572f8 | 4006 | |
a0d269ec TV |
4007 | dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; |
4008 | dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; | |
7d2572f8 | 4009 | |
8a7eda76 | 4010 | r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); |
7d2572f8 AT |
4011 | if (r) { |
4012 | DSSERR("Failed to calc dispc clocks\n"); | |
4013 | return r; | |
4014 | } | |
4015 | ||
4016 | dsi->mgr_config.clock_info = dispc_cinfo; | |
4017 | ||
4018 | return 0; | |
4019 | } | |
4020 | ||
f81b0fd4 | 4021 | static int dsi_display_init_dispc(struct dsi_data *dsi) |
7d2572f8 | 4022 | { |
f81b0fd4 | 4023 | enum omap_channel channel = dsi->output.dispc_channel; |
7d2572f8 | 4024 | int r; |
3de7a1dc | 4025 | |
8aea8e6a | 4026 | dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ? |
3b63ca75 TV |
4027 | DSS_CLK_SRC_PLL1_1 : |
4028 | DSS_CLK_SRC_PLL2_1); | |
5476e74a | 4029 | |
dca2b152 | 4030 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { |
28d79f3e | 4031 | r = dss_mgr_register_framedone_handler(&dsi->output, |
7093d6cd | 4032 | dsi_framedone_irq_callback, dsi); |
8af6ff01 | 4033 | if (r) { |
1550202d | 4034 | DSSERR("can't register FRAMEDONE handler\n"); |
7d2572f8 | 4035 | goto err; |
8af6ff01 AT |
4036 | } |
4037 | ||
7d2572f8 AT |
4038 | dsi->mgr_config.stallmode = true; |
4039 | dsi->mgr_config.fifohandcheck = true; | |
8af6ff01 | 4040 | } else { |
7d2572f8 AT |
4041 | dsi->mgr_config.stallmode = false; |
4042 | dsi->mgr_config.fifohandcheck = false; | |
3de7a1dc TV |
4043 | } |
4044 | ||
7093d6cd | 4045 | r = dsi_configure_dispc_clocks(dsi); |
7d2572f8 AT |
4046 | if (r) |
4047 | goto err1; | |
4048 | ||
4049 | dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; | |
4050 | dsi->mgr_config.video_port_width = | |
02c3960b | 4051 | dsi_get_pixel_size(dsi->pix_fmt); |
7d2572f8 AT |
4052 | dsi->mgr_config.lcden_sig_polarity = 0; |
4053 | ||
28d79f3e | 4054 | dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config); |
d21f43bc | 4055 | |
3de7a1dc | 4056 | return 0; |
7d2572f8 | 4057 | err1: |
dca2b152 | 4058 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) |
28d79f3e | 4059 | dss_mgr_unregister_framedone_handler(&dsi->output, |
7093d6cd | 4060 | dsi_framedone_irq_callback, dsi); |
7d2572f8 | 4061 | err: |
8aea8e6a | 4062 | dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); |
7d2572f8 | 4063 | return r; |
3de7a1dc TV |
4064 | } |
4065 | ||
f81b0fd4 | 4066 | static void dsi_display_uninit_dispc(struct dsi_data *dsi) |
3de7a1dc | 4067 | { |
f81b0fd4 LP |
4068 | enum omap_channel channel = dsi->output.dispc_channel; |
4069 | ||
1550202d | 4070 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) |
28d79f3e | 4071 | dss_mgr_unregister_framedone_handler(&dsi->output, |
7093d6cd | 4072 | dsi_framedone_irq_callback, dsi); |
b7dec9b6 | 4073 | |
8aea8e6a | 4074 | dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); |
3de7a1dc TV |
4075 | } |
4076 | ||
7093d6cd | 4077 | static int dsi_configure_dsi_clocks(struct dsi_data *dsi) |
3de7a1dc | 4078 | { |
2daea7af | 4079 | struct dss_pll_clock_info cinfo; |
3de7a1dc TV |
4080 | int r; |
4081 | ||
a0d269ec TV |
4082 | cinfo = dsi->user_dsi_cinfo; |
4083 | ||
2daea7af | 4084 | r = dss_pll_set_config(&dsi->pll, &cinfo); |
3de7a1dc TV |
4085 | if (r) { |
4086 | DSSERR("Failed to set dsi clocks\n"); | |
4087 | return r; | |
4088 | } | |
4089 | ||
4090 | return 0; | |
4091 | } | |
4092 | ||
7093d6cd | 4093 | static int dsi_display_init_dsi(struct dsi_data *dsi) |
3de7a1dc TV |
4094 | { |
4095 | int r; | |
4096 | ||
2daea7af | 4097 | r = dss_pll_enable(&dsi->pll); |
3de7a1dc TV |
4098 | if (r) |
4099 | goto err0; | |
4100 | ||
7093d6cd | 4101 | r = dsi_configure_dsi_clocks(dsi); |
3de7a1dc TV |
4102 | if (r) |
4103 | goto err1; | |
4104 | ||
8aea8e6a LP |
4105 | dss_select_dsi_clk_source(dsi->dss, dsi->module_id, |
4106 | dsi->module_id == 0 ? | |
4107 | DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2); | |
3de7a1dc TV |
4108 | |
4109 | DSSDBG("PLL OK\n"); | |
4110 | ||
7093d6cd | 4111 | r = dsi_cio_init(dsi); |
3de7a1dc TV |
4112 | if (r) |
4113 | goto err2; | |
4114 | ||
7093d6cd | 4115 | _dsi_print_reset_status(dsi); |
3de7a1dc | 4116 | |
7093d6cd LP |
4117 | dsi_proto_timings(dsi); |
4118 | dsi_set_lp_clk_divisor(dsi); | |
3de7a1dc TV |
4119 | |
4120 | if (1) | |
7093d6cd | 4121 | _dsi_print_reset_status(dsi); |
3de7a1dc | 4122 | |
7093d6cd | 4123 | r = dsi_proto_config(dsi); |
3de7a1dc TV |
4124 | if (r) |
4125 | goto err3; | |
4126 | ||
4127 | /* enable interface */ | |
7093d6cd LP |
4128 | dsi_vc_enable(dsi, 0, 1); |
4129 | dsi_vc_enable(dsi, 1, 1); | |
4130 | dsi_vc_enable(dsi, 2, 1); | |
4131 | dsi_vc_enable(dsi, 3, 1); | |
4132 | dsi_if_enable(dsi, 1); | |
4133 | dsi_force_tx_stop_mode_io(dsi); | |
3de7a1dc | 4134 | |
3de7a1dc | 4135 | return 0; |
3de7a1dc | 4136 | err3: |
7093d6cd | 4137 | dsi_cio_uninit(dsi); |
3de7a1dc | 4138 | err2: |
8aea8e6a | 4139 | dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); |
3de7a1dc | 4140 | err1: |
2daea7af | 4141 | dss_pll_disable(&dsi->pll); |
3de7a1dc TV |
4142 | err0: |
4143 | return r; | |
4144 | } | |
4145 | ||
7093d6cd LP |
4146 | static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes, |
4147 | bool enter_ulps) | |
3de7a1dc | 4148 | { |
f1da39d9 | 4149 | if (enter_ulps && !dsi->ulps_enabled) |
7093d6cd | 4150 | dsi_enter_ulps(dsi); |
40885ab3 | 4151 | |
d7370104 | 4152 | /* disable interface */ |
7093d6cd LP |
4153 | dsi_if_enable(dsi, 0); |
4154 | dsi_vc_enable(dsi, 0, 0); | |
4155 | dsi_vc_enable(dsi, 1, 0); | |
4156 | dsi_vc_enable(dsi, 2, 0); | |
4157 | dsi_vc_enable(dsi, 3, 0); | |
d7370104 | 4158 | |
8aea8e6a | 4159 | dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); |
7093d6cd LP |
4160 | dsi_cio_uninit(dsi); |
4161 | dsi_pll_uninit(dsi, disconnect_lanes); | |
3de7a1dc TV |
4162 | } |
4163 | ||
5cfc1c3c | 4164 | static int dsi_display_enable(struct omap_dss_device *dssdev) |
3de7a1dc | 4165 | { |
c068408e | 4166 | struct dsi_data *dsi = to_dsi_data(dssdev); |
3de7a1dc TV |
4167 | int r = 0; |
4168 | ||
4169 | DSSDBG("dsi_display_enable\n"); | |
4170 | ||
7093d6cd | 4171 | WARN_ON(!dsi_bus_is_locked(dsi)); |
37ac60e4 | 4172 | |
f1da39d9 | 4173 | mutex_lock(&dsi->lock); |
3de7a1dc | 4174 | |
7093d6cd | 4175 | r = dsi_runtime_get(dsi); |
3de7a1dc | 4176 | if (r) |
4fbafaf3 TV |
4177 | goto err_get_dsi; |
4178 | ||
7093d6cd | 4179 | _dsi_initialize_irq(dsi); |
3de7a1dc | 4180 | |
7093d6cd | 4181 | r = dsi_display_init_dsi(dsi); |
3de7a1dc | 4182 | if (r) |
4fbafaf3 | 4183 | goto err_init_dsi; |
3de7a1dc | 4184 | |
f1da39d9 | 4185 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4186 | |
4187 | return 0; | |
4188 | ||
4fbafaf3 | 4189 | err_init_dsi: |
7093d6cd | 4190 | dsi_runtime_put(dsi); |
4fbafaf3 | 4191 | err_get_dsi: |
f1da39d9 | 4192 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4193 | DSSDBG("dsi_display_enable FAILED\n"); |
4194 | return r; | |
4195 | } | |
4196 | ||
5cfc1c3c | 4197 | static void dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 4198 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4199 | { |
c068408e | 4200 | struct dsi_data *dsi = to_dsi_data(dssdev); |
a72b64b9 | 4201 | |
3de7a1dc TV |
4202 | DSSDBG("dsi_display_disable\n"); |
4203 | ||
7093d6cd | 4204 | WARN_ON(!dsi_bus_is_locked(dsi)); |
3de7a1dc | 4205 | |
f1da39d9 | 4206 | mutex_lock(&dsi->lock); |
3de7a1dc | 4207 | |
7093d6cd LP |
4208 | dsi_sync_vc(dsi, 0); |
4209 | dsi_sync_vc(dsi, 1); | |
4210 | dsi_sync_vc(dsi, 2); | |
4211 | dsi_sync_vc(dsi, 3); | |
15ffa1da | 4212 | |
7093d6cd | 4213 | dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps); |
3de7a1dc | 4214 | |
7093d6cd | 4215 | dsi_runtime_put(dsi); |
3de7a1dc | 4216 | |
f1da39d9 | 4217 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4218 | } |
4219 | ||
5cfc1c3c | 4220 | static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
3de7a1dc | 4221 | { |
c068408e | 4222 | struct dsi_data *dsi = to_dsi_data(dssdev); |
f1da39d9 AT |
4223 | |
4224 | dsi->te_enabled = enable; | |
225b650d | 4225 | return 0; |
3de7a1dc TV |
4226 | } |
4227 | ||
f1e0001f TV |
4228 | #ifdef PRINT_VERBOSE_VM_TIMINGS |
4229 | static void print_dsi_vm(const char *str, | |
4230 | const struct omap_dss_dsi_videomode_timings *t) | |
4231 | { | |
4232 | unsigned long byteclk = t->hsclk / 4; | |
4233 | int bl, wc, pps, tot; | |
4234 | ||
4235 | wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); | |
4236 | pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ | |
7e6d80dd | 4237 | bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; |
f1e0001f TV |
4238 | tot = bl + pps; |
4239 | ||
4240 | #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) | |
4241 | ||
4242 | pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " | |
4243 | "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", | |
4244 | str, | |
4245 | byteclk, | |
7e6d80dd | 4246 | t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, |
f1e0001f TV |
4247 | bl, pps, tot, |
4248 | TO_DSI_T(t->hss), | |
4249 | TO_DSI_T(t->hsa), | |
4250 | TO_DSI_T(t->hse), | |
4251 | TO_DSI_T(t->hbp), | |
4252 | TO_DSI_T(pps), | |
7e6d80dd | 4253 | TO_DSI_T(t->hfp), |
f1e0001f TV |
4254 | |
4255 | TO_DSI_T(bl), | |
4256 | TO_DSI_T(pps), | |
4257 | ||
4258 | TO_DSI_T(tot)); | |
4259 | #undef TO_DSI_T | |
4260 | } | |
4261 | ||
da11bbbb | 4262 | static void print_dispc_vm(const char *str, const struct videomode *vm) |
f1e0001f | 4263 | { |
da11bbbb | 4264 | unsigned long pck = vm->pixelclock; |
f1e0001f TV |
4265 | int hact, bl, tot; |
4266 | ||
da11bbbb | 4267 | hact = vm->hactive; |
7e6d80dd | 4268 | bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; |
f1e0001f TV |
4269 | tot = hact + bl; |
4270 | ||
4271 | #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) | |
4272 | ||
4273 | pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " | |
4274 | "%u/%u/%u/%u = %u + %u = %u\n", | |
4275 | str, | |
4276 | pck, | |
7e6d80dd | 4277 | vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, |
f1e0001f | 4278 | bl, hact, tot, |
da11bbbb | 4279 | TO_DISPC_T(vm->hsync_len), |
7e6d80dd | 4280 | TO_DISPC_T(vm->hback_porch), |
f1e0001f | 4281 | TO_DISPC_T(hact), |
da11bbbb | 4282 | TO_DISPC_T(vm->hfront_porch), |
f1e0001f TV |
4283 | TO_DISPC_T(bl), |
4284 | TO_DISPC_T(hact), | |
4285 | TO_DISPC_T(tot)); | |
4286 | #undef TO_DISPC_T | |
4287 | } | |
4288 | ||
4289 | /* note: this is not quite accurate */ | |
4290 | static void print_dsi_dispc_vm(const char *str, | |
4291 | const struct omap_dss_dsi_videomode_timings *t) | |
4292 | { | |
4520ff28 | 4293 | struct videomode vm = { 0 }; |
f1e0001f TV |
4294 | unsigned long byteclk = t->hsclk / 4; |
4295 | unsigned long pck; | |
4296 | u64 dsi_tput; | |
4297 | int dsi_hact, dsi_htot; | |
4298 | ||
4299 | dsi_tput = (u64)byteclk * t->ndl * 8; | |
4300 | pck = (u32)div64_u64(dsi_tput, t->bitspp); | |
4301 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); | |
7e6d80dd | 4302 | dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; |
f1e0001f | 4303 | |
d8d78941 | 4304 | vm.pixelclock = pck; |
4dc2250d | 4305 | vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); |
7e6d80dd NS |
4306 | vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); |
4307 | vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); | |
81899060 | 4308 | vm.hactive = t->hact; |
f1e0001f TV |
4309 | |
4310 | print_dispc_vm(str, &vm); | |
4311 | } | |
4312 | #endif /* PRINT_VERBOSE_VM_TIMINGS */ | |
4313 | ||
4314 | static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
4315 | unsigned long pck, void *data) | |
e67458a8 | 4316 | { |
f1e0001f | 4317 | struct dsi_clk_calc_ctx *ctx = data; |
da11bbbb | 4318 | struct videomode *vm = &ctx->vm; |
e67458a8 | 4319 | |
f1e0001f TV |
4320 | ctx->dispc_cinfo.lck_div = lckd; |
4321 | ctx->dispc_cinfo.pck_div = pckd; | |
4322 | ctx->dispc_cinfo.lck = lck; | |
4323 | ctx->dispc_cinfo.pck = pck; | |
e67458a8 | 4324 | |
da11bbbb PU |
4325 | *vm = *ctx->config->vm; |
4326 | vm->pixelclock = pck; | |
4327 | vm->hactive = ctx->config->vm->hactive; | |
4328 | vm->vactive = ctx->config->vm->vactive; | |
4329 | vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; | |
4330 | vm->vfront_porch = vm->vback_porch = 0; | |
e67458a8 | 4331 | |
f1e0001f | 4332 | return true; |
e67458a8 | 4333 | } |
e67458a8 | 4334 | |
2daea7af | 4335 | static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, |
f1e0001f | 4336 | void *data) |
e352574d | 4337 | { |
f1e0001f | 4338 | struct dsi_clk_calc_ctx *ctx = data; |
e352574d | 4339 | |
2daea7af | 4340 | ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; |
acf604b7 | 4341 | ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; |
e352574d | 4342 | |
8a7eda76 LP |
4343 | return dispc_div_calc(ctx->dsi->dss->dispc, dispc, |
4344 | ctx->req_pck_min, ctx->req_pck_max, | |
4345 | dsi_cm_calc_dispc_cb, ctx); | |
f1e0001f | 4346 | } |
e352574d | 4347 | |
2daea7af TV |
4348 | static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, |
4349 | unsigned long clkdco, void *data) | |
f1e0001f TV |
4350 | { |
4351 | struct dsi_clk_calc_ctx *ctx = data; | |
7093d6cd | 4352 | struct dsi_data *dsi = ctx->dsi; |
f1e0001f | 4353 | |
2daea7af TV |
4354 | ctx->dsi_cinfo.n = n; |
4355 | ctx->dsi_cinfo.m = m; | |
f1e0001f | 4356 | ctx->dsi_cinfo.fint = fint; |
2daea7af | 4357 | ctx->dsi_cinfo.clkdco = clkdco; |
f1e0001f | 4358 | |
cd0715ff | 4359 | return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, |
fe9964cb | 4360 | dsi->data->max_fck_freq, |
f1e0001f | 4361 | dsi_cm_calc_hsdiv_cb, ctx); |
e352574d | 4362 | } |
e352574d | 4363 | |
f1e0001f TV |
4364 | static bool dsi_cm_calc(struct dsi_data *dsi, |
4365 | const struct omap_dss_dsi_config *cfg, | |
4366 | struct dsi_clk_calc_ctx *ctx) | |
02c3960b | 4367 | { |
f1e0001f TV |
4368 | unsigned long clkin; |
4369 | int bitspp, ndl; | |
4370 | unsigned long pll_min, pll_max; | |
4371 | unsigned long pck, txbyteclk; | |
02c3960b | 4372 | |
2daea7af | 4373 | clkin = clk_get_rate(dsi->pll.clkin); |
f1e0001f TV |
4374 | bitspp = dsi_get_pixel_size(cfg->pixel_format); |
4375 | ndl = dsi->num_lanes_used - 1; | |
4376 | ||
4377 | /* | |
4378 | * Here we should calculate minimum txbyteclk to be able to send the | |
4379 | * frame in time, and also to handle TE. That's not very simple, though, | |
4380 | * especially as we go to LP between each pixel packet due to HW | |
4381 | * "feature". So let's just estimate very roughly and multiply by 1.5. | |
4382 | */ | |
da11bbbb | 4383 | pck = cfg->vm->pixelclock; |
f1e0001f TV |
4384 | pck = pck * 3 / 2; |
4385 | txbyteclk = pck * bitspp / 8 / ndl; | |
02c3960b | 4386 | |
f1e0001f | 4387 | memset(ctx, 0, sizeof(*ctx)); |
7093d6cd | 4388 | ctx->dsi = dsi; |
2daea7af | 4389 | ctx->pll = &dsi->pll; |
f1e0001f TV |
4390 | ctx->config = cfg; |
4391 | ctx->req_pck_min = pck; | |
4392 | ctx->req_pck_nom = pck; | |
4393 | ctx->req_pck_max = pck * 3 / 2; | |
02c3960b | 4394 | |
f1e0001f TV |
4395 | pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); |
4396 | pll_max = cfg->hs_clk_max * 4; | |
4397 | ||
cd0715ff | 4398 | return dss_pll_calc_a(ctx->pll, clkin, |
f1e0001f TV |
4399 | pll_min, pll_max, |
4400 | dsi_cm_calc_pll_cb, ctx); | |
02c3960b | 4401 | } |
02c3960b | 4402 | |
f1e0001f | 4403 | static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) |
dca2b152 | 4404 | { |
7093d6cd | 4405 | struct dsi_data *dsi = ctx->dsi; |
f1e0001f TV |
4406 | const struct omap_dss_dsi_config *cfg = ctx->config; |
4407 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
4408 | int ndl = dsi->num_lanes_used - 1; | |
4a38aede | 4409 | unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; |
f1e0001f | 4410 | unsigned long byteclk = hsclk / 4; |
dca2b152 | 4411 | |
f1e0001f TV |
4412 | unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; |
4413 | int xres; | |
4414 | int panel_htot, panel_hbl; /* pixels */ | |
4415 | int dispc_htot, dispc_hbl; /* pixels */ | |
4416 | int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ | |
4417 | int hfp, hsa, hbp; | |
4520ff28 PU |
4418 | const struct videomode *req_vm; |
4419 | struct videomode *dispc_vm; | |
f1e0001f TV |
4420 | struct omap_dss_dsi_videomode_timings *dsi_vm; |
4421 | u64 dsi_tput, dispc_tput; | |
dca2b152 | 4422 | |
f1e0001f | 4423 | dsi_tput = (u64)byteclk * ndl * 8; |
dca2b152 | 4424 | |
da11bbbb | 4425 | req_vm = cfg->vm; |
f1e0001f TV |
4426 | req_pck_min = ctx->req_pck_min; |
4427 | req_pck_max = ctx->req_pck_max; | |
4428 | req_pck_nom = ctx->req_pck_nom; | |
4429 | ||
4430 | dispc_pck = ctx->dispc_cinfo.pck; | |
4431 | dispc_tput = (u64)dispc_pck * bitspp; | |
4432 | ||
81899060 | 4433 | xres = req_vm->hactive; |
f1e0001f | 4434 | |
a85f4a80 PU |
4435 | panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + |
4436 | req_vm->hsync_len; | |
f1e0001f TV |
4437 | panel_htot = xres + panel_hbl; |
4438 | ||
4439 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); | |
4440 | ||
4441 | /* | |
4442 | * When there are no line buffers, DISPC and DSI must have the | |
4443 | * same tput. Otherwise DISPC tput needs to be higher than DSI's. | |
4444 | */ | |
4445 | if (dsi->line_buffer_size < xres * bitspp / 8) { | |
4446 | if (dispc_tput != dsi_tput) | |
4447 | return false; | |
4448 | } else { | |
4449 | if (dispc_tput < dsi_tput) | |
4450 | return false; | |
4451 | } | |
4452 | ||
4453 | /* DSI tput must be over the min requirement */ | |
4454 | if (dsi_tput < (u64)bitspp * req_pck_min) | |
4455 | return false; | |
4456 | ||
4457 | /* When non-burst mode, DSI tput must be below max requirement. */ | |
4458 | if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { | |
4459 | if (dsi_tput > (u64)bitspp * req_pck_max) | |
4460 | return false; | |
4461 | } | |
4462 | ||
4463 | hss = DIV_ROUND_UP(4, ndl); | |
4464 | ||
4465 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { | |
4dc2250d | 4466 | if (ndl == 3 && req_vm->hsync_len == 0) |
f1e0001f TV |
4467 | hse = 1; |
4468 | else | |
4469 | hse = DIV_ROUND_UP(4, ndl); | |
4470 | } else { | |
4471 | hse = 0; | |
4472 | } | |
4473 | ||
4474 | /* DSI htot to match the panel's nominal pck */ | |
4475 | dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); | |
4476 | ||
4477 | /* fail if there would be no time for blanking */ | |
4478 | if (dsi_htot < hss + hse + dsi_hact) | |
4479 | return false; | |
4480 | ||
4481 | /* total DSI blanking needed to achieve panel's TL */ | |
4482 | dsi_hbl = dsi_htot - dsi_hact; | |
4483 | ||
4484 | /* DISPC htot to match the DSI TL */ | |
4485 | dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); | |
4486 | ||
4487 | /* verify that the DSI and DISPC TLs are the same */ | |
4488 | if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) | |
4489 | return false; | |
4490 | ||
4491 | dispc_hbl = dispc_htot - xres; | |
4492 | ||
4493 | /* setup DSI videomode */ | |
4494 | ||
4495 | dsi_vm = &ctx->dsi_vm; | |
4496 | memset(dsi_vm, 0, sizeof(*dsi_vm)); | |
4497 | ||
4498 | dsi_vm->hsclk = hsclk; | |
4499 | ||
4500 | dsi_vm->ndl = ndl; | |
4501 | dsi_vm->bitspp = bitspp; | |
4502 | ||
4503 | if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { | |
4504 | hsa = 0; | |
4dc2250d | 4505 | } else if (ndl == 3 && req_vm->hsync_len == 0) { |
f1e0001f TV |
4506 | hsa = 0; |
4507 | } else { | |
4dc2250d | 4508 | hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); |
f1e0001f TV |
4509 | hsa = max(hsa - hse, 1); |
4510 | } | |
4511 | ||
a85f4a80 | 4512 | hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); |
f1e0001f TV |
4513 | hbp = max(hbp, 1); |
4514 | ||
4515 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4516 | if (hfp < 1) { | |
4517 | int t; | |
4518 | /* we need to take cycles from hbp */ | |
4519 | ||
4520 | t = 1 - hfp; | |
4521 | hbp = max(hbp - t, 1); | |
4522 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4523 | ||
4524 | if (hfp < 1 && hsa > 0) { | |
4525 | /* we need to take cycles from hsa */ | |
4526 | t = 1 - hfp; | |
4527 | hsa = max(hsa - t, 1); | |
4528 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4529 | } | |
4530 | } | |
4531 | ||
4532 | if (hfp < 1) | |
4533 | return false; | |
4534 | ||
4535 | dsi_vm->hss = hss; | |
4536 | dsi_vm->hsa = hsa; | |
4537 | dsi_vm->hse = hse; | |
4538 | dsi_vm->hbp = hbp; | |
4539 | dsi_vm->hact = xres; | |
4540 | dsi_vm->hfp = hfp; | |
4541 | ||
d5bcf0aa | 4542 | dsi_vm->vsa = req_vm->vsync_len; |
458540c6 | 4543 | dsi_vm->vbp = req_vm->vback_porch; |
fb7f3c43 | 4544 | dsi_vm->vact = req_vm->vactive; |
0996c68e | 4545 | dsi_vm->vfp = req_vm->vfront_porch; |
f1e0001f TV |
4546 | |
4547 | dsi_vm->trans_mode = cfg->trans_mode; | |
4548 | ||
4549 | dsi_vm->blanking_mode = 0; | |
4550 | dsi_vm->hsa_blanking_mode = 1; | |
4551 | dsi_vm->hfp_blanking_mode = 1; | |
4552 | dsi_vm->hbp_blanking_mode = 1; | |
4553 | ||
4554 | dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; | |
4555 | dsi_vm->window_sync = 4; | |
4556 | ||
4557 | /* setup DISPC videomode */ | |
4558 | ||
da11bbbb | 4559 | dispc_vm = &ctx->vm; |
f1e0001f | 4560 | *dispc_vm = *req_vm; |
d8d78941 | 4561 | dispc_vm->pixelclock = dispc_pck; |
f1e0001f TV |
4562 | |
4563 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { | |
4dc2250d | 4564 | hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, |
f1e0001f TV |
4565 | req_pck_nom); |
4566 | hsa = max(hsa, 1); | |
4567 | } else { | |
4568 | hsa = 1; | |
4569 | } | |
4570 | ||
a85f4a80 | 4571 | hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); |
f1e0001f TV |
4572 | hbp = max(hbp, 1); |
4573 | ||
4574 | hfp = dispc_hbl - hsa - hbp; | |
4575 | if (hfp < 1) { | |
4576 | int t; | |
4577 | /* we need to take cycles from hbp */ | |
4578 | ||
4579 | t = 1 - hfp; | |
4580 | hbp = max(hbp - t, 1); | |
4581 | hfp = dispc_hbl - hsa - hbp; | |
4582 | ||
4583 | if (hfp < 1) { | |
4584 | /* we need to take cycles from hsa */ | |
4585 | t = 1 - hfp; | |
4586 | hsa = max(hsa - t, 1); | |
4587 | hfp = dispc_hbl - hsa - hbp; | |
4588 | } | |
4589 | } | |
4590 | ||
4591 | if (hfp < 1) | |
4592 | return false; | |
4593 | ||
0a30e150 | 4594 | dispc_vm->hfront_porch = hfp; |
4dc2250d | 4595 | dispc_vm->hsync_len = hsa; |
a85f4a80 | 4596 | dispc_vm->hback_porch = hbp; |
f1e0001f TV |
4597 | |
4598 | return true; | |
4599 | } | |
4600 | ||
4601 | ||
4602 | static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
4603 | unsigned long pck, void *data) | |
4604 | { | |
4605 | struct dsi_clk_calc_ctx *ctx = data; | |
4606 | ||
4607 | ctx->dispc_cinfo.lck_div = lckd; | |
4608 | ctx->dispc_cinfo.pck_div = pckd; | |
4609 | ctx->dispc_cinfo.lck = lck; | |
4610 | ctx->dispc_cinfo.pck = pck; | |
4611 | ||
4612 | if (dsi_vm_calc_blanking(ctx) == false) | |
4613 | return false; | |
4614 | ||
4615 | #ifdef PRINT_VERBOSE_VM_TIMINGS | |
da11bbbb | 4616 | print_dispc_vm("dispc", &ctx->vm); |
f1e0001f | 4617 | print_dsi_vm("dsi ", &ctx->dsi_vm); |
da11bbbb | 4618 | print_dispc_vm("req ", ctx->config->vm); |
f1e0001f TV |
4619 | print_dsi_dispc_vm("act ", &ctx->dsi_vm); |
4620 | #endif | |
4621 | ||
4622 | return true; | |
4623 | } | |
4624 | ||
2daea7af | 4625 | static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, |
f1e0001f TV |
4626 | void *data) |
4627 | { | |
4628 | struct dsi_clk_calc_ctx *ctx = data; | |
4629 | unsigned long pck_max; | |
4630 | ||
2daea7af | 4631 | ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; |
acf604b7 | 4632 | ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; |
f1e0001f TV |
4633 | |
4634 | /* | |
4635 | * In burst mode we can let the dispc pck be arbitrarily high, but it | |
4636 | * limits our scaling abilities. So for now, don't aim too high. | |
4637 | */ | |
4638 | ||
4639 | if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) | |
4640 | pck_max = ctx->req_pck_max + 10000000; | |
4641 | else | |
4642 | pck_max = ctx->req_pck_max; | |
4643 | ||
8a7eda76 LP |
4644 | return dispc_div_calc(ctx->dsi->dss->dispc, dispc, |
4645 | ctx->req_pck_min, pck_max, | |
4646 | dsi_vm_calc_dispc_cb, ctx); | |
f1e0001f TV |
4647 | } |
4648 | ||
2daea7af TV |
4649 | static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, |
4650 | unsigned long clkdco, void *data) | |
f1e0001f TV |
4651 | { |
4652 | struct dsi_clk_calc_ctx *ctx = data; | |
7093d6cd | 4653 | struct dsi_data *dsi = ctx->dsi; |
f1e0001f | 4654 | |
2daea7af TV |
4655 | ctx->dsi_cinfo.n = n; |
4656 | ctx->dsi_cinfo.m = m; | |
f1e0001f | 4657 | ctx->dsi_cinfo.fint = fint; |
2daea7af | 4658 | ctx->dsi_cinfo.clkdco = clkdco; |
f1e0001f | 4659 | |
cd0715ff | 4660 | return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, |
fe9964cb | 4661 | dsi->data->max_fck_freq, |
f1e0001f TV |
4662 | dsi_vm_calc_hsdiv_cb, ctx); |
4663 | } | |
4664 | ||
4665 | static bool dsi_vm_calc(struct dsi_data *dsi, | |
4666 | const struct omap_dss_dsi_config *cfg, | |
4667 | struct dsi_clk_calc_ctx *ctx) | |
4668 | { | |
da11bbbb | 4669 | const struct videomode *vm = cfg->vm; |
f1e0001f TV |
4670 | unsigned long clkin; |
4671 | unsigned long pll_min; | |
4672 | unsigned long pll_max; | |
4673 | int ndl = dsi->num_lanes_used - 1; | |
4674 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
4675 | unsigned long byteclk_min; | |
4676 | ||
2daea7af | 4677 | clkin = clk_get_rate(dsi->pll.clkin); |
f1e0001f TV |
4678 | |
4679 | memset(ctx, 0, sizeof(*ctx)); | |
7093d6cd | 4680 | ctx->dsi = dsi; |
2daea7af | 4681 | ctx->pll = &dsi->pll; |
f1e0001f TV |
4682 | ctx->config = cfg; |
4683 | ||
f1e0001f | 4684 | /* these limits should come from the panel driver */ |
da11bbbb PU |
4685 | ctx->req_pck_min = vm->pixelclock - 1000; |
4686 | ctx->req_pck_nom = vm->pixelclock; | |
4687 | ctx->req_pck_max = vm->pixelclock + 1000; | |
f1e0001f TV |
4688 | |
4689 | byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); | |
4690 | pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); | |
4691 | ||
4692 | if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { | |
4693 | pll_max = cfg->hs_clk_max * 4; | |
4694 | } else { | |
4695 | unsigned long byteclk_max; | |
4696 | byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, | |
4697 | ndl * 8); | |
4698 | ||
4699 | pll_max = byteclk_max * 4 * 4; | |
4700 | } | |
4701 | ||
cd0715ff | 4702 | return dss_pll_calc_a(ctx->pll, clkin, |
f1e0001f TV |
4703 | pll_min, pll_max, |
4704 | dsi_vm_calc_pll_cb, ctx); | |
dca2b152 | 4705 | } |
dca2b152 | 4706 | |
5cfc1c3c | 4707 | static int dsi_set_config(struct omap_dss_device *dssdev, |
777f05cc | 4708 | const struct omap_dss_dsi_config *config) |
0b3ffe39 | 4709 | { |
c068408e | 4710 | struct dsi_data *dsi = to_dsi_data(dssdev); |
f1e0001f TV |
4711 | struct dsi_clk_calc_ctx ctx; |
4712 | bool ok; | |
4713 | int r; | |
0b3ffe39 AT |
4714 | |
4715 | mutex_lock(&dsi->lock); | |
4716 | ||
777f05cc TV |
4717 | dsi->pix_fmt = config->pixel_format; |
4718 | dsi->mode = config->mode; | |
e352574d | 4719 | |
f1e0001f TV |
4720 | if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) |
4721 | ok = dsi_vm_calc(dsi, config, &ctx); | |
4722 | else | |
4723 | ok = dsi_cm_calc(dsi, config, &ctx); | |
4724 | ||
4725 | if (!ok) { | |
4726 | DSSERR("failed to find suitable DSI clock settings\n"); | |
4727 | r = -EINVAL; | |
4728 | goto err; | |
4729 | } | |
4730 | ||
fe9964cb | 4731 | dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo); |
f1e0001f | 4732 | |
acf604b7 | 4733 | r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], |
7b71c410 | 4734 | config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); |
f1e0001f TV |
4735 | if (r) { |
4736 | DSSERR("failed to find suitable DSI LP clock settings\n"); | |
4737 | goto err; | |
4738 | } | |
4739 | ||
4740 | dsi->user_dsi_cinfo = ctx.dsi_cinfo; | |
4741 | dsi->user_dispc_cinfo = ctx.dispc_cinfo; | |
4742 | ||
da11bbbb | 4743 | dsi->vm = ctx.vm; |
7d39e59b LP |
4744 | |
4745 | /* | |
4746 | * override interlace, logic level and edge related parameters in | |
4747 | * videomode with default values | |
4748 | */ | |
4749 | dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; | |
4750 | dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; | |
4751 | dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; | |
4752 | dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; | |
4753 | dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; | |
4754 | ||
d8dbe791 LP |
4755 | dss_mgr_set_timings(&dsi->output, &dsi->vm); |
4756 | ||
f1e0001f | 4757 | dsi->vm_timings = ctx.dsi_vm; |
0b3ffe39 AT |
4758 | |
4759 | mutex_unlock(&dsi->lock); | |
e352574d | 4760 | |
777f05cc | 4761 | return 0; |
f1e0001f TV |
4762 | err: |
4763 | mutex_unlock(&dsi->lock); | |
4764 | ||
4765 | return r; | |
0b3ffe39 | 4766 | } |
0b3ffe39 | 4767 | |
2eea5ae6 TV |
4768 | /* |
4769 | * Return a hardcoded channel for the DSI output. This should work for | |
4770 | * current use cases, but this can be later expanded to either resolve | |
4771 | * the channel in some more dynamic manner, or get the channel as a user | |
4772 | * parameter. | |
4773 | */ | |
742e693b | 4774 | static enum omap_channel dsi_get_channel(struct dsi_data *dsi) |
2eea5ae6 | 4775 | { |
742e693b LP |
4776 | switch (dsi->data->model) { |
4777 | case DSI_MODEL_OMAP3: | |
2eea5ae6 TV |
4778 | return OMAP_DSS_CHANNEL_LCD; |
4779 | ||
742e693b LP |
4780 | case DSI_MODEL_OMAP4: |
4781 | switch (dsi->module_id) { | |
2eea5ae6 TV |
4782 | case 0: |
4783 | return OMAP_DSS_CHANNEL_LCD; | |
4784 | case 1: | |
4785 | return OMAP_DSS_CHANNEL_LCD2; | |
4786 | default: | |
4787 | DSSWARN("unsupported module id\n"); | |
4788 | return OMAP_DSS_CHANNEL_LCD; | |
4789 | } | |
4790 | ||
742e693b LP |
4791 | case DSI_MODEL_OMAP5: |
4792 | switch (dsi->module_id) { | |
2eea5ae6 TV |
4793 | case 0: |
4794 | return OMAP_DSS_CHANNEL_LCD; | |
4795 | case 1: | |
4796 | return OMAP_DSS_CHANNEL_LCD3; | |
4797 | default: | |
4798 | DSSWARN("unsupported module id\n"); | |
4799 | return OMAP_DSS_CHANNEL_LCD; | |
4800 | } | |
4801 | ||
4802 | default: | |
4803 | DSSWARN("unsupported DSS version\n"); | |
4804 | return OMAP_DSS_CHANNEL_LCD; | |
4805 | } | |
0b3ffe39 | 4806 | } |
0b3ffe39 | 4807 | |
5cfc1c3c | 4808 | static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
5ee3c144 | 4809 | { |
c068408e | 4810 | struct dsi_data *dsi = to_dsi_data(dssdev); |
5ee3c144 AT |
4811 | int i; |
4812 | ||
f1da39d9 AT |
4813 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
4814 | if (!dsi->vc[i].dssdev) { | |
4815 | dsi->vc[i].dssdev = dssdev; | |
5ee3c144 AT |
4816 | *channel = i; |
4817 | return 0; | |
4818 | } | |
4819 | } | |
4820 | ||
4821 | DSSERR("cannot get VC for display %s", dssdev->name); | |
4822 | return -ENOSPC; | |
4823 | } | |
5ee3c144 | 4824 | |
5cfc1c3c | 4825 | static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) |
5ee3c144 | 4826 | { |
c068408e | 4827 | struct dsi_data *dsi = to_dsi_data(dssdev); |
f1da39d9 | 4828 | |
5ee3c144 AT |
4829 | if (vc_id < 0 || vc_id > 3) { |
4830 | DSSERR("VC ID out of range\n"); | |
4831 | return -EINVAL; | |
4832 | } | |
4833 | ||
4834 | if (channel < 0 || channel > 3) { | |
4835 | DSSERR("Virtual Channel out of range\n"); | |
4836 | return -EINVAL; | |
4837 | } | |
4838 | ||
f1da39d9 | 4839 | if (dsi->vc[channel].dssdev != dssdev) { |
5ee3c144 AT |
4840 | DSSERR("Virtual Channel not allocated to display %s\n", |
4841 | dssdev->name); | |
4842 | return -EINVAL; | |
4843 | } | |
4844 | ||
f1da39d9 | 4845 | dsi->vc[channel].vc_id = vc_id; |
5ee3c144 AT |
4846 | |
4847 | return 0; | |
4848 | } | |
5ee3c144 | 4849 | |
5cfc1c3c | 4850 | static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) |
5ee3c144 | 4851 | { |
c068408e | 4852 | struct dsi_data *dsi = to_dsi_data(dssdev); |
f1da39d9 | 4853 | |
5ee3c144 | 4854 | if ((channel >= 0 && channel <= 3) && |
f1da39d9 AT |
4855 | dsi->vc[channel].dssdev == dssdev) { |
4856 | dsi->vc[channel].dssdev = NULL; | |
4857 | dsi->vc[channel].vc_id = 0; | |
5ee3c144 AT |
4858 | } |
4859 | } | |
5ee3c144 | 4860 | |
e406f907 | 4861 | |
7093d6cd | 4862 | static int dsi_get_clocks(struct dsi_data *dsi) |
4fbafaf3 | 4863 | { |
4fbafaf3 TV |
4864 | struct clk *clk; |
4865 | ||
4600ea9c | 4866 | clk = devm_clk_get(dsi->dev, "fck"); |
4fbafaf3 TV |
4867 | if (IS_ERR(clk)) { |
4868 | DSSERR("can't get fck\n"); | |
4869 | return PTR_ERR(clk); | |
4870 | } | |
4871 | ||
4872 | dsi->dss_clk = clk; | |
4873 | ||
4fbafaf3 TV |
4874 | return 0; |
4875 | } | |
4876 | ||
511afb44 LP |
4877 | static int dsi_connect(struct omap_dss_device *src, |
4878 | struct omap_dss_device *dst) | |
deb16df8 | 4879 | { |
deb16df8 TV |
4880 | int r; |
4881 | ||
71316556 | 4882 | r = omapdss_device_connect(dst->dss, dst, dst->next); |
43f7078f | 4883 | if (r) |
71316556 | 4884 | return r; |
deb16df8 | 4885 | |
0f37938c | 4886 | dst->dispc_channel_connected = true; |
deb16df8 TV |
4887 | return 0; |
4888 | } | |
4889 | ||
511afb44 LP |
4890 | static void dsi_disconnect(struct omap_dss_device *src, |
4891 | struct omap_dss_device *dst) | |
deb16df8 | 4892 | { |
0f37938c LP |
4893 | dst->dispc_channel_connected = false; |
4894 | ||
511afb44 | 4895 | omapdss_device_disconnect(dst, dst->next); |
deb16df8 TV |
4896 | } |
4897 | ||
b93109d7 | 4898 | static const struct omap_dss_device_ops dsi_ops = { |
deb16df8 TV |
4899 | .connect = dsi_connect, |
4900 | .disconnect = dsi_disconnect, | |
b93109d7 | 4901 | .enable = dsi_display_enable, |
deb16df8 | 4902 | |
b93109d7 LP |
4903 | .dsi = { |
4904 | .bus_lock = dsi_bus_lock, | |
4905 | .bus_unlock = dsi_bus_unlock, | |
deb16df8 | 4906 | |
b93109d7 | 4907 | .disable = dsi_display_disable, |
deb16df8 | 4908 | |
b93109d7 | 4909 | .enable_hs = dsi_vc_enable_hs, |
deb16df8 | 4910 | |
b93109d7 LP |
4911 | .configure_pins = dsi_configure_pins, |
4912 | .set_config = dsi_set_config, | |
deb16df8 | 4913 | |
b93109d7 LP |
4914 | .enable_video_output = dsi_enable_video_output, |
4915 | .disable_video_output = dsi_disable_video_output, | |
deb16df8 | 4916 | |
b93109d7 | 4917 | .update = dsi_update, |
deb16df8 | 4918 | |
b93109d7 | 4919 | .enable_te = dsi_enable_te, |
deb16df8 | 4920 | |
b93109d7 LP |
4921 | .request_vc = dsi_request_vc, |
4922 | .set_vc_id = dsi_set_vc_id, | |
4923 | .release_vc = dsi_release_vc, | |
deb16df8 | 4924 | |
b93109d7 LP |
4925 | .dcs_write = dsi_vc_dcs_write, |
4926 | .dcs_write_nosync = dsi_vc_dcs_write_nosync, | |
4927 | .dcs_read = dsi_vc_dcs_read, | |
deb16df8 | 4928 | |
b93109d7 LP |
4929 | .gen_write = dsi_vc_generic_write, |
4930 | .gen_write_nosync = dsi_vc_generic_write_nosync, | |
4931 | .gen_read = dsi_vc_generic_read, | |
deb16df8 | 4932 | |
b93109d7 | 4933 | .bta_sync = dsi_vc_send_bta_sync, |
deb16df8 | 4934 | |
b93109d7 LP |
4935 | .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, |
4936 | }, | |
deb16df8 TV |
4937 | }; |
4938 | ||
edb715df LP |
4939 | /* ----------------------------------------------------------------------------- |
4940 | * PLL | |
4941 | */ | |
6274a619 | 4942 | |
2daea7af TV |
4943 | static const struct dss_pll_ops dsi_pll_ops = { |
4944 | .enable = dsi_pll_enable, | |
4945 | .disable = dsi_pll_disable, | |
4946 | .set_config = dss_pll_write_config_type_a, | |
4947 | }; | |
4948 | ||
4949 | static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { | |
06ede3dd TV |
4950 | .type = DSS_PLL_TYPE_A, |
4951 | ||
2daea7af TV |
4952 | .n_max = (1 << 7) - 1, |
4953 | .m_max = (1 << 11) - 1, | |
4954 | .mX_max = (1 << 4) - 1, | |
4955 | .fint_min = 750000, | |
4956 | .fint_max = 2100000, | |
4957 | .clkdco_low = 1000000000, | |
4958 | .clkdco_max = 1800000000, | |
4959 | ||
4960 | .n_msb = 7, | |
4961 | .n_lsb = 1, | |
4962 | .m_msb = 18, | |
4963 | .m_lsb = 8, | |
4964 | ||
4965 | .mX_msb[0] = 22, | |
4966 | .mX_lsb[0] = 19, | |
4967 | .mX_msb[1] = 26, | |
4968 | .mX_lsb[1] = 23, | |
4969 | ||
4970 | .has_stopmode = true, | |
4971 | .has_freqsel = true, | |
4972 | .has_selfreqdco = false, | |
4973 | .has_refsel = false, | |
4974 | }; | |
4975 | ||
4976 | static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { | |
06ede3dd TV |
4977 | .type = DSS_PLL_TYPE_A, |
4978 | ||
2daea7af TV |
4979 | .n_max = (1 << 8) - 1, |
4980 | .m_max = (1 << 12) - 1, | |
4981 | .mX_max = (1 << 5) - 1, | |
4982 | .fint_min = 500000, | |
4983 | .fint_max = 2500000, | |
4984 | .clkdco_low = 1000000000, | |
4985 | .clkdco_max = 1800000000, | |
4986 | ||
4987 | .n_msb = 8, | |
4988 | .n_lsb = 1, | |
4989 | .m_msb = 20, | |
4990 | .m_lsb = 9, | |
4991 | ||
4992 | .mX_msb[0] = 25, | |
4993 | .mX_lsb[0] = 21, | |
4994 | .mX_msb[1] = 30, | |
4995 | .mX_lsb[1] = 26, | |
4996 | ||
4997 | .has_stopmode = true, | |
4998 | .has_freqsel = false, | |
4999 | .has_selfreqdco = false, | |
5000 | .has_refsel = false, | |
5001 | }; | |
5002 | ||
5003 | static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { | |
06ede3dd TV |
5004 | .type = DSS_PLL_TYPE_A, |
5005 | ||
2daea7af TV |
5006 | .n_max = (1 << 8) - 1, |
5007 | .m_max = (1 << 12) - 1, | |
5008 | .mX_max = (1 << 5) - 1, | |
5009 | .fint_min = 150000, | |
5010 | .fint_max = 52000000, | |
5011 | .clkdco_low = 1000000000, | |
5012 | .clkdco_max = 1800000000, | |
5013 | ||
5014 | .n_msb = 8, | |
5015 | .n_lsb = 1, | |
5016 | .m_msb = 20, | |
5017 | .m_lsb = 9, | |
5018 | ||
5019 | .mX_msb[0] = 25, | |
5020 | .mX_lsb[0] = 21, | |
5021 | .mX_msb[1] = 30, | |
5022 | .mX_lsb[1] = 26, | |
5023 | ||
5024 | .has_stopmode = true, | |
5025 | .has_freqsel = false, | |
5026 | .has_selfreqdco = true, | |
5027 | .has_refsel = true, | |
5028 | }; | |
5029 | ||
7093d6cd | 5030 | static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi) |
2daea7af | 5031 | { |
2daea7af TV |
5032 | struct dss_pll *pll = &dsi->pll; |
5033 | struct clk *clk; | |
5034 | int r; | |
5035 | ||
4600ea9c | 5036 | clk = devm_clk_get(dsi->dev, "sys_clk"); |
2daea7af TV |
5037 | if (IS_ERR(clk)) { |
5038 | DSSERR("can't get sys_clk\n"); | |
5039 | return PTR_ERR(clk); | |
5040 | } | |
5041 | ||
5042 | pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; | |
64e22ffd | 5043 | pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; |
2daea7af TV |
5044 | pll->clkin = clk; |
5045 | pll->base = dsi->pll_base; | |
742e693b | 5046 | pll->hw = dsi->data->pll_hw; |
2daea7af TV |
5047 | pll->ops = &dsi_pll_ops; |
5048 | ||
798957ae | 5049 | r = dss_pll_register(dss, pll); |
2daea7af TV |
5050 | if (r) |
5051 | return r; | |
5052 | ||
5053 | return 0; | |
5054 | } | |
5055 | ||
edb715df LP |
5056 | /* ----------------------------------------------------------------------------- |
5057 | * Component Bind & Unbind | |
5058 | */ | |
5059 | ||
5060 | static int dsi_bind(struct device *dev, struct device *master, void *data) | |
5061 | { | |
5062 | struct dss_device *dss = dss_get_device(master); | |
5063 | struct dsi_data *dsi = dev_get_drvdata(dev); | |
5064 | char name[10]; | |
5065 | u32 rev; | |
5066 | int r; | |
5067 | ||
5068 | dsi->dss = dss; | |
5069 | ||
5070 | dsi_init_pll_data(dss, dsi); | |
5071 | ||
5072 | r = dsi_runtime_get(dsi); | |
5073 | if (r) | |
5074 | return r; | |
5075 | ||
5076 | rev = dsi_read_reg(dsi, DSI_REVISION); | |
5077 | dev_dbg(dev, "OMAP DSI rev %d.%d\n", | |
5078 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
5079 | ||
5080 | dsi->line_buffer_size = dsi_get_line_buf_size(dsi); | |
5081 | ||
5082 | dsi_runtime_put(dsi); | |
5083 | ||
5084 | snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1); | |
5085 | dsi->debugfs.regs = dss_debugfs_create_file(dss, name, | |
4df04ac9 | 5086 | dsi_dump_dsi_regs, dsi); |
edb715df LP |
5087 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
5088 | snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1); | |
5089 | dsi->debugfs.irqs = dss_debugfs_create_file(dss, name, | |
4df04ac9 | 5090 | dsi_dump_dsi_irqs, dsi); |
edb715df LP |
5091 | #endif |
5092 | snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1); | |
5093 | dsi->debugfs.clks = dss_debugfs_create_file(dss, name, | |
4df04ac9 | 5094 | dsi_dump_dsi_clocks, dsi); |
edb715df LP |
5095 | |
5096 | return 0; | |
5097 | } | |
5098 | ||
5099 | static void dsi_unbind(struct device *dev, struct device *master, void *data) | |
5100 | { | |
5101 | struct dsi_data *dsi = dev_get_drvdata(dev); | |
5102 | ||
5103 | dss_debugfs_remove_file(dsi->debugfs.clks); | |
5104 | dss_debugfs_remove_file(dsi->debugfs.irqs); | |
5105 | dss_debugfs_remove_file(dsi->debugfs.regs); | |
5106 | ||
5107 | of_platform_depopulate(dev); | |
5108 | ||
5109 | WARN_ON(dsi->scp_clk_refcount > 0); | |
5110 | ||
5111 | dss_pll_unregister(&dsi->pll); | |
5112 | } | |
5113 | ||
5114 | static const struct component_ops dsi_component_ops = { | |
5115 | .bind = dsi_bind, | |
5116 | .unbind = dsi_unbind, | |
5117 | }; | |
5118 | ||
5119 | /* ----------------------------------------------------------------------------- | |
5120 | * Probe & Remove, Suspend & Resume | |
5121 | */ | |
5122 | ||
27d62452 | 5123 | static int dsi_init_output(struct dsi_data *dsi) |
edb715df LP |
5124 | { |
5125 | struct omap_dss_device *out = &dsi->output; | |
71316556 | 5126 | int r; |
edb715df LP |
5127 | |
5128 | out->dev = dsi->dev; | |
5129 | out->id = dsi->module_id == 0 ? | |
5130 | OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; | |
5131 | ||
5132 | out->output_type = OMAP_DISPLAY_TYPE_DSI; | |
5133 | out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; | |
5134 | out->dispc_channel = dsi_get_channel(dsi); | |
5135 | out->ops = &dsi_ops; | |
5136 | out->owner = THIS_MODULE; | |
5137 | out->of_ports = BIT(0); | |
b4935e3a LP |
5138 | out->bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE |
5139 | | DRM_BUS_FLAG_DE_HIGH | |
5140 | | DRM_BUS_FLAG_SYNC_NEGEDGE; | |
edb715df | 5141 | |
27d62452 LP |
5142 | out->next = omapdss_of_find_connected_device(out->dev->of_node, 0); |
5143 | if (IS_ERR(out->next)) { | |
5144 | if (PTR_ERR(out->next) != -EPROBE_DEFER) | |
5145 | dev_err(out->dev, "failed to find video sink\n"); | |
5146 | return PTR_ERR(out->next); | |
5147 | } | |
5148 | ||
71316556 LP |
5149 | r = omapdss_output_validate(out); |
5150 | if (r) { | |
5151 | omapdss_device_put(out->next); | |
5152 | out->next = NULL; | |
5153 | return r; | |
5154 | } | |
5155 | ||
edb715df | 5156 | omapdss_device_register(out); |
27d62452 LP |
5157 | |
5158 | return 0; | |
edb715df LP |
5159 | } |
5160 | ||
5161 | static void dsi_uninit_output(struct dsi_data *dsi) | |
5162 | { | |
5163 | struct omap_dss_device *out = &dsi->output; | |
5164 | ||
27d62452 LP |
5165 | if (out->next) |
5166 | omapdss_device_put(out->next); | |
edb715df LP |
5167 | omapdss_device_unregister(out); |
5168 | } | |
5169 | ||
5170 | static int dsi_probe_of(struct dsi_data *dsi) | |
5171 | { | |
5172 | struct device_node *node = dsi->dev->of_node; | |
5173 | struct property *prop; | |
5174 | u32 lane_arr[10]; | |
5175 | int len, num_pins; | |
5176 | int r, i; | |
5177 | struct device_node *ep; | |
5178 | struct omap_dsi_pin_config pin_cfg; | |
5179 | ||
5180 | ep = of_graph_get_endpoint_by_regs(node, 0, 0); | |
5181 | if (!ep) | |
5182 | return 0; | |
5183 | ||
5184 | prop = of_find_property(ep, "lanes", &len); | |
5185 | if (prop == NULL) { | |
5186 | dev_err(dsi->dev, "failed to find lane data\n"); | |
5187 | r = -EINVAL; | |
5188 | goto err; | |
5189 | } | |
5190 | ||
5191 | num_pins = len / sizeof(u32); | |
5192 | ||
5193 | if (num_pins < 4 || num_pins % 2 != 0 || | |
5194 | num_pins > dsi->num_lanes_supported * 2) { | |
5195 | dev_err(dsi->dev, "bad number of lanes\n"); | |
5196 | r = -EINVAL; | |
5197 | goto err; | |
5198 | } | |
5199 | ||
5200 | r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); | |
5201 | if (r) { | |
5202 | dev_err(dsi->dev, "failed to read lane data\n"); | |
5203 | goto err; | |
5204 | } | |
5205 | ||
5206 | pin_cfg.num_pins = num_pins; | |
5207 | for (i = 0; i < num_pins; ++i) | |
5208 | pin_cfg.pins[i] = (int)lane_arr[i]; | |
5209 | ||
5210 | r = dsi_configure_pins(&dsi->output, &pin_cfg); | |
5211 | if (r) { | |
5212 | dev_err(dsi->dev, "failed to configure pins"); | |
5213 | goto err; | |
5214 | } | |
5215 | ||
5216 | of_node_put(ep); | |
5217 | ||
5218 | return 0; | |
5219 | ||
5220 | err: | |
5221 | of_node_put(ep); | |
5222 | return r; | |
5223 | } | |
5224 | ||
44d8ca10 LP |
5225 | static const struct dsi_of_data dsi_of_data_omap34xx = { |
5226 | .model = DSI_MODEL_OMAP3, | |
5227 | .pll_hw = &dss_omap3_dsi_pll_hw, | |
5228 | .modules = (const struct dsi_module_id_data[]) { | |
5229 | { .address = 0x4804fc00, .id = 0, }, | |
5230 | { }, | |
5231 | }, | |
fe9964cb LP |
5232 | .max_fck_freq = 173000000, |
5233 | .max_pll_lpdiv = (1 << 13) - 1, | |
44d8ca10 LP |
5234 | .quirks = DSI_QUIRK_REVERSE_TXCLKESC, |
5235 | }; | |
5236 | ||
5237 | static const struct dsi_of_data dsi_of_data_omap36xx = { | |
5238 | .model = DSI_MODEL_OMAP3, | |
5239 | .pll_hw = &dss_omap3_dsi_pll_hw, | |
5240 | .modules = (const struct dsi_module_id_data[]) { | |
5241 | { .address = 0x4804fc00, .id = 0, }, | |
5242 | { }, | |
5243 | }, | |
fe9964cb LP |
5244 | .max_fck_freq = 173000000, |
5245 | .max_pll_lpdiv = (1 << 13) - 1, | |
44d8ca10 LP |
5246 | .quirks = DSI_QUIRK_PLL_PWR_BUG, |
5247 | }; | |
5248 | ||
5249 | static const struct dsi_of_data dsi_of_data_omap4 = { | |
5250 | .model = DSI_MODEL_OMAP4, | |
5251 | .pll_hw = &dss_omap4_dsi_pll_hw, | |
5252 | .modules = (const struct dsi_module_id_data[]) { | |
5253 | { .address = 0x58004000, .id = 0, }, | |
5254 | { .address = 0x58005000, .id = 1, }, | |
5255 | { }, | |
5256 | }, | |
fe9964cb LP |
5257 | .max_fck_freq = 170000000, |
5258 | .max_pll_lpdiv = (1 << 13) - 1, | |
44d8ca10 LP |
5259 | .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH |
5260 | | DSI_QUIRK_GNQ, | |
5261 | }; | |
5262 | ||
5263 | static const struct dsi_of_data dsi_of_data_omap5 = { | |
5264 | .model = DSI_MODEL_OMAP5, | |
5265 | .pll_hw = &dss_omap5_dsi_pll_hw, | |
5266 | .modules = (const struct dsi_module_id_data[]) { | |
5267 | { .address = 0x58004000, .id = 0, }, | |
5268 | { .address = 0x58009000, .id = 1, }, | |
5269 | { }, | |
5270 | }, | |
fe9964cb LP |
5271 | .max_fck_freq = 209250000, |
5272 | .max_pll_lpdiv = (1 << 13) - 1, | |
44d8ca10 LP |
5273 | .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH |
5274 | | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC, | |
5275 | }; | |
5276 | ||
5277 | static const struct of_device_id dsi_of_match[] = { | |
5278 | { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, }, | |
5279 | { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, }, | |
5280 | { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, }, | |
5281 | {}, | |
5282 | }; | |
5283 | ||
5284 | static const struct soc_device_attribute dsi_soc_devices[] = { | |
5285 | { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx }, | |
5286 | { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, | |
5287 | { /* sentinel */ } | |
5288 | }; | |
c7963f5f | 5289 | |
edb715df | 5290 | static int dsi_probe(struct platform_device *pdev) |
3de7a1dc | 5291 | { |
44d8ca10 | 5292 | const struct soc_device_attribute *soc; |
1dff212c | 5293 | const struct dsi_module_id_data *d; |
edb715df | 5294 | struct device *dev = &pdev->dev; |
f1da39d9 | 5295 | struct dsi_data *dsi; |
6274a619 | 5296 | struct resource *dsi_mem; |
68104467 | 5297 | struct resource *res; |
edb715df LP |
5298 | unsigned int i; |
5299 | int r; | |
f1da39d9 | 5300 | |
c7963f5f | 5301 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); |
cd3b3449 TV |
5302 | if (!dsi) |
5303 | return -ENOMEM; | |
3de7a1dc | 5304 | |
4600ea9c | 5305 | dsi->dev = dev; |
c7963f5f | 5306 | dev_set_drvdata(dev, dsi); |
a72b64b9 | 5307 | |
f1da39d9 AT |
5308 | spin_lock_init(&dsi->irq_lock); |
5309 | spin_lock_init(&dsi->errors_lock); | |
5310 | dsi->errors = 0; | |
3de7a1dc | 5311 | |
dfc0fd8d | 5312 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
f1da39d9 AT |
5313 | spin_lock_init(&dsi->irq_stats_lock); |
5314 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d TV |
5315 | #endif |
5316 | ||
f1da39d9 AT |
5317 | mutex_init(&dsi->lock); |
5318 | sema_init(&dsi->bus_lock, 1); | |
3de7a1dc | 5319 | |
203b42f7 TH |
5320 | INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, |
5321 | dsi_framedone_timeout_work_callback); | |
18946f62 | 5322 | |
3de7a1dc | 5323 | #ifdef DSI_CATCH_MISSING_TE |
e99e88a9 | 5324 | timer_setup(&dsi->te_timer, dsi_te_timeout, 0); |
3de7a1dc | 5325 | #endif |
68104467 | 5326 | |
c7963f5f LP |
5327 | dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto"); |
5328 | dsi->proto_base = devm_ioremap_resource(dev, dsi_mem); | |
b22622f0 LP |
5329 | if (IS_ERR(dsi->proto_base)) |
5330 | return PTR_ERR(dsi->proto_base); | |
68104467 | 5331 | |
c7963f5f LP |
5332 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); |
5333 | dsi->phy_base = devm_ioremap_resource(dev, res); | |
b22622f0 LP |
5334 | if (IS_ERR(dsi->phy_base)) |
5335 | return PTR_ERR(dsi->phy_base); | |
68104467 | 5336 | |
c7963f5f LP |
5337 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); |
5338 | dsi->pll_base = devm_ioremap_resource(dev, res); | |
b22622f0 LP |
5339 | if (IS_ERR(dsi->pll_base)) |
5340 | return PTR_ERR(dsi->pll_base); | |
cd3b3449 | 5341 | |
c7963f5f | 5342 | dsi->irq = platform_get_irq(pdev, 0); |
f1da39d9 | 5343 | if (dsi->irq < 0) { |
affe360d | 5344 | DSSERR("platform_get_irq failed\n"); |
cd3b3449 | 5345 | return -ENODEV; |
affe360d AT |
5346 | } |
5347 | ||
c7963f5f LP |
5348 | r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler, |
5349 | IRQF_SHARED, dev_name(dev), dsi); | |
affe360d AT |
5350 | if (r < 0) { |
5351 | DSSERR("request_irq failed\n"); | |
cd3b3449 | 5352 | return r; |
affe360d | 5353 | } |
3de7a1dc | 5354 | |
8a36357a LP |
5355 | dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd"); |
5356 | if (IS_ERR(dsi->vdds_dsi_reg)) { | |
5357 | if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER) | |
5358 | DSSERR("can't get DSI VDD regulator\n"); | |
5359 | return PTR_ERR(dsi->vdds_dsi_reg); | |
5360 | } | |
5361 | ||
44d8ca10 LP |
5362 | soc = soc_device_match(dsi_soc_devices); |
5363 | if (soc) | |
5364 | dsi->data = soc->data; | |
5365 | else | |
5366 | dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; | |
5367 | ||
742e693b | 5368 | d = dsi->data->modules; |
1dff212c LP |
5369 | while (d->address != 0 && d->address != dsi_mem->start) |
5370 | d++; | |
6274a619 | 5371 | |
1dff212c LP |
5372 | if (d->address == 0) { |
5373 | DSSERR("unsupported DSI module\n"); | |
5374 | return -ENODEV; | |
6274a619 TV |
5375 | } |
5376 | ||
1dff212c LP |
5377 | dsi->module_id = d->id; |
5378 | ||
eeb45f85 TV |
5379 | if (dsi->data->model == DSI_MODEL_OMAP4 || |
5380 | dsi->data->model == DSI_MODEL_OMAP5) { | |
9e1305d0 LP |
5381 | struct device_node *np; |
5382 | ||
5383 | /* | |
eeb45f85 | 5384 | * The OMAP4/5 display DT bindings don't reference the padconf |
9e1305d0 LP |
5385 | * syscon. Our only option to retrieve it is to find it by name. |
5386 | */ | |
eeb45f85 TV |
5387 | np = of_find_node_by_name(NULL, |
5388 | dsi->data->model == DSI_MODEL_OMAP4 ? | |
5389 | "omap4_padconf_global" : "omap5_padconf_global"); | |
9e1305d0 LP |
5390 | if (!np) |
5391 | return -ENODEV; | |
5392 | ||
5393 | dsi->syscon = syscon_node_to_regmap(np); | |
5394 | of_node_put(np); | |
5395 | } | |
5396 | ||
5ee3c144 | 5397 | /* DSI VCs initialization */ |
f1da39d9 | 5398 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
d6049144 | 5399 | dsi->vc[i].source = DSI_VC_SOURCE_L4; |
f1da39d9 AT |
5400 | dsi->vc[i].dssdev = NULL; |
5401 | dsi->vc[i].vc_id = 0; | |
5ee3c144 AT |
5402 | } |
5403 | ||
7093d6cd | 5404 | r = dsi_get_clocks(dsi); |
cd3b3449 TV |
5405 | if (r) |
5406 | return r; | |
5407 | ||
c7963f5f | 5408 | pm_runtime_enable(dev); |
cd3b3449 | 5409 | |
d9820850 TV |
5410 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number |
5411 | * of data to 3 by default */ | |
350c03e8 LP |
5412 | if (dsi->data->quirks & DSI_QUIRK_GNQ) { |
5413 | dsi_runtime_get(dsi); | |
d9820850 | 5414 | /* NB_DATA_LANES */ |
7093d6cd | 5415 | dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); |
350c03e8 LP |
5416 | dsi_runtime_put(dsi); |
5417 | } else { | |
d9820850 | 5418 | dsi->num_lanes_supported = 3; |
350c03e8 | 5419 | } |
75d7247c | 5420 | |
0a02d495 SR |
5421 | r = of_platform_populate(dev->of_node, NULL, NULL, dev); |
5422 | if (r) { | |
5423 | DSSERR("Failed to populate DSI child devices: %d\n", r); | |
5424 | goto err_pm_disable; | |
5425 | } | |
5426 | ||
27d62452 LP |
5427 | r = dsi_init_output(dsi); |
5428 | if (r) | |
0a02d495 | 5429 | goto err_of_depopulate; |
81b87f51 | 5430 | |
7093d6cd | 5431 | r = dsi_probe_of(dsi); |
1dff212c LP |
5432 | if (r) { |
5433 | DSSERR("Invalid DSI DT data\n"); | |
66aacfe2 | 5434 | goto err_uninit_output; |
6274a619 TV |
5435 | } |
5436 | ||
edb715df LP |
5437 | r = component_add(&pdev->dev, &dsi_component_ops); |
5438 | if (r) | |
0a02d495 | 5439 | goto err_uninit_output; |
6274a619 | 5440 | |
3de7a1dc | 5441 | return 0; |
4fbafaf3 | 5442 | |
66aacfe2 | 5443 | err_uninit_output: |
7093d6cd | 5444 | dsi_uninit_output(dsi); |
0a02d495 SR |
5445 | err_of_depopulate: |
5446 | of_platform_depopulate(dev); | |
27d62452 | 5447 | err_pm_disable: |
c7963f5f | 5448 | pm_runtime_disable(dev); |
3de7a1dc TV |
5449 | return r; |
5450 | } | |
5451 | ||
edb715df | 5452 | static int dsi_remove(struct platform_device *pdev) |
3de7a1dc | 5453 | { |
edb715df | 5454 | struct dsi_data *dsi = platform_get_drvdata(pdev); |
f1da39d9 | 5455 | |
edb715df | 5456 | component_del(&pdev->dev, &dsi_component_ops); |
2daea7af | 5457 | |
7093d6cd | 5458 | dsi_uninit_output(dsi); |
81b87f51 | 5459 | |
edb715df | 5460 | pm_runtime_disable(&pdev->dev); |
4fbafaf3 | 5461 | |
b2541c40 TV |
5462 | if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { |
5463 | regulator_disable(dsi->vdds_dsi_reg); | |
5464 | dsi->vdds_dsi_enabled = false; | |
c8aac01b | 5465 | } |
736e60dd | 5466 | |
c8aac01b SG |
5467 | return 0; |
5468 | } | |
5469 | ||
4fbafaf3 TV |
5470 | static int dsi_runtime_suspend(struct device *dev) |
5471 | { | |
c068408e | 5472 | struct dsi_data *dsi = dev_get_drvdata(dev); |
0925afc9 TV |
5473 | |
5474 | dsi->is_enabled = false; | |
5475 | /* ensure the irq handler sees the is_enabled value */ | |
5476 | smp_wmb(); | |
5477 | /* wait for current handler to finish before turning the DSI off */ | |
5478 | synchronize_irq(dsi->irq); | |
5479 | ||
4fbafaf3 TV |
5480 | return 0; |
5481 | } | |
5482 | ||
5483 | static int dsi_runtime_resume(struct device *dev) | |
5484 | { | |
c068408e | 5485 | struct dsi_data *dsi = dev_get_drvdata(dev); |
4fbafaf3 | 5486 | |
0925afc9 TV |
5487 | dsi->is_enabled = true; |
5488 | /* ensure the irq handler sees the is_enabled value */ | |
5489 | smp_wmb(); | |
5490 | ||
4fbafaf3 | 5491 | return 0; |
4fbafaf3 TV |
5492 | } |
5493 | ||
5494 | static const struct dev_pm_ops dsi_pm_ops = { | |
5495 | .runtime_suspend = dsi_runtime_suspend, | |
5496 | .runtime_resume = dsi_runtime_resume, | |
5497 | }; | |
5498 | ||
d66c36a3 | 5499 | struct platform_driver omap_dsihw_driver = { |
736e60dd TV |
5500 | .probe = dsi_probe, |
5501 | .remove = dsi_remove, | |
c8aac01b | 5502 | .driver = { |
7c68dd96 | 5503 | .name = "omapdss_dsi", |
4fbafaf3 | 5504 | .pm = &dsi_pm_ops, |
6274a619 | 5505 | .of_match_table = dsi_of_match, |
422ccbd5 | 5506 | .suppress_bind_attrs = true, |
c8aac01b SG |
5507 | }, |
5508 | }; |