[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / omapdrm / dss / dss.h

/*
 * linux/drivers/video/omap2/dss/dss.h
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __OMAP2_DSS_H
#define __OMAP2_DSS_H

#include <linux/interrupt.h>

#include "omapdss.h"

#ifdef pr_fmt
#undef pr_fmt
#endif

#ifdef DSS_SUBSYS_NAME
#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
#else
#define pr_fmt(fmt) fmt
#endif

#define DSSDBG(format, ...) \
	pr_debug(format, ## __VA_ARGS__)

#ifdef DSS_SUBSYS_NAME
#define DSSERR(format, ...) \
	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
	## __VA_ARGS__)
#else
#define DSSERR(format, ...) \
	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSINFO(format, ...) \
	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
	## __VA_ARGS__)
#else
#define DSSINFO(format, ...) \
	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSWARN(format, ...) \
	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
	## __VA_ARGS__)
#else
#define DSSWARN(format, ...) \
	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
#endif

/* OMAP TRM gives bitfields as start:end, where start is the higher bit
   number. For example 7:0 */
#define FLD_MASK(start, end)	(((1 << ((start) - (end) + 1)) - 1) << (end))
#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
#define FLD_MOD(orig, val, start, end) \
	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))

enum dss_io_pad_mode {
	DSS_IO_PAD_MODE_RESET,
	DSS_IO_PAD_MODE_RFBI,
	DSS_IO_PAD_MODE_BYPASS,
};

enum dss_hdmi_venc_clk_source_select {
	DSS_VENC_TV_CLK = 0,
	DSS_HDMI_M_PCLK = 1,
};

enum dss_dsi_content_type {
	DSS_DSI_CONTENT_DCS,
	DSS_DSI_CONTENT_GENERIC,
};

enum dss_writeback_channel {
	DSS_WB_LCD1_MGR =	0,
	DSS_WB_LCD2_MGR =	1,
	DSS_WB_TV_MGR =		2,
	DSS_WB_OVL0 =		3,
	DSS_WB_OVL1 =		4,
	DSS_WB_OVL2 =		5,
	DSS_WB_OVL3 =		6,
	DSS_WB_LCD3_MGR =	7,
};

enum dss_clk_source {
	DSS_CLK_SRC_FCK = 0,

	DSS_CLK_SRC_PLL1_1,
	DSS_CLK_SRC_PLL1_2,
	DSS_CLK_SRC_PLL1_3,

	DSS_CLK_SRC_PLL2_1,
	DSS_CLK_SRC_PLL2_2,
	DSS_CLK_SRC_PLL2_3,

	DSS_CLK_SRC_HDMI_PLL,
};

enum dss_pll_id {
	DSS_PLL_DSI1,
	DSS_PLL_DSI2,
	DSS_PLL_HDMI,
	DSS_PLL_VIDEO1,
	DSS_PLL_VIDEO2,
};

struct dss_pll;

#define DSS_PLL_MAX_HSDIVS 4

enum dss_pll_type {
	DSS_PLL_TYPE_A,
	DSS_PLL_TYPE_B,
};

/*
 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
 * Type-B PLLs: clkout[0] refers to m2.
 */
struct dss_pll_clock_info {
	/* rates that we get with dividers below */
	unsigned long fint;
	unsigned long clkdco;
	unsigned long clkout[DSS_PLL_MAX_HSDIVS];

	/* dividers */
	u16 n;
	u16 m;
	u32 mf;
	u16 mX[DSS_PLL_MAX_HSDIVS];
	u16 sd;
};

struct dss_pll_ops {
	int (*enable)(struct dss_pll *pll);
	void (*disable)(struct dss_pll *pll);
	int (*set_config)(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
};

struct dss_pll_hw {
	enum dss_pll_type type;

	unsigned n_max;
	unsigned m_min;
	unsigned m_max;
	unsigned mX_max;

	unsigned long fint_min, fint_max;
	unsigned long clkdco_min, clkdco_low, clkdco_max;

	u8 n_msb, n_lsb;
	u8 m_msb, m_lsb;
	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];

	bool has_stopmode;
	bool has_freqsel;
	bool has_selfreqdco;
	bool has_refsel;
};

struct dss_pll {
	const char *name;
	enum dss_pll_id id;

	struct clk *clkin;
	struct regulator *regulator;

	void __iomem *base;

	const struct dss_pll_hw *hw;

	const struct dss_pll_ops *ops;

	struct dss_pll_clock_info cinfo;
};

struct dispc_clock_info {
	/* rates that we get with dividers below */
	unsigned long lck;
	unsigned long pck;

	/* dividers */
	u16 lck_div;
	u16 pck_div;
};

struct dss_lcd_mgr_config {
	enum dss_io_pad_mode io_pad_mode;

	bool stallmode;
	bool fifohandcheck;

	struct dispc_clock_info clock_info;

	int video_port_width;

	int lcden_sig_polarity;
};

struct seq_file;
struct platform_device;

/* core */
struct platform_device *dss_get_core_pdev(void);
int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));

static inline bool dss_mgr_is_lcd(enum omap_channel id)
{
	if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
			id == OMAP_DSS_CHANNEL_LCD3)
		return true;
	else
		return false;
}

/* DSS */
int dss_init_platform_driver(void) __init;
void dss_uninit_platform_driver(void);

int dss_runtime_get(void);
void dss_runtime_put(void);

unsigned long dss_get_dispc_clk_rate(void);
int dss_dpi_select_source(int port, enum omap_channel channel);
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
void dss_dump_clocks(struct seq_file *s);

/* DSS VIDEO PLL */
struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
	struct regulator *regulator);
void dss_video_pll_uninit(struct dss_pll *pll);

/* dss-of */
struct device_node *dss_of_port_get_parent_device(struct device_node *port);
u32 dss_of_port_get_port_number(struct device_node *port);

#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
void dss_debug_dump_clocks(struct seq_file *s);
#endif

void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);

void dss_sdi_init(int datapairs);
int dss_sdi_enable(void);
void dss_sdi_disable(void);

void dss_select_dsi_clk_source(int dsi_module,
		enum dss_clk_source clk_src);
void dss_select_lcd_clk_source(enum omap_channel channel,
		enum dss_clk_source clk_src);
enum dss_clk_source dss_get_dispc_clk_source(void);
enum dss_clk_source dss_get_dsi_clk_source(int dsi_module);
enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);

void dss_set_venc_output(enum omap_dss_venc_type type);
void dss_set_dac_pwrdn_bgz(bool enable);

int dss_set_fck_rate(unsigned long rate);

typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
bool dss_div_calc(unsigned long pck, unsigned long fck_min,
		dss_div_calc_func func, void *data);

/* SDI */
int sdi_init_platform_driver(void) __init;
void sdi_uninit_platform_driver(void);

#ifdef CONFIG_OMAP2_DSS_SDI
int sdi_init_port(struct platform_device *pdev, struct device_node *port);
void sdi_uninit_port(struct device_node *port);
#else
static inline int sdi_init_port(struct platform_device *pdev,
		struct device_node *port)
{
	return 0;
}
static inline void sdi_uninit_port(struct device_node *port)
{
}
#endif

/* DSI */

#ifdef CONFIG_OMAP2_DSS_DSI

struct dentry;
struct file_operations;

int dsi_init_platform_driver(void) __init;
void dsi_uninit_platform_driver(void);

void dsi_dump_clocks(struct seq_file *s);

void dsi_irq_handler(void);
u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);

#else
static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
{
	WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
	     __func__);
	return 0;
}
#endif

/* DPI */
int dpi_init_platform_driver(void) __init;
void dpi_uninit_platform_driver(void);

#ifdef CONFIG_OMAP2_DSS_DPI
int dpi_init_port(struct platform_device *pdev, struct device_node *port);
void dpi_uninit_port(struct device_node *port);
#else
static inline int dpi_init_port(struct platform_device *pdev,
		struct device_node *port)
{
	return 0;
}
static inline void dpi_uninit_port(struct device_node *port)
{
}
#endif

/* DISPC */
int dispc_init_platform_driver(void) __init;
void dispc_uninit_platform_driver(void);
void dispc_dump_clocks(struct seq_file *s);

void dispc_enable_sidle(void);
void dispc_disable_sidle(void);

void dispc_lcd_enable_signal(bool enable);
void dispc_pck_free_enable(bool enable);
void dispc_enable_fifomerge(bool enable);
void dispc_enable_gamma_table(bool enable);

typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
		unsigned long pck, void *data);
bool dispc_div_calc(unsigned long dispc,
		unsigned long pck_min, unsigned long pck_max,
		dispc_div_calc_func func, void *data);

bool dispc_mgr_timings_ok(enum omap_channel channel,
		const struct omap_video_timings *timings);
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
		struct dispc_clock_info *cinfo);


void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
		u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
		bool manual_update);

void dispc_mgr_set_clock_div(enum omap_channel channel,
		const struct dispc_clock_info *cinfo);
int dispc_mgr_get_clock_div(enum omap_channel channel,
		struct dispc_clock_info *cinfo);
void dispc_set_tv_pclk(unsigned long pclk);

u32 dispc_wb_get_framedone_irq(void);
bool dispc_wb_go_busy(void);
void dispc_wb_go(void);
void dispc_wb_enable(bool enable);
bool dispc_wb_is_enabled(void);
void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
		bool mem_to_mem, const struct omap_video_timings *timings);

/* VENC */
int venc_init_platform_driver(void) __init;
void venc_uninit_platform_driver(void);

/* HDMI */
int hdmi4_init_platform_driver(void) __init;
void hdmi4_uninit_platform_driver(void);

int hdmi5_init_platform_driver(void) __init;
void hdmi5_uninit_platform_driver(void);

/* RFBI */
int rfbi_init_platform_driver(void) __init;
void rfbi_uninit_platform_driver(void);


#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
{
	int b;
	for (b = 0; b < 32; ++b) {
		if (irqstatus & (1 << b))
			irq_arr[b]++;
	}
}
#endif

/* PLL */
typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
		unsigned long clkdco, void *data);
typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
		void *data);

int dss_pll_register(struct dss_pll *pll);
void dss_pll_unregister(struct dss_pll *pll);
struct dss_pll *dss_pll_find(const char *name);
struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src);
unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
int dss_pll_enable(struct dss_pll *pll);
void dss_pll_disable(struct dss_pll *pll);
int dss_pll_set_config(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);

bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
		unsigned long out_min, unsigned long out_max,
		dss_hsdiv_calc_func func, void *data);
bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
		unsigned long pll_min, unsigned long pll_max,
		dss_pll_calc_func func, void *data);

bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
	unsigned long target_clkout, struct dss_pll_clock_info *cinfo);

int dss_pll_write_config_type_a(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
int dss_pll_write_config_type_b(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
int dss_pll_wait_reset_done(struct dss_pll *pll);

#endif
Commit	Line	Data
559d6701 TV	1	/*
	2	* linux/drivers/video/omap2/dss/dss.h
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	6	*
	7	* Some code and ideas taken from drivers/video/omap/ driver
	8	* by Imre Deak.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#ifndef __OMAP2_DSS_H
	24	#define __OMAP2_DSS_H
	25
96e2e637 TV	26	#include <linux/interrupt.h>
96e2e637 TV	27
35a339ac TV	28	#include "omapdss.h"
35a339ac TV	29
702d267e CM	30	#ifdef pr_fmt
702d267e CM	31	#undef pr_fmt
559d6701 TV	32	#endif
559d6701 TV	33
702d267e CM	34	#ifdef DSS_SUBSYS_NAME
	35	#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
	36	#else
	37	#define pr_fmt(fmt) fmt
559d6701 TV	38	#endif
559d6701 TV	39
702d267e CM	40	#define DSSDBG(format, ...) \
702d267e CM	41	pr_debug(format, ## __VA_ARGS__)
559d6701 TV	42
	43	#ifdef DSS_SUBSYS_NAME
	44	#define DSSERR(format, ...) \
	45	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
	46	## __VA_ARGS__)
	47	#else
	48	#define DSSERR(format, ...) \
	49	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
	50	#endif
	51
	52	#ifdef DSS_SUBSYS_NAME
	53	#define DSSINFO(format, ...) \
	54	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
	55	## __VA_ARGS__)
	56	#else
	57	#define DSSINFO(format, ...) \
	58	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
	59	#endif
	60
	61	#ifdef DSS_SUBSYS_NAME
	62	#define DSSWARN(format, ...) \
	63	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
	64	## __VA_ARGS__)
	65	#else
	66	#define DSSWARN(format, ...) \
	67	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
	68	#endif
	69
	70	/* OMAP TRM gives bitfields as start:end, where start is the higher bit
	71	number. For example 7:0 */
	72	#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
	73	#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
	74	#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
	75	#define FLD_MOD(orig, val, start, end) \
	76	(((orig) & ~FLD_MASK(start, end)) \| FLD_VAL(val, start, end))
	77
569969d6 AT	78	enum dss_io_pad_mode {
	79	DSS_IO_PAD_MODE_RESET,
	80	DSS_IO_PAD_MODE_RFBI,
	81	DSS_IO_PAD_MODE_BYPASS,
559d6701 TV	82	};
559d6701 TV	83
7ed024aa M	84	enum dss_hdmi_venc_clk_source_select {
	85	DSS_VENC_TV_CLK = 0,
	86	DSS_HDMI_M_PCLK = 1,
	87	};
	88
6ff8aa31 AT	89	enum dss_dsi_content_type {
	90	DSS_DSI_CONTENT_DCS,
	91	DSS_DSI_CONTENT_GENERIC,
	92	};
	93
d9ac773c AT	94	enum dss_writeback_channel {
	95	DSS_WB_LCD1_MGR = 0,
	96	DSS_WB_LCD2_MGR = 1,
	97	DSS_WB_TV_MGR = 2,
	98	DSS_WB_OVL0 = 3,
	99	DSS_WB_OVL1 = 4,
	100	DSS_WB_OVL2 = 5,
	101	DSS_WB_OVL3 = 6,
	102	DSS_WB_LCD3_MGR = 7,
	103	};
	104
dc0352d1	105	enum dss_clk_source {
3b63ca75 TV	106	DSS_CLK_SRC_FCK = 0,
	107
	108	DSS_CLK_SRC_PLL1_1,
	109	DSS_CLK_SRC_PLL1_2,
b5d8c757	110	DSS_CLK_SRC_PLL1_3,
3b63ca75 TV	111
	112	DSS_CLK_SRC_PLL2_1,
	113	DSS_CLK_SRC_PLL2_2,
b5d8c757 TV	114	DSS_CLK_SRC_PLL2_3,
	115
	116	DSS_CLK_SRC_HDMI_PLL,
be5d7319 TV	117	};
be5d7319 TV	118
64e22ffd TV	119	enum dss_pll_id {
	120	DSS_PLL_DSI1,
	121	DSS_PLL_DSI2,
	122	DSS_PLL_HDMI,
6d817880 TV	123	DSS_PLL_VIDEO1,
6d817880 TV	124	DSS_PLL_VIDEO2,
64e22ffd TV	125	};
64e22ffd TV	126
0a20170a TV	127	struct dss_pll;
	128
	129	#define DSS_PLL_MAX_HSDIVS 4
	130
06ede3dd TV	131	enum dss_pll_type {
	132	DSS_PLL_TYPE_A,
	133	DSS_PLL_TYPE_B,
	134	};
	135
0a20170a TV	136	/*
	137	* Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
	138	* Type-B PLLs: clkout[0] refers to m2.
	139	*/
	140	struct dss_pll_clock_info {
	141	/* rates that we get with dividers below */
	142	unsigned long fint;
	143	unsigned long clkdco;
	144	unsigned long clkout[DSS_PLL_MAX_HSDIVS];
	145
	146	/* dividers */
	147	u16 n;
	148	u16 m;
	149	u32 mf;
	150	u16 mX[DSS_PLL_MAX_HSDIVS];
	151	u16 sd;
	152	};
	153
	154	struct dss_pll_ops {
	155	int (enable)(struct dss_pll pll);
	156	void (disable)(struct dss_pll pll);
	157	int (set_config)(struct dss_pll pll,
	158	const struct dss_pll_clock_info *cinfo);
	159	};
	160
	161	struct dss_pll_hw {
06ede3dd TV	162	enum dss_pll_type type;
06ede3dd TV	163
0a20170a TV	164	unsigned n_max;
	165	unsigned m_min;
	166	unsigned m_max;
	167	unsigned mX_max;
	168
	169	unsigned long fint_min, fint_max;
	170	unsigned long clkdco_min, clkdco_low, clkdco_max;
	171
	172	u8 n_msb, n_lsb;
	173	u8 m_msb, m_lsb;
	174	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
	175
	176	bool has_stopmode;
	177	bool has_freqsel;
	178	bool has_selfreqdco;
	179	bool has_refsel;
	180	};
	181
	182	struct dss_pll {
	183	const char *name;
64e22ffd	184	enum dss_pll_id id;
0a20170a TV	185
	186	struct clk *clkin;
	187	struct regulator *regulator;
	188
	189	void __iomem *base;
	190
	191	const struct dss_pll_hw *hw;
	192
	193	const struct dss_pll_ops *ops;
	194
	195	struct dss_pll_clock_info cinfo;
	196	};
	197
559d6701 TV	198	struct dispc_clock_info {
	199	/* rates that we get with dividers below */
	200	unsigned long lck;
	201	unsigned long pck;
	202
	203	/* dividers */
	204	u16 lck_div;
	205	u16 pck_div;
	206	};
	207
c56fb3ef AT	208	struct dss_lcd_mgr_config {
	209	enum dss_io_pad_mode io_pad_mode;
	210
	211	bool stallmode;
	212	bool fifohandcheck;
	213
	214	struct dispc_clock_info clock_info;
	215
	216	int video_port_width;
	217
	218	int lcden_sig_polarity;
	219	};
	220
559d6701 TV	221	struct seq_file;
	222	struct platform_device;
	223
	224	/* core */
8f46efad	225	struct platform_device *dss_get_core_pdev(void);
00928eaf TV	226	int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
00928eaf TV	227	void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
a8081d31	228	int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
e40402cf	229	int dss_debugfs_create_file(const char name, void (write)(struct seq_file *));
559d6701	230
f476ae9d AT	231	static inline bool dss_mgr_is_lcd(enum omap_channel id)
	232	{
	233	if (id == OMAP_DSS_CHANNEL_LCD \|\| id == OMAP_DSS_CHANNEL_LCD2 \|\|
	234	id == OMAP_DSS_CHANNEL_LCD3)
	235	return true;
	236	else
	237	return false;
	238	}
	239
559d6701	240	/* DSS */
6e7e8f06	241	int dss_init_platform_driver(void) __init;
96c401bc	242	void dss_uninit_platform_driver(void);
559d6701	243
99767548 TV	244	int dss_runtime_get(void);
	245	void dss_runtime_put(void);
	246
5aaee69d	247	unsigned long dss_get_dispc_clk_rate(void);
064c2a47	248	int dss_dpi_select_source(int port, enum omap_channel channel);
7ed024aa	249	void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
4a61e267	250	enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
407bd564	251	const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
8b9cb3a8	252	void dss_dump_clocks(struct seq_file *s);
559d6701	253
99767548 TV	254	/* DSS VIDEO PLL */
	255	struct dss_pll dss_video_pll_init(struct platform_device pdev, int id,
	256	struct regulator *regulator);
	257	void dss_video_pll_uninit(struct dss_pll *pll);
	258
ef691ff4 AT	259	/* dss-of */
	260	struct device_node dss_of_port_get_parent_device(struct device_node port);
	261	u32 dss_of_port_get_port_number(struct device_node *port);
	262
1b3bcb33	263	#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
8b9cb3a8 SG	264	void dss_debug_dump_clocks(struct seq_file *s);
8b9cb3a8 SG	265	#endif
559d6701	266
be40eecf	267	void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
be40eecf	268
889b4fd7	269	void dss_sdi_init(int datapairs);
559d6701 TV	270	int dss_sdi_enable(void);
	271	void dss_sdi_disable(void);
	272
5a8b572d	273	void dss_select_dsi_clk_source(int dsi_module,
dc0352d1	274	enum dss_clk_source clk_src);
ea75159e	275	void dss_select_lcd_clk_source(enum omap_channel channel,
dc0352d1 TV	276	enum dss_clk_source clk_src);
	277	enum dss_clk_source dss_get_dispc_clk_source(void);
	278	enum dss_clk_source dss_get_dsi_clk_source(int dsi_module);
	279	enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
2f18c4d8	280
559d6701 TV	281	void dss_set_venc_output(enum omap_dss_venc_type type);
	282	void dss_set_dac_pwrdn_bgz(bool enable);
	283
d0f58bd3	284	int dss_set_fck_rate(unsigned long rate);
559d6701	285
d0f58bd3	286	typedef bool (dss_div_calc_func)(unsigned long fck, void data);
688af02d TV	287	bool dss_div_calc(unsigned long pck, unsigned long fck_min,
688af02d TV	288	dss_div_calc_func func, void *data);
43417823	289
559d6701	290	/* SDI */
6e7e8f06	291	int sdi_init_platform_driver(void) __init;
ede92695	292	void sdi_uninit_platform_driver(void);
559d6701	293
387ce9f2	294	#ifdef CONFIG_OMAP2_DSS_SDI
ede92695 TV	295	int sdi_init_port(struct platform_device pdev, struct device_node port);
ede92695 TV	296	void sdi_uninit_port(struct device_node *port);
387ce9f2	297	#else
ede92695	298	static inline int sdi_init_port(struct platform_device *pdev,
387ce9f2 AT	299	struct device_node *port)
	300	{
	301	return 0;
	302	}
ede92695	303	static inline void sdi_uninit_port(struct device_node *port)
387ce9f2 AT	304	{
	305	}
	306	#endif
2ecef246	307
559d6701	308	/* DSI */
989c79a8	309
368a148e	310	#ifdef CONFIG_OMAP2_DSS_DSI
5a8b572d AT	311
	312	struct dentry;
	313	struct file_operations;
	314
6e7e8f06	315	int dsi_init_platform_driver(void) __init;
ede92695	316	void dsi_uninit_platform_driver(void);
559d6701 TV	317
559d6701 TV	318	void dsi_dump_clocks(struct seq_file *s);
559d6701	319
559d6701	320	void dsi_irq_handler(void);
a3b3cc2b AT	321	u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
a3b3cc2b AT	322
368a148e	323	#else
a3b3cc2b AT	324	static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
a3b3cc2b AT	325	{
85d90b12 DC	326	WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
85d90b12 DC	327	__func__);
a3b3cc2b AT	328	return 0;
a3b3cc2b AT	329	}
368a148e	330	#endif
559d6701 TV	331
559d6701 TV	332	/* DPI */
6e7e8f06	333	int dpi_init_platform_driver(void) __init;
ede92695	334	void dpi_uninit_platform_driver(void);
559d6701	335
387ce9f2	336	#ifdef CONFIG_OMAP2_DSS_DPI
ede92695 TV	337	int dpi_init_port(struct platform_device pdev, struct device_node port);
ede92695 TV	338	void dpi_uninit_port(struct device_node *port);
387ce9f2	339	#else
ede92695	340	static inline int dpi_init_port(struct platform_device *pdev,
387ce9f2 AT	341	struct device_node *port)
	342	{
	343	return 0;
	344	}
ede92695	345	static inline void dpi_uninit_port(struct device_node *port)
387ce9f2 AT	346	{
	347	}
	348	#endif
2ecef246	349
559d6701	350	/* DISPC */
6e7e8f06	351	int dispc_init_platform_driver(void) __init;
ede92695	352	void dispc_uninit_platform_driver(void);
559d6701	353	void dispc_dump_clocks(struct seq_file *s);
559d6701 TV	354
	355	void dispc_enable_sidle(void);
	356	void dispc_disable_sidle(void);
	357
559d6701 TV	358	void dispc_lcd_enable_signal(bool enable);
559d6701 TV	359	void dispc_pck_free_enable(bool enable);
cd295aeb TV	360	void dispc_enable_fifomerge(bool enable);
cd295aeb TV	361	void dispc_enable_gamma_table(bool enable);
cd295aeb	362
7c284e6e TV	363	typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
	364	unsigned long pck, void *data);
	365	bool dispc_div_calc(unsigned long dispc,
	366	unsigned long pck_min, unsigned long pck_max,
	367	dispc_div_calc_func func, void *data);
	368
8f366162	369	bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39	370	const struct omap_video_timings *timings);
cd295aeb TV	371	int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
	372	struct dispc_clock_info *cinfo);
	373
	374
6f04e1bf	375	void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
83fa2f2e	376	void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4 TV	377	u32 fifo_low, u32 fifo_high, bool use_fifomerge,
3568f2a4 TV	378	bool manual_update);
348be69d	379
f0d08f89	380	void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1	381	const struct dispc_clock_info *cinfo);
26d9dd0d	382	int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde	383	struct dispc_clock_info *cinfo);
5391e87d	384	void dispc_set_tv_pclk(unsigned long pclk);
559d6701	385
0b23e5b8 AT	386	u32 dispc_wb_get_framedone_irq(void);
	387	bool dispc_wb_go_busy(void);
	388	void dispc_wb_go(void);
	389	void dispc_wb_enable(bool enable);
	390	bool dispc_wb_is_enabled(void);
d9ac773c	391	void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
749feffa	392	int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7	393	bool mem_to_mem, const struct omap_video_timings *timings);
d9ac773c	394
559d6701	395	/* VENC */
6e7e8f06	396	int venc_init_platform_driver(void) __init;
ede92695	397	void venc_uninit_platform_driver(void);
559d6701	398
c3198a5e	399	/* HDMI */
ef26958a	400	int hdmi4_init_platform_driver(void) __init;
ede92695	401	void hdmi4_uninit_platform_driver(void);
c3198a5e	402
f5bab222	403	int hdmi5_init_platform_driver(void) __init;
ede92695	404	void hdmi5_uninit_platform_driver(void);
f5bab222	405
559d6701	406	/* RFBI */
6e7e8f06	407	int rfbi_init_platform_driver(void) __init;
ede92695	408	void rfbi_uninit_platform_driver(void);
559d6701	409
dfc0fd8d TV	410
	411	#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
	412	static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
	413	{
	414	int b;
	415	for (b = 0; b < 32; ++b) {
	416	if (irqstatus & (1 << b))
	417	irq_arr[b]++;
	418	}
	419	}
	420	#endif
	421
0a20170a TV	422	/* PLL */
	423	typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
	424	unsigned long clkdco, void *data);
	425	typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
	426	void *data);
	427
	428	int dss_pll_register(struct dss_pll *pll);
	429	void dss_pll_unregister(struct dss_pll *pll);
	430	struct dss_pll dss_pll_find(const char name);
5670bd72 TV	431	struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src);
5670bd72 TV	432	unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
0a20170a TV	433	int dss_pll_enable(struct dss_pll *pll);
	434	void dss_pll_disable(struct dss_pll *pll);
	435	int dss_pll_set_config(struct dss_pll *pll,
	436	const struct dss_pll_clock_info *cinfo);
	437
cd0715ff	438	bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
0a20170a TV	439	unsigned long out_min, unsigned long out_max,
0a20170a TV	440	dss_hsdiv_calc_func func, void *data);
cd0715ff	441	bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
0a20170a TV	442	unsigned long pll_min, unsigned long pll_max,
0a20170a TV	443	dss_pll_calc_func func, void *data);
c17dc0e3 TV	444
c17dc0e3 TV	445	bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
c107751d	446	unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
c17dc0e3	447
0a20170a TV	448	int dss_pll_write_config_type_a(struct dss_pll *pll,
	449	const struct dss_pll_clock_info *cinfo);
	450	int dss_pll_write_config_type_b(struct dss_pll *pll,
	451	const struct dss_pll_clock_info *cinfo);
eb30199b	452	int dss_pll_wait_reset_done(struct dss_pll *pll);
0a20170a	453
559d6701	454	#endif