[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / omapdrm / dss / dss.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 */

#ifndef __OMAP2_DSS_H
#define __OMAP2_DSS_H

#include <linux/interrupt.h>

#include "omapdss.h"

struct dispc_device;
struct dss_debugfs_entry;
struct platform_device;
struct seq_file;

#define MAX_DSS_LCD_MANAGERS	3
#define MAX_NUM_DSI		2

#ifdef pr_fmt
#undef pr_fmt
#endif

#ifdef DSS_SUBSYS_NAME
#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
#else
#define pr_fmt(fmt) fmt
#endif

#define DSSDBG(format, ...) \
	pr_debug(format, ## __VA_ARGS__)

#ifdef DSS_SUBSYS_NAME
#define DSSERR(format, ...) \
	pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
#else
#define DSSERR(format, ...) \
	pr_err("omapdss error: " format, ##__VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSINFO(format, ...) \
	pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
#else
#define DSSINFO(format, ...) \
	pr_info("omapdss: " format, ## __VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSWARN(format, ...) \
	pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
#else
#define DSSWARN(format, ...) \
	pr_warn("omapdss: " format, ##__VA_ARGS__)
#endif

/* OMAP TRM gives bitfields as start:end, where start is the higher bit
   number. For example 7:0 */
#define FLD_MASK(start, end)	(((1 << ((start) - (end) + 1)) - 1) << (end))
#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
#define FLD_MOD(orig, val, start, end) \
	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))

enum dss_model {
	DSS_MODEL_OMAP2,
	DSS_MODEL_OMAP3,
	DSS_MODEL_OMAP4,
	DSS_MODEL_OMAP5,
	DSS_MODEL_DRA7,
};

enum dss_io_pad_mode {
	DSS_IO_PAD_MODE_RESET,
	DSS_IO_PAD_MODE_RFBI,
	DSS_IO_PAD_MODE_BYPASS,
};

enum dss_hdmi_venc_clk_source_select {
	DSS_VENC_TV_CLK = 0,
	DSS_HDMI_M_PCLK = 1,
};

enum dss_dsi_content_type {
	DSS_DSI_CONTENT_DCS,
	DSS_DSI_CONTENT_GENERIC,
};

enum dss_clk_source {
	DSS_CLK_SRC_FCK = 0,

	DSS_CLK_SRC_PLL1_1,
	DSS_CLK_SRC_PLL1_2,
	DSS_CLK_SRC_PLL1_3,

	DSS_CLK_SRC_PLL2_1,
	DSS_CLK_SRC_PLL2_2,
	DSS_CLK_SRC_PLL2_3,

	DSS_CLK_SRC_HDMI_PLL,
};

enum dss_pll_id {
	DSS_PLL_DSI1,
	DSS_PLL_DSI2,
	DSS_PLL_HDMI,
	DSS_PLL_VIDEO1,
	DSS_PLL_VIDEO2,
};

struct dss_pll;

#define DSS_PLL_MAX_HSDIVS 4

enum dss_pll_type {
	DSS_PLL_TYPE_A,
	DSS_PLL_TYPE_B,
};

/*
 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
 * Type-B PLLs: clkout[0] refers to m2.
 */
struct dss_pll_clock_info {
	/* rates that we get with dividers below */
	unsigned long fint;
	unsigned long clkdco;
	unsigned long clkout[DSS_PLL_MAX_HSDIVS];

	/* dividers */
	u16 n;
	u16 m;
	u32 mf;
	u16 mX[DSS_PLL_MAX_HSDIVS];
	u16 sd;
};

struct dss_pll_ops {
	int (*enable)(struct dss_pll *pll);
	void (*disable)(struct dss_pll *pll);
	int (*set_config)(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
};

struct dss_pll_hw {
	enum dss_pll_type type;

	unsigned int n_max;
	unsigned int m_min;
	unsigned int m_max;
	unsigned int mX_max;

	unsigned long fint_min, fint_max;
	unsigned long clkdco_min, clkdco_low, clkdco_max;

	u8 n_msb, n_lsb;
	u8 m_msb, m_lsb;
	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];

	bool has_stopmode;
	bool has_freqsel;
	bool has_selfreqdco;
	bool has_refsel;

	/* DRA7 errata i886: use high N & M to avoid jitter */
	bool errata_i886;

	/* DRA7 errata i932: retry pll lock on failure */
	bool errata_i932;
};

struct dss_pll {
	const char *name;
	enum dss_pll_id id;
	struct dss_device *dss;

	struct clk *clkin;
	struct regulator *regulator;

	void __iomem *base;

	const struct dss_pll_hw *hw;

	const struct dss_pll_ops *ops;

	struct dss_pll_clock_info cinfo;
};

/* Defines a generic omap register field */
struct dss_reg_field {
	u8 start, end;
};

struct dispc_clock_info {
	/* rates that we get with dividers below */
	unsigned long lck;
	unsigned long pck;

	/* dividers */
	u16 lck_div;
	u16 pck_div;
};

struct dss_lcd_mgr_config {
	enum dss_io_pad_mode io_pad_mode;

	bool stallmode;
	bool fifohandcheck;

	struct dispc_clock_info clock_info;

	int video_port_width;

	int lcden_sig_polarity;
};

#define DSS_SZ_REGS			SZ_512

struct dss_device {
	struct platform_device *pdev;
	void __iomem    *base;
	struct regmap	*syscon_pll_ctrl;
	u32		syscon_pll_ctrl_offset;

	struct platform_device *drm_pdev;

	struct clk	*parent_clk;
	struct clk	*dss_clk;
	unsigned long	dss_clk_rate;

	unsigned long	cache_req_pck;
	unsigned long	cache_prate;
	struct dispc_clock_info cache_dispc_cinfo;

	enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
	enum dss_clk_source dispc_clk_source;
	enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];

	bool		ctx_valid;
	u32		ctx[DSS_SZ_REGS / sizeof(u32)];

	const struct dss_features *feat;

	struct {
		struct dentry *root;
		struct dss_debugfs_entry *clk;
		struct dss_debugfs_entry *dss;
	} debugfs;

	struct dss_pll *plls[4];
	struct dss_pll	*video1_pll;
	struct dss_pll	*video2_pll;

	struct dispc_device *dispc;
	const struct dispc_ops *dispc_ops;
	const struct dss_mgr_ops *mgr_ops;
	struct omap_drm_private *mgr_ops_priv;
};

/* core */
static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	/* To be implemented when the OMAP platform will provide this feature */
	return 0;
}

static inline bool dss_mgr_is_lcd(enum omap_channel id)
{
	if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
			id == OMAP_DSS_CHANNEL_LCD3)
		return true;
	else
		return false;
}

/* DSS */
#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
struct dss_debugfs_entry *
dss_debugfs_create_file(struct dss_device *dss, const char *name,
			int (*show_fn)(struct seq_file *s, void *data),
			void *data);
void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
#else
static inline struct dss_debugfs_entry *
dss_debugfs_create_file(struct dss_device *dss, const char *name,
			int (*show_fn)(struct seq_file *s, void *data),
			void *data)
{
	return NULL;
}

static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
{
}
#endif /* CONFIG_OMAP2_DSS_DEBUGFS */

struct dss_device *dss_get_device(struct device *dev);

int dss_runtime_get(struct dss_device *dss);
void dss_runtime_put(struct dss_device *dss);

unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
unsigned long dss_get_max_fck_rate(struct dss_device *dss);
int dss_dpi_select_source(struct dss_device *dss, int port,
			  enum omap_channel channel);
void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
				     enum dss_hdmi_venc_clk_source_select src);
const char *dss_get_clk_source_name(enum dss_clk_source clk_src);

/* DSS VIDEO PLL */
struct dss_pll *dss_video_pll_init(struct dss_device *dss,
				   struct platform_device *pdev, int id,
				   struct regulator *regulator);
void dss_video_pll_uninit(struct dss_pll *pll);

void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);

void dss_sdi_init(struct dss_device *dss, int datapairs);
int dss_sdi_enable(struct dss_device *dss);
void dss_sdi_disable(struct dss_device *dss);

void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
			       enum dss_clk_source clk_src);
void dss_select_lcd_clk_source(struct dss_device *dss,
			       enum omap_channel channel,
			       enum dss_clk_source clk_src);
enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
					   int dsi_module);
enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
					   enum omap_channel channel);

void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);

int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);

typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
bool dss_div_calc(struct dss_device *dss, unsigned long pck,
		  unsigned long fck_min, dss_div_calc_func func, void *data);

/* SDI */
#ifdef CONFIG_OMAP2_DSS_SDI
int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
		  struct device_node *port);
void sdi_uninit_port(struct device_node *port);
#else
static inline int sdi_init_port(struct dss_device *dss,
				struct platform_device *pdev,
				struct device_node *port)
{
	return 0;
}
static inline void sdi_uninit_port(struct device_node *port)
{
}
#endif

/* DSI */

#ifdef CONFIG_OMAP2_DSS_DSI

void dsi_irq_handler(void);

#endif

/* DPI */
#ifdef CONFIG_OMAP2_DSS_DPI
int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
		  struct device_node *port, enum dss_model dss_model);
void dpi_uninit_port(struct device_node *port);
#else
static inline int dpi_init_port(struct dss_device *dss,
				struct platform_device *pdev,
				struct device_node *port,
				enum dss_model dss_model)
{
	return 0;
}
static inline void dpi_uninit_port(struct device_node *port)
{
}
#endif

/* DISPC */
void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);

int dispc_runtime_get(struct dispc_device *dispc);
void dispc_runtime_put(struct dispc_device *dispc);

void dispc_enable_sidle(struct dispc_device *dispc);
void dispc_disable_sidle(struct dispc_device *dispc);

void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);

typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
		unsigned long pck, void *data);
bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
		    unsigned long pck_min, unsigned long pck_max,
		    dispc_div_calc_func func, void *data);

int dispc_calc_clock_rates(struct dispc_device *dispc,
			   unsigned long dispc_fclk_rate,
			   struct dispc_clock_info *cinfo);


void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
				  enum omap_plane_id plane, u32 low, u32 high);
void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
				       enum omap_plane_id plane,
				       u32 *fifo_low, u32 *fifo_high,
				       bool use_fifomerge, bool manual_update);

void dispc_mgr_set_clock_div(struct dispc_device *dispc,
			     enum omap_channel channel,
			     const struct dispc_clock_info *cinfo);
int dispc_mgr_get_clock_div(struct dispc_device *dispc,
			    enum omap_channel channel,
			    struct dispc_clock_info *cinfo);
void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);

#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
{
	int b;
	for (b = 0; b < 32; ++b) {
		if (irqstatus & (1 << b))
			irq_arr[b]++;
	}
}
#endif

/* PLL */
typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
		unsigned long clkdco, void *data);
typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
		void *data);

int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
void dss_pll_unregister(struct dss_pll *pll);
struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
				    enum dss_clk_source src);
unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
int dss_pll_enable(struct dss_pll *pll);
void dss_pll_disable(struct dss_pll *pll);
int dss_pll_set_config(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);

bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
		unsigned long out_min, unsigned long out_max,
		dss_hsdiv_calc_func func, void *data);
bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
		unsigned long pll_min, unsigned long pll_max,
		dss_pll_calc_func func, void *data);

bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
	unsigned long target_clkout, struct dss_pll_clock_info *cinfo);

int dss_pll_write_config_type_a(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
int dss_pll_write_config_type_b(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
int dss_pll_wait_reset_done(struct dss_pll *pll);

extern struct platform_driver omap_dsshw_driver;
extern struct platform_driver omap_dispchw_driver;
#ifdef CONFIG_OMAP2_DSS_DSI
extern struct platform_driver omap_dsihw_driver;
#endif
#ifdef CONFIG_OMAP2_DSS_VENC
extern struct platform_driver omap_venchw_driver;
#endif
#ifdef CONFIG_OMAP4_DSS_HDMI
extern struct platform_driver omapdss_hdmi4hw_driver;
#endif
#ifdef CONFIG_OMAP5_DSS_HDMI
extern struct platform_driver omapdss_hdmi5hw_driver;
#endif

#endif
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
559d6701	2	/*
559d6701	3	* Copyright (C) 2009 Nokia Corporation
6505d75c	4	* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
559d6701 TV	5	*
	6	* Some code and ideas taken from drivers/video/omap/ driver
	7	* by Imre Deak.
559d6701 TV	8	*/
	9
	10	#ifndef __OMAP2_DSS_H
	11	#define __OMAP2_DSS_H
	12
96e2e637 TV	13	#include <linux/interrupt.h>
96e2e637 TV	14
35a339ac TV	15	#include "omapdss.h"
35a339ac TV	16
50638ae5	17	struct dispc_device;
f33656e1 LP	18	struct dss_debugfs_entry;
	19	struct platform_device;
	20	struct seq_file;
	21
d874b3a7 LP	22	#define MAX_DSS_LCD_MANAGERS 3
	23	#define MAX_NUM_DSI 2
	24
702d267e CM	25	#ifdef pr_fmt
702d267e CM	26	#undef pr_fmt
559d6701 TV	27	#endif
559d6701 TV	28
702d267e CM	29	#ifdef DSS_SUBSYS_NAME
	30	#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
	31	#else
	32	#define pr_fmt(fmt) fmt
559d6701 TV	33	#endif
559d6701 TV	34
702d267e CM	35	#define DSSDBG(format, ...) \
702d267e CM	36	pr_debug(format, ## __VA_ARGS__)
559d6701 TV	37
	38	#ifdef DSS_SUBSYS_NAME
	39	#define DSSERR(format, ...) \
8dfe162a	40	pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
559d6701 TV	41	#else
559d6701 TV	42	#define DSSERR(format, ...) \
8dfe162a	43	pr_err("omapdss error: " format, ##__VA_ARGS__)
559d6701 TV	44	#endif
	45
	46	#ifdef DSS_SUBSYS_NAME
	47	#define DSSINFO(format, ...) \
8dfe162a	48	pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
559d6701 TV	49	#else
559d6701 TV	50	#define DSSINFO(format, ...) \
8dfe162a	51	pr_info("omapdss: " format, ## __VA_ARGS__)
559d6701 TV	52	#endif
	53
	54	#ifdef DSS_SUBSYS_NAME
	55	#define DSSWARN(format, ...) \
8dfe162a	56	pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
559d6701 TV	57	#else
559d6701 TV	58	#define DSSWARN(format, ...) \
8dfe162a	59	pr_warn("omapdss: " format, ##__VA_ARGS__)
559d6701 TV	60	#endif
	61
	62	/* OMAP TRM gives bitfields as start:end, where start is the higher bit
	63	number. For example 7:0 */
	64	#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
	65	#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
	66	#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
	67	#define FLD_MOD(orig, val, start, end) \
	68	(((orig) & ~FLD_MASK(start, end)) \| FLD_VAL(val, start, end))
	69
b8dab2bd LP	70	enum dss_model {
	71	DSS_MODEL_OMAP2,
	72	DSS_MODEL_OMAP3,
	73	DSS_MODEL_OMAP4,
	74	DSS_MODEL_OMAP5,
	75	DSS_MODEL_DRA7,
	76	};
	77
569969d6 AT	78	enum dss_io_pad_mode {
	79	DSS_IO_PAD_MODE_RESET,
	80	DSS_IO_PAD_MODE_RFBI,
	81	DSS_IO_PAD_MODE_BYPASS,
559d6701 TV	82	};
559d6701 TV	83
7ed024aa M	84	enum dss_hdmi_venc_clk_source_select {
	85	DSS_VENC_TV_CLK = 0,
	86	DSS_HDMI_M_PCLK = 1,
	87	};
	88
6ff8aa31 AT	89	enum dss_dsi_content_type {
	90	DSS_DSI_CONTENT_DCS,
	91	DSS_DSI_CONTENT_GENERIC,
	92	};
	93
dc0352d1	94	enum dss_clk_source {
3b63ca75 TV	95	DSS_CLK_SRC_FCK = 0,
	96
	97	DSS_CLK_SRC_PLL1_1,
	98	DSS_CLK_SRC_PLL1_2,
b5d8c757	99	DSS_CLK_SRC_PLL1_3,
3b63ca75 TV	100
	101	DSS_CLK_SRC_PLL2_1,
	102	DSS_CLK_SRC_PLL2_2,
b5d8c757 TV	103	DSS_CLK_SRC_PLL2_3,
	104
	105	DSS_CLK_SRC_HDMI_PLL,
be5d7319 TV	106	};
be5d7319 TV	107
64e22ffd TV	108	enum dss_pll_id {
	109	DSS_PLL_DSI1,
	110	DSS_PLL_DSI2,
	111	DSS_PLL_HDMI,
6d817880 TV	112	DSS_PLL_VIDEO1,
6d817880 TV	113	DSS_PLL_VIDEO2,
64e22ffd TV	114	};
64e22ffd TV	115
0a20170a TV	116	struct dss_pll;
	117
	118	#define DSS_PLL_MAX_HSDIVS 4
	119
06ede3dd TV	120	enum dss_pll_type {
	121	DSS_PLL_TYPE_A,
	122	DSS_PLL_TYPE_B,
	123	};
	124
0a20170a TV	125	/*
	126	* Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
	127	* Type-B PLLs: clkout[0] refers to m2.
	128	*/
	129	struct dss_pll_clock_info {
	130	/* rates that we get with dividers below */
	131	unsigned long fint;
	132	unsigned long clkdco;
	133	unsigned long clkout[DSS_PLL_MAX_HSDIVS];
	134
	135	/* dividers */
	136	u16 n;
	137	u16 m;
	138	u32 mf;
	139	u16 mX[DSS_PLL_MAX_HSDIVS];
	140	u16 sd;
	141	};
	142
	143	struct dss_pll_ops {
	144	int (enable)(struct dss_pll pll);
	145	void (disable)(struct dss_pll pll);
	146	int (set_config)(struct dss_pll pll,
	147	const struct dss_pll_clock_info *cinfo);
	148	};
	149
	150	struct dss_pll_hw {
06ede3dd TV	151	enum dss_pll_type type;
06ede3dd TV	152
d11e5c82 LP	153	unsigned int n_max;
	154	unsigned int m_min;
	155	unsigned int m_max;
	156	unsigned int mX_max;
0a20170a TV	157
	158	unsigned long fint_min, fint_max;
	159	unsigned long clkdco_min, clkdco_low, clkdco_max;
	160
	161	u8 n_msb, n_lsb;
	162	u8 m_msb, m_lsb;
	163	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
	164
	165	bool has_stopmode;
	166	bool has_freqsel;
	167	bool has_selfreqdco;
	168	bool has_refsel;
0c43f1e0 TV	169
	170	/* DRA7 errata i886: use high N & M to avoid jitter */
	171	bool errata_i886;
c618a3a9 VRM	172
	173	/* DRA7 errata i932: retry pll lock on failure */
	174	bool errata_i932;
0a20170a TV	175	};
	176
	177	struct dss_pll {
	178	const char *name;
64e22ffd	179	enum dss_pll_id id;
7b295257	180	struct dss_device *dss;
0a20170a TV	181
	182	struct clk *clkin;
	183	struct regulator *regulator;
	184
	185	void __iomem *base;
	186
	187	const struct dss_pll_hw *hw;
	188
	189	const struct dss_pll_ops *ops;
	190
	191	struct dss_pll_clock_info cinfo;
	192	};
	193
6d85d4ad LP	194	/* Defines a generic omap register field */
	195	struct dss_reg_field {
	196	u8 start, end;
	197	};
	198
559d6701 TV	199	struct dispc_clock_info {
	200	/* rates that we get with dividers below */
	201	unsigned long lck;
	202	unsigned long pck;
	203
	204	/* dividers */
	205	u16 lck_div;
	206	u16 pck_div;
	207	};
	208
c56fb3ef AT	209	struct dss_lcd_mgr_config {
	210	enum dss_io_pad_mode io_pad_mode;
	211
	212	bool stallmode;
	213	bool fifohandcheck;
	214
	215	struct dispc_clock_info clock_info;
	216
	217	int video_port_width;
	218
	219	int lcden_sig_polarity;
	220	};
	221
0e546dfd LP	222	#define DSS_SZ_REGS SZ_512
	223
	224	struct dss_device {
	225	struct platform_device *pdev;
	226	void __iomem *base;
	227	struct regmap *syscon_pll_ctrl;
	228	u32 syscon_pll_ctrl_offset;
	229
cc1876ce JS	230	struct platform_device *drm_pdev;
cc1876ce JS	231
0e546dfd LP	232	struct clk *parent_clk;
	233	struct clk *dss_clk;
	234	unsigned long dss_clk_rate;
	235
	236	unsigned long cache_req_pck;
	237	unsigned long cache_prate;
	238	struct dispc_clock_info cache_dispc_cinfo;
	239
	240	enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
	241	enum dss_clk_source dispc_clk_source;
	242	enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
	243
	244	bool ctx_valid;
	245	u32 ctx[DSS_SZ_REGS / sizeof(u32)];
	246
	247	const struct dss_features *feat;
	248
f33656e1	249	struct {
1c4b92ee	250	struct dentry *root;
f33656e1 LP	251	struct dss_debugfs_entry *clk;
	252	struct dss_debugfs_entry *dss;
	253	} debugfs;
	254
798957ae	255	struct dss_pll *plls[4];
0e546dfd LP	256	struct dss_pll *video1_pll;
0e546dfd LP	257	struct dss_pll *video2_pll;
d3541ca8	258
50638ae5	259	struct dispc_device *dispc;
d3541ca8	260	const struct dispc_ops *dispc_ops;
845417b3 LP	261	const struct dss_mgr_ops *mgr_ops;
845417b3 LP	262	struct omap_drm_private *mgr_ops_priv;
0e546dfd LP	263	};
0e546dfd LP	264
559d6701	265	/* core */
493b683b LP	266	static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	267	{
	268	/* To be implemented when the OMAP platform will provide this feature */
	269	return 0;
	270	}
	271
f476ae9d AT	272	static inline bool dss_mgr_is_lcd(enum omap_channel id)
	273	{
	274	if (id == OMAP_DSS_CHANNEL_LCD \|\| id == OMAP_DSS_CHANNEL_LCD2 \|\|
	275	id == OMAP_DSS_CHANNEL_LCD3)
	276	return true;
	277	else
	278	return false;
	279	}
	280
559d6701	281	/* DSS */
11765d16	282	#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
1c4b92ee LP	283	struct dss_debugfs_entry *
	284	dss_debugfs_create_file(struct dss_device dss, const char name,
	285	int (show_fn)(struct seq_file s, void *data),
	286	void *data);
f33656e1	287	void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
11765d16	288	#else
f33656e1	289	static inline struct dss_debugfs_entry *
1c4b92ee	290	dss_debugfs_create_file(struct dss_device dss, const char name,
f33656e1 LP	291	int (show_fn)(struct seq_file s, void *data),
	292	void *data)
	293	{
	294	return NULL;
	295	}
	296
	297	static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
11765d16	298	{
11765d16 LP	299	}
	300	#endif /* CONFIG_OMAP2_DSS_DEBUGFS */
	301
7b295257 LP	302	struct dss_device dss_get_device(struct device dev);
	303
	304	int dss_runtime_get(struct dss_device *dss);
	305	void dss_runtime_put(struct dss_device *dss);
99767548	306
60f9c59f LP	307	unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
60f9c59f LP	308	unsigned long dss_get_max_fck_rate(struct dss_device *dss);
8aea8e6a LP	309	int dss_dpi_select_source(struct dss_device *dss, int port,
	310	enum omap_channel channel);
	311	void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
	312	enum dss_hdmi_venc_clk_source_select src);
407bd564	313	const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
559d6701	314
99767548	315	/* DSS VIDEO PLL */
7b295257 LP	316	struct dss_pll dss_video_pll_init(struct dss_device dss,
	317	struct platform_device *pdev, int id,
	318	struct regulator *regulator);
99767548 TV	319	void dss_video_pll_uninit(struct dss_pll *pll);
99767548 TV	320
27260999	321	void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
be40eecf	322
d7157dfe LP	323	void dss_sdi_init(struct dss_device *dss, int datapairs);
	324	int dss_sdi_enable(struct dss_device *dss);
	325	void dss_sdi_disable(struct dss_device *dss);
559d6701	326
8aea8e6a LP	327	void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
	328	enum dss_clk_source clk_src);
	329	void dss_select_lcd_clk_source(struct dss_device *dss,
	330	enum omap_channel channel,
	331	enum dss_clk_source clk_src);
3cc62aad LP	332	enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
	333	enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
	334	int dsi_module);
	335	enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
	336	enum omap_channel channel);
2f18c4d8	337
1ef904e1 LP	338	void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
1ef904e1 LP	339	void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
559d6701	340
60f9c59f	341	int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
559d6701	342
d0f58bd3	343	typedef bool (dss_div_calc_func)(unsigned long fck, void data);
60f9c59f LP	344	bool dss_div_calc(struct dss_device *dss, unsigned long pck,
60f9c59f LP	345	unsigned long fck_min, dss_div_calc_func func, void *data);
43417823	346
559d6701	347	/* SDI */
387ce9f2	348	#ifdef CONFIG_OMAP2_DSS_SDI
d7157dfe LP	349	int sdi_init_port(struct dss_device dss, struct platform_device pdev,
d7157dfe LP	350	struct device_node *port);
ede92695	351	void sdi_uninit_port(struct device_node *port);
387ce9f2	352	#else
d7157dfe LP	353	static inline int sdi_init_port(struct dss_device *dss,
	354	struct platform_device *pdev,
	355	struct device_node *port)
387ce9f2 AT	356	{
	357	return 0;
	358	}
ede92695	359	static inline void sdi_uninit_port(struct device_node *port)
387ce9f2 AT	360	{
	361	}
	362	#endif
2ecef246	363
559d6701	364	/* DSI */
989c79a8	365
368a148e	366	#ifdef CONFIG_OMAP2_DSS_DSI
5a8b572d	367
559d6701	368	void dsi_irq_handler(void);
a3b3cc2b	369
368a148e	370	#endif
559d6701 TV	371
559d6701 TV	372	/* DPI */
387ce9f2	373	#ifdef CONFIG_OMAP2_DSS_DPI
8aea8e6a LP	374	int dpi_init_port(struct dss_device dss, struct platform_device pdev,
8aea8e6a LP	375	struct device_node *port, enum dss_model dss_model);
ede92695	376	void dpi_uninit_port(struct device_node *port);
387ce9f2	377	#else
037f0315	378	static inline int dpi_init_port(struct dss_device *dss,
8aea8e6a LP	379	struct platform_device *pdev,
	380	struct device_node *port,
	381	enum dss_model dss_model)
387ce9f2 AT	382	{
	383	return 0;
	384	}
ede92695	385	static inline void dpi_uninit_port(struct device_node *port)
387ce9f2 AT	386	{
	387	}
	388	#endif
2ecef246	389
559d6701	390	/* DISPC */
8a7eda76	391	void dispc_dump_clocks(struct dispc_device dispc, struct seq_file s);
559d6701	392
50638ae5 LP	393	int dispc_runtime_get(struct dispc_device *dispc);
50638ae5 LP	394	void dispc_runtime_put(struct dispc_device *dispc);
5034b1fa	395
8a7eda76 LP	396	void dispc_enable_sidle(struct dispc_device *dispc);
8a7eda76 LP	397	void dispc_disable_sidle(struct dispc_device *dispc);
559d6701	398
8a7eda76 LP	399	void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
	400	void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
	401	void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
cd295aeb	402
7c284e6e TV	403	typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
7c284e6e TV	404	unsigned long pck, void *data);
8a7eda76 LP	405	bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
	406	unsigned long pck_min, unsigned long pck_max,
	407	dispc_div_calc_func func, void *data);
	408
8a7eda76 LP	409	int dispc_calc_clock_rates(struct dispc_device *dispc,
	410	unsigned long dispc_fclk_rate,
	411	struct dispc_clock_info *cinfo);
	412
	413
	414	void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
	415	enum omap_plane_id plane, u32 low, u32 high);
	416	void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
	417	enum omap_plane_id plane,
	418	u32 fifo_low, u32 fifo_high,
	419	bool use_fifomerge, bool manual_update);
	420
	421	void dispc_mgr_set_clock_div(struct dispc_device *dispc,
	422	enum omap_channel channel,
	423	const struct dispc_clock_info *cinfo);
	424	int dispc_mgr_get_clock_div(struct dispc_device *dispc,
	425	enum omap_channel channel,
	426	struct dispc_clock_info *cinfo);
	427	void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
	428
dfc0fd8d	429	#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
d11e5c82	430	static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
dfc0fd8d TV	431	{
	432	int b;
	433	for (b = 0; b < 32; ++b) {
	434	if (irqstatus & (1 << b))
	435	irq_arr[b]++;
	436	}
	437	}
	438	#endif
	439
0a20170a TV	440	/* PLL */
	441	typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
	442	unsigned long clkdco, void *data);
	443	typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
	444	void *data);
	445
798957ae	446	int dss_pll_register(struct dss_device dss, struct dss_pll pll);
0a20170a	447	void dss_pll_unregister(struct dss_pll *pll);
798957ae LP	448	struct dss_pll dss_pll_find(struct dss_device dss, const char *name);
	449	struct dss_pll dss_pll_find_by_src(struct dss_device dss,
	450	enum dss_clk_source src);
d11e5c82	451	unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
0a20170a TV	452	int dss_pll_enable(struct dss_pll *pll);
	453	void dss_pll_disable(struct dss_pll *pll);
	454	int dss_pll_set_config(struct dss_pll *pll,
	455	const struct dss_pll_clock_info *cinfo);
	456
cd0715ff	457	bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
0a20170a TV	458	unsigned long out_min, unsigned long out_max,
0a20170a TV	459	dss_hsdiv_calc_func func, void *data);
cd0715ff	460	bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
0a20170a TV	461	unsigned long pll_min, unsigned long pll_max,
0a20170a TV	462	dss_pll_calc_func func, void *data);
c17dc0e3 TV	463
c17dc0e3 TV	464	bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
c107751d	465	unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
c17dc0e3	466
0a20170a TV	467	int dss_pll_write_config_type_a(struct dss_pll *pll,
	468	const struct dss_pll_clock_info *cinfo);
	469	int dss_pll_write_config_type_b(struct dss_pll *pll,
	470	const struct dss_pll_clock_info *cinfo);
eb30199b	471	int dss_pll_wait_reset_done(struct dss_pll *pll);
0a20170a	472
d66c36a3 AD	473	extern struct platform_driver omap_dsshw_driver;
	474	extern struct platform_driver omap_dispchw_driver;
	475	#ifdef CONFIG_OMAP2_DSS_DSI
	476	extern struct platform_driver omap_dsihw_driver;
	477	#endif
	478	#ifdef CONFIG_OMAP2_DSS_VENC
	479	extern struct platform_driver omap_venchw_driver;
	480	#endif
	481	#ifdef CONFIG_OMAP4_DSS_HDMI
	482	extern struct platform_driver omapdss_hdmi4hw_driver;
	483	#endif
	484	#ifdef CONFIG_OMAP5_DSS_HDMI
	485	extern struct platform_driver omapdss_hdmi5hw_driver;
	486	#endif
	487
559d6701	488	#endif