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drm/omap: support double-pixel
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / dss / hdmi4.c
CommitLineData
c3198a5e 1/*
ef26958a 2 * HDMI interface DSS driver for TI's OMAP4 family of SoCs.
c3198a5e
M
3 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
4 * Authors: Yong Zhi
5 * Mythri pk <mythripk@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "HDMI"
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/interrupt.h>
27#include <linux/mutex.h>
28#include <linux/delay.h>
29#include <linux/string.h>
24e6289c 30#include <linux/platform_device.h>
4fbafaf3
TV
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
cca35017 33#include <linux/gpio.h>
17486943 34#include <linux/regulator/consumer.h>
736e60dd 35#include <linux/component.h>
a0b38cc4 36#include <video/omapdss.h>
4d594dff 37#include <sound/omap-hdmi-audio.h>
c3198a5e 38
ef26958a 39#include "hdmi4_core.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
945514b5 42#include "hdmi.h"
c3198a5e 43
945514b5 44static struct omap_hdmi hdmi;
c3198a5e 45
4fbafaf3
TV
46static int hdmi_runtime_get(void)
47{
48 int r;
49
50 DSSDBG("hdmi_runtime_get\n");
51
52 r = pm_runtime_get_sync(&hdmi.pdev->dev);
53 WARN_ON(r < 0);
a247ce78 54 if (r < 0)
852f0838 55 return r;
a247ce78
AT
56
57 return 0;
4fbafaf3
TV
58}
59
60static void hdmi_runtime_put(void)
61{
62 int r;
63
64 DSSDBG("hdmi_runtime_put\n");
65
0eaf9f52 66 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 67 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV
68}
69
dcf5f729
TV
70static irqreturn_t hdmi_irq_handler(int irq, void *data)
71{
72 struct hdmi_wp_data *wp = data;
73 u32 irqstatus;
74
75 irqstatus = hdmi_wp_get_irqstatus(wp);
76 hdmi_wp_set_irqstatus(wp, irqstatus);
77
78 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
79 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
80 /*
81 * If we get both connect and disconnect interrupts at the same
82 * time, turn off the PHY, clear interrupts, and restart, which
83 * raises connect interrupt if a cable is connected, or nothing
84 * if cable is not connected.
85 */
86 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
87
88 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
89 HDMI_IRQ_LINK_DISCONNECT);
90
91 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
92 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
93 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
94 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
95 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
96 }
97
98 return IRQ_HANDLED;
99}
100
e25001d8
TV
101static int hdmi_init_regulator(void)
102{
818a053c 103 int r;
e25001d8
TV
104 struct regulator *reg;
105
945514b5 106 if (hdmi.vdda_reg != NULL)
e25001d8
TV
107 return 0;
108
931d4bd6 109 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
e25001d8
TV
110
111 if (IS_ERR(reg)) {
40359a9b 112 if (PTR_ERR(reg) != -EPROBE_DEFER)
931d4bd6 113 DSSERR("can't get VDDA regulator\n");
e25001d8
TV
114 return PTR_ERR(reg);
115 }
116
818a053c
TV
117 if (regulator_can_change_voltage(reg)) {
118 r = regulator_set_voltage(reg, 1800000, 1800000);
119 if (r) {
120 devm_regulator_put(reg);
121 DSSWARN("can't set the regulator voltage\n");
122 return r;
123 }
124 }
125
945514b5 126 hdmi.vdda_reg = reg;
e25001d8
TV
127
128 return 0;
129}
130
bb426fc9 131static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 132{
46095b2d 133 int r;
c3198a5e 134
945514b5 135 r = regulator_enable(hdmi.vdda_reg);
17486943 136 if (r)
164ebdd1 137 return r;
17486943 138
4fbafaf3
TV
139 r = hdmi_runtime_get();
140 if (r)
cca35017 141 goto err_runtime_get;
c3198a5e 142
bb426fc9
TV
143 /* Make selection of HDMI in DSS */
144 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
145
0b450c31
TV
146 hdmi.core_enabled = true;
147
bb426fc9
TV
148 return 0;
149
150err_runtime_get:
945514b5 151 regulator_disable(hdmi.vdda_reg);
164ebdd1 152
bb426fc9
TV
153 return r;
154}
155
156static void hdmi_power_off_core(struct omap_dss_device *dssdev)
157{
0b450c31
TV
158 hdmi.core_enabled = false;
159
bb426fc9 160 hdmi_runtime_put();
945514b5 161 regulator_disable(hdmi.vdda_reg);
bb426fc9
TV
162}
163
164static int hdmi_power_on_full(struct omap_dss_device *dssdev)
165{
166 int r;
167 struct omap_video_timings *p;
7ae9a71e 168 struct omap_overlay_manager *mgr = hdmi.output.manager;
dcf5f729 169 struct hdmi_wp_data *wp = &hdmi.wp;
c84c3a5b 170 struct dss_pll_clock_info hdmi_cinfo = { 0 };
bb426fc9
TV
171
172 r = hdmi_power_on_core(dssdev);
173 if (r)
174 return r;
175
dcf5f729
TV
176 /* disable and clear irqs */
177 hdmi_wp_clear_irqenable(wp, 0xffffffff);
178 hdmi_wp_set_irqstatus(wp, 0xffffffff);
179
275cfa1a 180 p = &hdmi.cfg.timings;
c3198a5e 181
7849398f 182 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 183
c84c3a5b 184 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
c3198a5e 185
c84c3a5b 186 r = dss_pll_enable(&hdmi.pll.pll);
c3198a5e 187 if (r) {
c2fbd061 188 DSSERR("Failed to enable PLL\n");
cca35017 189 goto err_pll_enable;
c3198a5e
M
190 }
191
c84c3a5b 192 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
c2fbd061
TV
193 if (r) {
194 DSSERR("Failed to configure PLL\n");
195 goto err_pll_cfg;
196 }
197
c84c3a5b
TV
198 r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
199 hdmi_cinfo.clkout[0]);
c3198a5e 200 if (r) {
dcf5f729
TV
201 DSSDBG("Failed to configure PHY\n");
202 goto err_phy_cfg;
c3198a5e
M
203 }
204
dcf5f729
TV
205 r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
206 if (r)
207 goto err_phy_pwr;
208
275cfa1a 209 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
c3198a5e 210
c3198a5e
M
211 /* bypass TV gamma table */
212 dispc_enable_gamma_table(0);
213
214 /* tv size */
cea87b92 215 dss_mgr_set_timings(mgr, p);
c3198a5e 216
cea87b92 217 r = dss_mgr_enable(mgr);
33ca237f
TV
218 if (r)
219 goto err_mgr_enable;
3870c909 220
4e4b53ce
TV
221 r = hdmi_wp_video_start(&hdmi.wp);
222 if (r)
223 goto err_vid_enable;
224
dcf5f729
TV
225 hdmi_wp_set_irqenable(wp,
226 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
227
c3198a5e 228 return 0;
33ca237f 229
c0456be3 230err_vid_enable:
4e4b53ce
TV
231 dss_mgr_disable(mgr);
232err_mgr_enable:
dcf5f729
TV
233 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
234err_phy_pwr:
9bba13f0 235err_phy_cfg:
c2fbd061 236err_pll_cfg:
c84c3a5b 237 dss_pll_disable(&hdmi.pll.pll);
cca35017 238err_pll_enable:
bb426fc9 239 hdmi_power_off_core(dssdev);
c3198a5e
M
240 return -EIO;
241}
242
bb426fc9 243static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 244{
7ae9a71e 245 struct omap_overlay_manager *mgr = hdmi.output.manager;
cea87b92 246
dcf5f729
TV
247 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
248
275cfa1a 249 hdmi_wp_video_stop(&hdmi.wp);
dcf5f729 250
4e4b53ce
TV
251 dss_mgr_disable(mgr);
252
dcf5f729
TV
253 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
254
c84c3a5b 255 dss_pll_disable(&hdmi.pll.pll);
17486943 256
bb426fc9 257 hdmi_power_off_core(dssdev);
c3198a5e
M
258}
259
164ebdd1 260static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
c3198a5e
M
261 struct omap_video_timings *timings)
262{
1e676248 263 struct omap_dss_device *out = &hdmi.output;
c3198a5e 264
1e676248 265 if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
c3198a5e 266 return -EINVAL;
c3198a5e
M
267
268 return 0;
c3198a5e
M
269}
270
164ebdd1 271static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
7849398f 272 struct omap_video_timings *timings)
c3198a5e 273{
ed1aa900
AT
274 mutex_lock(&hdmi.lock);
275
ab0aee95 276 hdmi.cfg.timings = *timings;
5391e87d 277
ab0aee95 278 dispc_set_tv_pclk(timings->pixelclock);
1e676248 279
ed1aa900 280 mutex_unlock(&hdmi.lock);
c3198a5e
M
281}
282
164ebdd1 283static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
0b450c31
TV
284 struct omap_video_timings *timings)
285{
ab0aee95 286 *timings = hdmi.cfg.timings;
0b450c31
TV
287}
288
e40402cf 289static void hdmi_dump_regs(struct seq_file *s)
162874d5
M
290{
291 mutex_lock(&hdmi.lock);
292
f8fb7d7b
WY
293 if (hdmi_runtime_get()) {
294 mutex_unlock(&hdmi.lock);
162874d5 295 return;
f8fb7d7b 296 }
162874d5 297
275cfa1a
AT
298 hdmi_wp_dump(&hdmi.wp, s);
299 hdmi_pll_dump(&hdmi.pll, s);
300 hdmi_phy_dump(&hdmi.phy, s);
301 hdmi4_core_dump(&hdmi.core, s);
162874d5
M
302
303 hdmi_runtime_put();
304 mutex_unlock(&hdmi.lock);
305}
306
164ebdd1 307static int read_edid(u8 *buf, int len)
47024565
TV
308{
309 int r;
310
311 mutex_lock(&hdmi.lock);
312
313 r = hdmi_runtime_get();
314 BUG_ON(r);
315
275cfa1a 316 r = hdmi4_read_edid(&hdmi.core, buf, len);
47024565
TV
317
318 hdmi_runtime_put();
319 mutex_unlock(&hdmi.lock);
320
321 return r;
322}
323
8a9d4626
JS
324static void hdmi_start_audio_stream(struct omap_hdmi *hd)
325{
326 hdmi_wp_audio_enable(&hd->wp, true);
327 hdmi4_audio_start(&hd->core, &hd->wp);
328}
329
330static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
331{
332 hdmi4_audio_stop(&hd->core, &hd->wp);
333 hdmi_wp_audio_enable(&hd->wp, false);
334}
335
164ebdd1 336static int hdmi_display_enable(struct omap_dss_device *dssdev)
c3198a5e 337{
1f68d9c4 338 struct omap_dss_device *out = &hdmi.output;
8a9d4626 339 unsigned long flags;
c3198a5e
M
340 int r = 0;
341
342 DSSDBG("ENTER hdmi_display_enable\n");
343
344 mutex_lock(&hdmi.lock);
345
b742648c 346 if (out->manager == NULL) {
cea87b92 347 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV
348 r = -ENODEV;
349 goto err0;
350 }
351
bb426fc9 352 r = hdmi_power_on_full(dssdev);
c3198a5e
M
353 if (r) {
354 DSSERR("failed to power on device\n");
d3923933 355 goto err0;
c3198a5e
M
356 }
357
8a9d4626
JS
358 if (hdmi.audio_configured) {
359 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
360 hdmi.cfg.timings.pixelclock);
361 if (r) {
362 DSSERR("Error restoring audio configuration: %d", r);
363 hdmi.audio_abort_cb(&hdmi.pdev->dev);
364 hdmi.audio_configured = false;
365 }
366 }
367
368 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
369 if (hdmi.audio_configured && hdmi.audio_playing)
370 hdmi_start_audio_stream(&hdmi);
4d594dff 371 hdmi.display_enabled = true;
8a9d4626 372 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
4d594dff 373
c3198a5e
M
374 mutex_unlock(&hdmi.lock);
375 return 0;
376
c3198a5e
M
377err0:
378 mutex_unlock(&hdmi.lock);
379 return r;
380}
381
164ebdd1 382static void hdmi_display_disable(struct omap_dss_device *dssdev)
c3198a5e 383{
8a9d4626
JS
384 unsigned long flags;
385
c3198a5e
M
386 DSSDBG("Enter hdmi_display_disable\n");
387
388 mutex_lock(&hdmi.lock);
389
8a9d4626
JS
390 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
391 hdmi_stop_audio_stream(&hdmi);
392 hdmi.display_enabled = false;
393 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
4d594dff 394
bb426fc9 395 hdmi_power_off_full(dssdev);
c3198a5e 396
c3198a5e
M
397 mutex_unlock(&hdmi.lock);
398}
399
164ebdd1 400static int hdmi_core_enable(struct omap_dss_device *dssdev)
4489823c
TV
401{
402 int r = 0;
403
404 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
405
406 mutex_lock(&hdmi.lock);
407
4489823c
TV
408 r = hdmi_power_on_core(dssdev);
409 if (r) {
410 DSSERR("failed to power on device\n");
411 goto err0;
412 }
413
414 mutex_unlock(&hdmi.lock);
415 return 0;
416
417err0:
418 mutex_unlock(&hdmi.lock);
419 return r;
420}
421
164ebdd1 422static void hdmi_core_disable(struct omap_dss_device *dssdev)
4489823c
TV
423{
424 DSSDBG("Enter omapdss_hdmi_core_disable\n");
425
426 mutex_lock(&hdmi.lock);
427
428 hdmi_power_off_core(dssdev);
429
430 mutex_unlock(&hdmi.lock);
431}
432
0b450c31
TV
433static int hdmi_connect(struct omap_dss_device *dssdev,
434 struct omap_dss_device *dst)
435{
436 struct omap_overlay_manager *mgr;
437 int r;
438
0b450c31
TV
439 r = hdmi_init_regulator();
440 if (r)
441 return r;
442
443 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
444 if (!mgr)
445 return -ENODEV;
446
447 r = dss_mgr_connect(mgr, dssdev);
448 if (r)
449 return r;
450
451 r = omapdss_output_set_device(dssdev, dst);
452 if (r) {
453 DSSERR("failed to connect output to new device: %s\n",
454 dst->name);
455 dss_mgr_disconnect(mgr, dssdev);
456 return r;
457 }
458
459 return 0;
460}
461
462static void hdmi_disconnect(struct omap_dss_device *dssdev,
463 struct omap_dss_device *dst)
464{
9560dc10 465 WARN_ON(dst != dssdev->dst);
0b450c31 466
9560dc10 467 if (dst != dssdev->dst)
0b450c31
TV
468 return;
469
470 omapdss_output_unset_device(dssdev);
471
472 if (dssdev->manager)
473 dss_mgr_disconnect(dssdev->manager, dssdev);
474}
475
476static int hdmi_read_edid(struct omap_dss_device *dssdev,
477 u8 *edid, int len)
478{
479 bool need_enable;
480 int r;
481
482 need_enable = hdmi.core_enabled == false;
483
484 if (need_enable) {
164ebdd1 485 r = hdmi_core_enable(dssdev);
0b450c31
TV
486 if (r)
487 return r;
488 }
489
164ebdd1 490 r = read_edid(edid, len);
0b450c31
TV
491
492 if (need_enable)
164ebdd1 493 hdmi_core_disable(dssdev);
0b450c31
TV
494
495 return r;
496}
497
ab0aee95
TV
498static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
499 const struct hdmi_avi_infoframe *avi)
500{
501 hdmi.cfg.infoframe = *avi;
502 return 0;
503}
504
505static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
506 bool hdmi_mode)
507{
508 hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
509 return 0;
510}
511
0b450c31
TV
512static const struct omapdss_hdmi_ops hdmi_ops = {
513 .connect = hdmi_connect,
514 .disconnect = hdmi_disconnect,
515
164ebdd1
TV
516 .enable = hdmi_display_enable,
517 .disable = hdmi_display_disable,
0b450c31 518
164ebdd1
TV
519 .check_timings = hdmi_display_check_timing,
520 .set_timings = hdmi_display_set_timing,
521 .get_timings = hdmi_display_get_timings,
0b450c31
TV
522
523 .read_edid = hdmi_read_edid,
ab0aee95
TV
524 .set_infoframe = hdmi_set_infoframe,
525 .set_hdmi_mode = hdmi_set_hdmi_mode,
0b450c31
TV
526};
527
17ae4e8c 528static void hdmi_init_output(struct platform_device *pdev)
81b87f51 529{
1f68d9c4 530 struct omap_dss_device *out = &hdmi.output;
81b87f51 531
1f68d9c4 532 out->dev = &pdev->dev;
81b87f51 533 out->id = OMAP_DSS_OUTPUT_HDMI;
1f68d9c4 534 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
7286a08f 535 out->name = "hdmi.0";
2eea5ae6 536 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
0b450c31 537 out->ops.hdmi = &hdmi_ops;
b7328e14 538 out->owner = THIS_MODULE;
81b87f51 539
5d47dbc8 540 omapdss_register_output(out);
81b87f51
AT
541}
542
39c1b7bf 543static void hdmi_uninit_output(struct platform_device *pdev)
81b87f51 544{
1f68d9c4 545 struct omap_dss_device *out = &hdmi.output;
81b87f51 546
5d47dbc8 547 omapdss_unregister_output(out);
81b87f51
AT
548}
549
2f5dc676
TV
550static int hdmi_probe_of(struct platform_device *pdev)
551{
552 struct device_node *node = pdev->dev.of_node;
553 struct device_node *ep;
554 int r;
555
556 ep = omapdss_of_get_first_endpoint(node);
557 if (!ep)
558 return 0;
559
560 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
561 if (r)
562 goto err;
563
564 of_node_put(ep);
565 return 0;
566
567err:
568 of_node_put(ep);
569 return r;
570}
571
4d594dff
JS
572/* Audio callbacks */
573static int hdmi_audio_startup(struct device *dev,
574 void (*abort_cb)(struct device *dev))
575{
576 struct omap_hdmi *hd = dev_get_drvdata(dev);
577 int ret = 0;
578
579 mutex_lock(&hd->lock);
580
581 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
582 ret = -EPERM;
583 goto out;
584 }
585
586 hd->audio_abort_cb = abort_cb;
587
588out:
589 mutex_unlock(&hd->lock);
590
591 return ret;
592}
593
594static int hdmi_audio_shutdown(struct device *dev)
595{
596 struct omap_hdmi *hd = dev_get_drvdata(dev);
597
598 mutex_lock(&hd->lock);
599 hd->audio_abort_cb = NULL;
8a9d4626
JS
600 hd->audio_configured = false;
601 hd->audio_playing = false;
4d594dff
JS
602 mutex_unlock(&hd->lock);
603
604 return 0;
605}
606
607static int hdmi_audio_start(struct device *dev)
608{
609 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 610 unsigned long flags;
4d594dff
JS
611
612 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
4d594dff 613
8a9d4626
JS
614 spin_lock_irqsave(&hd->audio_playing_lock, flags);
615
616 if (hd->display_enabled)
617 hdmi_start_audio_stream(hd);
618 hd->audio_playing = true;
4d594dff 619
8a9d4626 620 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
4d594dff
JS
621 return 0;
622}
623
624static void hdmi_audio_stop(struct device *dev)
625{
626 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 627 unsigned long flags;
4d594dff
JS
628
629 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
4d594dff 630
8a9d4626
JS
631 spin_lock_irqsave(&hd->audio_playing_lock, flags);
632
633 if (hd->display_enabled)
634 hdmi_stop_audio_stream(hd);
635 hd->audio_playing = false;
636
637 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
4d594dff
JS
638}
639
640static int hdmi_audio_config(struct device *dev,
641 struct omap_dss_audio *dss_audio)
642{
643 struct omap_hdmi *hd = dev_get_drvdata(dev);
644 int ret;
645
646 mutex_lock(&hd->lock);
647
648 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
649 ret = -EPERM;
650 goto out;
651 }
652
653 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,
654 hd->cfg.timings.pixelclock);
8a9d4626
JS
655 if (!ret) {
656 hd->audio_configured = true;
657 hd->audio_config = *dss_audio;
658 }
4d594dff
JS
659out:
660 mutex_unlock(&hd->lock);
661
662 return ret;
663}
664
665static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
666 .audio_startup = hdmi_audio_startup,
667 .audio_shutdown = hdmi_audio_shutdown,
668 .audio_start = hdmi_audio_start,
669 .audio_stop = hdmi_audio_stop,
670 .audio_config = hdmi_audio_config,
671};
672
673static int hdmi_audio_register(struct device *dev)
674{
675 struct omap_hdmi_audio_pdata pdata = {
676 .dev = dev,
677 .dss_version = omapdss_get_version(),
678 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
679 .ops = &hdmi_audio_ops,
680 };
681
682 hdmi.audio_pdev = platform_device_register_data(
683 dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
684 &pdata, sizeof(pdata));
685
686 if (IS_ERR(hdmi.audio_pdev))
687 return PTR_ERR(hdmi.audio_pdev);
688
689 return 0;
690}
691
c3198a5e 692/* HDMI HW IP initialisation */
736e60dd 693static int hdmi4_bind(struct device *dev, struct device *master, void *data)
c3198a5e 694{
736e60dd 695 struct platform_device *pdev = to_platform_device(dev);
38f3daf6 696 int r;
dcf5f729 697 int irq;
c3198a5e 698
c3198a5e 699 hdmi.pdev = pdev;
945514b5 700 dev_set_drvdata(&pdev->dev, &hdmi);
c3198a5e
M
701
702 mutex_init(&hdmi.lock);
8a9d4626 703 spin_lock_init(&hdmi.audio_playing_lock);
c3198a5e 704
2f5dc676
TV
705 if (pdev->dev.of_node) {
706 r = hdmi_probe_of(pdev);
707 if (r)
708 return r;
709 }
710
275cfa1a 711 r = hdmi_wp_init(pdev, &hdmi.wp);
f382d9eb
AT
712 if (r)
713 return r;
c3198a5e 714
03aafa2c 715 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
c1577c1e
AT
716 if (r)
717 return r;
718
275cfa1a 719 r = hdmi_phy_init(pdev, &hdmi.phy);
5cac5aee 720 if (r)
c84c3a5b 721 goto err;
ddb1d5ca 722
275cfa1a 723 r = hdmi4_core_init(pdev, &hdmi.core);
425f02fd 724 if (r)
c84c3a5b 725 goto err;
4fbafaf3 726
dcf5f729
TV
727 irq = platform_get_irq(pdev, 0);
728 if (irq < 0) {
729 DSSERR("platform_get_irq failed\n");
c84c3a5b
TV
730 r = -ENODEV;
731 goto err;
dcf5f729
TV
732 }
733
734 r = devm_request_threaded_irq(&pdev->dev, irq,
735 NULL, hdmi_irq_handler,
736 IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
737 if (r) {
738 DSSERR("HDMI IRQ request failed\n");
c84c3a5b 739 goto err;
dcf5f729
TV
740 }
741
4fbafaf3
TV
742 pm_runtime_enable(&pdev->dev);
743
002d368d
TV
744 hdmi_init_output(pdev);
745
4d594dff
JS
746 r = hdmi_audio_register(&pdev->dev);
747 if (r) {
748 DSSERR("Registering HDMI audio failed\n");
749 hdmi_uninit_output(pdev);
750 pm_runtime_disable(&pdev->dev);
751 return r;
752 }
753
e40402cf
TV
754 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
755
cca35017 756 return 0;
c84c3a5b
TV
757err:
758 hdmi_pll_uninit(&hdmi.pll);
759 return r;
cca35017
TV
760}
761
736e60dd 762static void hdmi4_unbind(struct device *dev, struct device *master, void *data)
c3198a5e 763{
736e60dd
TV
764 struct platform_device *pdev = to_platform_device(dev);
765
4d594dff
JS
766 if (hdmi.audio_pdev)
767 platform_device_unregister(hdmi.audio_pdev);
768
81b87f51
AT
769 hdmi_uninit_output(pdev);
770
c84c3a5b
TV
771 hdmi_pll_uninit(&hdmi.pll);
772
4fbafaf3 773 pm_runtime_disable(&pdev->dev);
736e60dd
TV
774}
775
776static const struct component_ops hdmi4_component_ops = {
777 .bind = hdmi4_bind,
778 .unbind = hdmi4_unbind,
779};
4fbafaf3 780
736e60dd
TV
781static int hdmi4_probe(struct platform_device *pdev)
782{
783 return component_add(&pdev->dev, &hdmi4_component_ops);
784}
785
786static int hdmi4_remove(struct platform_device *pdev)
787{
788 component_del(&pdev->dev, &hdmi4_component_ops);
c3198a5e
M
789 return 0;
790}
791
4fbafaf3
TV
792static int hdmi_runtime_suspend(struct device *dev)
793{
4fbafaf3 794 dispc_runtime_put();
4fbafaf3
TV
795
796 return 0;
797}
798
799static int hdmi_runtime_resume(struct device *dev)
800{
801 int r;
802
4fbafaf3
TV
803 r = dispc_runtime_get();
804 if (r < 0)
852f0838 805 return r;
4fbafaf3 806
4fbafaf3 807 return 0;
4fbafaf3
TV
808}
809
810static const struct dev_pm_ops hdmi_pm_ops = {
811 .runtime_suspend = hdmi_runtime_suspend,
812 .runtime_resume = hdmi_runtime_resume,
813};
814
0465616d
TV
815static const struct of_device_id hdmi_of_match[] = {
816 { .compatible = "ti,omap4-hdmi", },
817 {},
818};
819
c3198a5e 820static struct platform_driver omapdss_hdmihw_driver = {
736e60dd
TV
821 .probe = hdmi4_probe,
822 .remove = hdmi4_remove,
c3198a5e
M
823 .driver = {
824 .name = "omapdss_hdmi",
4fbafaf3 825 .pm = &hdmi_pm_ops,
0465616d 826 .of_match_table = hdmi_of_match,
422ccbd5 827 .suppress_bind_attrs = true,
c3198a5e
M
828 },
829};
830
ef26958a 831int __init hdmi4_init_platform_driver(void)
c3198a5e 832{
17ae4e8c 833 return platform_driver_register(&omapdss_hdmihw_driver);
c3198a5e
M
834}
835
ede92695 836void hdmi4_uninit_platform_driver(void)
c3198a5e 837{
04c742c3 838 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 839}