]>
Commit | Line | Data |
---|---|---|
c3198a5e | 1 | /* |
ef26958a | 2 | * HDMI interface DSS driver for TI's OMAP4 family of SoCs. |
c3198a5e M |
3 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
4 | * Authors: Yong Zhi | |
5 | * Mythri pk <mythripk@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "HDMI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/mutex.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/string.h> | |
24e6289c | 30 | #include <linux/platform_device.h> |
4fbafaf3 TV |
31 | #include <linux/pm_runtime.h> |
32 | #include <linux/clk.h> | |
cca35017 | 33 | #include <linux/gpio.h> |
17486943 | 34 | #include <linux/regulator/consumer.h> |
736e60dd | 35 | #include <linux/component.h> |
d9e32ecd | 36 | #include <linux/of.h> |
4d594dff | 37 | #include <sound/omap-hdmi-audio.h> |
c3198a5e | 38 | |
32043da7 | 39 | #include "omapdss.h" |
ef26958a | 40 | #include "hdmi4_core.h" |
c3198a5e | 41 | #include "dss.h" |
ad44cc32 | 42 | #include "dss_features.h" |
945514b5 | 43 | #include "hdmi.h" |
c3198a5e | 44 | |
945514b5 | 45 | static struct omap_hdmi hdmi; |
c3198a5e | 46 | |
4fbafaf3 TV |
47 | static int hdmi_runtime_get(void) |
48 | { | |
49 | int r; | |
50 | ||
51 | DSSDBG("hdmi_runtime_get\n"); | |
52 | ||
53 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
54 | WARN_ON(r < 0); | |
a247ce78 | 55 | if (r < 0) |
852f0838 | 56 | return r; |
a247ce78 AT |
57 | |
58 | return 0; | |
4fbafaf3 TV |
59 | } |
60 | ||
61 | static void hdmi_runtime_put(void) | |
62 | { | |
63 | int r; | |
64 | ||
65 | DSSDBG("hdmi_runtime_put\n"); | |
66 | ||
0eaf9f52 | 67 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
5be3aebd | 68 | WARN_ON(r < 0 && r != -ENOSYS); |
4fbafaf3 TV |
69 | } |
70 | ||
dcf5f729 TV |
71 | static irqreturn_t hdmi_irq_handler(int irq, void *data) |
72 | { | |
73 | struct hdmi_wp_data *wp = data; | |
74 | u32 irqstatus; | |
75 | ||
76 | irqstatus = hdmi_wp_get_irqstatus(wp); | |
77 | hdmi_wp_set_irqstatus(wp, irqstatus); | |
78 | ||
79 | if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && | |
80 | irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
81 | /* | |
82 | * If we get both connect and disconnect interrupts at the same | |
83 | * time, turn off the PHY, clear interrupts, and restart, which | |
84 | * raises connect interrupt if a cable is connected, or nothing | |
85 | * if cable is not connected. | |
86 | */ | |
87 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); | |
88 | ||
89 | hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | | |
90 | HDMI_IRQ_LINK_DISCONNECT); | |
91 | ||
92 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
93 | } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { | |
94 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); | |
95 | } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
96 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
97 | } | |
98 | ||
99 | return IRQ_HANDLED; | |
100 | } | |
101 | ||
e25001d8 TV |
102 | static int hdmi_init_regulator(void) |
103 | { | |
104 | struct regulator *reg; | |
105 | ||
945514b5 | 106 | if (hdmi.vdda_reg != NULL) |
e25001d8 TV |
107 | return 0; |
108 | ||
931d4bd6 | 109 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); |
e25001d8 TV |
110 | |
111 | if (IS_ERR(reg)) { | |
40359a9b | 112 | if (PTR_ERR(reg) != -EPROBE_DEFER) |
931d4bd6 | 113 | DSSERR("can't get VDDA regulator\n"); |
e25001d8 TV |
114 | return PTR_ERR(reg); |
115 | } | |
116 | ||
945514b5 | 117 | hdmi.vdda_reg = reg; |
e25001d8 TV |
118 | |
119 | return 0; | |
120 | } | |
121 | ||
bb426fc9 | 122 | static int hdmi_power_on_core(struct omap_dss_device *dssdev) |
c3198a5e | 123 | { |
46095b2d | 124 | int r; |
c3198a5e | 125 | |
945514b5 | 126 | r = regulator_enable(hdmi.vdda_reg); |
17486943 | 127 | if (r) |
164ebdd1 | 128 | return r; |
17486943 | 129 | |
4fbafaf3 TV |
130 | r = hdmi_runtime_get(); |
131 | if (r) | |
cca35017 | 132 | goto err_runtime_get; |
c3198a5e | 133 | |
bb426fc9 TV |
134 | /* Make selection of HDMI in DSS */ |
135 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
136 | ||
0b450c31 TV |
137 | hdmi.core_enabled = true; |
138 | ||
bb426fc9 TV |
139 | return 0; |
140 | ||
141 | err_runtime_get: | |
945514b5 | 142 | regulator_disable(hdmi.vdda_reg); |
164ebdd1 | 143 | |
bb426fc9 TV |
144 | return r; |
145 | } | |
146 | ||
147 | static void hdmi_power_off_core(struct omap_dss_device *dssdev) | |
148 | { | |
0b450c31 TV |
149 | hdmi.core_enabled = false; |
150 | ||
bb426fc9 | 151 | hdmi_runtime_put(); |
945514b5 | 152 | regulator_disable(hdmi.vdda_reg); |
bb426fc9 TV |
153 | } |
154 | ||
155 | static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |
156 | { | |
157 | int r; | |
4520ff28 | 158 | struct videomode *p; |
46e1ef3b | 159 | enum omap_channel channel = dssdev->dispc_channel; |
dcf5f729 | 160 | struct hdmi_wp_data *wp = &hdmi.wp; |
c84c3a5b | 161 | struct dss_pll_clock_info hdmi_cinfo = { 0 }; |
67d8ffdd | 162 | unsigned pc; |
bb426fc9 TV |
163 | |
164 | r = hdmi_power_on_core(dssdev); | |
165 | if (r) | |
166 | return r; | |
167 | ||
dcf5f729 TV |
168 | /* disable and clear irqs */ |
169 | hdmi_wp_clear_irqenable(wp, 0xffffffff); | |
170 | hdmi_wp_set_irqstatus(wp, 0xffffffff); | |
171 | ||
275cfa1a | 172 | p = &hdmi.cfg.timings; |
c3198a5e | 173 | |
fb7f3c43 PU |
174 | DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", p->hactive, |
175 | p->vactive); | |
c3198a5e | 176 | |
67d8ffdd | 177 | pc = p->pixelclock; |
531efb38 | 178 | if (p->flags & DISPLAY_FLAGS_DOUBLECLK) |
67d8ffdd TV |
179 | pc *= 2; |
180 | ||
c107751d TV |
181 | /* DSS_HDMI_TCLK is bitclk / 10 */ |
182 | pc *= 10; | |
183 | ||
c17dc0e3 TV |
184 | dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin), |
185 | pc, &hdmi_cinfo); | |
c3198a5e | 186 | |
c84c3a5b | 187 | r = dss_pll_enable(&hdmi.pll.pll); |
c3198a5e | 188 | if (r) { |
c2fbd061 | 189 | DSSERR("Failed to enable PLL\n"); |
cca35017 | 190 | goto err_pll_enable; |
c3198a5e M |
191 | } |
192 | ||
c84c3a5b | 193 | r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); |
c2fbd061 TV |
194 | if (r) { |
195 | DSSERR("Failed to configure PLL\n"); | |
196 | goto err_pll_cfg; | |
197 | } | |
198 | ||
c84c3a5b TV |
199 | r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco, |
200 | hdmi_cinfo.clkout[0]); | |
c3198a5e | 201 | if (r) { |
dcf5f729 TV |
202 | DSSDBG("Failed to configure PHY\n"); |
203 | goto err_phy_cfg; | |
c3198a5e M |
204 | } |
205 | ||
dcf5f729 TV |
206 | r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); |
207 | if (r) | |
208 | goto err_phy_pwr; | |
209 | ||
275cfa1a | 210 | hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); |
c3198a5e | 211 | |
c3198a5e | 212 | /* tv size */ |
46e1ef3b | 213 | dss_mgr_set_timings(channel, p); |
c3198a5e | 214 | |
46e1ef3b | 215 | r = dss_mgr_enable(channel); |
33ca237f TV |
216 | if (r) |
217 | goto err_mgr_enable; | |
3870c909 | 218 | |
4e4b53ce TV |
219 | r = hdmi_wp_video_start(&hdmi.wp); |
220 | if (r) | |
221 | goto err_vid_enable; | |
222 | ||
dcf5f729 TV |
223 | hdmi_wp_set_irqenable(wp, |
224 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | |
225 | ||
c3198a5e | 226 | return 0; |
33ca237f | 227 | |
c0456be3 | 228 | err_vid_enable: |
46e1ef3b | 229 | dss_mgr_disable(channel); |
4e4b53ce | 230 | err_mgr_enable: |
dcf5f729 TV |
231 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); |
232 | err_phy_pwr: | |
9bba13f0 | 233 | err_phy_cfg: |
c2fbd061 | 234 | err_pll_cfg: |
c84c3a5b | 235 | dss_pll_disable(&hdmi.pll.pll); |
cca35017 | 236 | err_pll_enable: |
bb426fc9 | 237 | hdmi_power_off_core(dssdev); |
c3198a5e M |
238 | return -EIO; |
239 | } | |
240 | ||
bb426fc9 | 241 | static void hdmi_power_off_full(struct omap_dss_device *dssdev) |
c3198a5e | 242 | { |
46e1ef3b | 243 | enum omap_channel channel = dssdev->dispc_channel; |
cea87b92 | 244 | |
dcf5f729 TV |
245 | hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); |
246 | ||
275cfa1a | 247 | hdmi_wp_video_stop(&hdmi.wp); |
dcf5f729 | 248 | |
46e1ef3b | 249 | dss_mgr_disable(channel); |
4e4b53ce | 250 | |
dcf5f729 TV |
251 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); |
252 | ||
c84c3a5b | 253 | dss_pll_disable(&hdmi.pll.pll); |
17486943 | 254 | |
bb426fc9 | 255 | hdmi_power_off_core(dssdev); |
c3198a5e M |
256 | } |
257 | ||
164ebdd1 | 258 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, |
4520ff28 | 259 | struct videomode *timings) |
c3198a5e | 260 | { |
46e1ef3b | 261 | if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings)) |
c3198a5e | 262 | return -EINVAL; |
c3198a5e M |
263 | |
264 | return 0; | |
c3198a5e M |
265 | } |
266 | ||
164ebdd1 | 267 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, |
4520ff28 | 268 | struct videomode *timings) |
c3198a5e | 269 | { |
ed1aa900 AT |
270 | mutex_lock(&hdmi.lock); |
271 | ||
ab0aee95 | 272 | hdmi.cfg.timings = *timings; |
5391e87d | 273 | |
ab0aee95 | 274 | dispc_set_tv_pclk(timings->pixelclock); |
1e676248 | 275 | |
ed1aa900 | 276 | mutex_unlock(&hdmi.lock); |
c3198a5e M |
277 | } |
278 | ||
164ebdd1 | 279 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, |
4520ff28 | 280 | struct videomode *timings) |
0b450c31 | 281 | { |
ab0aee95 | 282 | *timings = hdmi.cfg.timings; |
0b450c31 TV |
283 | } |
284 | ||
e40402cf | 285 | static void hdmi_dump_regs(struct seq_file *s) |
162874d5 M |
286 | { |
287 | mutex_lock(&hdmi.lock); | |
288 | ||
f8fb7d7b WY |
289 | if (hdmi_runtime_get()) { |
290 | mutex_unlock(&hdmi.lock); | |
162874d5 | 291 | return; |
f8fb7d7b | 292 | } |
162874d5 | 293 | |
275cfa1a AT |
294 | hdmi_wp_dump(&hdmi.wp, s); |
295 | hdmi_pll_dump(&hdmi.pll, s); | |
296 | hdmi_phy_dump(&hdmi.phy, s); | |
297 | hdmi4_core_dump(&hdmi.core, s); | |
162874d5 M |
298 | |
299 | hdmi_runtime_put(); | |
300 | mutex_unlock(&hdmi.lock); | |
301 | } | |
302 | ||
164ebdd1 | 303 | static int read_edid(u8 *buf, int len) |
47024565 TV |
304 | { |
305 | int r; | |
306 | ||
307 | mutex_lock(&hdmi.lock); | |
308 | ||
309 | r = hdmi_runtime_get(); | |
310 | BUG_ON(r); | |
311 | ||
275cfa1a | 312 | r = hdmi4_read_edid(&hdmi.core, buf, len); |
47024565 TV |
313 | |
314 | hdmi_runtime_put(); | |
315 | mutex_unlock(&hdmi.lock); | |
316 | ||
317 | return r; | |
318 | } | |
319 | ||
8a9d4626 JS |
320 | static void hdmi_start_audio_stream(struct omap_hdmi *hd) |
321 | { | |
322 | hdmi_wp_audio_enable(&hd->wp, true); | |
323 | hdmi4_audio_start(&hd->core, &hd->wp); | |
324 | } | |
325 | ||
326 | static void hdmi_stop_audio_stream(struct omap_hdmi *hd) | |
327 | { | |
328 | hdmi4_audio_stop(&hd->core, &hd->wp); | |
329 | hdmi_wp_audio_enable(&hd->wp, false); | |
330 | } | |
331 | ||
164ebdd1 | 332 | static int hdmi_display_enable(struct omap_dss_device *dssdev) |
c3198a5e | 333 | { |
1f68d9c4 | 334 | struct omap_dss_device *out = &hdmi.output; |
8a9d4626 | 335 | unsigned long flags; |
c3198a5e M |
336 | int r = 0; |
337 | ||
338 | DSSDBG("ENTER hdmi_display_enable\n"); | |
339 | ||
340 | mutex_lock(&hdmi.lock); | |
341 | ||
f1504ad0 | 342 | if (!out->dispc_channel_connected) { |
cea87b92 | 343 | DSSERR("failed to enable display: no output/manager\n"); |
05e1d606 TV |
344 | r = -ENODEV; |
345 | goto err0; | |
346 | } | |
347 | ||
bb426fc9 | 348 | r = hdmi_power_on_full(dssdev); |
c3198a5e M |
349 | if (r) { |
350 | DSSERR("failed to power on device\n"); | |
d3923933 | 351 | goto err0; |
c3198a5e M |
352 | } |
353 | ||
8a9d4626 JS |
354 | if (hdmi.audio_configured) { |
355 | r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, | |
356 | hdmi.cfg.timings.pixelclock); | |
357 | if (r) { | |
358 | DSSERR("Error restoring audio configuration: %d", r); | |
359 | hdmi.audio_abort_cb(&hdmi.pdev->dev); | |
360 | hdmi.audio_configured = false; | |
361 | } | |
362 | } | |
363 | ||
364 | spin_lock_irqsave(&hdmi.audio_playing_lock, flags); | |
365 | if (hdmi.audio_configured && hdmi.audio_playing) | |
366 | hdmi_start_audio_stream(&hdmi); | |
4d594dff | 367 | hdmi.display_enabled = true; |
8a9d4626 | 368 | spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); |
4d594dff | 369 | |
c3198a5e M |
370 | mutex_unlock(&hdmi.lock); |
371 | return 0; | |
372 | ||
c3198a5e M |
373 | err0: |
374 | mutex_unlock(&hdmi.lock); | |
375 | return r; | |
376 | } | |
377 | ||
164ebdd1 | 378 | static void hdmi_display_disable(struct omap_dss_device *dssdev) |
c3198a5e | 379 | { |
8a9d4626 JS |
380 | unsigned long flags; |
381 | ||
c3198a5e M |
382 | DSSDBG("Enter hdmi_display_disable\n"); |
383 | ||
384 | mutex_lock(&hdmi.lock); | |
385 | ||
8a9d4626 JS |
386 | spin_lock_irqsave(&hdmi.audio_playing_lock, flags); |
387 | hdmi_stop_audio_stream(&hdmi); | |
388 | hdmi.display_enabled = false; | |
389 | spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); | |
4d594dff | 390 | |
bb426fc9 | 391 | hdmi_power_off_full(dssdev); |
c3198a5e | 392 | |
c3198a5e M |
393 | mutex_unlock(&hdmi.lock); |
394 | } | |
395 | ||
164ebdd1 | 396 | static int hdmi_core_enable(struct omap_dss_device *dssdev) |
4489823c TV |
397 | { |
398 | int r = 0; | |
399 | ||
400 | DSSDBG("ENTER omapdss_hdmi_core_enable\n"); | |
401 | ||
402 | mutex_lock(&hdmi.lock); | |
403 | ||
4489823c TV |
404 | r = hdmi_power_on_core(dssdev); |
405 | if (r) { | |
406 | DSSERR("failed to power on device\n"); | |
407 | goto err0; | |
408 | } | |
409 | ||
410 | mutex_unlock(&hdmi.lock); | |
411 | return 0; | |
412 | ||
413 | err0: | |
414 | mutex_unlock(&hdmi.lock); | |
415 | return r; | |
416 | } | |
417 | ||
164ebdd1 | 418 | static void hdmi_core_disable(struct omap_dss_device *dssdev) |
4489823c TV |
419 | { |
420 | DSSDBG("Enter omapdss_hdmi_core_disable\n"); | |
421 | ||
422 | mutex_lock(&hdmi.lock); | |
423 | ||
424 | hdmi_power_off_core(dssdev); | |
425 | ||
426 | mutex_unlock(&hdmi.lock); | |
427 | } | |
428 | ||
0b450c31 TV |
429 | static int hdmi_connect(struct omap_dss_device *dssdev, |
430 | struct omap_dss_device *dst) | |
431 | { | |
46e1ef3b | 432 | enum omap_channel channel = dssdev->dispc_channel; |
0b450c31 TV |
433 | int r; |
434 | ||
0b450c31 TV |
435 | r = hdmi_init_regulator(); |
436 | if (r) | |
437 | return r; | |
438 | ||
46e1ef3b | 439 | r = dss_mgr_connect(channel, dssdev); |
0b450c31 TV |
440 | if (r) |
441 | return r; | |
442 | ||
443 | r = omapdss_output_set_device(dssdev, dst); | |
444 | if (r) { | |
445 | DSSERR("failed to connect output to new device: %s\n", | |
446 | dst->name); | |
46e1ef3b | 447 | dss_mgr_disconnect(channel, dssdev); |
0b450c31 TV |
448 | return r; |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static void hdmi_disconnect(struct omap_dss_device *dssdev, | |
455 | struct omap_dss_device *dst) | |
456 | { | |
46e1ef3b TV |
457 | enum omap_channel channel = dssdev->dispc_channel; |
458 | ||
9560dc10 | 459 | WARN_ON(dst != dssdev->dst); |
0b450c31 | 460 | |
9560dc10 | 461 | if (dst != dssdev->dst) |
0b450c31 TV |
462 | return; |
463 | ||
464 | omapdss_output_unset_device(dssdev); | |
465 | ||
46e1ef3b | 466 | dss_mgr_disconnect(channel, dssdev); |
0b450c31 TV |
467 | } |
468 | ||
469 | static int hdmi_read_edid(struct omap_dss_device *dssdev, | |
470 | u8 *edid, int len) | |
471 | { | |
472 | bool need_enable; | |
473 | int r; | |
474 | ||
475 | need_enable = hdmi.core_enabled == false; | |
476 | ||
477 | if (need_enable) { | |
164ebdd1 | 478 | r = hdmi_core_enable(dssdev); |
0b450c31 TV |
479 | if (r) |
480 | return r; | |
481 | } | |
482 | ||
164ebdd1 | 483 | r = read_edid(edid, len); |
0b450c31 TV |
484 | |
485 | if (need_enable) | |
164ebdd1 | 486 | hdmi_core_disable(dssdev); |
0b450c31 TV |
487 | |
488 | return r; | |
489 | } | |
490 | ||
ab0aee95 TV |
491 | static int hdmi_set_infoframe(struct omap_dss_device *dssdev, |
492 | const struct hdmi_avi_infoframe *avi) | |
493 | { | |
494 | hdmi.cfg.infoframe = *avi; | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, | |
499 | bool hdmi_mode) | |
500 | { | |
501 | hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; | |
502 | return 0; | |
503 | } | |
504 | ||
0b450c31 TV |
505 | static const struct omapdss_hdmi_ops hdmi_ops = { |
506 | .connect = hdmi_connect, | |
507 | .disconnect = hdmi_disconnect, | |
508 | ||
164ebdd1 TV |
509 | .enable = hdmi_display_enable, |
510 | .disable = hdmi_display_disable, | |
0b450c31 | 511 | |
164ebdd1 TV |
512 | .check_timings = hdmi_display_check_timing, |
513 | .set_timings = hdmi_display_set_timing, | |
514 | .get_timings = hdmi_display_get_timings, | |
0b450c31 TV |
515 | |
516 | .read_edid = hdmi_read_edid, | |
ab0aee95 TV |
517 | .set_infoframe = hdmi_set_infoframe, |
518 | .set_hdmi_mode = hdmi_set_hdmi_mode, | |
0b450c31 TV |
519 | }; |
520 | ||
17ae4e8c | 521 | static void hdmi_init_output(struct platform_device *pdev) |
81b87f51 | 522 | { |
1f68d9c4 | 523 | struct omap_dss_device *out = &hdmi.output; |
81b87f51 | 524 | |
1f68d9c4 | 525 | out->dev = &pdev->dev; |
81b87f51 | 526 | out->id = OMAP_DSS_OUTPUT_HDMI; |
1f68d9c4 | 527 | out->output_type = OMAP_DISPLAY_TYPE_HDMI; |
7286a08f | 528 | out->name = "hdmi.0"; |
2eea5ae6 | 529 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; |
0b450c31 | 530 | out->ops.hdmi = &hdmi_ops; |
b7328e14 | 531 | out->owner = THIS_MODULE; |
81b87f51 | 532 | |
5d47dbc8 | 533 | omapdss_register_output(out); |
81b87f51 AT |
534 | } |
535 | ||
39c1b7bf | 536 | static void hdmi_uninit_output(struct platform_device *pdev) |
81b87f51 | 537 | { |
1f68d9c4 | 538 | struct omap_dss_device *out = &hdmi.output; |
81b87f51 | 539 | |
5d47dbc8 | 540 | omapdss_unregister_output(out); |
81b87f51 AT |
541 | } |
542 | ||
2f5dc676 TV |
543 | static int hdmi_probe_of(struct platform_device *pdev) |
544 | { | |
545 | struct device_node *node = pdev->dev.of_node; | |
546 | struct device_node *ep; | |
547 | int r; | |
548 | ||
549 | ep = omapdss_of_get_first_endpoint(node); | |
550 | if (!ep) | |
551 | return 0; | |
552 | ||
553 | r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); | |
554 | if (r) | |
555 | goto err; | |
556 | ||
557 | of_node_put(ep); | |
558 | return 0; | |
559 | ||
560 | err: | |
561 | of_node_put(ep); | |
562 | return r; | |
563 | } | |
564 | ||
4d594dff JS |
565 | /* Audio callbacks */ |
566 | static int hdmi_audio_startup(struct device *dev, | |
567 | void (*abort_cb)(struct device *dev)) | |
568 | { | |
569 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
570 | int ret = 0; | |
571 | ||
572 | mutex_lock(&hd->lock); | |
573 | ||
574 | if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { | |
575 | ret = -EPERM; | |
576 | goto out; | |
577 | } | |
578 | ||
579 | hd->audio_abort_cb = abort_cb; | |
580 | ||
581 | out: | |
582 | mutex_unlock(&hd->lock); | |
583 | ||
584 | return ret; | |
585 | } | |
586 | ||
587 | static int hdmi_audio_shutdown(struct device *dev) | |
588 | { | |
589 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
590 | ||
591 | mutex_lock(&hd->lock); | |
592 | hd->audio_abort_cb = NULL; | |
8a9d4626 JS |
593 | hd->audio_configured = false; |
594 | hd->audio_playing = false; | |
4d594dff JS |
595 | mutex_unlock(&hd->lock); |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | static int hdmi_audio_start(struct device *dev) | |
601 | { | |
602 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
8a9d4626 | 603 | unsigned long flags; |
4d594dff JS |
604 | |
605 | WARN_ON(!hdmi_mode_has_audio(&hd->cfg)); | |
4d594dff | 606 | |
8a9d4626 JS |
607 | spin_lock_irqsave(&hd->audio_playing_lock, flags); |
608 | ||
609 | if (hd->display_enabled) | |
610 | hdmi_start_audio_stream(hd); | |
611 | hd->audio_playing = true; | |
4d594dff | 612 | |
8a9d4626 | 613 | spin_unlock_irqrestore(&hd->audio_playing_lock, flags); |
4d594dff JS |
614 | return 0; |
615 | } | |
616 | ||
617 | static void hdmi_audio_stop(struct device *dev) | |
618 | { | |
619 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
8a9d4626 | 620 | unsigned long flags; |
4d594dff JS |
621 | |
622 | WARN_ON(!hdmi_mode_has_audio(&hd->cfg)); | |
4d594dff | 623 | |
8a9d4626 JS |
624 | spin_lock_irqsave(&hd->audio_playing_lock, flags); |
625 | ||
626 | if (hd->display_enabled) | |
627 | hdmi_stop_audio_stream(hd); | |
628 | hd->audio_playing = false; | |
629 | ||
630 | spin_unlock_irqrestore(&hd->audio_playing_lock, flags); | |
4d594dff JS |
631 | } |
632 | ||
633 | static int hdmi_audio_config(struct device *dev, | |
634 | struct omap_dss_audio *dss_audio) | |
635 | { | |
636 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
637 | int ret; | |
638 | ||
639 | mutex_lock(&hd->lock); | |
640 | ||
641 | if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { | |
642 | ret = -EPERM; | |
643 | goto out; | |
644 | } | |
645 | ||
646 | ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio, | |
647 | hd->cfg.timings.pixelclock); | |
8a9d4626 JS |
648 | if (!ret) { |
649 | hd->audio_configured = true; | |
650 | hd->audio_config = *dss_audio; | |
651 | } | |
4d594dff JS |
652 | out: |
653 | mutex_unlock(&hd->lock); | |
654 | ||
655 | return ret; | |
656 | } | |
657 | ||
658 | static const struct omap_hdmi_audio_ops hdmi_audio_ops = { | |
659 | .audio_startup = hdmi_audio_startup, | |
660 | .audio_shutdown = hdmi_audio_shutdown, | |
661 | .audio_start = hdmi_audio_start, | |
662 | .audio_stop = hdmi_audio_stop, | |
663 | .audio_config = hdmi_audio_config, | |
664 | }; | |
665 | ||
666 | static int hdmi_audio_register(struct device *dev) | |
667 | { | |
668 | struct omap_hdmi_audio_pdata pdata = { | |
669 | .dev = dev, | |
670 | .dss_version = omapdss_get_version(), | |
671 | .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), | |
672 | .ops = &hdmi_audio_ops, | |
673 | }; | |
674 | ||
675 | hdmi.audio_pdev = platform_device_register_data( | |
676 | dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO, | |
677 | &pdata, sizeof(pdata)); | |
678 | ||
679 | if (IS_ERR(hdmi.audio_pdev)) | |
680 | return PTR_ERR(hdmi.audio_pdev); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
c3198a5e | 685 | /* HDMI HW IP initialisation */ |
736e60dd | 686 | static int hdmi4_bind(struct device *dev, struct device *master, void *data) |
c3198a5e | 687 | { |
736e60dd | 688 | struct platform_device *pdev = to_platform_device(dev); |
38f3daf6 | 689 | int r; |
dcf5f729 | 690 | int irq; |
c3198a5e | 691 | |
c3198a5e | 692 | hdmi.pdev = pdev; |
945514b5 | 693 | dev_set_drvdata(&pdev->dev, &hdmi); |
c3198a5e M |
694 | |
695 | mutex_init(&hdmi.lock); | |
8a9d4626 | 696 | spin_lock_init(&hdmi.audio_playing_lock); |
c3198a5e | 697 | |
2f5dc676 TV |
698 | if (pdev->dev.of_node) { |
699 | r = hdmi_probe_of(pdev); | |
700 | if (r) | |
701 | return r; | |
702 | } | |
703 | ||
275cfa1a | 704 | r = hdmi_wp_init(pdev, &hdmi.wp); |
f382d9eb AT |
705 | if (r) |
706 | return r; | |
c3198a5e | 707 | |
03aafa2c | 708 | r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); |
c1577c1e AT |
709 | if (r) |
710 | return r; | |
711 | ||
275cfa1a | 712 | r = hdmi_phy_init(pdev, &hdmi.phy); |
5cac5aee | 713 | if (r) |
c84c3a5b | 714 | goto err; |
ddb1d5ca | 715 | |
275cfa1a | 716 | r = hdmi4_core_init(pdev, &hdmi.core); |
425f02fd | 717 | if (r) |
c84c3a5b | 718 | goto err; |
4fbafaf3 | 719 | |
dcf5f729 TV |
720 | irq = platform_get_irq(pdev, 0); |
721 | if (irq < 0) { | |
722 | DSSERR("platform_get_irq failed\n"); | |
c84c3a5b TV |
723 | r = -ENODEV; |
724 | goto err; | |
dcf5f729 TV |
725 | } |
726 | ||
727 | r = devm_request_threaded_irq(&pdev->dev, irq, | |
728 | NULL, hdmi_irq_handler, | |
729 | IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); | |
730 | if (r) { | |
731 | DSSERR("HDMI IRQ request failed\n"); | |
c84c3a5b | 732 | goto err; |
dcf5f729 TV |
733 | } |
734 | ||
4fbafaf3 TV |
735 | pm_runtime_enable(&pdev->dev); |
736 | ||
002d368d TV |
737 | hdmi_init_output(pdev); |
738 | ||
4d594dff JS |
739 | r = hdmi_audio_register(&pdev->dev); |
740 | if (r) { | |
741 | DSSERR("Registering HDMI audio failed\n"); | |
742 | hdmi_uninit_output(pdev); | |
743 | pm_runtime_disable(&pdev->dev); | |
744 | return r; | |
745 | } | |
746 | ||
e40402cf TV |
747 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
748 | ||
cca35017 | 749 | return 0; |
c84c3a5b TV |
750 | err: |
751 | hdmi_pll_uninit(&hdmi.pll); | |
752 | return r; | |
cca35017 TV |
753 | } |
754 | ||
736e60dd | 755 | static void hdmi4_unbind(struct device *dev, struct device *master, void *data) |
c3198a5e | 756 | { |
736e60dd TV |
757 | struct platform_device *pdev = to_platform_device(dev); |
758 | ||
4d594dff JS |
759 | if (hdmi.audio_pdev) |
760 | platform_device_unregister(hdmi.audio_pdev); | |
761 | ||
81b87f51 AT |
762 | hdmi_uninit_output(pdev); |
763 | ||
c84c3a5b TV |
764 | hdmi_pll_uninit(&hdmi.pll); |
765 | ||
4fbafaf3 | 766 | pm_runtime_disable(&pdev->dev); |
736e60dd TV |
767 | } |
768 | ||
769 | static const struct component_ops hdmi4_component_ops = { | |
770 | .bind = hdmi4_bind, | |
771 | .unbind = hdmi4_unbind, | |
772 | }; | |
4fbafaf3 | 773 | |
736e60dd TV |
774 | static int hdmi4_probe(struct platform_device *pdev) |
775 | { | |
776 | return component_add(&pdev->dev, &hdmi4_component_ops); | |
777 | } | |
778 | ||
779 | static int hdmi4_remove(struct platform_device *pdev) | |
780 | { | |
781 | component_del(&pdev->dev, &hdmi4_component_ops); | |
c3198a5e M |
782 | return 0; |
783 | } | |
784 | ||
4fbafaf3 TV |
785 | static int hdmi_runtime_suspend(struct device *dev) |
786 | { | |
4fbafaf3 | 787 | dispc_runtime_put(); |
4fbafaf3 TV |
788 | |
789 | return 0; | |
790 | } | |
791 | ||
792 | static int hdmi_runtime_resume(struct device *dev) | |
793 | { | |
794 | int r; | |
795 | ||
4fbafaf3 TV |
796 | r = dispc_runtime_get(); |
797 | if (r < 0) | |
852f0838 | 798 | return r; |
4fbafaf3 | 799 | |
4fbafaf3 | 800 | return 0; |
4fbafaf3 TV |
801 | } |
802 | ||
803 | static const struct dev_pm_ops hdmi_pm_ops = { | |
804 | .runtime_suspend = hdmi_runtime_suspend, | |
805 | .runtime_resume = hdmi_runtime_resume, | |
806 | }; | |
807 | ||
0465616d TV |
808 | static const struct of_device_id hdmi_of_match[] = { |
809 | { .compatible = "ti,omap4-hdmi", }, | |
810 | {}, | |
811 | }; | |
812 | ||
c3198a5e | 813 | static struct platform_driver omapdss_hdmihw_driver = { |
736e60dd TV |
814 | .probe = hdmi4_probe, |
815 | .remove = hdmi4_remove, | |
c3198a5e M |
816 | .driver = { |
817 | .name = "omapdss_hdmi", | |
4fbafaf3 | 818 | .pm = &hdmi_pm_ops, |
0465616d | 819 | .of_match_table = hdmi_of_match, |
422ccbd5 | 820 | .suppress_bind_attrs = true, |
c3198a5e M |
821 | }, |
822 | }; | |
823 | ||
ef26958a | 824 | int __init hdmi4_init_platform_driver(void) |
c3198a5e | 825 | { |
17ae4e8c | 826 | return platform_driver_register(&omapdss_hdmihw_driver); |
c3198a5e M |
827 | } |
828 | ||
ede92695 | 829 | void hdmi4_uninit_platform_driver(void) |
c3198a5e | 830 | { |
04c742c3 | 831 | platform_driver_unregister(&omapdss_hdmihw_driver); |
c3198a5e | 832 | } |