[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / omapdrm / dss / hdmi4_cec.c

/*
 * HDMI CEC
 *
 * Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
 * Authors: Yong Zhi
 *	Mythri pk <mythripk@ti.com>
 *
 * Heavily modified to use the linux CEC framework:
 *
 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
 *
 * This program is free software; you may redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "dss.h"
#include "hdmi.h"
#include "hdmi4_core.h"
#include "hdmi4_cec.h"

/* HDMI CEC */
#define HDMI_CEC_DEV_ID                         0x900
#define HDMI_CEC_SPEC                           0x904

/* Not really a debug register, more a low-level control register */
#define HDMI_CEC_DBG_3                          0x91C
#define HDMI_CEC_TX_INIT                        0x920
#define HDMI_CEC_TX_DEST                        0x924
#define HDMI_CEC_SETUP                          0x938
#define HDMI_CEC_TX_COMMAND                     0x93C
#define HDMI_CEC_TX_OPERAND                     0x940
#define HDMI_CEC_TRANSMIT_DATA                  0x97C
#define HDMI_CEC_CA_7_0                         0x988
#define HDMI_CEC_CA_15_8                        0x98C
#define HDMI_CEC_INT_STATUS_0                   0x998
#define HDMI_CEC_INT_STATUS_1                   0x99C
#define HDMI_CEC_INT_ENABLE_0                   0x990
#define HDMI_CEC_INT_ENABLE_1                   0x994
#define HDMI_CEC_RX_CONTROL                     0x9B0
#define HDMI_CEC_RX_COUNT                       0x9B4
#define HDMI_CEC_RX_CMD_HEADER                  0x9B8
#define HDMI_CEC_RX_COMMAND                     0x9BC
#define HDMI_CEC_RX_OPERAND                     0x9C0

#define HDMI_CEC_TX_FIFO_INT_MASK		0x64
#define HDMI_CEC_RETRANSMIT_CNT_INT_MASK	0x2

#define HDMI_CORE_CEC_RETRY    200

static void hdmi_cec_received_msg(struct hdmi_core_data *core)
{
	u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;

	/* While there are CEC frames in the FIFO */
	while (cnt & 0x70) {
		/* and the frame doesn't have an error */
		if (!(cnt & 0x80)) {
			struct cec_msg msg = {};
			unsigned int i;

			/* then read the message */
			msg.len = cnt & 0xf;
			if (msg.len > CEC_MAX_MSG_SIZE - 2)
				msg.len = CEC_MAX_MSG_SIZE - 2;
			msg.msg[0] = hdmi_read_reg(core->base,
						   HDMI_CEC_RX_CMD_HEADER);
			msg.msg[1] = hdmi_read_reg(core->base,
						   HDMI_CEC_RX_COMMAND);
			for (i = 0; i < msg.len; i++) {
				unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4;

				msg.msg[2 + i] =
					hdmi_read_reg(core->base, reg);
			}
			msg.len += 2;
			cec_received_msg(core->adap, &msg);
		}
		/* Clear the current frame from the FIFO */
		hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
		/* Wait until the current frame is cleared */
		while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
			udelay(1);
		/*
		 * Re-read the count register and loop to see if there are
		 * more messages in the FIFO.
		 */
		cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
	}
}

void hdmi4_cec_irq(struct hdmi_core_data *core)
{
	u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
	u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);

	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);

	if (stat0 & 0x20) {
		cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
				  0, 0, 0, 0);
		REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
	} else if (stat1 & 0x02) {
		u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);

		cec_transmit_done(core->adap,
				  CEC_TX_STATUS_NACK |
				  CEC_TX_STATUS_MAX_RETRIES,
				  0, (dbg3 >> 4) & 7, 0, 0);
		REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
	}
	if (stat0 & 0x02)
		hdmi_cec_received_msg(core);
}

static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
{
	struct hdmi_core_data *core = cec_get_drvdata(adap);
	int retry = HDMI_CORE_CEC_RETRY;
	int temp;

	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
	while (retry) {
		temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
		if (FLD_GET(temp, 7, 7) == 0)
			break;
		retry--;
	}
	return retry != 0;
}

static bool hdmi_cec_clear_rx_fifo(struct cec_adapter *adap)
{
	struct hdmi_core_data *core = cec_get_drvdata(adap);
	int retry = HDMI_CORE_CEC_RETRY;
	int temp;

	hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
	retry = HDMI_CORE_CEC_RETRY;
	while (retry) {
		temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
		if (FLD_GET(temp, 1, 0) == 0)
			break;
		retry--;
	}
	return retry != 0;
}

static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
{
	struct hdmi_core_data *core = cec_get_drvdata(adap);
	int temp, err;

	if (!enable) {
		hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
		hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
		REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
		hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
		hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
		hdmi4_core_disable(NULL);
		return 0;
	}
	err = hdmi4_core_enable(NULL);
	if (err)
		return err;

	/* Clear TX FIFO */
	if (!hdmi_cec_clear_tx_fifo(adap)) {
		pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
		return -EIO;
	}

	/* Clear RX FIFO */
	if (!hdmi_cec_clear_rx_fifo(adap)) {
		pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
		return -EIO;
	}

	/* Clear CEC interrupts */
	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
		hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
		hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));

	/* Enable HDMI core interrupts */
	hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);
	/* Unmask CEC interrupt */
	REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
	/*
	 * Enable CEC interrupts:
	 * Transmit Buffer Full/Empty Change event
	 * Receiver FIFO Not Empty event
	 */
	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22);
	/*
	 * Enable CEC interrupts:
	 * Frame Retransmit Count Exceeded event
	 */
	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02);

	/* cec calibration enable (self clearing) */
	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
	msleep(20);
	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);

	temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
	if (FLD_GET(temp, 4, 4) != 0) {
		temp = FLD_MOD(temp, 0, 4, 4);
		hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);

		/*
		 * If we enabled CEC in middle of a CEC message on the bus,
		 * we could have start bit irregularity and/or short
		 * pulse event. Clear them now.
		 */
		temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
		temp = FLD_MOD(0x0, 0x5, 2, 0);
		hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
	}
	return 0;
}

static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
{
	struct hdmi_core_data *core = cec_get_drvdata(adap);
	u32 v;

	if (log_addr == CEC_LOG_ADDR_INVALID) {
		hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
		hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
		return 0;
	}
	if (log_addr <= 7) {
		v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
		v |= 1 << log_addr;
		hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
	} else {
		v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
		v |= 1 << (log_addr - 8);
		hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
	}
	return 0;
}

static int hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
				   u32 signal_free_time, struct cec_msg *msg)
{
	struct hdmi_core_data *core = cec_get_drvdata(adap);
	int temp;
	u32 i;

	/* Clear TX FIFO */
	if (!hdmi_cec_clear_tx_fifo(adap)) {
		pr_err("cec-%s: could not clear TX FIFO for transmit\n",
		       adap->name);
		return -EIO;
	}

	/* Clear TX interrupts */
	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
		       HDMI_CEC_TX_FIFO_INT_MASK);

	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
		       HDMI_CEC_RETRANSMIT_CNT_INT_MASK);

	/* Set the retry count */
	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);

	/* Set the initiator addresses */
	hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));

	/* Set destination id */
	temp = cec_msg_destination(msg);
	if (msg->len == 1)
		temp |= 0x80;
	hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
	if (msg->len == 1)
		return 0;

	/* Setup command and arguments for the command */
	hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);

	for (i = 0; i < msg->len - 2; i++)
		hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
			       msg->msg[2 + i]);

	/* Operand count */
	hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
		       (msg->len - 2) | 0x10);
	return 0;
}

static const struct cec_adap_ops hdmi_cec_adap_ops = {
	.adap_enable = hdmi_cec_adap_enable,
	.adap_log_addr = hdmi_cec_adap_log_addr,
	.adap_transmit = hdmi_cec_adap_transmit,
};

void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
{
	cec_s_phys_addr(core->adap, pa, false);
}

int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
		  struct hdmi_wp_data *wp)
{
	const u32 caps = CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
			 CEC_CAP_PASSTHROUGH | CEC_CAP_RC;
	int ret;

	core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
		"omap4", caps, CEC_MAX_LOG_ADDRS);
	ret = PTR_ERR_OR_ZERO(core->adap);
	if (ret < 0)
		return ret;
	core->wp = wp;

	/*
	 * Initialize CEC clock divider: CEC needs 2MHz clock hence
	 * set the devider to 24 to get 48/24=2MHz clock
	 */
	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);

	ret = cec_register_adapter(core->adap, &pdev->dev);
	if (ret < 0) {
		cec_delete_adapter(core->adap);
		return ret;
	}
	return 0;
}

void hdmi4_cec_uninit(struct hdmi_core_data *core)
{
	cec_unregister_adapter(core->adap);
}
Commit	Line	Data
8d7f934d HV	1	/*
	2	* HDMI CEC
	3	*
	4	* Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
	5	*
	6	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
	7	* Authors: Yong Zhi
	8	* Mythri pk <mythripk@ti.com>
	9	*
	10	* Heavily modified to use the linux CEC framework:
	11	*
	12	* Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
	13	*
	14	* This program is free software; you may redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; version 2 of the License.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	19	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	20	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	21	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	22	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	23	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	24	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	25	* SOFTWARE.
	26	*/
	27
	28	#include <linux/kernel.h>
	29	#include <linux/err.h>
	30	#include <linux/io.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/slab.h>
	33
	34	#include "dss.h"
	35	#include "hdmi.h"
	36	#include "hdmi4_core.h"
	37	#include "hdmi4_cec.h"
	38
	39	/* HDMI CEC */
	40	#define HDMI_CEC_DEV_ID 0x900
	41	#define HDMI_CEC_SPEC 0x904
	42
	43	/* Not really a debug register, more a low-level control register */
	44	#define HDMI_CEC_DBG_3 0x91C
	45	#define HDMI_CEC_TX_INIT 0x920
	46	#define HDMI_CEC_TX_DEST 0x924
	47	#define HDMI_CEC_SETUP 0x938
	48	#define HDMI_CEC_TX_COMMAND 0x93C
	49	#define HDMI_CEC_TX_OPERAND 0x940
	50	#define HDMI_CEC_TRANSMIT_DATA 0x97C
	51	#define HDMI_CEC_CA_7_0 0x988
	52	#define HDMI_CEC_CA_15_8 0x98C
	53	#define HDMI_CEC_INT_STATUS_0 0x998
	54	#define HDMI_CEC_INT_STATUS_1 0x99C
	55	#define HDMI_CEC_INT_ENABLE_0 0x990
	56	#define HDMI_CEC_INT_ENABLE_1 0x994
	57	#define HDMI_CEC_RX_CONTROL 0x9B0
	58	#define HDMI_CEC_RX_COUNT 0x9B4
	59	#define HDMI_CEC_RX_CMD_HEADER 0x9B8
	60	#define HDMI_CEC_RX_COMMAND 0x9BC
	61	#define HDMI_CEC_RX_OPERAND 0x9C0
	62
	63	#define HDMI_CEC_TX_FIFO_INT_MASK 0x64
	64	#define HDMI_CEC_RETRANSMIT_CNT_INT_MASK 0x2
65
66	#define HDMI_CORE_CEC_RETRY 200
67
68	static void hdmi_cec_received_msg(struct hdmi_core_data *core)
69	{
70	u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
71
72	/* While there are CEC frames in the FIFO */
73	while (cnt & 0x70) {
74	/* and the frame doesn't have an error */
75	if (!(cnt & 0x80)) {
76	struct cec_msg msg = {};
77	unsigned int i;
78
79	/* then read the message */
80	msg.len = cnt & 0xf;
df29c9db HV	81	if (msg.len > CEC_MAX_MSG_SIZE - 2)
df29c9db HV	82	msg.len = CEC_MAX_MSG_SIZE - 2;
8d7f934d HV	83	msg.msg[0] = hdmi_read_reg(core->base,
	84	HDMI_CEC_RX_CMD_HEADER);
	85	msg.msg[1] = hdmi_read_reg(core->base,
	86	HDMI_CEC_RX_COMMAND);
	87	for (i = 0; i < msg.len; i++) {
	88	unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4;
	89
	90	msg.msg[2 + i] =
	91	hdmi_read_reg(core->base, reg);
	92	}
	93	msg.len += 2;
	94	cec_received_msg(core->adap, &msg);
	95	}
	96	/* Clear the current frame from the FIFO */
	97	hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
	98	/* Wait until the current frame is cleared */
	99	while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
	100	udelay(1);
	101	/*
	102	* Re-read the count register and loop to see if there are
	103	* more messages in the FIFO.
	104	*/
	105	cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
	106	}
	107	}
	108
8d7f934d HV	109	void hdmi4_cec_irq(struct hdmi_core_data *core)
	110	{
	111	u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
	112	u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
	113
	114	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
	115	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
	116
df29c9db HV	117	if (stat0 & 0x20) {
	118	cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
	119	0, 0, 0, 0);
8d7f934d	120	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
df29c9db	121	} else if (stat1 & 0x02) {
8d7f934d HV	122	u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
	123
	124	cec_transmit_done(core->adap,
	125	CEC_TX_STATUS_NACK \|
	126	CEC_TX_STATUS_MAX_RETRIES,
	127	0, (dbg3 >> 4) & 7, 0, 0);
df29c9db	128	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
8d7f934d HV	129	}
	130	if (stat0 & 0x02)
	131	hdmi_cec_received_msg(core);
8d7f934d HV	132	}
	133
	134	static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
	135	{
	136	struct hdmi_core_data *core = cec_get_drvdata(adap);
	137	int retry = HDMI_CORE_CEC_RETRY;
	138	int temp;
	139
	140	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
	141	while (retry) {
	142	temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
	143	if (FLD_GET(temp, 7, 7) == 0)
	144	break;
	145	retry--;
	146	}
	147	return retry != 0;
	148	}
	149
	150	static bool hdmi_cec_clear_rx_fifo(struct cec_adapter *adap)
	151	{
	152	struct hdmi_core_data *core = cec_get_drvdata(adap);
	153	int retry = HDMI_CORE_CEC_RETRY;
	154	int temp;
	155
	156	hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
	157	retry = HDMI_CORE_CEC_RETRY;
	158	while (retry) {
	159	temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
	160	if (FLD_GET(temp, 1, 0) == 0)
	161	break;
	162	retry--;
	163	}
	164	return retry != 0;
	165	}
	166
	167	static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
	168	{
	169	struct hdmi_core_data *core = cec_get_drvdata(adap);
	170	int temp, err;
	171
	172	if (!enable) {
	173	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
	174	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
	175	REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
	176	hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
	177	hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
	178	hdmi4_core_disable(NULL);
	179	return 0;
	180	}
	181	err = hdmi4_core_enable(NULL);
	182	if (err)
	183	return err;
	184
	185	/* Clear TX FIFO */
	186	if (!hdmi_cec_clear_tx_fifo(adap)) {
	187	pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
	188	return -EIO;
	189	}
	190
	191	/* Clear RX FIFO */
	192	if (!hdmi_cec_clear_rx_fifo(adap)) {
	193	pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
	194	return -EIO;
	195	}
196
197	/* Clear CEC interrupts */
198	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
199	hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
200	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
201	hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
202
203	/* Enable HDMI core interrupts */
204	hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);
205	/* Unmask CEC interrupt */
206	REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
207	/*
208	* Enable CEC interrupts:
209	* Transmit Buffer Full/Empty Change event
8d7f934d HV	210	* Receiver FIFO Not Empty event
8d7f934d HV	211	*/
df29c9db	212	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22);
8d7f934d HV	213	/*
8d7f934d HV	214	* Enable CEC interrupts:
8d7f934d	215	* Frame Retransmit Count Exceeded event
8d7f934d	216	*/
df29c9db	217	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02);
8d7f934d HV	218
	219	/* cec calibration enable (self clearing) */
	220	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
	221	msleep(20);
	222	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);
	223
	224	temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
	225	if (FLD_GET(temp, 4, 4) != 0) {
	226	temp = FLD_MOD(temp, 0, 4, 4);
	227	hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);
	228
	229	/*
	230	* If we enabled CEC in middle of a CEC message on the bus,
	231	* we could have start bit irregularity and/or short
	232	* pulse event. Clear them now.
	233	*/
	234	temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
	235	temp = FLD_MOD(0x0, 0x5, 2, 0);
	236	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
	237	}
	238	return 0;
	239	}
	240
	241	static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
	242	{
	243	struct hdmi_core_data *core = cec_get_drvdata(adap);
	244	u32 v;
	245
	246	if (log_addr == CEC_LOG_ADDR_INVALID) {
	247	hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
	248	hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
	249	return 0;
	250	}
	251	if (log_addr <= 7) {
	252	v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
	253	v \|= 1 << log_addr;
	254	hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
	255	} else {
	256	v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
	257	v \|= 1 << (log_addr - 8);
	258	hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
	259	}
	260	return 0;
	261	}
	262
	263	static int hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
	264	u32 signal_free_time, struct cec_msg *msg)
	265	{
	266	struct hdmi_core_data *core = cec_get_drvdata(adap);
	267	int temp;
	268	u32 i;
	269
	270	/* Clear TX FIFO */
	271	if (!hdmi_cec_clear_tx_fifo(adap)) {
	272	pr_err("cec-%s: could not clear TX FIFO for transmit\n",
	273	adap->name);
	274	return -EIO;
	275	}
	276
	277	/* Clear TX interrupts */
	278	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
	279	HDMI_CEC_TX_FIFO_INT_MASK);
	280
	281	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
282	HDMI_CEC_RETRANSMIT_CNT_INT_MASK);
283
284	/* Set the retry count */
285	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);
286
287	/* Set the initiator addresses */
288	hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));
289
290	/* Set destination id */
291	temp = cec_msg_destination(msg);
292	if (msg->len == 1)
293	temp \|= 0x80;
294	hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
295	if (msg->len == 1)
296	return 0;
297
298	/* Setup command and arguments for the command */
299	hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);
300
301	for (i = 0; i < msg->len - 2; i++)
302	hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
303	msg->msg[2 + i]);
304
305	/* Operand count */
306	hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
307	(msg->len - 2) \| 0x10);
308	return 0;
309	}
310
311	static const struct cec_adap_ops hdmi_cec_adap_ops = {
312	.adap_enable = hdmi_cec_adap_enable,
313	.adap_log_addr = hdmi_cec_adap_log_addr,
314	.adap_transmit = hdmi_cec_adap_transmit,
315	};
316
317	void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
318	{
319	cec_s_phys_addr(core->adap, pa, false);
320	}
321
322	int hdmi4_cec_init(struct platform_device pdev, struct hdmi_core_data core,
323	struct hdmi_wp_data *wp)
324	{
325	const u32 caps = CEC_CAP_TRANSMIT \| CEC_CAP_LOG_ADDRS \|
326	CEC_CAP_PASSTHROUGH \| CEC_CAP_RC;
bc2aba90	327	int ret;
8d7f934d HV	328
	329	core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
	330	"omap4", caps, CEC_MAX_LOG_ADDRS);
	331	ret = PTR_ERR_OR_ZERO(core->adap);
	332	if (ret < 0)
	333	return ret;
	334	core->wp = wp;
	335
	336	/*
	337	* Initialize CEC clock divider: CEC needs 2MHz clock hence
	338	* set the devider to 24 to get 48/24=2MHz clock
	339	*/
	340	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
	341
	342	ret = cec_register_adapter(core->adap, &pdev->dev);
	343	if (ret < 0) {
	344	cec_delete_adapter(core->adap);
	345	return ret;
	346	}
	347	return 0;
	348	}
	349
	350	void hdmi4_cec_uninit(struct hdmi_core_data *core)
	351	{
	352	cec_unregister_adapter(core->adap);
	353	}