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Merge tag 'soc-fsl-fix-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/leo...
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / omapdrm / dss / hdmi5.c
CommitLineData
f5bab222
TV
1/*
2 * HDMI driver for OMAP5
3 *
bb5cdf8d 4 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
f5bab222
TV
5 *
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25#define DSS_SUBSYS_NAME "HDMI"
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/err.h>
30#include <linux/io.h>
31#include <linux/interrupt.h>
32#include <linux/mutex.h>
33#include <linux/delay.h>
34#include <linux/string.h>
35#include <linux/platform_device.h>
36#include <linux/pm_runtime.h>
37#include <linux/clk.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
736e60dd 40#include <linux/component.h>
d9e32ecd 41#include <linux/of.h>
09bffa6e 42#include <linux/of_graph.h>
45302d7e 43#include <sound/omap-hdmi-audio.h>
f5bab222 44
32043da7 45#include "omapdss.h"
f5bab222
TV
46#include "hdmi5_core.h"
47#include "dss.h"
f5bab222 48
c44991ce 49static int hdmi_runtime_get(struct omap_hdmi *hdmi)
f5bab222
TV
50{
51 int r;
52
53 DSSDBG("hdmi_runtime_get\n");
54
c44991ce 55 r = pm_runtime_get_sync(&hdmi->pdev->dev);
f5bab222
TV
56 WARN_ON(r < 0);
57 if (r < 0)
58 return r;
59
60 return 0;
61}
62
c44991ce 63static void hdmi_runtime_put(struct omap_hdmi *hdmi)
f5bab222
TV
64{
65 int r;
66
67 DSSDBG("hdmi_runtime_put\n");
68
c44991ce 69 r = pm_runtime_put_sync(&hdmi->pdev->dev);
f5bab222
TV
70 WARN_ON(r < 0 && r != -ENOSYS);
71}
72
73static irqreturn_t hdmi_irq_handler(int irq, void *data)
74{
c44991ce
LP
75 struct omap_hdmi *hdmi = data;
76 struct hdmi_wp_data *wp = &hdmi->wp;
f5bab222
TV
77 u32 irqstatus;
78
79 irqstatus = hdmi_wp_get_irqstatus(wp);
80 hdmi_wp_set_irqstatus(wp, irqstatus);
81
82 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
83 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
84 u32 v;
85 /*
86 * If we get both connect and disconnect interrupts at the same
87 * time, turn off the PHY, clear interrupts, and restart, which
88 * raises connect interrupt if a cable is connected, or nothing
89 * if cable is not connected.
90 */
91
92 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
93
94 /*
95 * We always get bogus CONNECT & DISCONNECT interrupts when
96 * setting the PHY to LDOON. To ignore those, we force the RXDET
97 * line to 0 until the PHY power state has been changed.
98 */
c44991ce 99 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
f5bab222
TV
100 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
101 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
c44991ce 102 hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
f5bab222
TV
103
104 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
105 HDMI_IRQ_LINK_DISCONNECT);
106
107 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
108
c44991ce 109 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
f5bab222
TV
110
111 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
112 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
113 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
114 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
115 }
116
117 return IRQ_HANDLED;
118}
119
c44991ce 120static int hdmi_power_on_core(struct omap_hdmi *hdmi)
f5bab222
TV
121{
122 int r;
123
c44991ce 124 r = regulator_enable(hdmi->vdda_reg);
f5bab222
TV
125 if (r)
126 return r;
127
c44991ce 128 r = hdmi_runtime_get(hdmi);
f5bab222
TV
129 if (r)
130 goto err_runtime_get;
131
132 /* Make selection of HDMI in DSS */
c44991ce 133 dss_select_hdmi_venc_clk_source(hdmi->dss, DSS_HDMI_M_PCLK);
f5bab222 134
c44991ce 135 hdmi->core_enabled = true;
f5bab222
TV
136
137 return 0;
138
139err_runtime_get:
c44991ce 140 regulator_disable(hdmi->vdda_reg);
f5bab222
TV
141
142 return r;
143}
144
c44991ce 145static void hdmi_power_off_core(struct omap_hdmi *hdmi)
f5bab222 146{
c44991ce 147 hdmi->core_enabled = false;
f5bab222 148
c44991ce
LP
149 hdmi_runtime_put(hdmi);
150 regulator_disable(hdmi->vdda_reg);
f5bab222
TV
151}
152
c44991ce 153static int hdmi_power_on_full(struct omap_hdmi *hdmi)
f5bab222
TV
154{
155 int r;
95e472da 156 const struct videomode *vm;
c84c3a5b 157 struct dss_pll_clock_info hdmi_cinfo = { 0 };
d11e5c82 158 unsigned int pc;
f5bab222 159
c44991ce 160 r = hdmi_power_on_core(hdmi);
f5bab222
TV
161 if (r)
162 return r;
163
c44991ce 164 vm = &hdmi->cfg.vm;
f5bab222 165
da11bbbb
PU
166 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
167 vm->vactive);
f5bab222 168
da11bbbb
PU
169 pc = vm->pixelclock;
170 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
67d8ffdd
TV
171 pc *= 2;
172
c107751d
TV
173 /* DSS_HDMI_TCLK is bitclk / 10 */
174 pc *= 10;
175
c44991ce 176 dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
c17dc0e3 177 pc, &hdmi_cinfo);
f5bab222
TV
178
179 /* disable and clear irqs */
c44991ce
LP
180 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
181 hdmi_wp_set_irqstatus(&hdmi->wp,
182 hdmi_wp_get_irqstatus(&hdmi->wp));
f5bab222 183
c44991ce 184 r = dss_pll_enable(&hdmi->pll.pll);
f5bab222 185 if (r) {
c2fbd061 186 DSSERR("Failed to enable PLL\n");
f5bab222
TV
187 goto err_pll_enable;
188 }
189
c44991ce 190 r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
c2fbd061
TV
191 if (r) {
192 DSSERR("Failed to configure PLL\n");
193 goto err_pll_cfg;
194 }
195
c44991ce 196 r = hdmi_phy_configure(&hdmi->phy, hdmi_cinfo.clkdco,
c84c3a5b 197 hdmi_cinfo.clkout[0]);
f5bab222
TV
198 if (r) {
199 DSSDBG("Failed to start PHY\n");
200 goto err_phy_cfg;
201 }
202
c44991ce 203 r = hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_LDOON);
f5bab222
TV
204 if (r)
205 goto err_phy_pwr;
206
c44991ce 207 hdmi5_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);
f5bab222 208
c44991ce 209 r = dss_mgr_enable(&hdmi->output);
f5bab222
TV
210 if (r)
211 goto err_mgr_enable;
212
c44991ce 213 r = hdmi_wp_video_start(&hdmi->wp);
4e4b53ce
TV
214 if (r)
215 goto err_vid_enable;
216
c44991ce 217 hdmi_wp_set_irqenable(&hdmi->wp,
f5bab222
TV
218 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
219
220 return 0;
221
f5bab222 222err_vid_enable:
c44991ce 223 dss_mgr_disable(&hdmi->output);
4e4b53ce 224err_mgr_enable:
c44991ce 225 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
f5bab222
TV
226err_phy_pwr:
227err_phy_cfg:
c2fbd061 228err_pll_cfg:
c44991ce 229 dss_pll_disable(&hdmi->pll.pll);
f5bab222 230err_pll_enable:
c44991ce 231 hdmi_power_off_core(hdmi);
f5bab222
TV
232 return -EIO;
233}
234
c44991ce 235static void hdmi_power_off_full(struct omap_hdmi *hdmi)
f5bab222 236{
c44991ce 237 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
f5bab222 238
c44991ce 239 hdmi_wp_video_stop(&hdmi->wp);
f5bab222 240
c44991ce 241 dss_mgr_disable(&hdmi->output);
4e4b53ce 242
c44991ce 243 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
f5bab222 244
c44991ce 245 dss_pll_disable(&hdmi->pll.pll);
f5bab222 246
c44991ce 247 hdmi_power_off_core(hdmi);
f5bab222
TV
248}
249
ec68cd5a 250static void hdmi_display_set_timings(struct omap_dss_device *dssdev,
41322aa6 251 const struct drm_display_mode *mode)
f5bab222 252{
c44991ce
LP
253 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
254
255 mutex_lock(&hdmi->lock);
f5bab222 256
41322aa6 257 drm_display_mode_to_videomode(mode, &hdmi->cfg.vm);
f5bab222 258
41322aa6 259 dispc_set_tv_pclk(hdmi->dss->dispc, mode->clock * 1000);
f5bab222 260
c44991ce 261 mutex_unlock(&hdmi->lock);
f5bab222
TV
262}
263
f33656e1 264static int hdmi_dump_regs(struct seq_file *s, void *p)
f5bab222 265{
c44991ce
LP
266 struct omap_hdmi *hdmi = s->private;
267
268 mutex_lock(&hdmi->lock);
f5bab222 269
c44991ce
LP
270 if (hdmi_runtime_get(hdmi)) {
271 mutex_unlock(&hdmi->lock);
f33656e1 272 return 0;
f5bab222
TV
273 }
274
c44991ce
LP
275 hdmi_wp_dump(&hdmi->wp, s);
276 hdmi_pll_dump(&hdmi->pll, s);
277 hdmi_phy_dump(&hdmi->phy, s);
278 hdmi5_core_dump(&hdmi->core, s);
f5bab222 279
c44991ce
LP
280 hdmi_runtime_put(hdmi);
281 mutex_unlock(&hdmi->lock);
f33656e1 282 return 0;
f5bab222
TV
283}
284
c44991ce 285static int read_edid(struct omap_hdmi *hdmi, u8 *buf, int len)
f5bab222
TV
286{
287 int r;
288 int idlemode;
289
c44991ce 290 mutex_lock(&hdmi->lock);
f5bab222 291
c44991ce 292 r = hdmi_runtime_get(hdmi);
f5bab222
TV
293 BUG_ON(r);
294
c44991ce 295 idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
f5bab222 296 /* No-idle mode */
c44991ce 297 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
f5bab222 298
c44991ce 299 r = hdmi5_read_edid(&hdmi->core, buf, len);
f5bab222 300
c44991ce 301 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
f5bab222 302
c44991ce
LP
303 hdmi_runtime_put(hdmi);
304 mutex_unlock(&hdmi->lock);
f5bab222
TV
305
306 return r;
307}
308
8a9d4626
JS
309static void hdmi_start_audio_stream(struct omap_hdmi *hd)
310{
c44991ce 311 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
8a9d4626
JS
312 hdmi_wp_audio_enable(&hd->wp, true);
313 hdmi_wp_audio_core_req_enable(&hd->wp, true);
314}
315
316static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
317{
318 hdmi_wp_audio_core_req_enable(&hd->wp, false);
319 hdmi_wp_audio_enable(&hd->wp, false);
320 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
321}
322
19b4200d 323static void hdmi_display_enable(struct omap_dss_device *dssdev)
f5bab222 324{
c44991ce 325 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
8a9d4626 326 unsigned long flags;
19b4200d 327 int r;
f5bab222
TV
328
329 DSSDBG("ENTER hdmi_display_enable\n");
330
c44991ce 331 mutex_lock(&hdmi->lock);
f5bab222 332
c44991ce 333 r = hdmi_power_on_full(hdmi);
f5bab222
TV
334 if (r) {
335 DSSERR("failed to power on device\n");
19b4200d 336 goto done;
f5bab222
TV
337 }
338
c44991ce
LP
339 if (hdmi->audio_configured) {
340 r = hdmi5_audio_config(&hdmi->core, &hdmi->wp,
341 &hdmi->audio_config,
342 hdmi->cfg.vm.pixelclock);
8a9d4626
JS
343 if (r) {
344 DSSERR("Error restoring audio configuration: %d", r);
c44991ce
LP
345 hdmi->audio_abort_cb(&hdmi->pdev->dev);
346 hdmi->audio_configured = false;
8a9d4626
JS
347 }
348 }
349
c44991ce
LP
350 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
351 if (hdmi->audio_configured && hdmi->audio_playing)
352 hdmi_start_audio_stream(hdmi);
353 hdmi->display_enabled = true;
354 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
45302d7e 355
19b4200d 356done:
c44991ce 357 mutex_unlock(&hdmi->lock);
f5bab222
TV
358}
359
360static void hdmi_display_disable(struct omap_dss_device *dssdev)
361{
c44991ce 362 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
8a9d4626
JS
363 unsigned long flags;
364
f5bab222
TV
365 DSSDBG("Enter hdmi_display_disable\n");
366
c44991ce 367 mutex_lock(&hdmi->lock);
f5bab222 368
c44991ce
LP
369 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
370 hdmi_stop_audio_stream(hdmi);
371 hdmi->display_enabled = false;
372 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
45302d7e 373
c44991ce 374 hdmi_power_off_full(hdmi);
f5bab222 375
c44991ce 376 mutex_unlock(&hdmi->lock);
f5bab222
TV
377}
378
c44991ce 379static int hdmi_core_enable(struct omap_hdmi *hdmi)
f5bab222
TV
380{
381 int r = 0;
382
383 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
384
c44991ce 385 mutex_lock(&hdmi->lock);
f5bab222 386
c44991ce 387 r = hdmi_power_on_core(hdmi);
f5bab222
TV
388 if (r) {
389 DSSERR("failed to power on device\n");
390 goto err0;
391 }
392
c44991ce 393 mutex_unlock(&hdmi->lock);
f5bab222
TV
394 return 0;
395
396err0:
c44991ce 397 mutex_unlock(&hdmi->lock);
f5bab222
TV
398 return r;
399}
400
c44991ce 401static void hdmi_core_disable(struct omap_hdmi *hdmi)
f5bab222
TV
402{
403 DSSDBG("Enter omapdss_hdmi_core_disable\n");
404
c44991ce 405 mutex_lock(&hdmi->lock);
f5bab222 406
c44991ce 407 hdmi_power_off_core(hdmi);
f5bab222 408
c44991ce 409 mutex_unlock(&hdmi->lock);
f5bab222
TV
410}
411
511afb44
LP
412static int hdmi_connect(struct omap_dss_device *src,
413 struct omap_dss_device *dst)
f5bab222 414{
f8a8eabb 415 return omapdss_device_connect(dst->dss, dst, dst->next);
f5bab222
TV
416}
417
511afb44
LP
418static void hdmi_disconnect(struct omap_dss_device *src,
419 struct omap_dss_device *dst)
f5bab222 420{
511afb44 421 omapdss_device_disconnect(dst, dst->next);
f5bab222
TV
422}
423
424static int hdmi_read_edid(struct omap_dss_device *dssdev,
425 u8 *edid, int len)
426{
c44991ce 427 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
f5bab222
TV
428 bool need_enable;
429 int r;
430
c44991ce 431 need_enable = hdmi->core_enabled == false;
f5bab222
TV
432
433 if (need_enable) {
c44991ce 434 r = hdmi_core_enable(hdmi);
f5bab222
TV
435 if (r)
436 return r;
437 }
438
c44991ce 439 r = read_edid(hdmi, edid, len);
f5bab222
TV
440
441 if (need_enable)
c44991ce 442 hdmi_core_disable(hdmi);
f5bab222
TV
443
444 return r;
445}
446
769dcb11
TV
447static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
448 const struct hdmi_avi_infoframe *avi)
449{
c44991ce
LP
450 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
451
452 hdmi->cfg.infoframe = *avi;
769dcb11
TV
453 return 0;
454}
455
456static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
457 bool hdmi_mode)
458{
c44991ce
LP
459 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
460
461 hdmi->cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
769dcb11
TV
462 return 0;
463}
464
b93109d7 465static const struct omap_dss_device_ops hdmi_ops = {
f5bab222
TV
466 .connect = hdmi_connect,
467 .disconnect = hdmi_disconnect,
468
469 .enable = hdmi_display_enable,
470 .disable = hdmi_display_disable,
471
ec68cd5a 472 .set_timings = hdmi_display_set_timings,
f5bab222 473
83910ad3
LP
474 .read_edid = hdmi_read_edid,
475
b93109d7 476 .hdmi = {
b93109d7
LP
477 .set_infoframe = hdmi_set_infoframe,
478 .set_hdmi_mode = hdmi_set_hdmi_mode,
479 },
f5bab222
TV
480};
481
5f031b47
LP
482/* -----------------------------------------------------------------------------
483 * Audio Callbacks
484 */
f5bab222 485
45302d7e
JS
486static int hdmi_audio_startup(struct device *dev,
487 void (*abort_cb)(struct device *dev))
488{
489 struct omap_hdmi *hd = dev_get_drvdata(dev);
45302d7e
JS
490
491 mutex_lock(&hd->lock);
492
c1899cb3 493 WARN_ON(hd->audio_abort_cb != NULL);
45302d7e
JS
494
495 hd->audio_abort_cb = abort_cb;
496
45302d7e
JS
497 mutex_unlock(&hd->lock);
498
c1899cb3 499 return 0;
45302d7e
JS
500}
501
502static int hdmi_audio_shutdown(struct device *dev)
503{
504 struct omap_hdmi *hd = dev_get_drvdata(dev);
505
506 mutex_lock(&hd->lock);
507 hd->audio_abort_cb = NULL;
8a9d4626
JS
508 hd->audio_configured = false;
509 hd->audio_playing = false;
45302d7e
JS
510 mutex_unlock(&hd->lock);
511
512 return 0;
513}
514
515static int hdmi_audio_start(struct device *dev)
516{
517 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 518 unsigned long flags;
45302d7e 519
8a9d4626 520 spin_lock_irqsave(&hd->audio_playing_lock, flags);
2d7639bc 521
c1899cb3
JS
522 if (hd->display_enabled) {
523 if (!hdmi_mode_has_audio(&hd->cfg))
524 DSSERR("%s: Video mode does not support audio\n",
525 __func__);
8a9d4626 526 hdmi_start_audio_stream(hd);
c1899cb3 527 }
8a9d4626 528 hd->audio_playing = true;
45302d7e 529
8a9d4626 530 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
531 return 0;
532}
533
534static void hdmi_audio_stop(struct device *dev)
535{
536 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 537 unsigned long flags;
45302d7e 538
c1899cb3
JS
539 if (!hdmi_mode_has_audio(&hd->cfg))
540 DSSERR("%s: Video mode does not support audio\n", __func__);
45302d7e 541
8a9d4626
JS
542 spin_lock_irqsave(&hd->audio_playing_lock, flags);
543
544 if (hd->display_enabled)
545 hdmi_stop_audio_stream(hd);
546 hd->audio_playing = false;
2d7639bc 547
8a9d4626 548 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
549}
550
551static int hdmi_audio_config(struct device *dev,
552 struct omap_dss_audio *dss_audio)
553{
554 struct omap_hdmi *hd = dev_get_drvdata(dev);
77eeac24 555 int ret = 0;
45302d7e
JS
556
557 mutex_lock(&hd->lock);
558
c1899cb3
JS
559 if (hd->display_enabled) {
560 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
561 hd->cfg.vm.pixelclock);
562 if (ret)
563 goto out;
45302d7e
JS
564 }
565
c1899cb3
JS
566 hd->audio_configured = true;
567 hd->audio_config = *dss_audio;
45302d7e
JS
568out:
569 mutex_unlock(&hd->lock);
570
571 return ret;
572}
573
574static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
575 .audio_startup = hdmi_audio_startup,
576 .audio_shutdown = hdmi_audio_shutdown,
577 .audio_start = hdmi_audio_start,
578 .audio_stop = hdmi_audio_stop,
579 .audio_config = hdmi_audio_config,
580};
581
c44991ce 582static int hdmi_audio_register(struct omap_hdmi *hdmi)
45302d7e
JS
583{
584 struct omap_hdmi_audio_pdata pdata = {
c44991ce 585 .dev = &hdmi->pdev->dev,
d20fa5a0 586 .version = 5,
c44991ce 587 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),
45302d7e
JS
588 .ops = &hdmi_audio_ops,
589 };
590
c44991ce
LP
591 hdmi->audio_pdev = platform_device_register_data(
592 &hdmi->pdev->dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
45302d7e
JS
593 &pdata, sizeof(pdata));
594
c44991ce
LP
595 if (IS_ERR(hdmi->audio_pdev))
596 return PTR_ERR(hdmi->audio_pdev);
45302d7e 597
c44991ce
LP
598 hdmi_runtime_get(hdmi);
599 hdmi->wp_idlemode =
600 REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
601 hdmi_runtime_put(hdmi);
8a9d4626 602
45302d7e
JS
603 return 0;
604}
605
5f031b47
LP
606/* -----------------------------------------------------------------------------
607 * Component Bind & Unbind
608 */
609
736e60dd 610static int hdmi5_bind(struct device *dev, struct device *master, void *data)
f5bab222 611{
7b295257 612 struct dss_device *dss = dss_get_device(master);
5f031b47 613 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
f5bab222 614 int r;
5f031b47
LP
615
616 hdmi->dss = dss;
617
618 r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
619 if (r)
620 return r;
621
622 r = hdmi_audio_register(hdmi);
623 if (r) {
624 DSSERR("Registering HDMI audio failed %d\n", r);
625 goto err_pll_uninit;
626 }
627
628 hdmi->debugfs = dss_debugfs_create_file(dss, "hdmi", hdmi_dump_regs,
629 hdmi);
630
631 return 0;
632
633err_pll_uninit:
634 hdmi_pll_uninit(&hdmi->pll);
635 return r;
636}
637
638static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
639{
640 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
641
642 dss_debugfs_remove_file(hdmi->debugfs);
643
644 if (hdmi->audio_pdev)
645 platform_device_unregister(hdmi->audio_pdev);
646
647 hdmi_pll_uninit(&hdmi->pll);
648}
649
650static const struct component_ops hdmi5_component_ops = {
651 .bind = hdmi5_bind,
652 .unbind = hdmi5_unbind,
653};
654
655/* -----------------------------------------------------------------------------
656 * Probe & Remove, Suspend & Resume
657 */
658
27d62452 659static int hdmi5_init_output(struct omap_hdmi *hdmi)
5f031b47
LP
660{
661 struct omap_dss_device *out = &hdmi->output;
71316556 662 int r;
5f031b47
LP
663
664 out->dev = &hdmi->pdev->dev;
665 out->id = OMAP_DSS_OUTPUT_HDMI;
0dbfc396 666 out->type = OMAP_DISPLAY_TYPE_HDMI;
5f031b47
LP
667 out->name = "hdmi.0";
668 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
669 out->ops = &hdmi_ops;
670 out->owner = THIS_MODULE;
671 out->of_ports = BIT(0);
90279e95 672 out->ops_flags = OMAP_DSS_DEVICE_OP_EDID;
5f031b47 673
d17eb453
LP
674 r = omapdss_device_init_output(out);
675 if (r < 0)
71316556 676 return r;
71316556 677
5f031b47 678 omapdss_device_register(out);
27d62452
LP
679
680 return 0;
5f031b47
LP
681}
682
683static void hdmi5_uninit_output(struct omap_hdmi *hdmi)
684{
685 struct omap_dss_device *out = &hdmi->output;
686
687 omapdss_device_unregister(out);
d17eb453 688 omapdss_device_cleanup_output(out);
5f031b47
LP
689}
690
691static int hdmi5_probe_of(struct omap_hdmi *hdmi)
692{
693 struct platform_device *pdev = hdmi->pdev;
694 struct device_node *node = pdev->dev.of_node;
695 struct device_node *ep;
696 int r;
697
698 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
699 if (!ep)
700 return 0;
701
702 r = hdmi_parse_lanes_of(pdev, ep, &hdmi->phy);
703 of_node_put(ep);
704 return r;
705}
706
707static int hdmi5_probe(struct platform_device *pdev)
708{
709 struct omap_hdmi *hdmi;
f5bab222 710 int irq;
5f031b47 711 int r;
f5bab222 712
c44991ce
LP
713 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
714 if (!hdmi)
715 return -ENOMEM;
f5bab222 716
c44991ce 717 hdmi->pdev = pdev;
5f031b47 718
c44991ce 719 dev_set_drvdata(&pdev->dev, hdmi);
f5bab222 720
c44991ce
LP
721 mutex_init(&hdmi->lock);
722 spin_lock_init(&hdmi->audio_playing_lock);
723
5f031b47 724 r = hdmi5_probe_of(hdmi);
1dff212c 725 if (r)
c44991ce 726 goto err_free;
f5bab222 727
c44991ce 728 r = hdmi_wp_init(pdev, &hdmi->wp, 5);
f5bab222 729 if (r)
c44991ce 730 goto err_free;
f5bab222 731
c44991ce 732 r = hdmi_phy_init(pdev, &hdmi->phy, 5);
f5bab222 733 if (r)
5f031b47 734 goto err_free;
f5bab222 735
c44991ce 736 r = hdmi5_core_init(pdev, &hdmi->core);
f5bab222 737 if (r)
5f031b47 738 goto err_free;
f5bab222
TV
739
740 irq = platform_get_irq(pdev, 0);
741 if (irq < 0) {
742 DSSERR("platform_get_irq failed\n");
c84c3a5b 743 r = -ENODEV;
5f031b47 744 goto err_free;
f5bab222
TV
745 }
746
747 r = devm_request_threaded_irq(&pdev->dev, irq,
748 NULL, hdmi_irq_handler,
c44991ce 749 IRQF_ONESHOT, "OMAP HDMI", hdmi);
f5bab222
TV
750 if (r) {
751 DSSERR("HDMI IRQ request failed\n");
5f031b47 752 goto err_free;
f5bab222
TV
753 }
754
8a36357a
LP
755 hdmi->vdda_reg = devm_regulator_get(&pdev->dev, "vdda");
756 if (IS_ERR(hdmi->vdda_reg)) {
757 r = PTR_ERR(hdmi->vdda_reg);
758 if (r != -EPROBE_DEFER)
759 DSSERR("can't get VDDA regulator\n");
760 goto err_free;
761 }
762
f5bab222
TV
763 pm_runtime_enable(&pdev->dev);
764
27d62452
LP
765 r = hdmi5_init_output(hdmi);
766 if (r)
767 goto err_pm_disable;
f5bab222 768
5f031b47
LP
769 r = component_add(&pdev->dev, &hdmi5_component_ops);
770 if (r)
66aacfe2 771 goto err_uninit_output;
f5bab222
TV
772
773 return 0;
c44991ce 774
66aacfe2 775err_uninit_output:
5f031b47 776 hdmi5_uninit_output(hdmi);
27d62452 777err_pm_disable:
66aacfe2 778 pm_runtime_disable(&pdev->dev);
c44991ce
LP
779err_free:
780 kfree(hdmi);
c84c3a5b 781 return r;
f5bab222
TV
782}
783
5f031b47 784static int hdmi5_remove(struct platform_device *pdev)
f5bab222 785{
5f031b47 786 struct omap_hdmi *hdmi = platform_get_drvdata(pdev);
736e60dd 787
5f031b47 788 component_del(&pdev->dev, &hdmi5_component_ops);
45302d7e 789
5f031b47 790 hdmi5_uninit_output(hdmi);
f5bab222 791
5f031b47 792 pm_runtime_disable(&pdev->dev);
c84c3a5b 793
c44991ce 794 kfree(hdmi);
f5bab222
TV
795 return 0;
796}
797
f5bab222
TV
798static const struct of_device_id hdmi_of_match[] = {
799 { .compatible = "ti,omap5-hdmi", },
adb5ff83 800 { .compatible = "ti,dra7-hdmi", },
f5bab222
TV
801 {},
802};
803
d66c36a3 804struct platform_driver omapdss_hdmi5hw_driver = {
736e60dd
TV
805 .probe = hdmi5_probe,
806 .remove = hdmi5_remove,
f5bab222
TV
807 .driver = {
808 .name = "omapdss_hdmi5",
f5bab222 809 .of_match_table = hdmi_of_match,
422ccbd5 810 .suppress_bind_attrs = true,
f5bab222
TV
811 },
812};