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drm/omap: omap_display_timings: Use display_flags for pixel data edge
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / dss / omapdss.h
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35a339ac
TV		 1/*
2 * Copyright (C) 2016 Texas Instruments
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __OMAP_DRM_DSS_H
19#define __OMAP_DRM_DSS_H
20
26038aad
PU		 21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
24#include <linux/interrupt.h>
25#include <video/videomode.h>
26#include <linux/platform_data/omapdss.h>
acc3a231 27#include <uapi/drm/drm_mode.h>
26038aad
PU		 28
29#define DISPC_IRQ_FRAMEDONE (1 << 0)
30#define DISPC_IRQ_VSYNC (1 << 1)
31#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
32#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
33#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
34#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
35#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
36#define DISPC_IRQ_GFX_END_WIN (1 << 7)
37#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
38#define DISPC_IRQ_OCP_ERR (1 << 9)
39#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
40#define DISPC_IRQ_VID1_END_WIN (1 << 11)
41#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
42#define DISPC_IRQ_VID2_END_WIN (1 << 13)
43#define DISPC_IRQ_SYNC_LOST (1 << 14)
44#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
45#define DISPC_IRQ_WAKEUP (1 << 16)
46#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
47#define DISPC_IRQ_VSYNC2 (1 << 18)
48#define DISPC_IRQ_VID3_END_WIN (1 << 19)
49#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
50#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
51#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
52#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
53#define DISPC_IRQ_FRAMEDONETV (1 << 24)
54#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
55#define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
56#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
57#define DISPC_IRQ_VSYNC3 (1 << 28)
58#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
59#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
60
61struct omap_dss_device;
62struct omap_overlay_manager;
63struct dss_lcd_mgr_config;
64struct snd_aes_iec958;
65struct snd_cea_861_aud_if;
66struct hdmi_avi_infoframe;
67
68enum omap_display_type {
69 OMAP_DISPLAY_TYPE_NONE = 0,
70 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
71 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
72 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
73 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
74 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
75 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
76 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
77};
78
79enum omap_plane {
80 OMAP_DSS_GFX = 0,
81 OMAP_DSS_VIDEO1 = 1,
82 OMAP_DSS_VIDEO2 = 2,
83 OMAP_DSS_VIDEO3 = 3,
84 OMAP_DSS_WB = 4,
85};
86
87enum omap_channel {
88 OMAP_DSS_CHANNEL_LCD = 0,
89 OMAP_DSS_CHANNEL_DIGIT = 1,
90 OMAP_DSS_CHANNEL_LCD2 = 2,
91 OMAP_DSS_CHANNEL_LCD3 = 3,
92 OMAP_DSS_CHANNEL_WB = 4,
93};
94
95enum omap_color_mode {
96 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
97 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
98 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
99 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
100 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
101 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
102 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
103 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
104 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
105 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
106 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
107 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
108 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
109 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
110 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
111 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
112 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
113 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
114 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
115};
116
117enum omap_dss_load_mode {
118 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
119 OMAP_DSS_LOAD_CLUT_ONLY = 1,
120 OMAP_DSS_LOAD_FRAME_ONLY = 2,
121 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
122};
123
124enum omap_dss_trans_key_type {
125 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
126 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
127};
128
129enum omap_rfbi_te_mode {
130 OMAP_DSS_RFBI_TE_MODE_1 = 1,
131 OMAP_DSS_RFBI_TE_MODE_2 = 2,
132};
133
134enum omap_dss_signal_level {
135 OMAPDSS_SIG_ACTIVE_LOW,
136 OMAPDSS_SIG_ACTIVE_HIGH,
137};
138
139enum omap_dss_signal_edge {
140 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
141 OMAPDSS_DRIVE_SIG_RISING_EDGE,
142};
143
144enum omap_dss_venc_type {
145 OMAP_DSS_VENC_TYPE_COMPOSITE,
146 OMAP_DSS_VENC_TYPE_SVIDEO,
147};
148
149enum omap_dss_dsi_pixel_format {
150 OMAP_DSS_DSI_FMT_RGB888,
151 OMAP_DSS_DSI_FMT_RGB666,
152 OMAP_DSS_DSI_FMT_RGB666_PACKED,
153 OMAP_DSS_DSI_FMT_RGB565,
154};
155
156enum omap_dss_dsi_mode {
157 OMAP_DSS_DSI_CMD_MODE = 0,
158 OMAP_DSS_DSI_VIDEO_MODE,
159};
160
161enum omap_display_caps {
162 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
163 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
164};
165
166enum omap_dss_display_state {
167 OMAP_DSS_DISPLAY_DISABLED = 0,
168 OMAP_DSS_DISPLAY_ACTIVE,
169};
170
171enum omap_dss_rotation_type {
172 OMAP_DSS_ROT_DMA = 1 << 0,
173 OMAP_DSS_ROT_VRFB = 1 << 1,
174 OMAP_DSS_ROT_TILER = 1 << 2,
175};
176
177/* clockwise rotation angle */
178enum omap_dss_rotation_angle {
179 OMAP_DSS_ROT_0 = 0,
180 OMAP_DSS_ROT_90 = 1,
181 OMAP_DSS_ROT_180 = 2,
182 OMAP_DSS_ROT_270 = 3,
183};
184
185enum omap_overlay_caps {
186 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
187 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
188 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
189 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
190 OMAP_DSS_OVL_CAP_POS = 1 << 4,
191 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
192};
193
194enum omap_overlay_manager_caps {
195 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
196};
197
198enum omap_dss_clk_source {
199 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
200 * OMAP4: DSS_FCLK */
201 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
202 * OMAP4: PLL1_CLK1 */
203 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
204 * OMAP4: PLL1_CLK2 */
205 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
206 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
207};
208
209enum omap_hdmi_flags {
210 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
211};
212
213enum omap_dss_output_id {
214 OMAP_DSS_OUTPUT_DPI = 1 << 0,
215 OMAP_DSS_OUTPUT_DBI = 1 << 1,
216 OMAP_DSS_OUTPUT_SDI = 1 << 2,
217 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
218 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
219 OMAP_DSS_OUTPUT_VENC = 1 << 5,
220 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
221};
222
223/* RFBI */
224
225struct rfbi_timings {
226 int cs_on_time;
227 int cs_off_time;
228 int we_on_time;
229 int we_off_time;
230 int re_on_time;
231 int re_off_time;
232 int we_cycle_time;
233 int re_cycle_time;
234 int cs_pulse_width;
235 int access_time;
236
237 int clk_div;
238
239 u32 tim[5]; /* set by rfbi_convert_timings() */
240
241 int converted;
242};
243
244/* DSI */
245
246enum omap_dss_dsi_trans_mode {
247 /* Sync Pulses: both sync start and end packets sent */
248 OMAP_DSS_DSI_PULSE_MODE,
249 /* Sync Events: only sync start packets sent */
250 OMAP_DSS_DSI_EVENT_MODE,
251 /* Burst: only sync start packets sent, pixels are time compressed */
252 OMAP_DSS_DSI_BURST_MODE,
253};
254
255struct omap_dss_dsi_videomode_timings {
256 unsigned long hsclk;
257
258 unsigned ndl;
259 unsigned bitspp;
260
261 /* pixels */
262 u16 hact;
263 /* lines */
264 u16 vact;
265
266 /* DSI video mode blanking data */
267 /* Unit: byte clock cycles */
268 u16 hss;
269 u16 hsa;
270 u16 hse;
271 u16 hfp;
272 u16 hbp;
273 /* Unit: line clocks */
274 u16 vsa;
275 u16 vfp;
276 u16 vbp;
277
278 /* DSI blanking modes */
279 int blanking_mode;
280 int hsa_blanking_mode;
281 int hbp_blanking_mode;
282 int hfp_blanking_mode;
283
284 enum omap_dss_dsi_trans_mode trans_mode;
285
286 bool ddr_clk_always_on;
287 int window_sync;
288};
289
290struct omap_dss_dsi_config {
291 enum omap_dss_dsi_mode mode;
292 enum omap_dss_dsi_pixel_format pixel_format;
293 const struct omap_video_timings *timings;
294
295 unsigned long hs_clk_min, hs_clk_max;
296 unsigned long lp_clk_min, lp_clk_max;
297
298 bool ddr_clk_always_on;
299 enum omap_dss_dsi_trans_mode trans_mode;
300};
301
302struct omap_video_timings {
303 /* Unit: pixels */
81899060 304 u16 hactive;
26038aad 305 /* Unit: pixels */
fb7f3c43 306 u16 vactive;
26038aad
PU		 307 /* Unit: Hz */
308 u32 pixelclock;
309 /* Unit: pixel clocks */
4dc2250d 310 u16 hsync_len; /* Horizontal synchronization pulse width */
26038aad 311 /* Unit: pixel clocks */
0a30e150 312 u16 hfront_porch; /* Horizontal front porch */
26038aad 313 /* Unit: pixel clocks */
a85f4a80 314 u16 hback_porch; /* Horizontal back porch */
26038aad 315 /* Unit: line clocks */
d5bcf0aa 316 u16 vsync_len; /* Vertical synchronization pulse width */
26038aad 317 /* Unit: line clocks */
0996c68e 318 u16 vfront_porch; /* Vertical front porch */
26038aad 319 /* Unit: line clocks */
458540c6 320 u16 vback_porch; /* Vertical back porch */
26038aad 321
26038aad
PU		 322 /* Pixel clock edges to drive HSYNC and VSYNC signals */
323 enum omap_dss_signal_edge sync_pclk_edge;
324
53058299 325 enum display_flags flags;
26038aad
PU		 326};
327
328/* Hardcoded timings for tv modes. Venc only uses these to
329 * identify the mode, and does not actually use the configs
330 * itself. However, the configs should be something that
331 * a normal monitor can also show */
332extern const struct omap_video_timings omap_dss_pal_timings;
333extern const struct omap_video_timings omap_dss_ntsc_timings;
334
335struct omap_dss_cpr_coefs {
336 s16 rr, rg, rb;
337 s16 gr, gg, gb;
338 s16 br, bg, bb;
339};
340
341struct omap_overlay_info {
342 dma_addr_t paddr;
343 dma_addr_t p_uv_addr; /* for NV12 format */
344 u16 screen_width;
345 u16 width;
346 u16 height;
347 enum omap_color_mode color_mode;
348 u8 rotation;
349 enum omap_dss_rotation_type rotation_type;
350 bool mirror;
351
352 u16 pos_x;
353 u16 pos_y;
354 u16 out_width; /* if 0, out_width == width */
355 u16 out_height; /* if 0, out_height == height */
356 u8 global_alpha;
357 u8 pre_mult_alpha;
358 u8 zorder;
359};
360
361struct omap_overlay {
362 struct kobject kobj;
363 struct list_head list;
364
365 /* static fields */
366 const char *name;
367 enum omap_plane id;
368 enum omap_color_mode supported_modes;
369 enum omap_overlay_caps caps;
370
371 /* dynamic fields */
372 struct omap_overlay_manager *manager;
373
374 /*
375 * The following functions do not block:
376 *
377 * is_enabled
378 * set_overlay_info
379 * get_overlay_info
380 *
381 * The rest of the functions may block and cannot be called from
382 * interrupt context
383 */
384
385 int (*enable)(struct omap_overlay *ovl);
386 int (*disable)(struct omap_overlay *ovl);
387 bool (*is_enabled)(struct omap_overlay *ovl);
388
389 int (*set_manager)(struct omap_overlay *ovl,
390 struct omap_overlay_manager *mgr);
391 int (*unset_manager)(struct omap_overlay *ovl);
392
393 int (*set_overlay_info)(struct omap_overlay *ovl,
394 struct omap_overlay_info *info);
395 void (*get_overlay_info)(struct omap_overlay *ovl,
396 struct omap_overlay_info *info);
397
398 int (*wait_for_go)(struct omap_overlay *ovl);
399
400 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
401};
402
403struct omap_overlay_manager_info {
404 u32 default_color;
405
406 enum omap_dss_trans_key_type trans_key_type;
407 u32 trans_key;
408 bool trans_enabled;
409
410 bool partial_alpha_enabled;
411
412 bool cpr_enable;
413 struct omap_dss_cpr_coefs cpr_coefs;
414};
415
416struct omap_overlay_manager {
417 struct kobject kobj;
418
419 /* static fields */
420 const char *name;
421 enum omap_channel id;
422 enum omap_overlay_manager_caps caps;
423 struct list_head overlays;
424 enum omap_display_type supported_displays;
425 enum omap_dss_output_id supported_outputs;
426
427 /* dynamic fields */
428 struct omap_dss_device *output;
429
430 /*
431 * The following functions do not block:
432 *
433 * set_manager_info
434 * get_manager_info
435 * apply
436 *
437 * The rest of the functions may block and cannot be called from
438 * interrupt context
439 */
440
441 int (*set_output)(struct omap_overlay_manager *mgr,
442 struct omap_dss_device *output);
443 int (*unset_output)(struct omap_overlay_manager *mgr);
444
445 int (*set_manager_info)(struct omap_overlay_manager *mgr,
446 struct omap_overlay_manager_info *info);
447 void (*get_manager_info)(struct omap_overlay_manager *mgr,
448 struct omap_overlay_manager_info *info);
449
450 int (*apply)(struct omap_overlay_manager *mgr);
451 int (*wait_for_go)(struct omap_overlay_manager *mgr);
452 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
453
454 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
455};
456
457/* 22 pins means 1 clk lane and 10 data lanes */
458#define OMAP_DSS_MAX_DSI_PINS 22
459
460struct omap_dsi_pin_config {
461 int num_pins;
462 /*
463 * pin numbers in the following order:
464 * clk+, clk-
465 * data1+, data1-
466 * data2+, data2-
467 * ...
468 */
469 int pins[OMAP_DSS_MAX_DSI_PINS];
470};
471
472struct omap_dss_writeback_info {
473 u32 paddr;
474 u32 p_uv_addr;
475 u16 buf_width;
476 u16 width;
477 u16 height;
478 enum omap_color_mode color_mode;
479 u8 rotation;
480 enum omap_dss_rotation_type rotation_type;
481 bool mirror;
482 u8 pre_mult_alpha;
483};
484
485struct omapdss_dpi_ops {
486 int (*connect)(struct omap_dss_device *dssdev,
487 struct omap_dss_device *dst);
488 void (*disconnect)(struct omap_dss_device *dssdev,
489 struct omap_dss_device *dst);
490
491 int (*enable)(struct omap_dss_device *dssdev);
492 void (*disable)(struct omap_dss_device *dssdev);
493
494 int (*check_timings)(struct omap_dss_device *dssdev,
495 struct omap_video_timings *timings);
496 void (*set_timings)(struct omap_dss_device *dssdev,
497 struct omap_video_timings *timings);
498 void (*get_timings)(struct omap_dss_device *dssdev,
499 struct omap_video_timings *timings);
500
501 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
502};
503
504struct omapdss_sdi_ops {
505 int (*connect)(struct omap_dss_device *dssdev,
506 struct omap_dss_device *dst);
507 void (*disconnect)(struct omap_dss_device *dssdev,
508 struct omap_dss_device *dst);
509
510 int (*enable)(struct omap_dss_device *dssdev);
511 void (*disable)(struct omap_dss_device *dssdev);
512
513 int (*check_timings)(struct omap_dss_device *dssdev,
514 struct omap_video_timings *timings);
515 void (*set_timings)(struct omap_dss_device *dssdev,
516 struct omap_video_timings *timings);
517 void (*get_timings)(struct omap_dss_device *dssdev,
518 struct omap_video_timings *timings);
519
520 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
521};
522
523struct omapdss_dvi_ops {
524 int (*connect)(struct omap_dss_device *dssdev,
525 struct omap_dss_device *dst);
526 void (*disconnect)(struct omap_dss_device *dssdev,
527 struct omap_dss_device *dst);
528
529 int (*enable)(struct omap_dss_device *dssdev);
530 void (*disable)(struct omap_dss_device *dssdev);
531
532 int (*check_timings)(struct omap_dss_device *dssdev,
533 struct omap_video_timings *timings);
534 void (*set_timings)(struct omap_dss_device *dssdev,
535 struct omap_video_timings *timings);
536 void (*get_timings)(struct omap_dss_device *dssdev,
537 struct omap_video_timings *timings);
538};
539
540struct omapdss_atv_ops {
541 int (*connect)(struct omap_dss_device *dssdev,
542 struct omap_dss_device *dst);
543 void (*disconnect)(struct omap_dss_device *dssdev,
544 struct omap_dss_device *dst);
545
546 int (*enable)(struct omap_dss_device *dssdev);
547 void (*disable)(struct omap_dss_device *dssdev);
548
549 int (*check_timings)(struct omap_dss_device *dssdev,
550 struct omap_video_timings *timings);
551 void (*set_timings)(struct omap_dss_device *dssdev,
552 struct omap_video_timings *timings);
553 void (*get_timings)(struct omap_dss_device *dssdev,
554 struct omap_video_timings *timings);
555
556 void (*set_type)(struct omap_dss_device *dssdev,
557 enum omap_dss_venc_type type);
558 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
559 bool invert_polarity);
560
561 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
562 u32 (*get_wss)(struct omap_dss_device *dssdev);
563};
564
565struct omapdss_hdmi_ops {
566 int (*connect)(struct omap_dss_device *dssdev,
567 struct omap_dss_device *dst);
568 void (*disconnect)(struct omap_dss_device *dssdev,
569 struct omap_dss_device *dst);
570
571 int (*enable)(struct omap_dss_device *dssdev);
572 void (*disable)(struct omap_dss_device *dssdev);
573
574 int (*check_timings)(struct omap_dss_device *dssdev,
575 struct omap_video_timings *timings);
576 void (*set_timings)(struct omap_dss_device *dssdev,
577 struct omap_video_timings *timings);
578 void (*get_timings)(struct omap_dss_device *dssdev,
579 struct omap_video_timings *timings);
580
581 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
582 bool (*detect)(struct omap_dss_device *dssdev);
583
584 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
585 int (*set_infoframe)(struct omap_dss_device *dssdev,
586 const struct hdmi_avi_infoframe *avi);
587};
588
589struct omapdss_dsi_ops {
590 int (*connect)(struct omap_dss_device *dssdev,
591 struct omap_dss_device *dst);
592 void (*disconnect)(struct omap_dss_device *dssdev,
593 struct omap_dss_device *dst);
594
595 int (*enable)(struct omap_dss_device *dssdev);
596 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
597 bool enter_ulps);
598
599 /* bus configuration */
600 int (*set_config)(struct omap_dss_device *dssdev,
601 const struct omap_dss_dsi_config *cfg);
602 int (*configure_pins)(struct omap_dss_device *dssdev,
603 const struct omap_dsi_pin_config *pin_cfg);
604
605 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
606 bool enable);
607 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
608
609 int (*update)(struct omap_dss_device *dssdev, int channel,
610 void (*callback)(int, void *), void *data);
611
612 void (*bus_lock)(struct omap_dss_device *dssdev);
613 void (*bus_unlock)(struct omap_dss_device *dssdev);
614
615 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
616 void (*disable_video_output)(struct omap_dss_device *dssdev,
617 int channel);
618
619 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
620 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
621 int vc_id);
622 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
623
624 /* data transfer */
625 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
626 u8 *data, int len);
627 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
628 u8 *data, int len);
629 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
630 u8 *data, int len);
631
632 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
633 u8 *data, int len);
634 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
635 u8 *data, int len);
636 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
637 u8 *reqdata, int reqlen,
638 u8 *data, int len);
639
640 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
641
642 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
643 int channel, u16 plen);
644};
645
646struct omap_dss_device {
647 struct kobject kobj;
648 struct device *dev;
649
650 struct module *owner;
651
652 struct list_head panel_list;
653
654 /* alias in the form of "display%d" */
655 char alias[16];
656
657 enum omap_display_type type;
658 enum omap_display_type output_type;
659
660 union {
661 struct {
662 u8 data_lines;
663 } dpi;
664
665 struct {
666 u8 channel;
667 u8 data_lines;
668 } rfbi;
669
670 struct {
671 u8 datapairs;
672 } sdi;
673
674 struct {
675 int module;
676 } dsi;
677
678 struct {
679 enum omap_dss_venc_type type;
680 bool invert_polarity;
681 } venc;
682 } phy;
683
684 struct {
685 struct omap_video_timings timings;
686
687 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
688 enum omap_dss_dsi_mode dsi_mode;
689 } panel;
690
691 struct {
692 u8 pixel_size;
693 struct rfbi_timings rfbi_timings;
694 } ctrl;
695
696 const char *name;
697
698 /* used to match device to driver */
699 const char *driver_name;
700
701 void *data;
702
703 struct omap_dss_driver *driver;
704
705 union {
706 const struct omapdss_dpi_ops *dpi;
707 const struct omapdss_sdi_ops *sdi;
708 const struct omapdss_dvi_ops *dvi;
709 const struct omapdss_hdmi_ops *hdmi;
710 const struct omapdss_atv_ops *atv;
711 const struct omapdss_dsi_ops *dsi;
712 } ops;
713
714 /* helper variable for driver suspend/resume */
715 bool activate_after_resume;
716
717 enum omap_display_caps caps;
718
719 struct omap_dss_device *src;
720
721 enum omap_dss_display_state state;
722
723 /* OMAP DSS output specific fields */
724
725 struct list_head list;
726
727 /* DISPC channel for this output */
728 enum omap_channel dispc_channel;
729 bool dispc_channel_connected;
730
731 /* output instance */
732 enum omap_dss_output_id id;
733
734 /* the port number in the DT node */
735 int port_num;
736
737 /* dynamic fields */
738 struct omap_overlay_manager *manager;
739
740 struct omap_dss_device *dst;
741};
742
743struct omap_dss_driver {
744 int (*probe)(struct omap_dss_device *);
745 void (*remove)(struct omap_dss_device *);
746
747 int (*connect)(struct omap_dss_device *dssdev);
748 void (*disconnect)(struct omap_dss_device *dssdev);
749
750 int (*enable)(struct omap_dss_device *display);
751 void (*disable)(struct omap_dss_device *display);
752 int (*run_test)(struct omap_dss_device *display, int test);
753
754 int (*update)(struct omap_dss_device *dssdev,
755 u16 x, u16 y, u16 w, u16 h);
756 int (*sync)(struct omap_dss_device *dssdev);
757
758 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
759 int (*get_te)(struct omap_dss_device *dssdev);
760
761 u8 (*get_rotate)(struct omap_dss_device *dssdev);
762 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
763
764 bool (*get_mirror)(struct omap_dss_device *dssdev);
765 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
766
767 int (*memory_read)(struct omap_dss_device *dssdev,
768 void *buf, size_t size,
769 u16 x, u16 y, u16 w, u16 h);
770
771 void (*get_resolution)(struct omap_dss_device *dssdev,
772 u16 *xres, u16 *yres);
773 void (*get_dimensions)(struct omap_dss_device *dssdev,
774 u32 *width, u32 *height);
775 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
776
777 int (*check_timings)(struct omap_dss_device *dssdev,
778 struct omap_video_timings *timings);
779 void (*set_timings)(struct omap_dss_device *dssdev,
780 struct omap_video_timings *timings);
781 void (*get_timings)(struct omap_dss_device *dssdev,
782 struct omap_video_timings *timings);
783
784 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
785 u32 (*get_wss)(struct omap_dss_device *dssdev);
786
787 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
788 bool (*detect)(struct omap_dss_device *dssdev);
789
790 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
791 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
792 const struct hdmi_avi_infoframe *avi);
793};
794
795enum omapdss_version omapdss_get_version(void);
796bool omapdss_is_initialized(void);
797
798int omap_dss_register_driver(struct omap_dss_driver *);
799void omap_dss_unregister_driver(struct omap_dss_driver *);
800
801int omapdss_register_display(struct omap_dss_device *dssdev);
802void omapdss_unregister_display(struct omap_dss_device *dssdev);
803
804struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
805void omap_dss_put_device(struct omap_dss_device *dssdev);
806#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
807struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
808struct omap_dss_device *omap_dss_find_device(void *data,
809 int (*match)(struct omap_dss_device *dssdev, void *data));
810const char *omapdss_get_default_display_name(void);
811
812void videomode_to_omap_video_timings(const struct videomode *vm,
813 struct omap_video_timings *ovt);
814void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
815 struct videomode *vm);
816
817int dss_feat_get_num_mgrs(void);
818int dss_feat_get_num_ovls(void);
819enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
820
821
822
823int omap_dss_get_num_overlay_managers(void);
824struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
825
826int omap_dss_get_num_overlays(void);
827struct omap_overlay *omap_dss_get_overlay(int num);
828
829int omapdss_register_output(struct omap_dss_device *output);
830void omapdss_unregister_output(struct omap_dss_device *output);
831struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
832struct omap_dss_device *omap_dss_find_output(const char *name);
833struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
834int omapdss_output_set_device(struct omap_dss_device *out,
835 struct omap_dss_device *dssdev);
836int omapdss_output_unset_device(struct omap_dss_device *out);
837
838struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
839struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
840
841void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
842 u16 *xres, u16 *yres);
843int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
844void omapdss_default_get_timings(struct omap_dss_device *dssdev,
845 struct omap_video_timings *timings);
846
847typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
848int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
849int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
850
851int omapdss_compat_init(void);
852void omapdss_compat_uninit(void);
853
854static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
855{
856 return dssdev->src;
857}
858
859static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
860{
861 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
862}
863
864struct device_node *
865omapdss_of_get_next_port(const struct device_node *parent,
866 struct device_node *prev);
867
868struct device_node *
869omapdss_of_get_next_endpoint(const struct device_node *parent,
870 struct device_node *prev);
871
872struct device_node *
873omapdss_of_get_first_endpoint(const struct device_node *parent);
874
875struct omap_dss_device *
876omapdss_of_find_source_for_first_ep(struct device_node *node);
35a339ac
TV		 877
878u32 dispc_read_irqstatus(void);
879void dispc_clear_irqstatus(u32 mask);
880u32 dispc_read_irqenable(void);
881void dispc_write_irqenable(u32 mask);
882
883int dispc_request_irq(irq_handler_t handler, void *dev_id);
884void dispc_free_irq(void *dev_id);
885
886int dispc_runtime_get(void);
887void dispc_runtime_put(void);
888
889void dispc_mgr_enable(enum omap_channel channel, bool enable);
890bool dispc_mgr_is_enabled(enum omap_channel channel);
891u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
892u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
893u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
894bool dispc_mgr_go_busy(enum omap_channel channel);
895void dispc_mgr_go(enum omap_channel channel);
896void dispc_mgr_set_lcd_config(enum omap_channel channel,
897 const struct dss_lcd_mgr_config *config);
898void dispc_mgr_set_timings(enum omap_channel channel,
899 const struct omap_video_timings *timings);
900void dispc_mgr_setup(enum omap_channel channel,
901 const struct omap_overlay_manager_info *info);
acc3a231
JS		 902u32 dispc_mgr_gamma_size(enum omap_channel channel);
903void dispc_mgr_set_gamma(enum omap_channel channel,
904 const struct drm_color_lut *lut,
905 unsigned int length);
35a339ac 906
35a339ac
TV		 907int dispc_ovl_enable(enum omap_plane plane, bool enable);
908bool dispc_ovl_enabled(enum omap_plane plane);
909void dispc_ovl_set_channel_out(enum omap_plane plane,
910 enum omap_channel channel);
911int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
912 bool replication, const struct omap_video_timings *mgr_timings,
913 bool mem_to_mem);
914
7b9cb5ee
TV		 915enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);
916
564c7c75 917struct dss_mgr_ops {
e5cbb6e8 918 int (*connect)(enum omap_channel channel,
564c7c75 919 struct omap_dss_device *dst);
e5cbb6e8 920 void (*disconnect)(enum omap_channel channel,
564c7c75
TV		 921 struct omap_dss_device *dst);
922
e5cbb6e8
TV		 923 void (*start_update)(enum omap_channel channel);
924 int (*enable)(enum omap_channel channel);
925 void (*disable)(enum omap_channel channel);
926 void (*set_timings)(enum omap_channel channel,
564c7c75 927 const struct omap_video_timings *timings);
e5cbb6e8 928 void (*set_lcd_config)(enum omap_channel channel,
564c7c75 929 const struct dss_lcd_mgr_config *config);
e5cbb6e8 930 int (*register_framedone_handler)(enum omap_channel channel,
564c7c75 931 void (*handler)(void *), void *data);
e5cbb6e8 932 void (*unregister_framedone_handler)(enum omap_channel channel,
564c7c75
TV		 933 void (*handler)(void *), void *data);
934};
935
936int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
937void dss_uninstall_mgr_ops(void);
938
1b07b066 939int dss_mgr_connect(enum omap_channel channel,
caaecd9a 940 struct omap_dss_device *dst);
bdac3bb9 941void dss_mgr_disconnect(enum omap_channel channel,
caaecd9a 942 struct omap_dss_device *dst);
5c6ff3cd 943void dss_mgr_set_timings(enum omap_channel channel,
caaecd9a 944 const struct omap_video_timings *timings);
bb772e1a 945void dss_mgr_set_lcd_config(enum omap_channel channel,
caaecd9a 946 const struct dss_lcd_mgr_config *config);
85a8c622 947int dss_mgr_enable(enum omap_channel channel);
705fd454 948void dss_mgr_disable(enum omap_channel channel);
1f03f934 949void dss_mgr_start_update(enum omap_channel channel);
af235e31 950int dss_mgr_register_framedone_handler(enum omap_channel channel,
caaecd9a 951 void (*handler)(void *), void *data);
34218998 952void dss_mgr_unregister_framedone_handler(enum omap_channel channel,
caaecd9a
TV		 953 void (*handler)(void *), void *data);
954
35a339ac 955#endif /* __OMAP_DRM_DSS_H */
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