[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / omapdrm / dss / pll.c

/*
 * Copyright (C) 2014 Texas Instruments Incorporated
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "PLL"

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/regulator/consumer.h>
#include <linux/sched.h>

#include "omapdss.h"
#include "dss.h"

#define PLL_CONTROL			0x0000
#define PLL_STATUS			0x0004
#define PLL_GO				0x0008
#define PLL_CONFIGURATION1		0x000C
#define PLL_CONFIGURATION2		0x0010
#define PLL_CONFIGURATION3		0x0014
#define PLL_SSC_CONFIGURATION1		0x0018
#define PLL_SSC_CONFIGURATION2		0x001C
#define PLL_CONFIGURATION4		0x0020

static struct dss_pll *dss_plls[4];

int dss_pll_register(struct dss_pll *pll)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
		if (!dss_plls[i]) {
			dss_plls[i] = pll;
			return 0;
		}
	}

	return -EBUSY;
}

void dss_pll_unregister(struct dss_pll *pll)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
		if (dss_plls[i] == pll) {
			dss_plls[i] = NULL;
			return;
		}
	}
}

struct dss_pll *dss_pll_find(const char *name)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
		if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0)
			return dss_plls[i];
	}

	return NULL;
}

struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src)
{
	struct dss_pll *pll;

	switch (src) {
	default:
	case DSS_CLK_SRC_FCK:
		return NULL;

	case DSS_CLK_SRC_HDMI_PLL:
		return dss_pll_find("hdmi");

	case DSS_CLK_SRC_PLL1_1:
	case DSS_CLK_SRC_PLL1_2:
	case DSS_CLK_SRC_PLL1_3:
		pll = dss_pll_find("dsi0");
		if (!pll)
			pll = dss_pll_find("video0");
		return pll;

	case DSS_CLK_SRC_PLL2_1:
	case DSS_CLK_SRC_PLL2_2:
	case DSS_CLK_SRC_PLL2_3:
		pll = dss_pll_find("dsi1");
		if (!pll)
			pll = dss_pll_find("video1");
		return pll;
	}
}

unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src)
{
	switch (src) {
	case DSS_CLK_SRC_HDMI_PLL:
		return 0;

	case DSS_CLK_SRC_PLL1_1:
	case DSS_CLK_SRC_PLL2_1:
		return 0;

	case DSS_CLK_SRC_PLL1_2:
	case DSS_CLK_SRC_PLL2_2:
		return 1;

	case DSS_CLK_SRC_PLL1_3:
	case DSS_CLK_SRC_PLL2_3:
		return 2;

	default:
		return 0;
	}
}

int dss_pll_enable(struct dss_pll *pll)
{
	int r;

	r = clk_prepare_enable(pll->clkin);
	if (r)
		return r;

	if (pll->regulator) {
		r = regulator_enable(pll->regulator);
		if (r)
			goto err_reg;
	}

	r = pll->ops->enable(pll);
	if (r)
		goto err_enable;

	return 0;

err_enable:
	if (pll->regulator)
		regulator_disable(pll->regulator);
err_reg:
	clk_disable_unprepare(pll->clkin);
	return r;
}

void dss_pll_disable(struct dss_pll *pll)
{
	pll->ops->disable(pll);

	if (pll->regulator)
		regulator_disable(pll->regulator);

	clk_disable_unprepare(pll->clkin);

	memset(&pll->cinfo, 0, sizeof(pll->cinfo));
}

int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo)
{
	int r;

	r = pll->ops->set_config(pll, cinfo);
	if (r)
		return r;

	pll->cinfo = *cinfo;

	return 0;
}

bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
		unsigned long out_min, unsigned long out_max,
		dss_hsdiv_calc_func func, void *data)
{
	const struct dss_pll_hw *hw = pll->hw;
	int m, m_start, m_stop;
	unsigned long out;

	out_min = out_min ? out_min : 1;
	out_max = out_max ? out_max : ULONG_MAX;

	m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);

	m_stop = min((unsigned)(clkdco / out_min), hw->mX_max);

	for (m = m_start; m <= m_stop; ++m) {
		out = clkdco / m;

		if (func(m, out, data))
			return true;
	}

	return false;
}

/*
 * clkdco = clkin / n * m * 2
 * clkoutX = clkdco / mX
 */
bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
		unsigned long pll_min, unsigned long pll_max,
		dss_pll_calc_func func, void *data)
{
	const struct dss_pll_hw *hw = pll->hw;
	int n, n_min, n_max;
	int m, m_min, m_max;
	unsigned long fint, clkdco;
	unsigned long pll_hw_max;
	unsigned long fint_hw_min, fint_hw_max;

	pll_hw_max = hw->clkdco_max;

	fint_hw_min = hw->fint_min;
	fint_hw_max = hw->fint_max;

	n_min = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
	n_max = min((unsigned)(clkin / fint_hw_min), hw->n_max);

	pll_max = pll_max ? pll_max : ULONG_MAX;

	/* Try to find high N & M to avoid jitter (DRA7 errata i886) */
	for (n = n_max; n >= n_min; --n) {
		fint = clkin / n;

		m_min = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
				1ul);
		m_max = min3((unsigned)(pll_max / fint / 2),
				(unsigned)(pll_hw_max / fint / 2),
				hw->m_max);

		for (m = m_max; m >= m_min; --m) {
			clkdco = 2 * m * fint;

			if (func(n, m, fint, clkdco, data))
				return true;
		}
	}

	return false;
}

/*
 * This calculates a PLL config that will provide the target_clkout rate
 * for clkout. Additionally clkdco rate will be the same as clkout rate
 * when clkout rate is >= min_clkdco.
 *
 * clkdco = clkin / n * m + clkin / n * mf / 262144
 * clkout = clkdco / m2
 */
bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
	unsigned long target_clkout, struct dss_pll_clock_info *cinfo)
{
	unsigned long fint, clkdco, clkout;
	unsigned long target_clkdco;
	unsigned long min_dco;
	unsigned n, m, mf, m2, sd;
	const struct dss_pll_hw *hw = pll->hw;

	DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout);

	/* Fint */
	n = DIV_ROUND_UP(clkin, hw->fint_max);
	fint = clkin / n;

	/* adjust m2 so that the clkdco will be high enough */
	min_dco = roundup(hw->clkdco_min, fint);
	m2 = DIV_ROUND_UP(min_dco, target_clkout);
	if (m2 == 0)
		m2 = 1;

	target_clkdco = target_clkout * m2;
	m = target_clkdco / fint;

	clkdco = fint * m;

	/* adjust clkdco with fractional mf */
	if (WARN_ON(target_clkdco - clkdco > fint))
		mf = 0;
	else
		mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);

	if (mf > 0)
		clkdco += (u32)div_u64((u64)mf * fint, 262144);

	clkout = clkdco / m2;

	/* sigma-delta */
	sd = DIV_ROUND_UP(fint * m, 250000000);

	DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
		n, m, mf, m2, sd);
	DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);

	cinfo->n = n;
	cinfo->m = m;
	cinfo->mf = mf;
	cinfo->mX[0] = m2;
	cinfo->sd = sd;

	cinfo->fint = fint;
	cinfo->clkdco = clkdco;
	cinfo->clkout[0] = clkout;

	return true;
}

static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
{
	unsigned long timeout;
	ktime_t wait;
	int t;

	/* first busyloop to see if the bit changes right away */
	t = 100;
	while (t-- > 0) {
		if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
			return value;
	}

	/* then loop for 500ms, sleeping for 1ms in between */
	timeout = jiffies + msecs_to_jiffies(500);
	while (time_before(jiffies, timeout)) {
		if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
			return value;

		wait = ns_to_ktime(1000 * 1000);
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
	}

	return !value;
}

int dss_pll_wait_reset_done(struct dss_pll *pll)
{
	void __iomem *base = pll->base;

	if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
		return -ETIMEDOUT;
	else
		return 0;
}

static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
{
	int t = 100;

	while (t-- > 0) {
		u32 v = readl_relaxed(pll->base + PLL_STATUS);
		v &= hsdiv_ack_mask;
		if (v == hsdiv_ack_mask)
			return 0;
	}

	return -ETIMEDOUT;
}

int dss_pll_write_config_type_a(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo)
{
	const struct dss_pll_hw *hw = pll->hw;
	void __iomem *base = pll->base;
	int r = 0;
	u32 l;

	l = 0;
	if (hw->has_stopmode)
		l = FLD_MOD(l, 1, 0, 0);		/* PLL_STOPMODE */
	l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb);	/* PLL_REGN */
	l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb);		/* PLL_REGM */
	/* M4 */
	l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,
			hw->mX_msb[0], hw->mX_lsb[0]);
	/* M5 */
	l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,
			hw->mX_msb[1], hw->mX_lsb[1]);
	writel_relaxed(l, base + PLL_CONFIGURATION1);

	l = 0;
	/* M6 */
	l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,
			hw->mX_msb[2], hw->mX_lsb[2]);
	/* M7 */
	l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,
			hw->mX_msb[3], hw->mX_lsb[3]);
	writel_relaxed(l, base + PLL_CONFIGURATION3);

	l = readl_relaxed(base + PLL_CONFIGURATION2);
	if (hw->has_freqsel) {
		u32 f = cinfo->fint < 1000000 ? 0x3 :
			cinfo->fint < 1250000 ? 0x4 :
			cinfo->fint < 1500000 ? 0x5 :
			cinfo->fint < 1750000 ? 0x6 :
			0x7;

		l = FLD_MOD(l, f, 4, 1);	/* PLL_FREQSEL */
	} else if (hw->has_selfreqdco) {
		u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4;

		l = FLD_MOD(l, f, 3, 1);	/* PLL_SELFREQDCO */
	}
	l = FLD_MOD(l, 1, 13, 13);		/* PLL_REFEN */
	l = FLD_MOD(l, 0, 14, 14);		/* PHY_CLKINEN */
	l = FLD_MOD(l, 0, 16, 16);		/* M4_CLOCK_EN */
	l = FLD_MOD(l, 0, 18, 18);		/* M5_CLOCK_EN */
	l = FLD_MOD(l, 1, 20, 20);		/* HSDIVBYPASS */
	if (hw->has_refsel)
		l = FLD_MOD(l, 3, 22, 21);	/* REFSEL = sysclk */
	l = FLD_MOD(l, 0, 23, 23);		/* M6_CLOCK_EN */
	l = FLD_MOD(l, 0, 25, 25);		/* M7_CLOCK_EN */
	writel_relaxed(l, base + PLL_CONFIGURATION2);

	writel_relaxed(1, base + PLL_GO);	/* PLL_GO */

	if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
		DSSERR("DSS DPLL GO bit not going down.\n");
		r = -EIO;
		goto err;
	}

	if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
		DSSERR("cannot lock DSS DPLL\n");
		r = -EIO;
		goto err;
	}

	l = readl_relaxed(base + PLL_CONFIGURATION2);
	l = FLD_MOD(l, 1, 14, 14);			/* PHY_CLKINEN */
	l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16);	/* M4_CLOCK_EN */
	l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18);	/* M5_CLOCK_EN */
	l = FLD_MOD(l, 0, 20, 20);			/* HSDIVBYPASS */
	l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23);	/* M6_CLOCK_EN */
	l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25);	/* M7_CLOCK_EN */
	writel_relaxed(l, base + PLL_CONFIGURATION2);

	r = dss_wait_hsdiv_ack(pll,
		(cinfo->mX[0] ? BIT(7) : 0) |
		(cinfo->mX[1] ? BIT(8) : 0) |
		(cinfo->mX[2] ? BIT(10) : 0) |
		(cinfo->mX[3] ? BIT(11) : 0));
	if (r) {
		DSSERR("failed to enable HSDIV clocks\n");
		goto err;
	}

err:
	return r;
}

int dss_pll_write_config_type_b(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo)
{
	const struct dss_pll_hw *hw = pll->hw;
	void __iomem *base = pll->base;
	u32 l;

	l = 0;
	l = FLD_MOD(l, cinfo->m, 20, 9);	/* PLL_REGM */
	l = FLD_MOD(l, cinfo->n - 1, 8, 1);	/* PLL_REGN */
	writel_relaxed(l, base + PLL_CONFIGURATION1);

	l = readl_relaxed(base + PLL_CONFIGURATION2);
	l = FLD_MOD(l, 0x0, 12, 12);	/* PLL_HIGHFREQ divide by 2 */
	l = FLD_MOD(l, 0x1, 13, 13);	/* PLL_REFEN */
	l = FLD_MOD(l, 0x0, 14, 14);	/* PHY_CLKINEN */
	if (hw->has_refsel)
		l = FLD_MOD(l, 0x3, 22, 21);	/* REFSEL = SYSCLK */

	/* PLL_SELFREQDCO */
	if (cinfo->clkdco > hw->clkdco_low)
		l = FLD_MOD(l, 0x4, 3, 1);
	else
		l = FLD_MOD(l, 0x2, 3, 1);
	writel_relaxed(l, base + PLL_CONFIGURATION2);

	l = readl_relaxed(base + PLL_CONFIGURATION3);
	l = FLD_MOD(l, cinfo->sd, 17, 10);	/* PLL_REGSD */
	writel_relaxed(l, base + PLL_CONFIGURATION3);

	l = readl_relaxed(base + PLL_CONFIGURATION4);
	l = FLD_MOD(l, cinfo->mX[0], 24, 18);	/* PLL_REGM2 */
	l = FLD_MOD(l, cinfo->mf, 17, 0);	/* PLL_REGM_F */
	writel_relaxed(l, base + PLL_CONFIGURATION4);

	writel_relaxed(1, base + PLL_GO);	/* PLL_GO */

	if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
		DSSERR("DSS DPLL GO bit not going down.\n");
		return -EIO;
	}

	if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
		DSSERR("cannot lock DSS DPLL\n");
		return -ETIMEDOUT;
	}

	return 0;
}
Commit	Line	Data
0a20170a TV	1	/*
	2	* Copyright (C) 2014 Texas Instruments Incorporated
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License version 2 as published by
	6	* the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#define DSS_SUBSYS_NAME "PLL"
	18
	19	#include <linux/clk.h>
	20	#include <linux/io.h>
	21	#include <linux/kernel.h>
	22	#include <linux/regulator/consumer.h>
	23	#include <linux/sched.h>
	24
32043da7	25	#include "omapdss.h"
0a20170a TV	26	#include "dss.h"
	27
	28	#define PLL_CONTROL 0x0000
	29	#define PLL_STATUS 0x0004
	30	#define PLL_GO 0x0008
	31	#define PLL_CONFIGURATION1 0x000C
	32	#define PLL_CONFIGURATION2 0x0010
	33	#define PLL_CONFIGURATION3 0x0014
	34	#define PLL_SSC_CONFIGURATION1 0x0018
	35	#define PLL_SSC_CONFIGURATION2 0x001C
	36	#define PLL_CONFIGURATION4 0x0020
	37
	38	static struct dss_pll *dss_plls[4];
	39
	40	int dss_pll_register(struct dss_pll *pll)
	41	{
	42	int i;
	43
	44	for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
	45	if (!dss_plls[i]) {
	46	dss_plls[i] = pll;
	47	return 0;
	48	}
	49	}
	50
	51	return -EBUSY;
	52	}
	53
	54	void dss_pll_unregister(struct dss_pll *pll)
	55	{
	56	int i;
	57
	58	for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
	59	if (dss_plls[i] == pll) {
	60	dss_plls[i] = NULL;
	61	return;
	62	}
	63	}
	64	}
	65
	66	struct dss_pll dss_pll_find(const char name)
	67	{
	68	int i;
	69
	70	for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) {
	71	if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0)
	72	return dss_plls[i];
	73	}
	74
	75	return NULL;
	76	}
	77
5670bd72 TV	78	struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src)
	79	{
	80	struct dss_pll *pll;
	81
	82	switch (src) {
	83	default:
	84	case DSS_CLK_SRC_FCK:
	85	return NULL;
	86
	87	case DSS_CLK_SRC_HDMI_PLL:
	88	return dss_pll_find("hdmi");
	89
	90	case DSS_CLK_SRC_PLL1_1:
	91	case DSS_CLK_SRC_PLL1_2:
	92	case DSS_CLK_SRC_PLL1_3:
	93	pll = dss_pll_find("dsi0");
	94	if (!pll)
	95	pll = dss_pll_find("video0");
	96	return pll;
	97
	98	case DSS_CLK_SRC_PLL2_1:
	99	case DSS_CLK_SRC_PLL2_2:
	100	case DSS_CLK_SRC_PLL2_3:
	101	pll = dss_pll_find("dsi1");
	102	if (!pll)
	103	pll = dss_pll_find("video1");
	104	return pll;
	105	}
	106	}
	107
	108	unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src)
	109	{
	110	switch (src) {
	111	case DSS_CLK_SRC_HDMI_PLL:
	112	return 0;
	113
	114	case DSS_CLK_SRC_PLL1_1:
	115	case DSS_CLK_SRC_PLL2_1:
	116	return 0;
	117
	118	case DSS_CLK_SRC_PLL1_2:
	119	case DSS_CLK_SRC_PLL2_2:
	120	return 1;
	121
	122	case DSS_CLK_SRC_PLL1_3:
	123	case DSS_CLK_SRC_PLL2_3:
	124	return 2;
	125
	126	default:
	127	return 0;
	128	}
	129	}
	130
0a20170a TV	131	int dss_pll_enable(struct dss_pll *pll)
	132	{
	133	int r;
	134
	135	r = clk_prepare_enable(pll->clkin);
	136	if (r)
	137	return r;
	138
	139	if (pll->regulator) {
	140	r = regulator_enable(pll->regulator);
	141	if (r)
	142	goto err_reg;
	143	}
	144
	145	r = pll->ops->enable(pll);
	146	if (r)
	147	goto err_enable;
	148
	149	return 0;
	150
	151	err_enable:
811174f4 DC	152	if (pll->regulator)
811174f4 DC	153	regulator_disable(pll->regulator);
0a20170a TV	154	err_reg:
	155	clk_disable_unprepare(pll->clkin);
	156	return r;
	157	}
	158
	159	void dss_pll_disable(struct dss_pll *pll)
	160	{
	161	pll->ops->disable(pll);
	162
	163	if (pll->regulator)
	164	regulator_disable(pll->regulator);
	165
	166	clk_disable_unprepare(pll->clkin);
	167
	168	memset(&pll->cinfo, 0, sizeof(pll->cinfo));
	169	}
	170
	171	int dss_pll_set_config(struct dss_pll pll, const struct dss_pll_clock_info cinfo)
	172	{
	173	int r;
	174
	175	r = pll->ops->set_config(pll, cinfo);
	176	if (r)
	177	return r;
	178
	179	pll->cinfo = *cinfo;
	180
	181	return 0;
	182	}
	183
cd0715ff	184	bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
0a20170a TV	185	unsigned long out_min, unsigned long out_max,
	186	dss_hsdiv_calc_func func, void *data)
	187	{
	188	const struct dss_pll_hw *hw = pll->hw;
	189	int m, m_start, m_stop;
	190	unsigned long out;
	191
	192	out_min = out_min ? out_min : 1;
	193	out_max = out_max ? out_max : ULONG_MAX;
	194
	195	m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);
	196
	197	m_stop = min((unsigned)(clkdco / out_min), hw->mX_max);
	198
	199	for (m = m_start; m <= m_stop; ++m) {
	200	out = clkdco / m;
	201
	202	if (func(m, out, data))
	203	return true;
	204	}
	205
	206	return false;
	207	}
	208
f44b717c TV	209	/*
	210	* clkdco = clkin / n * m * 2
	211	* clkoutX = clkdco / mX
	212	*/
cd0715ff	213	bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
0a20170a TV	214	unsigned long pll_min, unsigned long pll_max,
	215	dss_pll_calc_func func, void *data)
	216	{
	217	const struct dss_pll_hw *hw = pll->hw;
7d267f06 TV	218	int n, n_min, n_max;
7d267f06 TV	219	int m, m_min, m_max;
0a20170a TV	220	unsigned long fint, clkdco;
	221	unsigned long pll_hw_max;
	222	unsigned long fint_hw_min, fint_hw_max;
	223
	224	pll_hw_max = hw->clkdco_max;
	225
	226	fint_hw_min = hw->fint_min;
	227	fint_hw_max = hw->fint_max;
	228
7d267f06 TV	229	n_min = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
7d267f06 TV	230	n_max = min((unsigned)(clkin / fint_hw_min), hw->n_max);
0a20170a TV	231
	232	pll_max = pll_max ? pll_max : ULONG_MAX;
	233
7d267f06 TV	234	/* Try to find high N & M to avoid jitter (DRA7 errata i886) */
7d267f06 TV	235	for (n = n_max; n >= n_min; --n) {
0a20170a TV	236	fint = clkin / n;
0a20170a TV	237
7d267f06	238	m_min = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
0a20170a	239	1ul);
7d267f06	240	m_max = min3((unsigned)(pll_max / fint / 2),
0a20170a TV	241	(unsigned)(pll_hw_max / fint / 2),
	242	hw->m_max);
	243
7d267f06	244	for (m = m_max; m >= m_min; --m) {
0a20170a TV	245	clkdco = 2 * m * fint;
	246
	247	if (func(n, m, fint, clkdco, data))
	248	return true;
	249	}
	250	}
	251
	252	return false;
	253	}
	254
c107751d TV	255	/*
	256	* This calculates a PLL config that will provide the target_clkout rate
	257	* for clkout. Additionally clkdco rate will be the same as clkout rate
	258	* when clkout rate is >= min_clkdco.
f44b717c TV	259	*
	260	* clkdco = clkin / n * m + clkin / n * mf / 262144
	261	* clkout = clkdco / m2
c107751d	262	*/
c17dc0e3	263	bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
c107751d	264	unsigned long target_clkout, struct dss_pll_clock_info *cinfo)
c17dc0e3 TV	265	{
c17dc0e3 TV	266	unsigned long fint, clkdco, clkout;
c107751d	267	unsigned long target_clkdco;
c17dc0e3 TV	268	unsigned long min_dco;
	269	unsigned n, m, mf, m2, sd;
	270	const struct dss_pll_hw *hw = pll->hw;
	271
c107751d	272	DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout);
c17dc0e3 TV	273
	274	/* Fint */
	275	n = DIV_ROUND_UP(clkin, hw->fint_max);
	276	fint = clkin / n;
	277
	278	/* adjust m2 so that the clkdco will be high enough */
	279	min_dco = roundup(hw->clkdco_min, fint);
c107751d	280	m2 = DIV_ROUND_UP(min_dco, target_clkout);
c17dc0e3 TV	281	if (m2 == 0)
	282	m2 = 1;
	283
c107751d	284	target_clkdco = target_clkout * m2;
c17dc0e3 TV	285	m = target_clkdco / fint;
	286
	287	clkdco = fint * m;
	288
	289	/* adjust clkdco with fractional mf */
	290	if (WARN_ON(target_clkdco - clkdco > fint))
	291	mf = 0;
	292	else
	293	mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
	294
	295	if (mf > 0)
	296	clkdco += (u32)div_u64((u64)mf * fint, 262144);
	297
	298	clkout = clkdco / m2;
	299
	300	/* sigma-delta */
	301	sd = DIV_ROUND_UP(fint * m, 250000000);
	302
	303	DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
	304	n, m, mf, m2, sd);
	305	DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
	306
	307	cinfo->n = n;
	308	cinfo->m = m;
	309	cinfo->mf = mf;
	310	cinfo->mX[0] = m2;
	311	cinfo->sd = sd;
	312
	313	cinfo->fint = fint;
	314	cinfo->clkdco = clkdco;
	315	cinfo->clkout[0] = clkout;
	316
	317	return true;
	318	}
	319
0a20170a TV	320	static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
	321	{
	322	unsigned long timeout;
	323	ktime_t wait;
	324	int t;
	325
	326	/* first busyloop to see if the bit changes right away */
	327	t = 100;
	328	while (t-- > 0) {
	329	if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
	330	return value;
	331	}
	332
	333	/* then loop for 500ms, sleeping for 1ms in between */
	334	timeout = jiffies + msecs_to_jiffies(500);
	335	while (time_before(jiffies, timeout)) {
	336	if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value)
	337	return value;
	338
	339	wait = ns_to_ktime(1000 * 1000);
	340	set_current_state(TASK_UNINTERRUPTIBLE);
	341	schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
	342	}
	343
	344	return !value;
	345	}
	346
eb30199b TV	347	int dss_pll_wait_reset_done(struct dss_pll *pll)
	348	{
	349	void __iomem *base = pll->base;
	350
	351	if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
	352	return -ETIMEDOUT;
	353	else
	354	return 0;
	355	}
	356
0a20170a TV	357	static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
	358	{
	359	int t = 100;
	360
	361	while (t-- > 0) {
	362	u32 v = readl_relaxed(pll->base + PLL_STATUS);
	363	v &= hsdiv_ack_mask;
	364	if (v == hsdiv_ack_mask)
	365	return 0;
	366	}
	367
	368	return -ETIMEDOUT;
	369	}
	370
	371	int dss_pll_write_config_type_a(struct dss_pll *pll,
	372	const struct dss_pll_clock_info *cinfo)
	373	{
	374	const struct dss_pll_hw *hw = pll->hw;
	375	void __iomem *base = pll->base;
	376	int r = 0;
	377	u32 l;
	378
	379	l = 0;
	380	if (hw->has_stopmode)
	381	l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */
	382	l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb); /* PLL_REGN */
	383	l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb); /* PLL_REGM */
	384	/* M4 */
	385	l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,
	386	hw->mX_msb[0], hw->mX_lsb[0]);
	387	/* M5 */
	388	l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,
	389	hw->mX_msb[1], hw->mX_lsb[1]);
	390	writel_relaxed(l, base + PLL_CONFIGURATION1);
	391
	392	l = 0;
	393	/* M6 */
	394	l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,
	395	hw->mX_msb[2], hw->mX_lsb[2]);
	396	/* M7 */
	397	l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,
	398	hw->mX_msb[3], hw->mX_lsb[3]);
	399	writel_relaxed(l, base + PLL_CONFIGURATION3);
	400
	401	l = readl_relaxed(base + PLL_CONFIGURATION2);
	402	if (hw->has_freqsel) {
	403	u32 f = cinfo->fint < 1000000 ? 0x3 :
	404	cinfo->fint < 1250000 ? 0x4 :
	405	cinfo->fint < 1500000 ? 0x5 :
	406	cinfo->fint < 1750000 ? 0x6 :
	407	0x7;
	408
	409	l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */
	410	} else if (hw->has_selfreqdco) {
	411	u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4;
	412
	413	l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */
	414	}
	415	l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
	416	l = FLD_MOD(l, 0, 14, 14); /* PHY_CLKINEN */
	417	l = FLD_MOD(l, 0, 16, 16); /* M4_CLOCK_EN */
	418	l = FLD_MOD(l, 0, 18, 18); /* M5_CLOCK_EN */
	419	l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */
	420	if (hw->has_refsel)
421	l = FLD_MOD(l, 3, 22, 21); /* REFSEL = sysclk */
422	l = FLD_MOD(l, 0, 23, 23); /* M6_CLOCK_EN */
423	l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */
424	writel_relaxed(l, base + PLL_CONFIGURATION2);
425
426	writel_relaxed(1, base + PLL_GO); /* PLL_GO */
427
428	if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
429	DSSERR("DSS DPLL GO bit not going down.\n");
430	r = -EIO;
431	goto err;
432	}
433
434	if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
435	DSSERR("cannot lock DSS DPLL\n");
436	r = -EIO;
437	goto err;
438	}
439
440	l = readl_relaxed(base + PLL_CONFIGURATION2);
441	l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */
442	l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */
443	l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */
444	l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */
445	l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */
446	l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */
447	writel_relaxed(l, base + PLL_CONFIGURATION2);
448
449	r = dss_wait_hsdiv_ack(pll,
450	(cinfo->mX[0] ? BIT(7) : 0) \|
451	(cinfo->mX[1] ? BIT(8) : 0) \|
452	(cinfo->mX[2] ? BIT(10) : 0) \|
453	(cinfo->mX[3] ? BIT(11) : 0));
454	if (r) {
455	DSSERR("failed to enable HSDIV clocks\n");
456	goto err;
457	}
458
459	err:
460	return r;
461	}
462
463	int dss_pll_write_config_type_b(struct dss_pll *pll,
464	const struct dss_pll_clock_info *cinfo)
465	{
466	const struct dss_pll_hw *hw = pll->hw;
467	void __iomem *base = pll->base;
468	u32 l;
469
470	l = 0;
471	l = FLD_MOD(l, cinfo->m, 20, 9); /* PLL_REGM */
472	l = FLD_MOD(l, cinfo->n - 1, 8, 1); /* PLL_REGN */
473	writel_relaxed(l, base + PLL_CONFIGURATION1);
474
475	l = readl_relaxed(base + PLL_CONFIGURATION2);
476	l = FLD_MOD(l, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
477	l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */
478	l = FLD_MOD(l, 0x0, 14, 14); /* PHY_CLKINEN */
479	if (hw->has_refsel)
480	l = FLD_MOD(l, 0x3, 22, 21); /* REFSEL = SYSCLK */
481
482	/* PLL_SELFREQDCO */
483	if (cinfo->clkdco > hw->clkdco_low)
484	l = FLD_MOD(l, 0x4, 3, 1);
485	else
486	l = FLD_MOD(l, 0x2, 3, 1);
487	writel_relaxed(l, base + PLL_CONFIGURATION2);
488
489	l = readl_relaxed(base + PLL_CONFIGURATION3);
490	l = FLD_MOD(l, cinfo->sd, 17, 10); /* PLL_REGSD */
491	writel_relaxed(l, base + PLL_CONFIGURATION3);
492
493	l = readl_relaxed(base + PLL_CONFIGURATION4);
494	l = FLD_MOD(l, cinfo->mX[0], 24, 18); /* PLL_REGM2 */
495	l = FLD_MOD(l, cinfo->mf, 17, 0); /* PLL_REGM_F */
496	writel_relaxed(l, base + PLL_CONFIGURATION4);
497
498	writel_relaxed(1, base + PLL_GO); /* PLL_GO */
499
500	if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
501	DSSERR("DSS DPLL GO bit not going down.\n");
502	return -EIO;
503	}
504
505	if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
506	DSSERR("cannot lock DSS DPLL\n");
507	return -ETIMEDOUT;
508	}
509
510	return 0;
511	}