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b2886273 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/venc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * VENC settings from TI's DSS driver | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "VENC" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/completion.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/regulator/consumer.h> | |
4fbafaf3 | 36 | #include <linux/pm_runtime.h> |
a2207021 | 37 | #include <linux/of.h> |
09bffa6e | 38 | #include <linux/of_graph.h> |
736e60dd | 39 | #include <linux/component.h> |
b2886273 | 40 | |
32043da7 | 41 | #include "omapdss.h" |
b2886273 | 42 | #include "dss.h" |
525dae61 | 43 | #include "dss_features.h" |
b2886273 | 44 | |
b2886273 TV |
45 | /* Venc registers */ |
46 | #define VENC_REV_ID 0x00 | |
47 | #define VENC_STATUS 0x04 | |
48 | #define VENC_F_CONTROL 0x08 | |
49 | #define VENC_VIDOUT_CTRL 0x10 | |
50 | #define VENC_SYNC_CTRL 0x14 | |
51 | #define VENC_LLEN 0x1C | |
52 | #define VENC_FLENS 0x20 | |
53 | #define VENC_HFLTR_CTRL 0x24 | |
54 | #define VENC_CC_CARR_WSS_CARR 0x28 | |
55 | #define VENC_C_PHASE 0x2C | |
56 | #define VENC_GAIN_U 0x30 | |
57 | #define VENC_GAIN_V 0x34 | |
58 | #define VENC_GAIN_Y 0x38 | |
59 | #define VENC_BLACK_LEVEL 0x3C | |
60 | #define VENC_BLANK_LEVEL 0x40 | |
61 | #define VENC_X_COLOR 0x44 | |
62 | #define VENC_M_CONTROL 0x48 | |
63 | #define VENC_BSTAMP_WSS_DATA 0x4C | |
64 | #define VENC_S_CARR 0x50 | |
65 | #define VENC_LINE21 0x54 | |
66 | #define VENC_LN_SEL 0x58 | |
67 | #define VENC_L21__WC_CTL 0x5C | |
68 | #define VENC_HTRIGGER_VTRIGGER 0x60 | |
69 | #define VENC_SAVID__EAVID 0x64 | |
70 | #define VENC_FLEN__FAL 0x68 | |
71 | #define VENC_LAL__PHASE_RESET 0x6C | |
72 | #define VENC_HS_INT_START_STOP_X 0x70 | |
73 | #define VENC_HS_EXT_START_STOP_X 0x74 | |
74 | #define VENC_VS_INT_START_X 0x78 | |
75 | #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C | |
76 | #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 | |
77 | #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 | |
78 | #define VENC_VS_EXT_STOP_Y 0x88 | |
79 | #define VENC_AVID_START_STOP_X 0x90 | |
80 | #define VENC_AVID_START_STOP_Y 0x94 | |
81 | #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 | |
82 | #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 | |
83 | #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 | |
84 | #define VENC_TVDETGP_INT_START_STOP_X 0xB0 | |
85 | #define VENC_TVDETGP_INT_START_STOP_Y 0xB4 | |
86 | #define VENC_GEN_CTRL 0xB8 | |
87 | #define VENC_OUTPUT_CONTROL 0xC4 | |
88 | #define VENC_OUTPUT_TEST 0xC8 | |
89 | #define VENC_DAC_B__DAC_C 0xC8 | |
90 | ||
91 | struct venc_config { | |
92 | u32 f_control; | |
93 | u32 vidout_ctrl; | |
94 | u32 sync_ctrl; | |
95 | u32 llen; | |
96 | u32 flens; | |
97 | u32 hfltr_ctrl; | |
98 | u32 cc_carr_wss_carr; | |
99 | u32 c_phase; | |
100 | u32 gain_u; | |
101 | u32 gain_v; | |
102 | u32 gain_y; | |
103 | u32 black_level; | |
104 | u32 blank_level; | |
105 | u32 x_color; | |
106 | u32 m_control; | |
107 | u32 bstamp_wss_data; | |
108 | u32 s_carr; | |
109 | u32 line21; | |
110 | u32 ln_sel; | |
111 | u32 l21__wc_ctl; | |
112 | u32 htrigger_vtrigger; | |
113 | u32 savid__eavid; | |
114 | u32 flen__fal; | |
115 | u32 lal__phase_reset; | |
116 | u32 hs_int_start_stop_x; | |
117 | u32 hs_ext_start_stop_x; | |
118 | u32 vs_int_start_x; | |
119 | u32 vs_int_stop_x__vs_int_start_y; | |
120 | u32 vs_int_stop_y__vs_ext_start_x; | |
121 | u32 vs_ext_stop_x__vs_ext_start_y; | |
122 | u32 vs_ext_stop_y; | |
123 | u32 avid_start_stop_x; | |
124 | u32 avid_start_stop_y; | |
125 | u32 fid_int_start_x__fid_int_start_y; | |
126 | u32 fid_int_offset_y__fid_ext_start_x; | |
127 | u32 fid_ext_start_y__fid_ext_offset_y; | |
128 | u32 tvdetgp_int_start_stop_x; | |
129 | u32 tvdetgp_int_start_stop_y; | |
130 | u32 gen_ctrl; | |
131 | }; | |
132 | ||
133 | /* from TRM */ | |
134 | static const struct venc_config venc_config_pal_trm = { | |
135 | .f_control = 0, | |
136 | .vidout_ctrl = 1, | |
137 | .sync_ctrl = 0x40, | |
138 | .llen = 0x35F, /* 863 */ | |
139 | .flens = 0x270, /* 624 */ | |
140 | .hfltr_ctrl = 0, | |
141 | .cc_carr_wss_carr = 0x2F7225ED, | |
142 | .c_phase = 0, | |
143 | .gain_u = 0x111, | |
144 | .gain_v = 0x181, | |
145 | .gain_y = 0x140, | |
146 | .black_level = 0x3B, | |
147 | .blank_level = 0x3B, | |
148 | .x_color = 0x7, | |
149 | .m_control = 0x2, | |
150 | .bstamp_wss_data = 0x3F, | |
151 | .s_carr = 0x2A098ACB, | |
152 | .line21 = 0, | |
153 | .ln_sel = 0x01290015, | |
154 | .l21__wc_ctl = 0x0000F603, | |
155 | .htrigger_vtrigger = 0, | |
156 | ||
157 | .savid__eavid = 0x06A70108, | |
158 | .flen__fal = 0x00180270, | |
159 | .lal__phase_reset = 0x00040135, | |
160 | .hs_int_start_stop_x = 0x00880358, | |
161 | .hs_ext_start_stop_x = 0x000F035F, | |
162 | .vs_int_start_x = 0x01A70000, | |
163 | .vs_int_stop_x__vs_int_start_y = 0x000001A7, | |
164 | .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, | |
165 | .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, | |
166 | .vs_ext_stop_y = 0x00000025, | |
167 | .avid_start_stop_x = 0x03530083, | |
168 | .avid_start_stop_y = 0x026C002E, | |
169 | .fid_int_start_x__fid_int_start_y = 0x0001008A, | |
170 | .fid_int_offset_y__fid_ext_start_x = 0x002E0138, | |
171 | .fid_ext_start_y__fid_ext_offset_y = 0x01380001, | |
172 | ||
173 | .tvdetgp_int_start_stop_x = 0x00140001, | |
174 | .tvdetgp_int_start_stop_y = 0x00010001, | |
175 | .gen_ctrl = 0x00FF0000, | |
176 | }; | |
177 | ||
178 | /* from TRM */ | |
179 | static const struct venc_config venc_config_ntsc_trm = { | |
180 | .f_control = 0, | |
181 | .vidout_ctrl = 1, | |
182 | .sync_ctrl = 0x8040, | |
183 | .llen = 0x359, | |
184 | .flens = 0x20C, | |
185 | .hfltr_ctrl = 0, | |
186 | .cc_carr_wss_carr = 0x043F2631, | |
187 | .c_phase = 0, | |
188 | .gain_u = 0x102, | |
189 | .gain_v = 0x16C, | |
190 | .gain_y = 0x12F, | |
191 | .black_level = 0x43, | |
192 | .blank_level = 0x38, | |
193 | .x_color = 0x7, | |
194 | .m_control = 0x1, | |
195 | .bstamp_wss_data = 0x38, | |
196 | .s_carr = 0x21F07C1F, | |
197 | .line21 = 0, | |
198 | .ln_sel = 0x01310011, | |
199 | .l21__wc_ctl = 0x0000F003, | |
200 | .htrigger_vtrigger = 0, | |
201 | ||
202 | .savid__eavid = 0x069300F4, | |
203 | .flen__fal = 0x0016020C, | |
204 | .lal__phase_reset = 0x00060107, | |
205 | .hs_int_start_stop_x = 0x008E0350, | |
206 | .hs_ext_start_stop_x = 0x000F0359, | |
207 | .vs_int_start_x = 0x01A00000, | |
208 | .vs_int_stop_x__vs_int_start_y = 0x020701A0, | |
209 | .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, | |
210 | .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, | |
211 | .vs_ext_stop_y = 0x00000006, | |
212 | .avid_start_stop_x = 0x03480078, | |
213 | .avid_start_stop_y = 0x02060024, | |
214 | .fid_int_start_x__fid_int_start_y = 0x0001008A, | |
215 | .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, | |
216 | .fid_ext_start_y__fid_ext_offset_y = 0x01060006, | |
217 | ||
218 | .tvdetgp_int_start_stop_x = 0x00140001, | |
219 | .tvdetgp_int_start_stop_y = 0x00010001, | |
220 | .gen_ctrl = 0x00F90000, | |
221 | }; | |
222 | ||
223 | static const struct venc_config venc_config_pal_bdghi = { | |
224 | .f_control = 0, | |
225 | .vidout_ctrl = 0, | |
226 | .sync_ctrl = 0, | |
227 | .hfltr_ctrl = 0, | |
228 | .x_color = 0, | |
229 | .line21 = 0, | |
230 | .ln_sel = 21, | |
231 | .htrigger_vtrigger = 0, | |
232 | .tvdetgp_int_start_stop_x = 0x00140001, | |
233 | .tvdetgp_int_start_stop_y = 0x00010001, | |
234 | .gen_ctrl = 0x00FB0000, | |
235 | ||
236 | .llen = 864-1, | |
237 | .flens = 625-1, | |
238 | .cc_carr_wss_carr = 0x2F7625ED, | |
239 | .c_phase = 0xDF, | |
240 | .gain_u = 0x111, | |
241 | .gain_v = 0x181, | |
242 | .gain_y = 0x140, | |
243 | .black_level = 0x3e, | |
244 | .blank_level = 0x3e, | |
245 | .m_control = 0<<2 | 1<<1, | |
246 | .bstamp_wss_data = 0x42, | |
247 | .s_carr = 0x2a098acb, | |
248 | .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, | |
249 | .savid__eavid = 0x06A70108, | |
250 | .flen__fal = 23<<16 | 624<<0, | |
251 | .lal__phase_reset = 2<<17 | 310<<0, | |
252 | .hs_int_start_stop_x = 0x00920358, | |
253 | .hs_ext_start_stop_x = 0x000F035F, | |
254 | .vs_int_start_x = 0x1a7<<16, | |
255 | .vs_int_stop_x__vs_int_start_y = 0x000601A7, | |
256 | .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, | |
257 | .vs_ext_stop_x__vs_ext_start_y = 0x27101af, | |
258 | .vs_ext_stop_y = 0x05, | |
259 | .avid_start_stop_x = 0x03530082, | |
260 | .avid_start_stop_y = 0x0270002E, | |
261 | .fid_int_start_x__fid_int_start_y = 0x0005008A, | |
262 | .fid_int_offset_y__fid_ext_start_x = 0x002E0138, | |
263 | .fid_ext_start_y__fid_ext_offset_y = 0x01380005, | |
264 | }; | |
265 | ||
da11bbbb | 266 | const struct videomode omap_dss_pal_vm = { |
81899060 | 267 | .hactive = 720, |
fb7f3c43 | 268 | .vactive = 574, |
d8d78941 | 269 | .pixelclock = 13500000, |
4dc2250d | 270 | .hsync_len = 64, |
0a30e150 | 271 | .hfront_porch = 12, |
a85f4a80 | 272 | .hback_porch = 68, |
d5bcf0aa | 273 | .vsync_len = 5, |
0996c68e | 274 | .vfront_porch = 5, |
458540c6 | 275 | .vback_porch = 41, |
23c8f88e | 276 | |
6b44cd27 | 277 | .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | |
f149e17a | 278 | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | |
d34afb73 PU |
279 | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
280 | DISPLAY_FLAGS_SYNC_NEGEDGE, | |
b2886273 | 281 | }; |
da11bbbb | 282 | EXPORT_SYMBOL(omap_dss_pal_vm); |
b2886273 | 283 | |
da11bbbb | 284 | const struct videomode omap_dss_ntsc_vm = { |
81899060 | 285 | .hactive = 720, |
fb7f3c43 | 286 | .vactive = 482, |
d8d78941 | 287 | .pixelclock = 13500000, |
4dc2250d | 288 | .hsync_len = 64, |
0a30e150 | 289 | .hfront_porch = 16, |
a85f4a80 | 290 | .hback_porch = 58, |
d5bcf0aa | 291 | .vsync_len = 6, |
0996c68e | 292 | .vfront_porch = 6, |
458540c6 | 293 | .vback_porch = 31, |
23c8f88e | 294 | |
6b44cd27 | 295 | .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW | |
f149e17a | 296 | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | |
d34afb73 PU |
297 | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
298 | DISPLAY_FLAGS_SYNC_NEGEDGE, | |
b2886273 | 299 | }; |
da11bbbb | 300 | EXPORT_SYMBOL(omap_dss_ntsc_vm); |
b2886273 TV |
301 | |
302 | static struct { | |
30ea50c9 | 303 | struct platform_device *pdev; |
b2886273 TV |
304 | void __iomem *base; |
305 | struct mutex venc_lock; | |
306 | u32 wss_data; | |
307 | struct regulator *vdda_dac_reg; | |
4fbafaf3 | 308 | |
4fbafaf3 | 309 | struct clk *tv_dac_clk; |
a5abf472 | 310 | |
da11bbbb | 311 | struct videomode vm; |
febe2905 | 312 | enum omap_dss_venc_type type; |
89e71956 | 313 | bool invert_polarity; |
81b87f51 | 314 | |
1f68d9c4 | 315 | struct omap_dss_device output; |
b2886273 TV |
316 | } venc; |
317 | ||
318 | static inline void venc_write_reg(int idx, u32 val) | |
319 | { | |
320 | __raw_writel(val, venc.base + idx); | |
321 | } | |
322 | ||
323 | static inline u32 venc_read_reg(int idx) | |
324 | { | |
325 | u32 l = __raw_readl(venc.base + idx); | |
326 | return l; | |
327 | } | |
328 | ||
329 | static void venc_write_config(const struct venc_config *config) | |
330 | { | |
331 | DSSDBG("write venc conf\n"); | |
332 | ||
333 | venc_write_reg(VENC_LLEN, config->llen); | |
334 | venc_write_reg(VENC_FLENS, config->flens); | |
335 | venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); | |
336 | venc_write_reg(VENC_C_PHASE, config->c_phase); | |
337 | venc_write_reg(VENC_GAIN_U, config->gain_u); | |
338 | venc_write_reg(VENC_GAIN_V, config->gain_v); | |
339 | venc_write_reg(VENC_GAIN_Y, config->gain_y); | |
340 | venc_write_reg(VENC_BLACK_LEVEL, config->black_level); | |
341 | venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); | |
342 | venc_write_reg(VENC_M_CONTROL, config->m_control); | |
343 | venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | | |
344 | venc.wss_data); | |
345 | venc_write_reg(VENC_S_CARR, config->s_carr); | |
346 | venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); | |
347 | venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); | |
348 | venc_write_reg(VENC_FLEN__FAL, config->flen__fal); | |
349 | venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); | |
350 | venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); | |
351 | venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); | |
352 | venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); | |
353 | venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, | |
354 | config->vs_int_stop_x__vs_int_start_y); | |
355 | venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, | |
356 | config->vs_int_stop_y__vs_ext_start_x); | |
357 | venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, | |
358 | config->vs_ext_stop_x__vs_ext_start_y); | |
359 | venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); | |
360 | venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); | |
361 | venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); | |
362 | venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, | |
363 | config->fid_int_start_x__fid_int_start_y); | |
364 | venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, | |
365 | config->fid_int_offset_y__fid_ext_start_x); | |
366 | venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, | |
367 | config->fid_ext_start_y__fid_ext_offset_y); | |
368 | ||
369 | venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); | |
370 | venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); | |
371 | venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); | |
372 | venc_write_reg(VENC_X_COLOR, config->x_color); | |
373 | venc_write_reg(VENC_LINE21, config->line21); | |
374 | venc_write_reg(VENC_LN_SEL, config->ln_sel); | |
375 | venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); | |
376 | venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, | |
377 | config->tvdetgp_int_start_stop_x); | |
378 | venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, | |
379 | config->tvdetgp_int_start_stop_y); | |
380 | venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); | |
381 | venc_write_reg(VENC_F_CONTROL, config->f_control); | |
382 | venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); | |
383 | } | |
384 | ||
385 | static void venc_reset(void) | |
386 | { | |
387 | int t = 1000; | |
388 | ||
389 | venc_write_reg(VENC_F_CONTROL, 1<<8); | |
390 | while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { | |
391 | if (--t == 0) { | |
392 | DSSERR("Failed to reset venc\n"); | |
393 | return; | |
394 | } | |
395 | } | |
396 | ||
c6f65e1a | 397 | #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET |
b2886273 | 398 | /* the magical sleep that makes things work */ |
c6f65e1a | 399 | /* XXX more info? What bug this circumvents? */ |
b2886273 | 400 | msleep(20); |
c6f65e1a | 401 | #endif |
b2886273 TV |
402 | } |
403 | ||
4fbafaf3 | 404 | static int venc_runtime_get(void) |
b2886273 | 405 | { |
4fbafaf3 TV |
406 | int r; |
407 | ||
408 | DSSDBG("venc_runtime_get\n"); | |
409 | ||
410 | r = pm_runtime_get_sync(&venc.pdev->dev); | |
411 | WARN_ON(r < 0); | |
412 | return r < 0 ? r : 0; | |
413 | } | |
414 | ||
415 | static void venc_runtime_put(void) | |
416 | { | |
417 | int r; | |
418 | ||
419 | DSSDBG("venc_runtime_put\n"); | |
420 | ||
0eaf9f52 | 421 | r = pm_runtime_put_sync(&venc.pdev->dev); |
5be3aebd | 422 | WARN_ON(r < 0 && r != -ENOSYS); |
b2886273 TV |
423 | } |
424 | ||
da11bbbb | 425 | static const struct venc_config *venc_timings_to_config(struct videomode *vm) |
b2886273 | 426 | { |
da11bbbb | 427 | if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0) |
b2886273 TV |
428 | return &venc_config_pal_trm; |
429 | ||
da11bbbb | 430 | if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0) |
b2886273 TV |
431 | return &venc_config_ntsc_trm; |
432 | ||
433 | BUG(); | |
c6eee968 | 434 | return NULL; |
b2886273 TV |
435 | } |
436 | ||
33ca237f | 437 | static int venc_power_on(struct omap_dss_device *dssdev) |
37ac60e4 | 438 | { |
532a2cba | 439 | enum omap_channel channel = dssdev->dispc_channel; |
37ac60e4 | 440 | u32 l; |
33ca237f | 441 | int r; |
37ac60e4 | 442 | |
156fd99e AT |
443 | r = venc_runtime_get(); |
444 | if (r) | |
445 | goto err0; | |
446 | ||
37ac60e4 | 447 | venc_reset(); |
da11bbbb | 448 | venc_write_config(venc_timings_to_config(&venc.vm)); |
37ac60e4 | 449 | |
febe2905 | 450 | dss_set_venc_output(venc.type); |
37ac60e4 TV |
451 | dss_set_dac_pwrdn_bgz(1); |
452 | ||
453 | l = 0; | |
454 | ||
febe2905 | 455 | if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) |
37ac60e4 TV |
456 | l |= 1 << 1; |
457 | else /* S-Video */ | |
458 | l |= (1 << 0) | (1 << 2); | |
459 | ||
89e71956 | 460 | if (venc.invert_polarity == false) |
37ac60e4 TV |
461 | l |= 1 << 3; |
462 | ||
463 | venc_write_reg(VENC_OUTPUT_CONTROL, l); | |
464 | ||
da11bbbb | 465 | dss_mgr_set_timings(channel, &venc.vm); |
37ac60e4 | 466 | |
ec874107 MB |
467 | r = regulator_enable(venc.vdda_dac_reg); |
468 | if (r) | |
156fd99e | 469 | goto err1; |
37ac60e4 | 470 | |
532a2cba | 471 | r = dss_mgr_enable(channel); |
33ca237f | 472 | if (r) |
156fd99e | 473 | goto err2; |
33ca237f TV |
474 | |
475 | return 0; | |
476 | ||
156fd99e AT |
477 | err2: |
478 | regulator_disable(venc.vdda_dac_reg); | |
479 | err1: | |
33ca237f TV |
480 | venc_write_reg(VENC_OUTPUT_CONTROL, 0); |
481 | dss_set_dac_pwrdn_bgz(0); | |
482 | ||
156fd99e AT |
483 | venc_runtime_put(); |
484 | err0: | |
33ca237f | 485 | return r; |
37ac60e4 TV |
486 | } |
487 | ||
488 | static void venc_power_off(struct omap_dss_device *dssdev) | |
489 | { | |
532a2cba | 490 | enum omap_channel channel = dssdev->dispc_channel; |
8f1f736c | 491 | |
37ac60e4 TV |
492 | venc_write_reg(VENC_OUTPUT_CONTROL, 0); |
493 | dss_set_dac_pwrdn_bgz(0); | |
494 | ||
532a2cba | 495 | dss_mgr_disable(channel); |
37ac60e4 | 496 | |
37ac60e4 | 497 | regulator_disable(venc.vdda_dac_reg); |
156fd99e AT |
498 | |
499 | venc_runtime_put(); | |
37ac60e4 TV |
500 | } |
501 | ||
09d2e7cd | 502 | static int venc_display_enable(struct omap_dss_device *dssdev) |
0aca3c63 | 503 | { |
1f68d9c4 | 504 | struct omap_dss_device *out = &venc.output; |
156fd99e | 505 | int r; |
0aca3c63 | 506 | |
156fd99e | 507 | DSSDBG("venc_display_enable\n"); |
0aca3c63 GI |
508 | |
509 | mutex_lock(&venc.venc_lock); | |
510 | ||
f1504ad0 | 511 | if (!out->dispc_channel_connected) { |
8f1f736c | 512 | DSSERR("Failed to enable display: no output/manager\n"); |
156fd99e AT |
513 | r = -ENODEV; |
514 | goto err0; | |
0aca3c63 GI |
515 | } |
516 | ||
33ca237f TV |
517 | r = venc_power_on(dssdev); |
518 | if (r) | |
d3923933 | 519 | goto err0; |
37ac60e4 TV |
520 | |
521 | venc.wss_data = 0; | |
522 | ||
14572c63 | 523 | mutex_unlock(&venc.venc_lock); |
156fd99e | 524 | |
14572c63 | 525 | return 0; |
14572c63 | 526 | err0: |
37ac60e4 | 527 | mutex_unlock(&venc.venc_lock); |
b2886273 TV |
528 | return r; |
529 | } | |
530 | ||
09d2e7cd | 531 | static void venc_display_disable(struct omap_dss_device *dssdev) |
b2886273 | 532 | { |
156fd99e | 533 | DSSDBG("venc_display_disable\n"); |
b2886273 | 534 | |
37ac60e4 TV |
535 | mutex_lock(&venc.venc_lock); |
536 | ||
37ac60e4 TV |
537 | venc_power_off(dssdev); |
538 | ||
156fd99e | 539 | mutex_unlock(&venc.venc_lock); |
b2886273 TV |
540 | } |
541 | ||
09d2e7cd | 542 | static void venc_set_timings(struct omap_dss_device *dssdev, |
da11bbbb | 543 | struct videomode *vm) |
69b2048f TV |
544 | { |
545 | DSSDBG("venc_set_timings\n"); | |
546 | ||
156fd99e AT |
547 | mutex_lock(&venc.venc_lock); |
548 | ||
69b2048f | 549 | /* Reset WSS data when the TV standard changes. */ |
da11bbbb | 550 | if (memcmp(&venc.vm, vm, sizeof(*vm))) |
69b2048f TV |
551 | venc.wss_data = 0; |
552 | ||
da11bbbb | 553 | venc.vm = *vm; |
156fd99e | 554 | |
5391e87d TV |
555 | dispc_set_tv_pclk(13500000); |
556 | ||
156fd99e | 557 | mutex_unlock(&venc.venc_lock); |
69b2048f TV |
558 | } |
559 | ||
09d2e7cd | 560 | static int venc_check_timings(struct omap_dss_device *dssdev, |
da11bbbb | 561 | struct videomode *vm) |
69b2048f TV |
562 | { |
563 | DSSDBG("venc_check_timings\n"); | |
564 | ||
da11bbbb | 565 | if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0) |
69b2048f TV |
566 | return 0; |
567 | ||
da11bbbb | 568 | if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0) |
69b2048f TV |
569 | return 0; |
570 | ||
571 | return -EINVAL; | |
572 | } | |
573 | ||
fb8efa49 | 574 | static void venc_get_timings(struct omap_dss_device *dssdev, |
da11bbbb | 575 | struct videomode *vm) |
fb8efa49 TV |
576 | { |
577 | mutex_lock(&venc.venc_lock); | |
578 | ||
da11bbbb | 579 | *vm = venc.vm; |
fb8efa49 TV |
580 | |
581 | mutex_unlock(&venc.venc_lock); | |
582 | } | |
583 | ||
09d2e7cd | 584 | static u32 venc_get_wss(struct omap_dss_device *dssdev) |
36511312 TV |
585 | { |
586 | /* Invert due to VENC_L21_WC_CTL:INV=1 */ | |
587 | return (venc.wss_data >> 8) ^ 0xfffff; | |
588 | } | |
589 | ||
09d2e7cd | 590 | static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) |
36511312 TV |
591 | { |
592 | const struct venc_config *config; | |
4fbafaf3 | 593 | int r; |
36511312 TV |
594 | |
595 | DSSDBG("venc_set_wss\n"); | |
596 | ||
597 | mutex_lock(&venc.venc_lock); | |
598 | ||
da11bbbb | 599 | config = venc_timings_to_config(&venc.vm); |
36511312 TV |
600 | |
601 | /* Invert due to VENC_L21_WC_CTL:INV=1 */ | |
602 | venc.wss_data = (wss ^ 0xfffff) << 8; | |
603 | ||
4fbafaf3 TV |
604 | r = venc_runtime_get(); |
605 | if (r) | |
606 | goto err; | |
36511312 TV |
607 | |
608 | venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | | |
609 | venc.wss_data); | |
610 | ||
4fbafaf3 | 611 | venc_runtime_put(); |
36511312 | 612 | |
4fbafaf3 | 613 | err: |
36511312 TV |
614 | mutex_unlock(&venc.venc_lock); |
615 | ||
4fbafaf3 | 616 | return r; |
36511312 TV |
617 | } |
618 | ||
7e436bb2 | 619 | static int venc_init_regulator(void) |
b2886273 | 620 | { |
7e436bb2 | 621 | struct regulator *vdda_dac; |
b2886273 | 622 | |
7e436bb2 TV |
623 | if (venc.vdda_dac_reg != NULL) |
624 | return 0; | |
5f42f2ce | 625 | |
1dff212c | 626 | vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); |
7e436bb2 | 627 | if (IS_ERR(vdda_dac)) { |
40359a9b TV |
628 | if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) |
629 | DSSERR("can't get VDDA_DAC regulator\n"); | |
7e436bb2 | 630 | return PTR_ERR(vdda_dac); |
5f42f2ce TV |
631 | } |
632 | ||
7e436bb2 TV |
633 | venc.vdda_dac_reg = vdda_dac; |
634 | ||
b2886273 TV |
635 | return 0; |
636 | } | |
637 | ||
e40402cf | 638 | static void venc_dump_regs(struct seq_file *s) |
b2886273 TV |
639 | { |
640 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) | |
641 | ||
4fbafaf3 TV |
642 | if (venc_runtime_get()) |
643 | return; | |
b2886273 TV |
644 | |
645 | DUMPREG(VENC_F_CONTROL); | |
646 | DUMPREG(VENC_VIDOUT_CTRL); | |
647 | DUMPREG(VENC_SYNC_CTRL); | |
648 | DUMPREG(VENC_LLEN); | |
649 | DUMPREG(VENC_FLENS); | |
650 | DUMPREG(VENC_HFLTR_CTRL); | |
651 | DUMPREG(VENC_CC_CARR_WSS_CARR); | |
652 | DUMPREG(VENC_C_PHASE); | |
653 | DUMPREG(VENC_GAIN_U); | |
654 | DUMPREG(VENC_GAIN_V); | |
655 | DUMPREG(VENC_GAIN_Y); | |
656 | DUMPREG(VENC_BLACK_LEVEL); | |
657 | DUMPREG(VENC_BLANK_LEVEL); | |
658 | DUMPREG(VENC_X_COLOR); | |
659 | DUMPREG(VENC_M_CONTROL); | |
660 | DUMPREG(VENC_BSTAMP_WSS_DATA); | |
661 | DUMPREG(VENC_S_CARR); | |
662 | DUMPREG(VENC_LINE21); | |
663 | DUMPREG(VENC_LN_SEL); | |
664 | DUMPREG(VENC_L21__WC_CTL); | |
665 | DUMPREG(VENC_HTRIGGER_VTRIGGER); | |
666 | DUMPREG(VENC_SAVID__EAVID); | |
667 | DUMPREG(VENC_FLEN__FAL); | |
668 | DUMPREG(VENC_LAL__PHASE_RESET); | |
669 | DUMPREG(VENC_HS_INT_START_STOP_X); | |
670 | DUMPREG(VENC_HS_EXT_START_STOP_X); | |
671 | DUMPREG(VENC_VS_INT_START_X); | |
672 | DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); | |
673 | DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); | |
674 | DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); | |
675 | DUMPREG(VENC_VS_EXT_STOP_Y); | |
676 | DUMPREG(VENC_AVID_START_STOP_X); | |
677 | DUMPREG(VENC_AVID_START_STOP_Y); | |
678 | DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); | |
679 | DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); | |
680 | DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); | |
681 | DUMPREG(VENC_TVDETGP_INT_START_STOP_X); | |
682 | DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); | |
683 | DUMPREG(VENC_GEN_CTRL); | |
684 | DUMPREG(VENC_OUTPUT_CONTROL); | |
685 | DUMPREG(VENC_OUTPUT_TEST); | |
686 | ||
4fbafaf3 | 687 | venc_runtime_put(); |
b2886273 TV |
688 | |
689 | #undef DUMPREG | |
690 | } | |
30ea50c9 | 691 | |
4fbafaf3 TV |
692 | static int venc_get_clocks(struct platform_device *pdev) |
693 | { | |
694 | struct clk *clk; | |
695 | ||
4fbafaf3 | 696 | if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) { |
b2c9c8ee | 697 | clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); |
4fbafaf3 TV |
698 | if (IS_ERR(clk)) { |
699 | DSSERR("can't get tv_dac_clk\n"); | |
4fbafaf3 TV |
700 | return PTR_ERR(clk); |
701 | } | |
702 | } else { | |
703 | clk = NULL; | |
704 | } | |
705 | ||
706 | venc.tv_dac_clk = clk; | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
fb8efa49 TV |
711 | static int venc_connect(struct omap_dss_device *dssdev, |
712 | struct omap_dss_device *dst) | |
713 | { | |
532a2cba | 714 | enum omap_channel channel = dssdev->dispc_channel; |
fb8efa49 TV |
715 | int r; |
716 | ||
717 | r = venc_init_regulator(); | |
718 | if (r) | |
719 | return r; | |
720 | ||
532a2cba | 721 | r = dss_mgr_connect(channel, dssdev); |
fb8efa49 TV |
722 | if (r) |
723 | return r; | |
724 | ||
725 | r = omapdss_output_set_device(dssdev, dst); | |
726 | if (r) { | |
727 | DSSERR("failed to connect output to new device: %s\n", | |
728 | dst->name); | |
532a2cba | 729 | dss_mgr_disconnect(channel, dssdev); |
fb8efa49 TV |
730 | return r; |
731 | } | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
736 | static void venc_disconnect(struct omap_dss_device *dssdev, | |
737 | struct omap_dss_device *dst) | |
738 | { | |
532a2cba TV |
739 | enum omap_channel channel = dssdev->dispc_channel; |
740 | ||
9560dc10 | 741 | WARN_ON(dst != dssdev->dst); |
fb8efa49 | 742 | |
9560dc10 | 743 | if (dst != dssdev->dst) |
fb8efa49 TV |
744 | return; |
745 | ||
746 | omapdss_output_unset_device(dssdev); | |
747 | ||
532a2cba | 748 | dss_mgr_disconnect(channel, dssdev); |
fb8efa49 TV |
749 | } |
750 | ||
751 | static const struct omapdss_atv_ops venc_ops = { | |
752 | .connect = venc_connect, | |
753 | .disconnect = venc_disconnect, | |
754 | ||
09d2e7cd TV |
755 | .enable = venc_display_enable, |
756 | .disable = venc_display_disable, | |
fb8efa49 | 757 | |
09d2e7cd TV |
758 | .check_timings = venc_check_timings, |
759 | .set_timings = venc_set_timings, | |
fb8efa49 TV |
760 | .get_timings = venc_get_timings, |
761 | ||
09d2e7cd TV |
762 | .set_wss = venc_set_wss, |
763 | .get_wss = venc_get_wss, | |
fb8efa49 TV |
764 | }; |
765 | ||
b5a99c26 | 766 | static void venc_init_output(struct platform_device *pdev) |
81b87f51 | 767 | { |
1f68d9c4 | 768 | struct omap_dss_device *out = &venc.output; |
81b87f51 | 769 | |
1f68d9c4 | 770 | out->dev = &pdev->dev; |
81b87f51 | 771 | out->id = OMAP_DSS_OUTPUT_VENC; |
1f68d9c4 | 772 | out->output_type = OMAP_DISPLAY_TYPE_VENC; |
7286a08f | 773 | out->name = "venc.0"; |
2eea5ae6 | 774 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; |
fb8efa49 | 775 | out->ops.atv = &venc_ops; |
b7328e14 | 776 | out->owner = THIS_MODULE; |
81b87f51 | 777 | |
5d47dbc8 | 778 | omapdss_register_output(out); |
81b87f51 AT |
779 | } |
780 | ||
ede92695 | 781 | static void venc_uninit_output(struct platform_device *pdev) |
81b87f51 | 782 | { |
1f68d9c4 | 783 | struct omap_dss_device *out = &venc.output; |
81b87f51 | 784 | |
5d47dbc8 | 785 | omapdss_unregister_output(out); |
81b87f51 AT |
786 | } |
787 | ||
a2207021 TV |
788 | static int venc_probe_of(struct platform_device *pdev) |
789 | { | |
790 | struct device_node *node = pdev->dev.of_node; | |
791 | struct device_node *ep; | |
792 | u32 channels; | |
793 | int r; | |
794 | ||
09bffa6e | 795 | ep = of_graph_get_endpoint_by_regs(node, 0, 0); |
a2207021 TV |
796 | if (!ep) |
797 | return 0; | |
798 | ||
799 | venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); | |
800 | ||
801 | r = of_property_read_u32(ep, "ti,channels", &channels); | |
802 | if (r) { | |
803 | dev_err(&pdev->dev, | |
804 | "failed to read property 'ti,channels': %d\n", r); | |
805 | goto err; | |
806 | } | |
807 | ||
808 | switch (channels) { | |
809 | case 1: | |
810 | venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE; | |
811 | break; | |
812 | case 2: | |
813 | venc.type = OMAP_DSS_VENC_TYPE_SVIDEO; | |
814 | break; | |
815 | default: | |
816 | dev_err(&pdev->dev, "bad channel propert '%d'\n", channels); | |
817 | r = -EINVAL; | |
818 | goto err; | |
819 | } | |
820 | ||
821 | of_node_put(ep); | |
822 | ||
823 | return 0; | |
824 | err: | |
825 | of_node_put(ep); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
30ea50c9 | 830 | /* VENC HW IP initialisation */ |
736e60dd | 831 | static int venc_bind(struct device *dev, struct device *master, void *data) |
30ea50c9 | 832 | { |
736e60dd | 833 | struct platform_device *pdev = to_platform_device(dev); |
30ea50c9 | 834 | u8 rev_id; |
ea9da36a | 835 | struct resource *venc_mem; |
38f3daf6 | 836 | int r; |
ea9da36a | 837 | |
30ea50c9 SG |
838 | venc.pdev = pdev; |
839 | ||
840 | mutex_init(&venc.venc_lock); | |
841 | ||
842 | venc.wss_data = 0; | |
843 | ||
ea9da36a | 844 | venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); |
b22622f0 LP |
845 | venc.base = devm_ioremap_resource(&pdev->dev, venc_mem); |
846 | if (IS_ERR(venc.base)) | |
847 | return PTR_ERR(venc.base); | |
30ea50c9 | 848 | |
4fbafaf3 TV |
849 | r = venc_get_clocks(pdev); |
850 | if (r) | |
cd3b3449 | 851 | return r; |
4fbafaf3 TV |
852 | |
853 | pm_runtime_enable(&pdev->dev); | |
854 | ||
855 | r = venc_runtime_get(); | |
856 | if (r) | |
cd3b3449 | 857 | goto err_runtime_get; |
30ea50c9 SG |
858 | |
859 | rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); | |
a06b62f8 | 860 | dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); |
30ea50c9 | 861 | |
4fbafaf3 | 862 | venc_runtime_put(); |
30ea50c9 | 863 | |
1dff212c LP |
864 | r = venc_probe_of(pdev); |
865 | if (r) { | |
866 | DSSERR("Invalid DT data\n"); | |
867 | goto err_probe_of; | |
a2207021 TV |
868 | } |
869 | ||
e40402cf TV |
870 | dss_debugfs_create_file("venc", venc_dump_regs); |
871 | ||
81b87f51 AT |
872 | venc_init_output(pdev); |
873 | ||
cd3b3449 | 874 | return 0; |
4fbafaf3 | 875 | |
a2207021 | 876 | err_probe_of: |
cd3b3449 | 877 | err_runtime_get: |
4fbafaf3 | 878 | pm_runtime_disable(&pdev->dev); |
4fbafaf3 | 879 | return r; |
30ea50c9 SG |
880 | } |
881 | ||
736e60dd | 882 | static void venc_unbind(struct device *dev, struct device *master, void *data) |
30ea50c9 | 883 | { |
736e60dd TV |
884 | struct platform_device *pdev = to_platform_device(dev); |
885 | ||
81b87f51 AT |
886 | venc_uninit_output(pdev); |
887 | ||
4fbafaf3 | 888 | pm_runtime_disable(&pdev->dev); |
736e60dd | 889 | } |
4fbafaf3 | 890 | |
736e60dd TV |
891 | static const struct component_ops venc_component_ops = { |
892 | .bind = venc_bind, | |
893 | .unbind = venc_unbind, | |
894 | }; | |
895 | ||
896 | static int venc_probe(struct platform_device *pdev) | |
897 | { | |
898 | return component_add(&pdev->dev, &venc_component_ops); | |
899 | } | |
900 | ||
901 | static int venc_remove(struct platform_device *pdev) | |
902 | { | |
903 | component_del(&pdev->dev, &venc_component_ops); | |
30ea50c9 SG |
904 | return 0; |
905 | } | |
906 | ||
4fbafaf3 TV |
907 | static int venc_runtime_suspend(struct device *dev) |
908 | { | |
909 | if (venc.tv_dac_clk) | |
f11766d1 | 910 | clk_disable_unprepare(venc.tv_dac_clk); |
4fbafaf3 TV |
911 | |
912 | dispc_runtime_put(); | |
4fbafaf3 TV |
913 | |
914 | return 0; | |
915 | } | |
916 | ||
917 | static int venc_runtime_resume(struct device *dev) | |
918 | { | |
919 | int r; | |
920 | ||
4fbafaf3 TV |
921 | r = dispc_runtime_get(); |
922 | if (r < 0) | |
852f0838 | 923 | return r; |
4fbafaf3 | 924 | |
4fbafaf3 | 925 | if (venc.tv_dac_clk) |
f11766d1 | 926 | clk_prepare_enable(venc.tv_dac_clk); |
4fbafaf3 TV |
927 | |
928 | return 0; | |
4fbafaf3 TV |
929 | } |
930 | ||
931 | static const struct dev_pm_ops venc_pm_ops = { | |
932 | .runtime_suspend = venc_runtime_suspend, | |
933 | .runtime_resume = venc_runtime_resume, | |
934 | }; | |
935 | ||
a2207021 TV |
936 | static const struct of_device_id venc_of_match[] = { |
937 | { .compatible = "ti,omap2-venc", }, | |
938 | { .compatible = "ti,omap3-venc", }, | |
939 | { .compatible = "ti,omap4-venc", }, | |
940 | {}, | |
941 | }; | |
942 | ||
30ea50c9 | 943 | static struct platform_driver omap_venchw_driver = { |
736e60dd TV |
944 | .probe = venc_probe, |
945 | .remove = venc_remove, | |
30ea50c9 SG |
946 | .driver = { |
947 | .name = "omapdss_venc", | |
4fbafaf3 | 948 | .pm = &venc_pm_ops, |
a2207021 | 949 | .of_match_table = venc_of_match, |
422ccbd5 | 950 | .suppress_bind_attrs = true, |
30ea50c9 SG |
951 | }, |
952 | }; | |
953 | ||
6e7e8f06 | 954 | int __init venc_init_platform_driver(void) |
30ea50c9 | 955 | { |
b5a99c26 | 956 | return platform_driver_register(&omap_venchw_driver); |
30ea50c9 SG |
957 | } |
958 | ||
ede92695 | 959 | void venc_uninit_platform_driver(void) |
30ea50c9 | 960 | { |
04c742c3 | 961 | platform_driver_unregister(&omap_venchw_driver); |
30ea50c9 | 962 | } |