[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / omap_crtc.c

/*
 * drivers/gpu/drm/omapdrm/omap_crtc.c
 *
 * Copyright (C) 2011 Texas Instruments
 * Author: Rob Clark <rob@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_mode.h>
#include <drm/drm_plane_helper.h>

#include "omap_drv.h"

#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)

struct omap_crtc {
	struct drm_crtc base;

	const char *name;
	enum omap_channel channel;

	/*
	 * Temporary: eventually this will go away, but it is needed
	 * for now to keep the output's happy.  (They only need
	 * mgr->id.)  Eventually this will be replaced w/ something
	 * more common-panel-framework-y
	 */
	struct omap_overlay_manager *mgr;

	struct omap_video_timings timings;

	struct omap_drm_irq vblank_irq;
	struct omap_drm_irq error_irq;

	bool ignore_digit_sync_lost;

	bool pending;
	wait_queue_head_t pending_wait;
};

/* -----------------------------------------------------------------------------
 * Helper Functions
 */

uint32_t pipe2vbl(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	return dispc_mgr_get_vsync_irq(omap_crtc->channel);
}

struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	return &omap_crtc->timings;
}

enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	return omap_crtc->channel;
}

int omap_crtc_wait_pending(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	return wait_event_timeout(omap_crtc->pending_wait,
				  !omap_crtc->pending,
				  msecs_to_jiffies(50));
}

/* -----------------------------------------------------------------------------
 * DSS Manager Functions
 */

/*
 * Manager-ops, callbacks from output when they need to configure
 * the upstream part of the video pipe.
 *
 * Most of these we can ignore until we add support for command-mode
 * panels.. for video-mode the crtc-helpers already do an adequate
 * job of sequencing the setup of the video pipe in the proper order
 */

/* ovl-mgr-id -> crtc */
static struct omap_crtc *omap_crtcs[8];

/* we can probably ignore these until we support command-mode panels: */
static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
		struct omap_dss_device *dst)
{
	if (mgr->output)
		return -EINVAL;

	if ((mgr->supported_outputs & dst->id) == 0)
		return -EINVAL;

	dst->manager = mgr;
	mgr->output = dst;

	return 0;
}

static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
		struct omap_dss_device *dst)
{
	mgr->output->manager = NULL;
	mgr->output = NULL;
}

static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
{
}

/* Called only from the encoder enable/disable and suspend/resume handlers. */
static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
{
	struct drm_device *dev = crtc->dev;
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	enum omap_channel channel = omap_crtc->channel;
	struct omap_irq_wait *wait;
	u32 framedone_irq, vsync_irq;
	int ret;

	if (dispc_mgr_is_enabled(channel) == enable)
		return;

	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
		/*
		 * Digit output produces some sync lost interrupts during the
		 * first frame when enabling, so we need to ignore those.
		 */
		omap_crtc->ignore_digit_sync_lost = true;
	}

	framedone_irq = dispc_mgr_get_framedone_irq(channel);
	vsync_irq = dispc_mgr_get_vsync_irq(channel);

	if (enable) {
		wait = omap_irq_wait_init(dev, vsync_irq, 1);
	} else {
		/*
		 * When we disable the digit output, we need to wait for
		 * FRAMEDONE to know that DISPC has finished with the output.
		 *
		 * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
		 * that case we need to use vsync interrupt, and wait for both
		 * even and odd frames.
		 */

		if (framedone_irq)
			wait = omap_irq_wait_init(dev, framedone_irq, 1);
		else
			wait = omap_irq_wait_init(dev, vsync_irq, 2);
	}

	dispc_mgr_enable(channel, enable);

	ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
	if (ret) {
		dev_err(dev->dev, "%s: timeout waiting for %s\n",
				omap_crtc->name, enable ? "enable" : "disable");
	}

	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
		omap_crtc->ignore_digit_sync_lost = false;
		/* make sure the irq handler sees the value above */
		mb();
	}
}


static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
{
	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
	struct omap_overlay_manager_info info;

	memset(&info, 0, sizeof(info));
	info.default_color = 0x00000000;
	info.trans_key = 0x00000000;
	info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
	info.trans_enabled = false;

	dispc_mgr_setup(omap_crtc->channel, &info);
	dispc_mgr_set_timings(omap_crtc->channel,
			&omap_crtc->timings);
	omap_crtc_set_enabled(&omap_crtc->base, true);

	return 0;
}

static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
{
	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];

	omap_crtc_set_enabled(&omap_crtc->base, false);
}

static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
		const struct omap_video_timings *timings)
{
	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
	DBG("%s", omap_crtc->name);
	omap_crtc->timings = *timings;
}

static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
		const struct dss_lcd_mgr_config *config)
{
	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
	DBG("%s", omap_crtc->name);
	dispc_mgr_set_lcd_config(omap_crtc->channel, config);
}

static int omap_crtc_dss_register_framedone(
		struct omap_overlay_manager *mgr,
		void (*handler)(void *), void *data)
{
	return 0;
}

static void omap_crtc_dss_unregister_framedone(
		struct omap_overlay_manager *mgr,
		void (*handler)(void *), void *data)
{
}

static const struct dss_mgr_ops mgr_ops = {
	.connect = omap_crtc_dss_connect,
	.disconnect = omap_crtc_dss_disconnect,
	.start_update = omap_crtc_dss_start_update,
	.enable = omap_crtc_dss_enable,
	.disable = omap_crtc_dss_disable,
	.set_timings = omap_crtc_dss_set_timings,
	.set_lcd_config = omap_crtc_dss_set_lcd_config,
	.register_framedone_handler = omap_crtc_dss_register_framedone,
	.unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
};

/* -----------------------------------------------------------------------------
 * Setup, Flush and Page Flip
 */

static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
{
	struct drm_pending_vblank_event *event;
	struct drm_device *dev = crtc->dev;
	unsigned long flags;

	event = crtc->state->event;

	if (!event)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	drm_crtc_send_vblank_event(crtc, event);
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
{
	struct omap_crtc *omap_crtc =
			container_of(irq, struct omap_crtc, error_irq);

	if (omap_crtc->ignore_digit_sync_lost) {
		irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
		if (!irqstatus)
			return;
	}

	DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
}

static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
{
	struct omap_crtc *omap_crtc =
			container_of(irq, struct omap_crtc, vblank_irq);
	struct drm_device *dev = omap_crtc->base.dev;

	if (dispc_mgr_go_busy(omap_crtc->channel))
		return;

	DBG("%s: apply done", omap_crtc->name);

	__omap_irq_unregister(dev, &omap_crtc->vblank_irq);

	rmb();
	WARN_ON(!omap_crtc->pending);
	omap_crtc->pending = false;
	wmb();

	/* wake up userspace */
	omap_crtc_complete_page_flip(&omap_crtc->base);

	/* wake up omap_atomic_complete */
	wake_up(&omap_crtc->pending_wait);
}

/* -----------------------------------------------------------------------------
 * CRTC Functions
 */

static void omap_crtc_destroy(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	DBG("%s", omap_crtc->name);

	WARN_ON(omap_crtc->vblank_irq.registered);
	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);

	drm_crtc_cleanup(crtc);

	kfree(omap_crtc);
}

static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
		const struct drm_display_mode *mode,
		struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void omap_crtc_enable(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	DBG("%s", omap_crtc->name);

	rmb();
	WARN_ON(omap_crtc->pending);
	omap_crtc->pending = true;
	wmb();

	omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);

	drm_crtc_vblank_on(crtc);
}

static void omap_crtc_disable(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	DBG("%s", omap_crtc->name);

	drm_crtc_vblank_off(crtc);
}

static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	struct drm_display_mode *mode = &crtc->state->adjusted_mode;

	DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
	    omap_crtc->name, mode->base.id, mode->name,
	    mode->vrefresh, mode->clock,
	    mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
	    mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
	    mode->type, mode->flags);

	copy_timings_drm_to_omap(&omap_crtc->timings, mode);
}

static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
                                  struct drm_crtc_state *old_crtc_state)
{
}

static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
                                  struct drm_crtc_state *old_crtc_state)
{
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);

	WARN_ON(omap_crtc->vblank_irq.registered);

	if (dispc_mgr_is_enabled(omap_crtc->channel)) {

		DBG("%s: GO", omap_crtc->name);

		rmb();
		WARN_ON(omap_crtc->pending);
		omap_crtc->pending = true;
		wmb();

		dispc_mgr_go(omap_crtc->channel);
		omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
	}
}

static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
					 struct drm_crtc_state *state,
					 struct drm_property *property,
					 uint64_t val)
{
	struct drm_plane_state *plane_state;
	struct drm_plane *plane = crtc->primary;

	/*
	 * Delegate property set to the primary plane. Get the plane state and
	 * set the property directly.
	 */

	plane_state = drm_atomic_get_plane_state(state->state, plane);
	if (!plane_state)
		return -EINVAL;

	return drm_atomic_plane_set_property(plane, plane_state, property, val);
}

static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
					 const struct drm_crtc_state *state,
					 struct drm_property *property,
					 uint64_t *val)
{
	/*
	 * Delegate property get to the primary plane. The
	 * drm_atomic_plane_get_property() function isn't exported, but can be
	 * called through drm_object_property_get_value() as that will call
	 * drm_atomic_get_property() for atomic drivers.
	 */
	return drm_object_property_get_value(&crtc->primary->base, property,
					     val);
}

static const struct drm_crtc_funcs omap_crtc_funcs = {
	.reset = drm_atomic_helper_crtc_reset,
	.set_config = drm_atomic_helper_set_config,
	.destroy = omap_crtc_destroy,
	.page_flip = drm_atomic_helper_page_flip,
	.set_property = drm_atomic_helper_crtc_set_property,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	.atomic_set_property = omap_crtc_atomic_set_property,
	.atomic_get_property = omap_crtc_atomic_get_property,
};

static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
	.mode_fixup = omap_crtc_mode_fixup,
	.mode_set_nofb = omap_crtc_mode_set_nofb,
	.disable = omap_crtc_disable,
	.enable = omap_crtc_enable,
	.atomic_begin = omap_crtc_atomic_begin,
	.atomic_flush = omap_crtc_atomic_flush,
};

/* -----------------------------------------------------------------------------
 * Init and Cleanup
 */

static const char *channel_names[] = {
	[OMAP_DSS_CHANNEL_LCD] = "lcd",
	[OMAP_DSS_CHANNEL_DIGIT] = "tv",
	[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
	[OMAP_DSS_CHANNEL_LCD3] = "lcd3",
};

void omap_crtc_pre_init(void)
{
	dss_install_mgr_ops(&mgr_ops);
}

void omap_crtc_pre_uninit(void)
{
	dss_uninstall_mgr_ops();
}

/* initialize crtc */
struct drm_crtc *omap_crtc_init(struct drm_device *dev,
		struct drm_plane *plane, enum omap_channel channel, int id)
{
	struct drm_crtc *crtc = NULL;
	struct omap_crtc *omap_crtc;
	int ret;

	DBG("%s", channel_names[channel]);

	omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
	if (!omap_crtc)
		return NULL;

	crtc = &omap_crtc->base;

	init_waitqueue_head(&omap_crtc->pending_wait);

	omap_crtc->channel = channel;
	omap_crtc->name = channel_names[channel];

	omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
	omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;

	omap_crtc->error_irq.irqmask =
			dispc_mgr_get_sync_lost_irq(channel);
	omap_crtc->error_irq.irq = omap_crtc_error_irq;
	omap_irq_register(dev, &omap_crtc->error_irq);

	/* temporary: */
	omap_crtc->mgr = omap_dss_get_overlay_manager(channel);

	ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
					&omap_crtc_funcs, NULL);
	if (ret < 0) {
		kfree(omap_crtc);
		return NULL;
	}

	drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);

	omap_plane_install_properties(crtc->primary, &crtc->base);

	omap_crtcs[channel] = omap_crtc;

	return crtc;
}
Commit	Line	Data
cd5351f4	1	/*
8bb0daff	2	* drivers/gpu/drm/omapdrm/omap_crtc.c
cd5351f4 RC	3	*
	4	* Copyright (C) 2011 Texas Instruments
	5	* Author: Rob Clark <rob@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
69a12263 LP	20	#include <drm/drm_atomic.h>
69a12263 LP	21	#include <drm/drm_atomic_helper.h>
2d278f54 LP	22	#include <drm/drm_crtc.h>
2d278f54 LP	23	#include <drm/drm_crtc_helper.h>
b9ed9f0e	24	#include <drm/drm_mode.h>
3cb9ae4f	25	#include <drm/drm_plane_helper.h>
2d278f54 LP	26
2d278f54 LP	27	#include "omap_drv.h"
cd5351f4 RC	28
	29	#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
	30
	31	struct omap_crtc {
	32	struct drm_crtc base;
f5f9454c	33
bb5c2d9a	34	const char *name;
f5f9454c	35	enum omap_channel channel;
f5f9454c RC	36
	37	/*
	38	* Temporary: eventually this will go away, but it is needed
	39	* for now to keep the output's happy. (They only need
	40	* mgr->id.) Eventually this will be replaced w/ something
	41	* more common-panel-framework-y
	42	*/
04b1fc02	43	struct omap_overlay_manager *mgr;
f5f9454c RC	44
f5f9454c RC	45	struct omap_video_timings timings;
f5f9454c	46
a42133a7	47	struct omap_drm_irq vblank_irq;
f5f9454c RC	48	struct omap_drm_irq error_irq;
f5f9454c RC	49
a36af73f	50	bool ignore_digit_sync_lost;
5f741b39 TV	51
	52	bool pending;
	53	wait_queue_head_t pending_wait;
f5f9454c RC	54	};
f5f9454c RC	55
971fb3e5 LP	56	/* -----------------------------------------------------------------------------
	57	* Helper Functions
	58	*/
	59
0d8f371f AT	60	uint32_t pipe2vbl(struct drm_crtc *crtc)
	61	{
	62	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	63
	64	return dispc_mgr_get_vsync_irq(omap_crtc->channel);
	65	}
	66
4029755e	67	struct omap_video_timings omap_crtc_timings(struct drm_crtc crtc)
971fb3e5 LP	68	{
	69	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	70	return &omap_crtc->timings;
	71	}
	72
	73	enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
	74	{
	75	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	76	return omap_crtc->channel;
	77	}
	78
5f741b39 TV	79	int omap_crtc_wait_pending(struct drm_crtc *crtc)
	80	{
	81	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	82
	83	return wait_event_timeout(omap_crtc->pending_wait,
	84	!omap_crtc->pending,
	85	msecs_to_jiffies(50));
	86	}
	87
971fb3e5 LP	88	/* -----------------------------------------------------------------------------
	89	* DSS Manager Functions
	90	*/
	91
f5f9454c RC	92	/*
	93	* Manager-ops, callbacks from output when they need to configure
	94	* the upstream part of the video pipe.
	95	*
	96	* Most of these we can ignore until we add support for command-mode
	97	* panels.. for video-mode the crtc-helpers already do an adequate
	98	* job of sequencing the setup of the video pipe in the proper order
	99	*/
	100
04b1fc02 TV	101	/* ovl-mgr-id -> crtc */
	102	static struct omap_crtc *omap_crtcs[8];
	103
f5f9454c	104	/* we can probably ignore these until we support command-mode panels: */
4343f0f8	105	static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
1f68d9c4	106	struct omap_dss_device *dst)
a7e71e7f TV	107	{
	108	if (mgr->output)
	109	return -EINVAL;
	110
	111	if ((mgr->supported_outputs & dst->id) == 0)
	112	return -EINVAL;
	113
	114	dst->manager = mgr;
	115	mgr->output = dst;
	116
	117	return 0;
	118	}
	119
4343f0f8	120	static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
1f68d9c4	121	struct omap_dss_device *dst)
a7e71e7f TV	122	{
	123	mgr->output->manager = NULL;
	124	mgr->output = NULL;
	125	}
	126
4343f0f8	127	static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
f5f9454c RC	128	{
	129	}
	130
4029755e	131	/* Called only from the encoder enable/disable and suspend/resume handlers. */
8472b570 LP	132	static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
	133	{
	134	struct drm_device *dev = crtc->dev;
	135	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	136	enum omap_channel channel = omap_crtc->channel;
	137	struct omap_irq_wait *wait;
	138	u32 framedone_irq, vsync_irq;
	139	int ret;
	140
	141	if (dispc_mgr_is_enabled(channel) == enable)
	142	return;
	143
ef422283 TV	144	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
	145	/*
	146	* Digit output produces some sync lost interrupts during the
	147	* first frame when enabling, so we need to ignore those.
	148	*/
	149	omap_crtc->ignore_digit_sync_lost = true;
	150	}
8472b570 LP	151
	152	framedone_irq = dispc_mgr_get_framedone_irq(channel);
	153	vsync_irq = dispc_mgr_get_vsync_irq(channel);
	154
	155	if (enable) {
	156	wait = omap_irq_wait_init(dev, vsync_irq, 1);
	157	} else {
	158	/*
	159	* When we disable the digit output, we need to wait for
	160	* FRAMEDONE to know that DISPC has finished with the output.
	161	*
	162	* OMAP2/3 does not have FRAMEDONE irq for digit output, and in
	163	* that case we need to use vsync interrupt, and wait for both
	164	* even and odd frames.
	165	*/
	166
	167	if (framedone_irq)
	168	wait = omap_irq_wait_init(dev, framedone_irq, 1);
	169	else
	170	wait = omap_irq_wait_init(dev, vsync_irq, 2);
	171	}
	172
	173	dispc_mgr_enable(channel, enable);
	174
	175	ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
	176	if (ret) {
	177	dev_err(dev->dev, "%s: timeout waiting for %s\n",
	178	omap_crtc->name, enable ? "enable" : "disable");
	179	}
	180
ef422283 TV	181	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
	182	omap_crtc->ignore_digit_sync_lost = false;
	183	/* make sure the irq handler sees the value above */
	184	mb();
	185	}
8472b570 LP	186	}
8472b570 LP	187
506096a1	188
4343f0f8	189	static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
f5f9454c	190	{
506096a1	191	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
dee8260d	192	struct omap_overlay_manager_info info;
506096a1	193
dee8260d LP	194	memset(&info, 0, sizeof(info));
	195	info.default_color = 0x00000000;
	196	info.trans_key = 0x00000000;
	197	info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
	198	info.trans_enabled = false;
	199
	200	dispc_mgr_setup(omap_crtc->channel, &info);
506096a1 TV	201	dispc_mgr_set_timings(omap_crtc->channel,
506096a1 TV	202	&omap_crtc->timings);
8472b570	203	omap_crtc_set_enabled(&omap_crtc->base, true);
506096a1	204
f5f9454c RC	205	return 0;
	206	}
	207
4343f0f8	208	static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
f5f9454c	209	{
506096a1 TV	210	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
506096a1 TV	211
8472b570	212	omap_crtc_set_enabled(&omap_crtc->base, false);
f5f9454c RC	213	}
f5f9454c RC	214
4343f0f8	215	static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
f5f9454c RC	216	const struct omap_video_timings *timings)
f5f9454c RC	217	{
04b1fc02	218	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
f5f9454c RC	219	DBG("%s", omap_crtc->name);
f5f9454c RC	220	omap_crtc->timings = *timings;
f5f9454c RC	221	}
f5f9454c RC	222
4343f0f8	223	static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
f5f9454c RC	224	const struct dss_lcd_mgr_config *config)
f5f9454c RC	225	{
04b1fc02	226	struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
f5f9454c RC	227	DBG("%s", omap_crtc->name);
	228	dispc_mgr_set_lcd_config(omap_crtc->channel, config);
	229	}
	230
4343f0f8	231	static int omap_crtc_dss_register_framedone(
f5f9454c RC	232	struct omap_overlay_manager *mgr,
	233	void (handler)(void ), void *data)
	234	{
	235	return 0;
	236	}
	237
4343f0f8	238	static void omap_crtc_dss_unregister_framedone(
f5f9454c RC	239	struct omap_overlay_manager *mgr,
	240	void (handler)(void ), void *data)
	241	{
	242	}
	243
	244	static const struct dss_mgr_ops mgr_ops = {
4343f0f8 LP	245	.connect = omap_crtc_dss_connect,
	246	.disconnect = omap_crtc_dss_disconnect,
	247	.start_update = omap_crtc_dss_start_update,
	248	.enable = omap_crtc_dss_enable,
	249	.disable = omap_crtc_dss_disable,
	250	.set_timings = omap_crtc_dss_set_timings,
	251	.set_lcd_config = omap_crtc_dss_set_lcd_config,
	252	.register_framedone_handler = omap_crtc_dss_register_framedone,
	253	.unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
cd5351f4 RC	254	};
cd5351f4 RC	255
971fb3e5	256	/* -----------------------------------------------------------------------------
1d5e5ea1	257	* Setup, Flush and Page Flip
971fb3e5 LP	258	*/
971fb3e5 LP	259
fa16d262	260	static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
15d02e92	261	{
fa16d262	262	struct drm_pending_vblank_event *event;
15d02e92	263	struct drm_device *dev = crtc->dev;
fa16d262	264	unsigned long flags;
15d02e92	265
5f741b39	266	event = crtc->state->event;
c397cfd4	267
5f741b39 TV	268	if (!event)
5f741b39 TV	269	return;
c397cfd4 LP	270
c397cfd4 LP	271	spin_lock_irqsave(&dev->event_lock, flags);
8c04fdee	272	drm_crtc_send_vblank_event(crtc, event);
5f741b39	273	spin_unlock_irqrestore(&dev->event_lock, flags);
15d02e92 LP	274	}
15d02e92 LP	275
971fb3e5 LP	276	static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
	277	{
	278	struct omap_crtc *omap_crtc =
	279	container_of(irq, struct omap_crtc, error_irq);
a36af73f TV	280
	281	if (omap_crtc->ignore_digit_sync_lost) {
	282	irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
	283	if (!irqstatus)
	284	return;
	285	}
	286
3b143fc8	287	DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
971fb3e5 LP	288	}
971fb3e5 LP	289
a42133a7	290	static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
971fb3e5 LP	291	{
971fb3e5 LP	292	struct omap_crtc *omap_crtc =
a42133a7 LP	293	container_of(irq, struct omap_crtc, vblank_irq);
a42133a7 LP	294	struct drm_device *dev = omap_crtc->base.dev;
971fb3e5	295
a42133a7 LP	296	if (dispc_mgr_go_busy(omap_crtc->channel))
	297	return;
	298
	299	DBG("%s: apply done", omap_crtc->name);
5f741b39	300
a42133a7 LP	301	__omap_irq_unregister(dev, &omap_crtc->vblank_irq);
a42133a7 LP	302
5f741b39 TV	303	rmb();
	304	WARN_ON(!omap_crtc->pending);
	305	omap_crtc->pending = false;
	306	wmb();
	307
	308	/* wake up userspace */
fa16d262	309	omap_crtc_complete_page_flip(&omap_crtc->base);
a42133a7	310
5f741b39 TV	311	/* wake up omap_atomic_complete */
5f741b39 TV	312	wake_up(&omap_crtc->pending_wait);
971fb3e5 LP	313	}
971fb3e5 LP	314
971fb3e5 LP	315	/* -----------------------------------------------------------------------------
971fb3e5 LP	316	* CRTC Functions
f5f9454c RC	317	*/
f5f9454c RC	318
cd5351f4 RC	319	static void omap_crtc_destroy(struct drm_crtc *crtc)
	320	{
	321	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
f5f9454c RC	322
	323	DBG("%s", omap_crtc->name);
	324
a42133a7	325	WARN_ON(omap_crtc->vblank_irq.registered);
f5f9454c RC	326	omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
f5f9454c RC	327
cd5351f4	328	drm_crtc_cleanup(crtc);
f5f9454c	329
cd5351f4 RC	330	kfree(omap_crtc);
	331	}
	332
f1d57fb5 LP	333	static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
	334	const struct drm_display_mode *mode,
	335	struct drm_display_mode *adjusted_mode)
	336	{
	337	return true;
	338	}
	339
	340	static void omap_crtc_enable(struct drm_crtc *crtc)
cd5351f4 RC	341	{
	342	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	343
f1d57fb5	344	DBG("%s", omap_crtc->name);
f5f9454c	345
5f741b39 TV	346	rmb();
	347	WARN_ON(omap_crtc->pending);
	348	omap_crtc->pending = true;
	349	wmb();
	350
	351	omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
	352
f1d57fb5	353	drm_crtc_vblank_on(crtc);
cd5351f4 RC	354	}
cd5351f4 RC	355
f1d57fb5	356	static void omap_crtc_disable(struct drm_crtc *crtc)
cd5351f4	357	{
f1d57fb5	358	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
f1d57fb5 LP	359
	360	DBG("%s", omap_crtc->name);
	361
f1d57fb5	362	drm_crtc_vblank_off(crtc);
cd5351f4 RC	363	}
cd5351f4 RC	364
f7a73b65	365	static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
cd5351f4 RC	366	{
cd5351f4 RC	367	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
f7a73b65	368	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
f5f9454c RC	369
f5f9454c RC	370	DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
f7a73b65 LP	371	omap_crtc->name, mode->base.id, mode->name,
	372	mode->vrefresh, mode->clock,
	373	mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
	374	mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
	375	mode->type, mode->flags);
f5f9454c RC	376
f5f9454c RC	377	copy_timings_drm_to_omap(&omap_crtc->timings, mode);
cd5351f4 RC	378	}
cd5351f4 RC	379
c201d00f DV	380	static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
c201d00f DV	381	struct drm_crtc_state *old_crtc_state)
de8e4100	382	{
fa16d262	383	}
cd5351f4	384
c201d00f DV	385	static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
c201d00f DV	386	struct drm_crtc_state *old_crtc_state)
fa16d262	387	{
6646dfd0 TV	388	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
	389
	390	WARN_ON(omap_crtc->vblank_irq.registered);
	391
	392	if (dispc_mgr_is_enabled(omap_crtc->channel)) {
5f741b39	393
6646dfd0 TV	394	DBG("%s: GO", omap_crtc->name);
6646dfd0 TV	395
5f741b39 TV	396	rmb();
	397	WARN_ON(omap_crtc->pending);
	398	omap_crtc->pending = true;
	399	wmb();
	400
6646dfd0 TV	401	dispc_mgr_go(omap_crtc->channel);
6646dfd0 TV	402	omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
6646dfd0	403	}
cd5351f4 RC	404	}
cd5351f4 RC	405
afc34932 LP	406	static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
	407	struct drm_crtc_state *state,
	408	struct drm_property *property,
	409	uint64_t val)
3c810c61	410	{
afc34932 LP	411	struct drm_plane_state *plane_state;
	412	struct drm_plane *plane = crtc->primary;
	413
	414	/*
	415	* Delegate property set to the primary plane. Get the plane state and
	416	* set the property directly.
	417	*/
	418
	419	plane_state = drm_atomic_get_plane_state(state->state, plane);
	420	if (!plane_state)
	421	return -EINVAL;
	422
	423	return drm_atomic_plane_set_property(plane, plane_state, property, val);
	424	}
1e0fdfc2	425
afc34932 LP	426	static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
	427	const struct drm_crtc_state *state,
	428	struct drm_property *property,
	429	uint64_t *val)
	430	{
	431	/*
	432	* Delegate property get to the primary plane. The
	433	* drm_atomic_plane_get_property() function isn't exported, but can be
	434	* called through drm_object_property_get_value() as that will call
	435	* drm_atomic_get_property() for atomic drivers.
	436	*/
	437	return drm_object_property_get_value(&crtc->primary->base, property,
	438	val);
3c810c61 RC	439	}
3c810c61 RC	440
cd5351f4	441	static const struct drm_crtc_funcs omap_crtc_funcs = {
69a12263	442	.reset = drm_atomic_helper_crtc_reset,
9416c9df	443	.set_config = drm_atomic_helper_set_config,
cd5351f4	444	.destroy = omap_crtc_destroy,
fa16d262	445	.page_flip = drm_atomic_helper_page_flip,
afc34932	446	.set_property = drm_atomic_helper_crtc_set_property,
69a12263 LP	447	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
69a12263 LP	448	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
afc34932 LP	449	.atomic_set_property = omap_crtc_atomic_set_property,
afc34932 LP	450	.atomic_get_property = omap_crtc_atomic_get_property,
cd5351f4 RC	451	};
	452
	453	static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
cd5351f4	454	.mode_fixup = omap_crtc_mode_fixup,
f7a73b65	455	.mode_set_nofb = omap_crtc_mode_set_nofb,
f1d57fb5 LP	456	.disable = omap_crtc_disable,
f1d57fb5 LP	457	.enable = omap_crtc_enable,
de8e4100 LP	458	.atomic_begin = omap_crtc_atomic_begin,
de8e4100 LP	459	.atomic_flush = omap_crtc_atomic_flush,
cd5351f4 RC	460	};
cd5351f4 RC	461
971fb3e5 LP	462	/* -----------------------------------------------------------------------------
	463	* Init and Cleanup
	464	*/
e2f8fd74	465
f5f9454c	466	static const char *channel_names[] = {
222025e4 LP	467	[OMAP_DSS_CHANNEL_LCD] = "lcd",
	468	[OMAP_DSS_CHANNEL_DIGIT] = "tv",
	469	[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
	470	[OMAP_DSS_CHANNEL_LCD3] = "lcd3",
f5f9454c RC	471	};
f5f9454c RC	472
04b1fc02 TV	473	void omap_crtc_pre_init(void)
	474	{
	475	dss_install_mgr_ops(&mgr_ops);
	476	}
	477
3a01ab25 AT	478	void omap_crtc_pre_uninit(void)
	479	{
	480	dss_uninstall_mgr_ops();
	481	}
	482
cd5351f4 RC	483	/* initialize crtc */
cd5351f4 RC	484	struct drm_crtc omap_crtc_init(struct drm_device dev,
f5f9454c	485	struct drm_plane *plane, enum omap_channel channel, int id)
cd5351f4 RC	486	{
cd5351f4 RC	487	struct drm_crtc *crtc = NULL;
f5f9454c	488	struct omap_crtc *omap_crtc;
ef6b0e02	489	int ret;
f5f9454c RC	490
f5f9454c RC	491	DBG("%s", channel_names[channel]);
cd5351f4	492
f5f9454c	493	omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
78110bb8	494	if (!omap_crtc)
ef6b0e02	495	return NULL;
cd5351f4	496
cd5351f4	497	crtc = &omap_crtc->base;
bb5c2d9a	498
5f741b39	499	init_waitqueue_head(&omap_crtc->pending_wait);
f5f9454c	500
0d8f371f	501	omap_crtc->channel = channel;
0d8f371f	502	omap_crtc->name = channel_names[channel];
0d8f371f	503
a42133a7 LP	504	omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
a42133a7 LP	505	omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
f5f9454c RC	506
	507	omap_crtc->error_irq.irqmask =
	508	dispc_mgr_get_sync_lost_irq(channel);
	509	omap_crtc->error_irq.irq = omap_crtc_error_irq;
	510	omap_irq_register(dev, &omap_crtc->error_irq);
	511
f5f9454c	512	/* temporary: */
04b1fc02	513	omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
f5f9454c	514
ef6b0e02	515	ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
f9882876	516	&omap_crtc_funcs, NULL);
ef6b0e02 LP	517	if (ret < 0) {
	518	kfree(omap_crtc);
	519	return NULL;
	520	}
	521
cd5351f4 RC	522	drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
cd5351f4 RC	523
ef6b0e02	524	omap_plane_install_properties(crtc->primary, &crtc->base);
3c810c61	525
04b1fc02 TV	526	omap_crtcs[channel] = omap_crtc;
04b1fc02 TV	527
cd5351f4	528	return crtc;
cd5351f4	529	}