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Commit | Line | Data |
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cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_crtc.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
b9ed9f0e | 22 | #include <drm/drm_mode.h> |
cd5351f4 RC |
23 | #include "drm_crtc.h" |
24 | #include "drm_crtc_helper.h" | |
25 | ||
26 | #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) | |
27 | ||
28 | struct omap_crtc { | |
29 | struct drm_crtc base; | |
bb5c2d9a | 30 | struct drm_plane *plane; |
f5f9454c | 31 | |
bb5c2d9a | 32 | const char *name; |
f5f9454c RC |
33 | int pipe; |
34 | enum omap_channel channel; | |
35 | struct omap_overlay_manager_info info; | |
36 | ||
37 | /* | |
38 | * Temporary: eventually this will go away, but it is needed | |
39 | * for now to keep the output's happy. (They only need | |
40 | * mgr->id.) Eventually this will be replaced w/ something | |
41 | * more common-panel-framework-y | |
42 | */ | |
04b1fc02 | 43 | struct omap_overlay_manager *mgr; |
f5f9454c RC |
44 | |
45 | struct omap_video_timings timings; | |
46 | bool enabled; | |
47 | bool full_update; | |
48 | ||
49 | struct omap_drm_apply apply; | |
50 | ||
51 | struct omap_drm_irq apply_irq; | |
52 | struct omap_drm_irq error_irq; | |
53 | ||
54 | /* list of in-progress apply's: */ | |
55 | struct list_head pending_applies; | |
56 | ||
57 | /* list of queued apply's: */ | |
58 | struct list_head queued_applies; | |
59 | ||
60 | /* for handling queued and in-progress applies: */ | |
61 | struct work_struct apply_work; | |
cd5351f4 | 62 | |
bb5c2d9a | 63 | /* if there is a pending flip, these will be non-null: */ |
cd5351f4 | 64 | struct drm_pending_vblank_event *event; |
bb5c2d9a | 65 | struct drm_framebuffer *old_fb; |
f5f9454c RC |
66 | |
67 | /* for handling page flips without caring about what | |
68 | * the callback is called from. Possibly we should just | |
69 | * make omap_gem always call the cb from the worker so | |
70 | * we don't have to care about this.. | |
71 | * | |
72 | * XXX maybe fold into apply_work?? | |
73 | */ | |
74 | struct work_struct page_flip_work; | |
75 | }; | |
76 | ||
0d8f371f AT |
77 | uint32_t pipe2vbl(struct drm_crtc *crtc) |
78 | { | |
79 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
80 | ||
81 | return dispc_mgr_get_vsync_irq(omap_crtc->channel); | |
82 | } | |
83 | ||
f5f9454c RC |
84 | /* |
85 | * Manager-ops, callbacks from output when they need to configure | |
86 | * the upstream part of the video pipe. | |
87 | * | |
88 | * Most of these we can ignore until we add support for command-mode | |
89 | * panels.. for video-mode the crtc-helpers already do an adequate | |
90 | * job of sequencing the setup of the video pipe in the proper order | |
91 | */ | |
92 | ||
04b1fc02 TV |
93 | /* ovl-mgr-id -> crtc */ |
94 | static struct omap_crtc *omap_crtcs[8]; | |
95 | ||
f5f9454c | 96 | /* we can probably ignore these until we support command-mode panels: */ |
a7e71e7f | 97 | static int omap_crtc_connect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 98 | struct omap_dss_device *dst) |
a7e71e7f TV |
99 | { |
100 | if (mgr->output) | |
101 | return -EINVAL; | |
102 | ||
103 | if ((mgr->supported_outputs & dst->id) == 0) | |
104 | return -EINVAL; | |
105 | ||
106 | dst->manager = mgr; | |
107 | mgr->output = dst; | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
112 | static void omap_crtc_disconnect(struct omap_overlay_manager *mgr, | |
1f68d9c4 | 113 | struct omap_dss_device *dst) |
a7e71e7f TV |
114 | { |
115 | mgr->output->manager = NULL; | |
116 | mgr->output = NULL; | |
117 | } | |
118 | ||
f5f9454c RC |
119 | static void omap_crtc_start_update(struct omap_overlay_manager *mgr) |
120 | { | |
121 | } | |
122 | ||
123 | static int omap_crtc_enable(struct omap_overlay_manager *mgr) | |
124 | { | |
125 | return 0; | |
126 | } | |
127 | ||
128 | static void omap_crtc_disable(struct omap_overlay_manager *mgr) | |
129 | { | |
130 | } | |
131 | ||
132 | static void omap_crtc_set_timings(struct omap_overlay_manager *mgr, | |
133 | const struct omap_video_timings *timings) | |
134 | { | |
04b1fc02 | 135 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
136 | DBG("%s", omap_crtc->name); |
137 | omap_crtc->timings = *timings; | |
138 | omap_crtc->full_update = true; | |
139 | } | |
140 | ||
141 | static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr, | |
142 | const struct dss_lcd_mgr_config *config) | |
143 | { | |
04b1fc02 | 144 | struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; |
f5f9454c RC |
145 | DBG("%s", omap_crtc->name); |
146 | dispc_mgr_set_lcd_config(omap_crtc->channel, config); | |
147 | } | |
148 | ||
149 | static int omap_crtc_register_framedone_handler( | |
150 | struct omap_overlay_manager *mgr, | |
151 | void (*handler)(void *), void *data) | |
152 | { | |
153 | return 0; | |
154 | } | |
155 | ||
156 | static void omap_crtc_unregister_framedone_handler( | |
157 | struct omap_overlay_manager *mgr, | |
158 | void (*handler)(void *), void *data) | |
159 | { | |
160 | } | |
161 | ||
162 | static const struct dss_mgr_ops mgr_ops = { | |
a7e71e7f TV |
163 | .connect = omap_crtc_connect, |
164 | .disconnect = omap_crtc_disconnect, | |
f5f9454c RC |
165 | .start_update = omap_crtc_start_update, |
166 | .enable = omap_crtc_enable, | |
167 | .disable = omap_crtc_disable, | |
168 | .set_timings = omap_crtc_set_timings, | |
169 | .set_lcd_config = omap_crtc_set_lcd_config, | |
170 | .register_framedone_handler = omap_crtc_register_framedone_handler, | |
171 | .unregister_framedone_handler = omap_crtc_unregister_framedone_handler, | |
cd5351f4 RC |
172 | }; |
173 | ||
f5f9454c RC |
174 | /* |
175 | * CRTC funcs: | |
176 | */ | |
177 | ||
cd5351f4 RC |
178 | static void omap_crtc_destroy(struct drm_crtc *crtc) |
179 | { | |
180 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c RC |
181 | |
182 | DBG("%s", omap_crtc->name); | |
183 | ||
184 | WARN_ON(omap_crtc->apply_irq.registered); | |
185 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); | |
186 | ||
bb5c2d9a | 187 | omap_crtc->plane->funcs->destroy(omap_crtc->plane); |
cd5351f4 | 188 | drm_crtc_cleanup(crtc); |
f5f9454c | 189 | |
cd5351f4 RC |
190 | kfree(omap_crtc); |
191 | } | |
192 | ||
193 | static void omap_crtc_dpms(struct drm_crtc *crtc, int mode) | |
194 | { | |
bb5c2d9a | 195 | struct omap_drm_private *priv = crtc->dev->dev_private; |
cd5351f4 | 196 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
f5f9454c | 197 | bool enabled = (mode == DRM_MODE_DPMS_ON); |
bb5c2d9a | 198 | int i; |
cd5351f4 | 199 | |
f5f9454c RC |
200 | DBG("%s: %d", omap_crtc->name, mode); |
201 | ||
202 | if (enabled != omap_crtc->enabled) { | |
203 | omap_crtc->enabled = enabled; | |
204 | omap_crtc->full_update = true; | |
205 | omap_crtc_apply(crtc, &omap_crtc->apply); | |
cd5351f4 | 206 | |
f5f9454c RC |
207 | /* also enable our private plane: */ |
208 | WARN_ON(omap_plane_dpms(omap_crtc->plane, mode)); | |
209 | ||
210 | /* and any attached overlay planes: */ | |
211 | for (i = 0; i < priv->num_planes; i++) { | |
212 | struct drm_plane *plane = priv->planes[i]; | |
213 | if (plane->crtc == crtc) | |
214 | WARN_ON(omap_plane_dpms(plane, mode)); | |
215 | } | |
cd5351f4 | 216 | } |
cd5351f4 RC |
217 | } |
218 | ||
219 | static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, | |
e811f5ae | 220 | const struct drm_display_mode *mode, |
bb5c2d9a | 221 | struct drm_display_mode *adjusted_mode) |
cd5351f4 | 222 | { |
cd5351f4 RC |
223 | return true; |
224 | } | |
225 | ||
226 | static int omap_crtc_mode_set(struct drm_crtc *crtc, | |
bb5c2d9a RC |
227 | struct drm_display_mode *mode, |
228 | struct drm_display_mode *adjusted_mode, | |
229 | int x, int y, | |
230 | struct drm_framebuffer *old_fb) | |
cd5351f4 RC |
231 | { |
232 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
233 | ||
f5f9454c RC |
234 | mode = adjusted_mode; |
235 | ||
236 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
237 | omap_crtc->name, mode->base.id, mode->name, | |
238 | mode->vrefresh, mode->clock, | |
239 | mode->hdisplay, mode->hsync_start, | |
240 | mode->hsync_end, mode->htotal, | |
241 | mode->vdisplay, mode->vsync_start, | |
242 | mode->vsync_end, mode->vtotal, | |
243 | mode->type, mode->flags); | |
244 | ||
245 | copy_timings_drm_to_omap(&omap_crtc->timings, mode); | |
246 | omap_crtc->full_update = true; | |
247 | ||
f4510a27 | 248 | return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->primary->fb, |
bb5c2d9a RC |
249 | 0, 0, mode->hdisplay, mode->vdisplay, |
250 | x << 16, y << 16, | |
f5f9454c RC |
251 | mode->hdisplay << 16, mode->vdisplay << 16, |
252 | NULL, NULL); | |
cd5351f4 RC |
253 | } |
254 | ||
255 | static void omap_crtc_prepare(struct drm_crtc *crtc) | |
256 | { | |
257 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a | 258 | DBG("%s", omap_crtc->name); |
cd5351f4 RC |
259 | omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
260 | } | |
261 | ||
262 | static void omap_crtc_commit(struct drm_crtc *crtc) | |
263 | { | |
264 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a | 265 | DBG("%s", omap_crtc->name); |
cd5351f4 RC |
266 | omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
267 | } | |
268 | ||
269 | static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
bb5c2d9a | 270 | struct drm_framebuffer *old_fb) |
cd5351f4 RC |
271 | { |
272 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
bb5c2d9a RC |
273 | struct drm_plane *plane = omap_crtc->plane; |
274 | struct drm_display_mode *mode = &crtc->mode; | |
cd5351f4 | 275 | |
f4510a27 | 276 | return omap_plane_mode_set(plane, crtc, crtc->primary->fb, |
bb5c2d9a RC |
277 | 0, 0, mode->hdisplay, mode->vdisplay, |
278 | x << 16, y << 16, | |
f5f9454c RC |
279 | mode->hdisplay << 16, mode->vdisplay << 16, |
280 | NULL, NULL); | |
cd5351f4 RC |
281 | } |
282 | ||
72d0c336 | 283 | static void vblank_cb(void *arg) |
cd5351f4 RC |
284 | { |
285 | struct drm_crtc *crtc = arg; | |
286 | struct drm_device *dev = crtc->dev; | |
287 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
cd5351f4 RC |
288 | unsigned long flags; |
289 | ||
f5f9454c RC |
290 | spin_lock_irqsave(&dev->event_lock, flags); |
291 | ||
292 | /* wakeup userspace */ | |
293 | if (omap_crtc->event) | |
294 | drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event); | |
cd5351f4 RC |
295 | |
296 | omap_crtc->event = NULL; | |
f5f9454c | 297 | omap_crtc->old_fb = NULL; |
cd5351f4 | 298 | |
f5f9454c | 299 | spin_unlock_irqrestore(&dev->event_lock, flags); |
cd5351f4 RC |
300 | } |
301 | ||
f5f9454c | 302 | static void page_flip_worker(struct work_struct *work) |
72d0c336 | 303 | { |
f5f9454c RC |
304 | struct omap_crtc *omap_crtc = |
305 | container_of(work, struct omap_crtc, page_flip_work); | |
306 | struct drm_crtc *crtc = &omap_crtc->base; | |
f5f9454c | 307 | struct drm_display_mode *mode = &crtc->mode; |
119c0814 | 308 | struct drm_gem_object *bo; |
72d0c336 | 309 | |
16ef3dfe | 310 | mutex_lock(&crtc->mutex); |
f4510a27 | 311 | omap_plane_mode_set(omap_crtc->plane, crtc, crtc->primary->fb, |
f5f9454c RC |
312 | 0, 0, mode->hdisplay, mode->vdisplay, |
313 | crtc->x << 16, crtc->y << 16, | |
314 | mode->hdisplay << 16, mode->vdisplay << 16, | |
315 | vblank_cb, crtc); | |
16ef3dfe | 316 | mutex_unlock(&crtc->mutex); |
119c0814 | 317 | |
f4510a27 | 318 | bo = omap_framebuffer_bo(crtc->primary->fb, 0); |
119c0814 | 319 | drm_gem_object_unreference_unlocked(bo); |
72d0c336 RC |
320 | } |
321 | ||
f5f9454c RC |
322 | static void page_flip_cb(void *arg) |
323 | { | |
324 | struct drm_crtc *crtc = arg; | |
325 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
326 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
327 | ||
328 | /* avoid assumptions about what ctxt we are called from: */ | |
329 | queue_work(priv->wq, &omap_crtc->page_flip_work); | |
330 | } | |
331 | ||
cd5351f4 RC |
332 | static int omap_crtc_page_flip_locked(struct drm_crtc *crtc, |
333 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
334 | struct drm_pending_vblank_event *event, |
335 | uint32_t page_flip_flags) | |
cd5351f4 RC |
336 | { |
337 | struct drm_device *dev = crtc->dev; | |
338 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f4510a27 | 339 | struct drm_plane *primary = crtc->primary; |
119c0814 | 340 | struct drm_gem_object *bo; |
cd5351f4 | 341 | |
f4510a27 | 342 | DBG("%d -> %d (event=%p)", primary->fb ? primary->fb->base.id : -1, |
f5f9454c | 343 | fb->base.id, event); |
cd5351f4 | 344 | |
f5f9454c | 345 | if (omap_crtc->old_fb) { |
cd5351f4 RC |
346 | dev_err(dev->dev, "already a pending flip\n"); |
347 | return -EINVAL; | |
348 | } | |
349 | ||
cd5351f4 | 350 | omap_crtc->event = event; |
f4510a27 | 351 | primary->fb = fb; |
cd5351f4 | 352 | |
119c0814 RC |
353 | /* |
354 | * Hold a reference temporarily until the crtc is updated | |
355 | * and takes the reference to the bo. This avoids it | |
356 | * getting freed from under us: | |
357 | */ | |
358 | bo = omap_framebuffer_bo(fb, 0); | |
359 | drm_gem_object_reference(bo); | |
360 | ||
361 | omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc); | |
cd5351f4 RC |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
3c810c61 RC |
366 | static int omap_crtc_set_property(struct drm_crtc *crtc, |
367 | struct drm_property *property, uint64_t val) | |
368 | { | |
369 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
1e0fdfc2 RC |
370 | struct omap_drm_private *priv = crtc->dev->dev_private; |
371 | ||
372 | if (property == priv->rotation_prop) { | |
373 | crtc->invert_dimensions = | |
374 | !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270))); | |
375 | } | |
376 | ||
3c810c61 RC |
377 | return omap_plane_set_property(omap_crtc->plane, property, val); |
378 | } | |
379 | ||
cd5351f4 | 380 | static const struct drm_crtc_funcs omap_crtc_funcs = { |
cd5351f4 RC |
381 | .set_config = drm_crtc_helper_set_config, |
382 | .destroy = omap_crtc_destroy, | |
383 | .page_flip = omap_crtc_page_flip_locked, | |
3c810c61 | 384 | .set_property = omap_crtc_set_property, |
cd5351f4 RC |
385 | }; |
386 | ||
387 | static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { | |
388 | .dpms = omap_crtc_dpms, | |
389 | .mode_fixup = omap_crtc_mode_fixup, | |
390 | .mode_set = omap_crtc_mode_set, | |
391 | .prepare = omap_crtc_prepare, | |
392 | .commit = omap_crtc_commit, | |
393 | .mode_set_base = omap_crtc_mode_set_base, | |
cd5351f4 RC |
394 | }; |
395 | ||
f5f9454c RC |
396 | const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) |
397 | { | |
398 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
399 | return &omap_crtc->timings; | |
400 | } | |
401 | ||
402 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) | |
403 | { | |
404 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
405 | return omap_crtc->channel; | |
406 | } | |
407 | ||
408 | static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) | |
409 | { | |
410 | struct omap_crtc *omap_crtc = | |
411 | container_of(irq, struct omap_crtc, error_irq); | |
412 | struct drm_crtc *crtc = &omap_crtc->base; | |
413 | DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus); | |
414 | /* avoid getting in a flood, unregister the irq until next vblank */ | |
6da9f891 | 415 | __omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); |
f5f9454c RC |
416 | } |
417 | ||
418 | static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus) | |
419 | { | |
420 | struct omap_crtc *omap_crtc = | |
421 | container_of(irq, struct omap_crtc, apply_irq); | |
422 | struct drm_crtc *crtc = &omap_crtc->base; | |
423 | ||
424 | if (!omap_crtc->error_irq.registered) | |
6da9f891 | 425 | __omap_irq_register(crtc->dev, &omap_crtc->error_irq); |
f5f9454c RC |
426 | |
427 | if (!dispc_mgr_go_busy(omap_crtc->channel)) { | |
428 | struct omap_drm_private *priv = | |
429 | crtc->dev->dev_private; | |
430 | DBG("%s: apply done", omap_crtc->name); | |
6da9f891 | 431 | __omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq); |
f5f9454c RC |
432 | queue_work(priv->wq, &omap_crtc->apply_work); |
433 | } | |
434 | } | |
435 | ||
436 | static void apply_worker(struct work_struct *work) | |
437 | { | |
438 | struct omap_crtc *omap_crtc = | |
439 | container_of(work, struct omap_crtc, apply_work); | |
440 | struct drm_crtc *crtc = &omap_crtc->base; | |
441 | struct drm_device *dev = crtc->dev; | |
442 | struct omap_drm_apply *apply, *n; | |
443 | bool need_apply; | |
444 | ||
445 | /* | |
446 | * Synchronize everything on mode_config.mutex, to keep | |
447 | * the callbacks and list modification all serialized | |
448 | * with respect to modesetting ioctls from userspace. | |
449 | */ | |
16ef3dfe | 450 | mutex_lock(&crtc->mutex); |
f5f9454c RC |
451 | dispc_runtime_get(); |
452 | ||
453 | /* | |
454 | * If we are still pending a previous update, wait.. when the | |
455 | * pending update completes, we get kicked again. | |
456 | */ | |
457 | if (omap_crtc->apply_irq.registered) | |
458 | goto out; | |
459 | ||
460 | /* finish up previous apply's: */ | |
461 | list_for_each_entry_safe(apply, n, | |
462 | &omap_crtc->pending_applies, pending_node) { | |
463 | apply->post_apply(apply); | |
464 | list_del(&apply->pending_node); | |
465 | } | |
466 | ||
467 | need_apply = !list_empty(&omap_crtc->queued_applies); | |
468 | ||
469 | /* then handle the next round of of queued apply's: */ | |
470 | list_for_each_entry_safe(apply, n, | |
471 | &omap_crtc->queued_applies, queued_node) { | |
472 | apply->pre_apply(apply); | |
473 | list_del(&apply->queued_node); | |
474 | apply->queued = false; | |
475 | list_add_tail(&apply->pending_node, | |
476 | &omap_crtc->pending_applies); | |
477 | } | |
478 | ||
479 | if (need_apply) { | |
480 | enum omap_channel channel = omap_crtc->channel; | |
481 | ||
482 | DBG("%s: GO", omap_crtc->name); | |
483 | ||
484 | if (dispc_mgr_is_enabled(channel)) { | |
485 | omap_irq_register(dev, &omap_crtc->apply_irq); | |
486 | dispc_mgr_go(channel); | |
487 | } else { | |
488 | struct omap_drm_private *priv = dev->dev_private; | |
489 | queue_work(priv->wq, &omap_crtc->apply_work); | |
490 | } | |
491 | } | |
492 | ||
493 | out: | |
494 | dispc_runtime_put(); | |
16ef3dfe | 495 | mutex_unlock(&crtc->mutex); |
f5f9454c RC |
496 | } |
497 | ||
498 | int omap_crtc_apply(struct drm_crtc *crtc, | |
499 | struct omap_drm_apply *apply) | |
500 | { | |
501 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c | 502 | |
16ef3dfe | 503 | WARN_ON(!mutex_is_locked(&crtc->mutex)); |
f5f9454c RC |
504 | |
505 | /* no need to queue it again if it is already queued: */ | |
506 | if (apply->queued) | |
507 | return 0; | |
508 | ||
509 | apply->queued = true; | |
510 | list_add_tail(&apply->queued_node, &omap_crtc->queued_applies); | |
511 | ||
512 | /* | |
513 | * If there are no currently pending updates, then go ahead and | |
514 | * kick the worker immediately, otherwise it will run again when | |
515 | * the current update finishes. | |
516 | */ | |
517 | if (list_empty(&omap_crtc->pending_applies)) { | |
518 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
519 | queue_work(priv->wq, &omap_crtc->apply_work); | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | /* called only from apply */ | |
526 | static void set_enabled(struct drm_crtc *crtc, bool enable) | |
527 | { | |
528 | struct drm_device *dev = crtc->dev; | |
529 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
530 | enum omap_channel channel = omap_crtc->channel; | |
2ec8e378 TV |
531 | struct omap_irq_wait *wait; |
532 | u32 framedone_irq, vsync_irq; | |
533 | int ret; | |
f5f9454c RC |
534 | |
535 | if (dispc_mgr_is_enabled(channel) == enable) | |
536 | return; | |
537 | ||
2ec8e378 TV |
538 | /* |
539 | * Digit output produces some sync lost interrupts during the first | |
540 | * frame when enabling, so we need to ignore those. | |
541 | */ | |
f5f9454c RC |
542 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); |
543 | ||
2ec8e378 TV |
544 | framedone_irq = dispc_mgr_get_framedone_irq(channel); |
545 | vsync_irq = dispc_mgr_get_vsync_irq(channel); | |
546 | ||
547 | if (enable) { | |
548 | wait = omap_irq_wait_init(dev, vsync_irq, 1); | |
f5f9454c RC |
549 | } else { |
550 | /* | |
2ec8e378 TV |
551 | * When we disable the digit output, we need to wait for |
552 | * FRAMEDONE to know that DISPC has finished with the output. | |
553 | * | |
554 | * OMAP2/3 does not have FRAMEDONE irq for digit output, and in | |
555 | * that case we need to use vsync interrupt, and wait for both | |
556 | * even and odd frames. | |
f5f9454c | 557 | */ |
2ec8e378 TV |
558 | |
559 | if (framedone_irq) | |
560 | wait = omap_irq_wait_init(dev, framedone_irq, 1); | |
561 | else | |
562 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | |
f5f9454c RC |
563 | } |
564 | ||
565 | dispc_mgr_enable(channel, enable); | |
566 | ||
2ec8e378 TV |
567 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); |
568 | if (ret) { | |
569 | dev_err(dev->dev, "%s: timeout waiting for %s\n", | |
570 | omap_crtc->name, enable ? "enable" : "disable"); | |
f5f9454c RC |
571 | } |
572 | ||
573 | omap_irq_register(crtc->dev, &omap_crtc->error_irq); | |
574 | } | |
575 | ||
576 | static void omap_crtc_pre_apply(struct omap_drm_apply *apply) | |
577 | { | |
578 | struct omap_crtc *omap_crtc = | |
579 | container_of(apply, struct omap_crtc, apply); | |
580 | struct drm_crtc *crtc = &omap_crtc->base; | |
581 | struct drm_encoder *encoder = NULL; | |
582 | ||
583 | DBG("%s: enabled=%d, full=%d", omap_crtc->name, | |
584 | omap_crtc->enabled, omap_crtc->full_update); | |
585 | ||
586 | if (omap_crtc->full_update) { | |
587 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
588 | int i; | |
589 | for (i = 0; i < priv->num_encoders; i++) { | |
590 | if (priv->encoders[i]->crtc == crtc) { | |
591 | encoder = priv->encoders[i]; | |
592 | break; | |
593 | } | |
594 | } | |
595 | } | |
596 | ||
597 | if (!omap_crtc->enabled) { | |
598 | set_enabled(&omap_crtc->base, false); | |
599 | if (encoder) | |
600 | omap_encoder_set_enabled(encoder, false); | |
601 | } else { | |
602 | if (encoder) { | |
603 | omap_encoder_set_enabled(encoder, false); | |
04b1fc02 | 604 | omap_encoder_update(encoder, omap_crtc->mgr, |
f5f9454c RC |
605 | &omap_crtc->timings); |
606 | omap_encoder_set_enabled(encoder, true); | |
607 | omap_crtc->full_update = false; | |
608 | } | |
609 | ||
610 | dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info); | |
611 | dispc_mgr_set_timings(omap_crtc->channel, | |
612 | &omap_crtc->timings); | |
613 | set_enabled(&omap_crtc->base, true); | |
614 | } | |
615 | ||
616 | omap_crtc->full_update = false; | |
617 | } | |
618 | ||
619 | static void omap_crtc_post_apply(struct omap_drm_apply *apply) | |
620 | { | |
621 | /* nothing needed for post-apply */ | |
622 | } | |
623 | ||
e2f8fd74 TV |
624 | void omap_crtc_flush(struct drm_crtc *crtc) |
625 | { | |
626 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
627 | int loops = 0; | |
628 | ||
629 | while (!list_empty(&omap_crtc->pending_applies) || | |
630 | !list_empty(&omap_crtc->queued_applies) || | |
631 | omap_crtc->event || omap_crtc->old_fb) { | |
632 | ||
633 | if (++loops > 10) { | |
634 | dev_err(crtc->dev->dev, | |
635 | "omap_crtc_flush() timeout\n"); | |
636 | break; | |
637 | } | |
638 | ||
639 | schedule_timeout_uninterruptible(msecs_to_jiffies(20)); | |
640 | } | |
641 | } | |
642 | ||
f5f9454c RC |
643 | static const char *channel_names[] = { |
644 | [OMAP_DSS_CHANNEL_LCD] = "lcd", | |
645 | [OMAP_DSS_CHANNEL_DIGIT] = "tv", | |
646 | [OMAP_DSS_CHANNEL_LCD2] = "lcd2", | |
647 | }; | |
648 | ||
04b1fc02 TV |
649 | void omap_crtc_pre_init(void) |
650 | { | |
651 | dss_install_mgr_ops(&mgr_ops); | |
652 | } | |
653 | ||
3a01ab25 AT |
654 | void omap_crtc_pre_uninit(void) |
655 | { | |
656 | dss_uninstall_mgr_ops(); | |
657 | } | |
658 | ||
cd5351f4 RC |
659 | /* initialize crtc */ |
660 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |
f5f9454c | 661 | struct drm_plane *plane, enum omap_channel channel, int id) |
cd5351f4 RC |
662 | { |
663 | struct drm_crtc *crtc = NULL; | |
f5f9454c RC |
664 | struct omap_crtc *omap_crtc; |
665 | struct omap_overlay_manager_info *info; | |
666 | ||
667 | DBG("%s", channel_names[channel]); | |
cd5351f4 | 668 | |
f5f9454c | 669 | omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); |
78110bb8 | 670 | if (!omap_crtc) |
cd5351f4 | 671 | goto fail; |
cd5351f4 | 672 | |
cd5351f4 | 673 | crtc = &omap_crtc->base; |
bb5c2d9a | 674 | |
f5f9454c RC |
675 | INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker); |
676 | INIT_WORK(&omap_crtc->apply_work, apply_worker); | |
677 | ||
678 | INIT_LIST_HEAD(&omap_crtc->pending_applies); | |
679 | INIT_LIST_HEAD(&omap_crtc->queued_applies); | |
680 | ||
681 | omap_crtc->apply.pre_apply = omap_crtc_pre_apply; | |
682 | omap_crtc->apply.post_apply = omap_crtc_post_apply; | |
683 | ||
0d8f371f AT |
684 | omap_crtc->channel = channel; |
685 | omap_crtc->plane = plane; | |
686 | omap_crtc->plane->crtc = crtc; | |
687 | omap_crtc->name = channel_names[channel]; | |
688 | omap_crtc->pipe = id; | |
689 | ||
690 | omap_crtc->apply_irq.irqmask = pipe2vbl(crtc); | |
f5f9454c RC |
691 | omap_crtc->apply_irq.irq = omap_crtc_apply_irq; |
692 | ||
693 | omap_crtc->error_irq.irqmask = | |
694 | dispc_mgr_get_sync_lost_irq(channel); | |
695 | omap_crtc->error_irq.irq = omap_crtc_error_irq; | |
696 | omap_irq_register(dev, &omap_crtc->error_irq); | |
697 | ||
f5f9454c | 698 | /* temporary: */ |
04b1fc02 | 699 | omap_crtc->mgr = omap_dss_get_overlay_manager(channel); |
f5f9454c RC |
700 | |
701 | /* TODO: fix hard-coded setup.. add properties! */ | |
702 | info = &omap_crtc->info; | |
703 | info->default_color = 0x00000000; | |
704 | info->trans_key = 0x00000000; | |
705 | info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST; | |
706 | info->trans_enabled = false; | |
bb5c2d9a | 707 | |
cd5351f4 RC |
708 | drm_crtc_init(dev, crtc, &omap_crtc_funcs); |
709 | drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); | |
710 | ||
3c810c61 RC |
711 | omap_plane_install_properties(omap_crtc->plane, &crtc->base); |
712 | ||
04b1fc02 TV |
713 | omap_crtcs[channel] = omap_crtc; |
714 | ||
cd5351f4 RC |
715 | return crtc; |
716 | ||
717 | fail: | |
d21a9d3b | 718 | if (crtc) |
65b0bd06 | 719 | omap_crtc_destroy(crtc); |
d21a9d3b | 720 | |
cd5351f4 RC |
721 | return NULL; |
722 | } |