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drm/omap: add writeback funcs to dispc_ops
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / omapdrm / omap_drv.c
CommitLineData
cd5351f4 1/*
bb5cdf8d 2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
cd5351f4
RC
3 * Author: Rob Clark <rob@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
6e471fab
LP
18#include <linux/sys_soc.h>
19
748471a5 20#include <drm/drm_atomic.h>
cef77d40 21#include <drm/drm_atomic_helper.h>
2d278f54
LP
22#include <drm/drm_crtc_helper.h>
23#include <drm/drm_fb_helper.h>
cd5351f4 24
5c137797 25#include "omap_dmm_tiler.h"
2d278f54 26#include "omap_drv.h"
cd5351f4
RC
27
28#define DRIVER_NAME MODULE_NAME
29#define DRIVER_DESC "OMAP DRM"
30#define DRIVER_DATE "20110917"
31#define DRIVER_MAJOR 1
32#define DRIVER_MINOR 0
33#define DRIVER_PATCHLEVEL 0
34
cd5351f4
RC
35/*
36 * mode config funcs
37 */
38
39/* Notes about mapping DSS and DRM entities:
40 * CRTC: overlay
41 * encoder: manager.. with some extension to allow one primary CRTC
42 * and zero or more video CRTC's to be mapped to one encoder?
43 * connector: dssdev.. manager can be attached/detached from different
44 * devices
45 */
46
5f741b39
TV
47static void omap_atomic_wait_for_completion(struct drm_device *dev,
48 struct drm_atomic_state *old_state)
49{
34d88237 50 struct drm_crtc_state *new_crtc_state;
5f741b39
TV
51 struct drm_crtc *crtc;
52 unsigned int i;
53 int ret;
54
34d88237
ML
55 for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
56 if (!new_crtc_state->active)
5f741b39
TV
57 continue;
58
59 ret = omap_crtc_wait_pending(crtc);
60
61 if (!ret)
62 dev_warn(dev->dev,
63 "atomic complete timeout (pipe %u)!\n", i);
64 }
65}
66
a9e6f9f7 67static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
748471a5 68{
a9e6f9f7 69 struct drm_device *dev = old_state->dev;
748471a5 70 struct omap_drm_private *priv = dev->dev_private;
748471a5 71
50638ae5 72 priv->dispc_ops->runtime_get(priv->dispc);
69fb7c85 73
a9e6f9f7 74 /* Apply the atomic update. */
748471a5 75 drm_atomic_helper_commit_modeset_disables(dev, old_state);
897145d0 76
fc5cc967
TV
77 if (priv->omaprev != 0x3430) {
78 /* With the current dss dispc implementation we have to enable
79 * the new modeset before we can commit planes. The dispc ovl
80 * configuration relies on the video mode configuration been
81 * written into the HW when the ovl configuration is
82 * calculated.
83 *
84 * This approach is not ideal because after a mode change the
85 * plane update is executed only after the first vblank
86 * interrupt. The dispc implementation should be fixed so that
87 * it is able use uncommitted drm state information.
88 */
89 drm_atomic_helper_commit_modeset_enables(dev, old_state);
90 omap_atomic_wait_for_completion(dev, old_state);
91
92 drm_atomic_helper_commit_planes(dev, old_state, 0);
93
94 drm_atomic_helper_commit_hw_done(old_state);
95 } else {
96 /*
97 * OMAP3 DSS seems to have issues with the work-around above,
98 * resulting in endless sync losts if a crtc is enabled without
99 * a plane. For now, skip the WA for OMAP3.
100 */
101 drm_atomic_helper_commit_planes(dev, old_state, 0);
102
103 drm_atomic_helper_commit_modeset_enables(dev, old_state);
104
105 drm_atomic_helper_commit_hw_done(old_state);
106 }
a9e6f9f7
LP
107
108 /*
109 * Wait for completion of the page flips to ensure that old buffers
110 * can't be touched by the hardware anymore before cleaning up planes.
111 */
5f741b39 112 omap_atomic_wait_for_completion(dev, old_state);
748471a5
LP
113
114 drm_atomic_helper_cleanup_planes(dev, old_state);
115
50638ae5 116 priv->dispc_ops->runtime_put(priv->dispc);
748471a5
LP
117}
118
a9e6f9f7
LP
119static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
120 .atomic_commit_tail = omap_atomic_commit_tail,
121};
748471a5 122
e6ecefaa 123static const struct drm_mode_config_funcs omap_mode_config_funcs = {
cd5351f4 124 .fb_create = omap_framebuffer_create,
ef62d308 125 .output_poll_changed = drm_fb_helper_output_poll_changed,
cef77d40 126 .atomic_check = drm_atomic_helper_check,
a9e6f9f7 127 .atomic_commit = drm_atomic_helper_commit,
cd5351f4
RC
128};
129
130static int get_connector_type(struct omap_dss_device *dssdev)
131{
132 switch (dssdev->type) {
133 case OMAP_DISPLAY_TYPE_HDMI:
134 return DRM_MODE_CONNECTOR_HDMIA;
4635c17d
TV
135 case OMAP_DISPLAY_TYPE_DVI:
136 return DRM_MODE_CONNECTOR_DVID;
4a64b908
SR
137 case OMAP_DISPLAY_TYPE_DSI:
138 return DRM_MODE_CONNECTOR_DSI;
564f88c1
TV
139 case OMAP_DISPLAY_TYPE_DPI:
140 case OMAP_DISPLAY_TYPE_DBI:
141 return DRM_MODE_CONNECTOR_DPI;
142 case OMAP_DISPLAY_TYPE_VENC:
143 /* TODO: This could also be composite */
144 return DRM_MODE_CONNECTOR_SVIDEO;
145 case OMAP_DISPLAY_TYPE_SDI:
146 return DRM_MODE_CONNECTOR_LVDS;
cd5351f4
RC
147 default:
148 return DRM_MODE_CONNECTOR_Unknown;
149 }
150}
151
cc823bdc
AT
152static void omap_disconnect_dssdevs(void)
153{
154 struct omap_dss_device *dssdev = NULL;
155
156 for_each_dss_dev(dssdev)
157 dssdev->driver->disconnect(dssdev);
158}
0d8f371f 159
3a01ab25
AT
160static int omap_connect_dssdevs(void)
161{
162 int r;
163 struct omap_dss_device *dssdev = NULL;
a09d2bc1
PU
164
165 if (!omapdss_stack_is_ready())
166 return -EPROBE_DEFER;
3a01ab25
AT
167
168 for_each_dss_dev(dssdev) {
169 r = dssdev->driver->connect(dssdev);
170 if (r == -EPROBE_DEFER) {
171 omap_dss_put_device(dssdev);
172 goto cleanup;
173 } else if (r) {
174 dev_warn(dssdev->dev, "could not connect display: %s\n",
175 dssdev->name);
3a01ab25
AT
176 }
177 }
178
3a01ab25
AT
179 return 0;
180
181cleanup:
182 /*
183 * if we are deferring probe, we disconnect the devices we previously
184 * connected
185 */
cc823bdc 186 omap_disconnect_dssdevs();
3a01ab25
AT
187
188 return r;
189}
0d8f371f 190
e2cd09b2
LP
191static int omap_modeset_init_properties(struct drm_device *dev)
192{
193 struct omap_drm_private *priv = dev->dev_private;
50638ae5 194 unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
e2cd09b2 195
dff6c246
LP
196 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
197 num_planes - 1);
e2cd09b2
LP
198 if (!priv->zorder_prop)
199 return -ENOMEM;
200
201 return 0;
202}
203
f5f9454c 204static int omap_modeset_init(struct drm_device *dev)
cd5351f4
RC
205{
206 struct omap_drm_private *priv = dev->dev_private;
f5f9454c 207 struct omap_dss_device *dssdev = NULL;
50638ae5
LP
208 int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
209 int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
e8e13b15 210 int num_crtcs, crtc_idx, plane_idx;
fb9a35f8 211 int ret;
e8e13b15 212 u32 plane_crtc_mask;
04b1fc02 213
f5f9454c 214 drm_mode_config_init(dev);
cd5351f4 215
e2cd09b2
LP
216 ret = omap_modeset_init_properties(dev);
217 if (ret < 0)
218 return ret;
219
f5f9454c 220 /*
e8e13b15
JS
221 * This function creates exactly one connector, encoder, crtc,
222 * and primary plane per each connected dss-device. Each
223 * connector->encoder->crtc chain is expected to be separate
224 * and each crtc is connect to a single dss-channel. If the
225 * configuration does not match the expectations or exceeds
226 * the available resources, the configuration is rejected.
f5f9454c 227 */
e8e13b15 228 num_crtcs = 0;
f1118b89
JS
229 for_each_dss_dev(dssdev)
230 if (omapdss_device_is_connected(dssdev))
231 num_crtcs++;
232
e8e13b15
JS
233 if (num_crtcs > num_mgrs || num_crtcs > num_ovls ||
234 num_crtcs > ARRAY_SIZE(priv->crtcs) ||
235 num_crtcs > ARRAY_SIZE(priv->planes) ||
236 num_crtcs > ARRAY_SIZE(priv->encoders) ||
237 num_crtcs > ARRAY_SIZE(priv->connectors)) {
238 dev_err(dev->dev, "%s(): Too many connected displays\n",
239 __func__);
240 return -EINVAL;
241 }
242
243 /* All planes can be put to any CRTC */
244 plane_crtc_mask = (1 << num_crtcs) - 1;
cd5351f4 245
0d8f371f 246 dssdev = NULL;
cd5351f4 247
e8e13b15
JS
248 crtc_idx = 0;
249 plane_idx = 0;
f5f9454c
RC
250 for_each_dss_dev(dssdev) {
251 struct drm_connector *connector;
252 struct drm_encoder *encoder;
e8e13b15
JS
253 struct drm_plane *plane;
254 struct drm_crtc *crtc;
c7f904b3 255
3a01ab25 256 if (!omapdss_device_is_connected(dssdev))
581382e3 257 continue;
a7e71e7f 258
f5f9454c 259 encoder = omap_encoder_init(dev, dssdev);
e8e13b15 260 if (!encoder)
f5f9454c 261 return -ENOMEM;
cd5351f4 262
f5f9454c
RC
263 connector = omap_connector_init(dev,
264 get_connector_type(dssdev), dssdev, encoder);
e8e13b15 265 if (!connector)
f5f9454c 266 return -ENOMEM;
bb5c2d9a 267
e8e13b15
JS
268 plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY,
269 plane_crtc_mask);
270 if (IS_ERR(plane))
271 return PTR_ERR(plane);
cd5351f4 272
e8e13b15
JS
273 crtc = omap_crtc_init(dev, plane, dssdev);
274 if (IS_ERR(crtc))
275 return PTR_ERR(crtc);
cd5351f4 276
f5f9454c 277 drm_mode_connector_attach_encoder(connector, encoder);
e8e13b15 278 encoder->possible_crtcs = (1 << crtc_idx);
cd5351f4 279
e8e13b15
JS
280 priv->crtcs[priv->num_crtcs++] = crtc;
281 priv->planes[priv->num_planes++] = plane;
282 priv->encoders[priv->num_encoders++] = encoder;
283 priv->connectors[priv->num_connectors++] = connector;
0d8f371f 284
e8e13b15
JS
285 plane_idx++;
286 crtc_idx++;
0d8f371f
AT
287 }
288
0d8f371f
AT
289 /*
290 * Create normal planes for the remaining overlays:
291 */
e8e13b15 292 for (; plane_idx < num_ovls; plane_idx++) {
fb9a35f8
LP
293 struct drm_plane *plane;
294
e8e13b15
JS
295 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
296 return -EINVAL;
297
298 plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY,
299 plane_crtc_mask);
fb9a35f8
LP
300 if (IS_ERR(plane))
301 return PTR_ERR(plane);
0d8f371f 302
0d8f371f
AT
303 priv->planes[priv->num_planes++] = plane;
304 }
305
0d8f371f
AT
306 DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
307 priv->num_planes, priv->num_crtcs, priv->num_encoders,
308 priv->num_connectors);
309
1e90711d
TV
310 dev->mode_config.min_width = 8;
311 dev->mode_config.min_height = 2;
cd5351f4
RC
312
313 /* note: eventually will need some cpu_is_omapXYZ() type stuff here
314 * to fill in these limits properly on different OMAP generations..
315 */
316 dev->mode_config.max_width = 2048;
317 dev->mode_config.max_height = 2048;
318
319 dev->mode_config.funcs = &omap_mode_config_funcs;
a9e6f9f7 320 dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
cd5351f4 321
69a12263
LP
322 drm_mode_config_reset(dev);
323
728ae8dd
LP
324 omap_drm_irq_install(dev);
325
cd5351f4
RC
326 return 0;
327}
328
3c596800
PU
329/*
330 * Enable the HPD in external components if supported
331 */
332static void omap_modeset_enable_external_hpd(void)
333{
334 struct omap_dss_device *dssdev = NULL;
335
336 for_each_dss_dev(dssdev) {
337 if (dssdev->driver->enable_hpd)
338 dssdev->driver->enable_hpd(dssdev);
339 }
340}
341
342/*
343 * Disable the HPD in external components if supported
344 */
345static void omap_modeset_disable_external_hpd(void)
346{
347 struct omap_dss_device *dssdev = NULL;
348
349 for_each_dss_dev(dssdev) {
350 if (dssdev->driver->disable_hpd)
351 dssdev->driver->disable_hpd(dssdev);
352 }
353}
354
cd5351f4
RC
355/*
356 * drm ioctl funcs
357 */
358
359
360static int ioctl_get_param(struct drm_device *dev, void *data,
361 struct drm_file *file_priv)
362{
5e3b0874 363 struct omap_drm_private *priv = dev->dev_private;
cd5351f4
RC
364 struct drm_omap_param *args = data;
365
366 DBG("%p: param=%llu", dev, args->param);
367
368 switch (args->param) {
369 case OMAP_PARAM_CHIPSET_ID:
5e3b0874 370 args->value = priv->omaprev;
cd5351f4
RC
371 break;
372 default:
373 DBG("unknown parameter %lld", args->param);
374 return -EINVAL;
375 }
376
377 return 0;
378}
379
380static int ioctl_set_param(struct drm_device *dev, void *data,
381 struct drm_file *file_priv)
382{
383 struct drm_omap_param *args = data;
384
385 switch (args->param) {
386 default:
387 DBG("unknown parameter %lld", args->param);
388 return -EINVAL;
389 }
390
391 return 0;
392}
393
ef3f4e99
LP
394#define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
395
cd5351f4
RC
396static int ioctl_gem_new(struct drm_device *dev, void *data,
397 struct drm_file *file_priv)
398{
399 struct drm_omap_gem_new *args = data;
ef3f4e99
LP
400 u32 flags = args->flags & OMAP_BO_USER_MASK;
401
f5f9454c 402 VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
ef3f4e99
LP
403 args->size.bytes, flags);
404
405 return omap_gem_new_handle(dev, file_priv, args->size, flags,
406 &args->handle);
cd5351f4
RC
407}
408
cd5351f4
RC
409static int ioctl_gem_info(struct drm_device *dev, void *data,
410 struct drm_file *file_priv)
411{
412 struct drm_omap_gem_info *args = data;
413 struct drm_gem_object *obj;
414 int ret = 0;
415
f5f9454c 416 VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
cd5351f4 417
a8ad0bd8 418 obj = drm_gem_object_lookup(file_priv, args->handle);
c7f904b3 419 if (!obj)
cd5351f4 420 return -ENOENT;
cd5351f4 421
f7f9f453 422 args->size = omap_gem_mmap_size(obj);
cd5351f4
RC
423 args->offset = omap_gem_mmap_offset(obj);
424
425 drm_gem_object_unreference_unlocked(obj);
426
427 return ret;
428}
429
baa70943 430static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
5f6ab8ca
HH
431 DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
432 DRM_AUTH | DRM_RENDER_ALLOW),
433 DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
434 DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
435 DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
436 DRM_AUTH | DRM_RENDER_ALLOW),
d6f544f6
LP
437 /* Deprecated, to be removed. */
438 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
5f6ab8ca 439 DRM_AUTH | DRM_RENDER_ALLOW),
d6f544f6
LP
440 /* Deprecated, to be removed. */
441 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
5f6ab8ca
HH
442 DRM_AUTH | DRM_RENDER_ALLOW),
443 DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
444 DRM_AUTH | DRM_RENDER_ALLOW),
cd5351f4
RC
445};
446
447/*
448 * drm driver funcs
449 */
450
cd5351f4
RC
451static int dev_open(struct drm_device *dev, struct drm_file *file)
452{
453 file->driver_priv = NULL;
454
455 DBG("open: dev=%p, file=%p", dev, file);
456
457 return 0;
458}
459
78b68556 460static const struct vm_operations_struct omap_gem_vm_ops = {
cd5351f4
RC
461 .fault = omap_gem_fault,
462 .open = drm_gem_vm_open,
463 .close = drm_gem_vm_close,
464};
465
ff4f3876 466static const struct file_operations omapdriver_fops = {
222025e4
LP
467 .owner = THIS_MODULE,
468 .open = drm_open,
469 .unlocked_ioctl = drm_ioctl,
9d24159a 470 .compat_ioctl = drm_compat_ioctl,
222025e4
LP
471 .release = drm_release,
472 .mmap = omap_gem_mmap,
473 .poll = drm_poll,
474 .read = drm_read,
475 .llseek = noop_llseek,
ff4f3876
RC
476};
477
cd5351f4 478static struct drm_driver omap_drm_driver = {
728fea77 479 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
5f6ab8ca 480 DRIVER_ATOMIC | DRIVER_RENDER,
222025e4 481 .open = dev_open,
ef62d308 482 .lastclose = drm_fb_helper_lastclose,
6169a148 483#ifdef CONFIG_DEBUG_FS
222025e4 484 .debugfs_init = omap_debugfs_init,
6169a148 485#endif
222025e4
LP
486 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
487 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
488 .gem_prime_export = omap_gem_prime_export,
489 .gem_prime_import = omap_gem_prime_import,
490 .gem_free_object = omap_gem_free_object,
491 .gem_vm_ops = &omap_gem_vm_ops,
492 .dumb_create = omap_gem_dumb_create,
493 .dumb_map_offset = omap_gem_dumb_map_offset,
222025e4
LP
494 .ioctls = ioctls,
495 .num_ioctls = DRM_OMAP_NUM_IOCTLS,
496 .fops = &omapdriver_fops,
497 .name = DRIVER_NAME,
498 .desc = DRIVER_DESC,
499 .date = DRIVER_DATE,
500 .major = DRIVER_MAJOR,
501 .minor = DRIVER_MINOR,
502 .patchlevel = DRIVER_PATCHLEVEL,
cd5351f4
RC
503};
504
6e471fab
LP
505static const struct soc_device_attribute omapdrm_soc_devices[] = {
506 { .family = "OMAP3", .data = (void *)0x3430 },
507 { .family = "OMAP4", .data = (void *)0x4430 },
508 { .family = "OMAP5", .data = (void *)0x5430 },
509 { .family = "DRA7", .data = (void *)0x0752 },
510 { /* sentinel */ }
511};
512
a82f0347 513static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
cd5351f4 514{
6e471fab 515 const struct soc_device_attribute *soc;
2f95bc6d
LP
516 struct drm_device *ddev;
517 unsigned int i;
518 int ret;
519
a82f0347 520 DBG("%s", dev_name(dev));
591a0ac7 521
a82f0347 522 priv->dev = dev;
d3541ca8 523 priv->dss = omapdss_get_dss();
50638ae5 524 priv->dispc = dispc_get_dispc(priv->dss);
d3541ca8 525 priv->dispc_ops = dispc_get_ops(priv->dss);
510c74c5 526
64cb8179 527 omap_crtc_pre_init(priv);
3a01ab25 528
2f95bc6d
LP
529 ret = omap_connect_dssdevs();
530 if (ret)
531 goto err_crtc_uninit;
532
6e471fab
LP
533 soc = soc_device_match(omapdrm_soc_devices);
534 priv->omaprev = soc ? (unsigned int)soc->data : 0;
2f95bc6d
LP
535 priv->wq = alloc_ordered_workqueue("omapdrm", 0);
536
2f95bc6d
LP
537 spin_lock_init(&priv->list_lock);
538 INIT_LIST_HEAD(&priv->obj_list);
539
540 /* Allocate and initialize the DRM device. */
a82f0347 541 ddev = drm_dev_alloc(&omap_drm_driver, priv->dev);
2f95bc6d
LP
542 if (IS_ERR(ddev)) {
543 ret = PTR_ERR(ddev);
a82f0347 544 goto err_destroy_wq;
2f95bc6d
LP
545 }
546
a82f0347 547 priv->ddev = ddev;
2f95bc6d 548 ddev->dev_private = priv;
2f95bc6d 549
a7631c4b
PU
550 /* Get memory bandwidth limits */
551 if (priv->dispc_ops->get_memory_bandwidth_limit)
552 priv->max_bandwidth =
50638ae5 553 priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
a7631c4b 554
2f95bc6d
LP
555 omap_gem_init(ddev);
556
557 ret = omap_modeset_init(ddev);
558 if (ret) {
a82f0347 559 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
2f95bc6d
LP
560 goto err_free_drm_dev;
561 }
562
563 /* Initialize vblank handling, start with all CRTCs disabled. */
564 ret = drm_vblank_init(ddev, priv->num_crtcs);
565 if (ret) {
a82f0347 566 dev_err(priv->dev, "could not init vblank\n");
2f95bc6d 567 goto err_cleanup_modeset;
3a01ab25
AT
568 }
569
2f95bc6d
LP
570 for (i = 0; i < priv->num_crtcs; i++)
571 drm_crtc_vblank_off(priv->crtcs[i]);
572
efd1f06b 573 omap_fbdev_init(ddev);
2f95bc6d
LP
574
575 drm_kms_helper_poll_init(ddev);
3c596800 576 omap_modeset_enable_external_hpd();
2f95bc6d
LP
577
578 /*
579 * Register the DRM device with the core and the connectors with
580 * sysfs.
581 */
582 ret = drm_dev_register(ddev, 0);
583 if (ret)
584 goto err_cleanup_helpers;
585
586 return 0;
587
588err_cleanup_helpers:
3c596800 589 omap_modeset_disable_external_hpd();
2f95bc6d 590 drm_kms_helper_poll_fini(ddev);
efd1f06b
TV
591
592 omap_fbdev_fini(ddev);
2f95bc6d
LP
593err_cleanup_modeset:
594 drm_mode_config_cleanup(ddev);
595 omap_drm_irq_uninstall(ddev);
596err_free_drm_dev:
597 omap_gem_deinit(ddev);
598 drm_dev_unref(ddev);
a82f0347 599err_destroy_wq:
2f95bc6d 600 destroy_workqueue(priv->wq);
2f95bc6d
LP
601 omap_disconnect_dssdevs();
602err_crtc_uninit:
603 omap_crtc_pre_uninit();
604 return ret;
cd5351f4
RC
605}
606
a82f0347 607static void omapdrm_cleanup(struct omap_drm_private *priv)
cd5351f4 608{
a82f0347 609 struct drm_device *ddev = priv->ddev;
2f95bc6d 610
cd5351f4 611 DBG("");
5c137797 612
2f95bc6d
LP
613 drm_dev_unregister(ddev);
614
3c596800 615 omap_modeset_disable_external_hpd();
2f95bc6d
LP
616 drm_kms_helper_poll_fini(ddev);
617
efd1f06b 618 omap_fbdev_fini(ddev);
2f95bc6d 619
8a54aa92
TV
620 drm_atomic_helper_shutdown(ddev);
621
2f95bc6d
LP
622 drm_mode_config_cleanup(ddev);
623
624 omap_drm_irq_uninstall(ddev);
625 omap_gem_deinit(ddev);
626
627 drm_dev_unref(ddev);
628
629 destroy_workqueue(priv->wq);
707cf58a 630
cc823bdc
AT
631 omap_disconnect_dssdevs();
632 omap_crtc_pre_uninit();
a82f0347
LP
633}
634
635static int pdev_probe(struct platform_device *pdev)
636{
637 struct omap_drm_private *priv;
638 int ret;
639
640 if (omapdss_is_initialized() == false)
641 return -EPROBE_DEFER;
642
643 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
644 if (ret) {
645 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
646 return ret;
647 }
648
649 /* Allocate and initialize the driver private structure. */
650 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
651 if (!priv)
652 return -ENOMEM;
653
654 platform_set_drvdata(pdev, priv);
655
656 ret = omapdrm_init(priv, &pdev->dev);
657 if (ret < 0)
658 kfree(priv);
659
660 return ret;
661}
662
663static int pdev_remove(struct platform_device *pdev)
664{
665 struct omap_drm_private *priv = platform_get_drvdata(pdev);
666
667 omapdrm_cleanup(priv);
668 kfree(priv);
fd3c0253 669
cd5351f4
RC
670 return 0;
671}
672
8450c8d0 673#ifdef CONFIG_PM_SLEEP
92bf0f9e
TV
674static int omap_drm_suspend_all_displays(void)
675{
676 struct omap_dss_device *dssdev = NULL;
677
678 for_each_dss_dev(dssdev) {
679 if (!dssdev->driver)
680 continue;
681
682 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
683 dssdev->driver->disable(dssdev);
684 dssdev->activate_after_resume = true;
685 } else {
686 dssdev->activate_after_resume = false;
687 }
688 }
689
690 return 0;
691}
692
693static int omap_drm_resume_all_displays(void)
694{
695 struct omap_dss_device *dssdev = NULL;
696
697 for_each_dss_dev(dssdev) {
698 if (!dssdev->driver)
699 continue;
700
701 if (dssdev->activate_after_resume) {
702 dssdev->driver->enable(dssdev);
703 dssdev->activate_after_resume = false;
704 }
705 }
706
707 return 0;
708}
709
ccd7b5ed
TV
710static int omap_drm_suspend(struct device *dev)
711{
a82f0347
LP
712 struct omap_drm_private *priv = dev_get_drvdata(dev);
713 struct drm_device *drm_dev = priv->ddev;
ccd7b5ed
TV
714
715 drm_kms_helper_poll_disable(drm_dev);
716
92bf0f9e
TV
717 drm_modeset_lock_all(drm_dev);
718 omap_drm_suspend_all_displays();
719 drm_modeset_unlock_all(drm_dev);
720
ccd7b5ed
TV
721 return 0;
722}
723
724static int omap_drm_resume(struct device *dev)
725{
a82f0347
LP
726 struct omap_drm_private *priv = dev_get_drvdata(dev);
727 struct drm_device *drm_dev = priv->ddev;
ccd7b5ed 728
92bf0f9e
TV
729 drm_modeset_lock_all(drm_dev);
730 omap_drm_resume_all_displays();
731 drm_modeset_unlock_all(drm_dev);
732
ccd7b5ed
TV
733 drm_kms_helper_poll_enable(drm_dev);
734
7fb15c48 735 return omap_gem_resume(drm_dev);
ccd7b5ed 736}
e78edba1
AG
737#endif
738
8450c8d0
GS
739static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
740
6717cd29 741static struct platform_driver pdev = {
222025e4 742 .driver = {
f64eafa0 743 .name = "omapdrm",
222025e4 744 .pm = &omapdrm_pm_ops,
222025e4
LP
745 },
746 .probe = pdev_probe,
747 .remove = pdev_remove,
cd5351f4
RC
748};
749
e1c49bdc
TR
750static struct platform_driver * const drivers[] = {
751 &omap_dmm_driver,
752 &pdev,
753};
754
cd5351f4
RC
755static int __init omap_drm_init(void)
756{
757 DBG("init");
ea7e3a66 758
e1c49bdc 759 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
cd5351f4
RC
760}
761
762static void __exit omap_drm_fini(void)
763{
764 DBG("fini");
ea7e3a66 765
e1c49bdc 766 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
cd5351f4
RC
767}
768
769/* need late_initcall() so we load after dss_driver's are loaded */
770late_initcall(omap_drm_init);
771module_exit(omap_drm_fini);
772
773MODULE_AUTHOR("Rob Clark <rob@ti.com>");
774MODULE_DESCRIPTION("OMAP DRM Display Driver");
775MODULE_ALIAS("platform:" DRIVER_NAME);
776MODULE_LICENSE("GPL v2");