]>
Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_drv.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
748471a5 LP |
20 | #include <linux/wait.h> |
21 | ||
22 | #include <drm/drm_atomic.h> | |
cef77d40 | 23 | #include <drm/drm_atomic_helper.h> |
2d278f54 LP |
24 | #include <drm/drm_crtc_helper.h> |
25 | #include <drm/drm_fb_helper.h> | |
cd5351f4 | 26 | |
5c137797 | 27 | #include "omap_dmm_tiler.h" |
2d278f54 | 28 | #include "omap_drv.h" |
cd5351f4 RC |
29 | |
30 | #define DRIVER_NAME MODULE_NAME | |
31 | #define DRIVER_DESC "OMAP DRM" | |
32 | #define DRIVER_DATE "20110917" | |
33 | #define DRIVER_MAJOR 1 | |
34 | #define DRIVER_MINOR 0 | |
35 | #define DRIVER_PATCHLEVEL 0 | |
36 | ||
cd5351f4 RC |
37 | static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS; |
38 | ||
39 | MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs"); | |
40 | module_param(num_crtc, int, 0600); | |
41 | ||
42 | /* | |
43 | * mode config funcs | |
44 | */ | |
45 | ||
46 | /* Notes about mapping DSS and DRM entities: | |
47 | * CRTC: overlay | |
48 | * encoder: manager.. with some extension to allow one primary CRTC | |
49 | * and zero or more video CRTC's to be mapped to one encoder? | |
50 | * connector: dssdev.. manager can be attached/detached from different | |
51 | * devices | |
52 | */ | |
53 | ||
54 | static void omap_fb_output_poll_changed(struct drm_device *dev) | |
55 | { | |
56 | struct omap_drm_private *priv = dev->dev_private; | |
57 | DBG("dev=%p", dev); | |
c7f904b3 | 58 | if (priv->fbdev) |
cd5351f4 | 59 | drm_fb_helper_hotplug_event(priv->fbdev); |
cd5351f4 RC |
60 | } |
61 | ||
748471a5 LP |
62 | struct omap_atomic_state_commit { |
63 | struct work_struct work; | |
64 | struct drm_device *dev; | |
65 | struct drm_atomic_state *state; | |
66 | u32 crtcs; | |
67 | }; | |
68 | ||
5f741b39 TV |
69 | static void omap_atomic_wait_for_completion(struct drm_device *dev, |
70 | struct drm_atomic_state *old_state) | |
71 | { | |
72 | struct drm_crtc_state *old_crtc_state; | |
73 | struct drm_crtc *crtc; | |
74 | unsigned int i; | |
75 | int ret; | |
76 | ||
77 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { | |
78 | if (!crtc->state->enable) | |
79 | continue; | |
80 | ||
81 | ret = omap_crtc_wait_pending(crtc); | |
82 | ||
83 | if (!ret) | |
84 | dev_warn(dev->dev, | |
85 | "atomic complete timeout (pipe %u)!\n", i); | |
86 | } | |
87 | } | |
88 | ||
748471a5 LP |
89 | static void omap_atomic_complete(struct omap_atomic_state_commit *commit) |
90 | { | |
91 | struct drm_device *dev = commit->dev; | |
92 | struct omap_drm_private *priv = dev->dev_private; | |
93 | struct drm_atomic_state *old_state = commit->state; | |
94 | ||
95 | /* Apply the atomic update. */ | |
9f759225 | 96 | priv->dispc_ops->runtime_get(); |
69fb7c85 | 97 | |
748471a5 | 98 | drm_atomic_helper_commit_modeset_disables(dev, old_state); |
897145d0 JS |
99 | |
100 | /* With the current dss dispc implementation we have to enable | |
101 | * the new modeset before we can commit planes. The dispc ovl | |
102 | * configuration relies on the video mode configuration been | |
103 | * written into the HW when the ovl configuration is | |
104 | * calculated. | |
105 | * | |
106 | * This approach is not ideal because after a mode change the | |
107 | * plane update is executed only after the first vblank | |
108 | * interrupt. The dispc implementation should be fixed so that | |
109 | * it is able use uncommitted drm state information. | |
110 | */ | |
748471a5 | 111 | drm_atomic_helper_commit_modeset_enables(dev, old_state); |
897145d0 JS |
112 | omap_atomic_wait_for_completion(dev, old_state); |
113 | ||
114 | drm_atomic_helper_commit_planes(dev, old_state, 0); | |
748471a5 | 115 | |
5f741b39 | 116 | omap_atomic_wait_for_completion(dev, old_state); |
748471a5 LP |
117 | |
118 | drm_atomic_helper_cleanup_planes(dev, old_state); | |
119 | ||
9f759225 | 120 | priv->dispc_ops->runtime_put(); |
69fb7c85 | 121 | |
0853695c | 122 | drm_atomic_state_put(old_state); |
748471a5 LP |
123 | |
124 | /* Complete the commit, wake up any waiter. */ | |
125 | spin_lock(&priv->commit.lock); | |
126 | priv->commit.pending &= ~commit->crtcs; | |
127 | spin_unlock(&priv->commit.lock); | |
128 | ||
129 | wake_up_all(&priv->commit.wait); | |
130 | ||
131 | kfree(commit); | |
132 | } | |
133 | ||
134 | static void omap_atomic_work(struct work_struct *work) | |
135 | { | |
136 | struct omap_atomic_state_commit *commit = | |
137 | container_of(work, struct omap_atomic_state_commit, work); | |
138 | ||
139 | omap_atomic_complete(commit); | |
140 | } | |
141 | ||
142 | static bool omap_atomic_is_pending(struct omap_drm_private *priv, | |
143 | struct omap_atomic_state_commit *commit) | |
144 | { | |
145 | bool pending; | |
146 | ||
147 | spin_lock(&priv->commit.lock); | |
148 | pending = priv->commit.pending & commit->crtcs; | |
149 | spin_unlock(&priv->commit.lock); | |
150 | ||
151 | return pending; | |
152 | } | |
153 | ||
154 | static int omap_atomic_commit(struct drm_device *dev, | |
6fc17fb2 | 155 | struct drm_atomic_state *state, bool nonblock) |
748471a5 LP |
156 | { |
157 | struct omap_drm_private *priv = dev->dev_private; | |
158 | struct omap_atomic_state_commit *commit; | |
82072573 DV |
159 | struct drm_crtc *crtc; |
160 | struct drm_crtc_state *crtc_state; | |
161 | int i, ret; | |
748471a5 LP |
162 | |
163 | ret = drm_atomic_helper_prepare_planes(dev, state); | |
164 | if (ret) | |
165 | return ret; | |
166 | ||
167 | /* Allocate the commit object. */ | |
168 | commit = kzalloc(sizeof(*commit), GFP_KERNEL); | |
169 | if (commit == NULL) { | |
170 | ret = -ENOMEM; | |
171 | goto error; | |
172 | } | |
173 | ||
174 | INIT_WORK(&commit->work, omap_atomic_work); | |
175 | commit->dev = dev; | |
176 | commit->state = state; | |
177 | ||
178 | /* Wait until all affected CRTCs have completed previous commits and | |
179 | * mark them as pending. | |
180 | */ | |
82072573 DV |
181 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
182 | commit->crtcs |= drm_crtc_mask(crtc); | |
748471a5 LP |
183 | |
184 | wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit)); | |
185 | ||
186 | spin_lock(&priv->commit.lock); | |
187 | priv->commit.pending |= commit->crtcs; | |
188 | spin_unlock(&priv->commit.lock); | |
189 | ||
190 | /* Swap the state, this is the point of no return. */ | |
5e84c269 | 191 | drm_atomic_helper_swap_state(state, true); |
748471a5 | 192 | |
0853695c | 193 | drm_atomic_state_get(state); |
6fc17fb2 | 194 | if (nonblock) |
748471a5 LP |
195 | schedule_work(&commit->work); |
196 | else | |
197 | omap_atomic_complete(commit); | |
198 | ||
199 | return 0; | |
200 | ||
201 | error: | |
202 | drm_atomic_helper_cleanup_planes(dev, state); | |
203 | return ret; | |
204 | } | |
205 | ||
e6ecefaa | 206 | static const struct drm_mode_config_funcs omap_mode_config_funcs = { |
cd5351f4 RC |
207 | .fb_create = omap_framebuffer_create, |
208 | .output_poll_changed = omap_fb_output_poll_changed, | |
cef77d40 | 209 | .atomic_check = drm_atomic_helper_check, |
748471a5 | 210 | .atomic_commit = omap_atomic_commit, |
cd5351f4 RC |
211 | }; |
212 | ||
213 | static int get_connector_type(struct omap_dss_device *dssdev) | |
214 | { | |
215 | switch (dssdev->type) { | |
216 | case OMAP_DISPLAY_TYPE_HDMI: | |
217 | return DRM_MODE_CONNECTOR_HDMIA; | |
4635c17d TV |
218 | case OMAP_DISPLAY_TYPE_DVI: |
219 | return DRM_MODE_CONNECTOR_DVID; | |
4a64b908 SR |
220 | case OMAP_DISPLAY_TYPE_DSI: |
221 | return DRM_MODE_CONNECTOR_DSI; | |
cd5351f4 RC |
222 | default: |
223 | return DRM_MODE_CONNECTOR_Unknown; | |
224 | } | |
225 | } | |
226 | ||
0d8f371f AT |
227 | static bool channel_used(struct drm_device *dev, enum omap_channel channel) |
228 | { | |
229 | struct omap_drm_private *priv = dev->dev_private; | |
230 | int i; | |
231 | ||
232 | for (i = 0; i < priv->num_crtcs; i++) { | |
233 | struct drm_crtc *crtc = priv->crtcs[i]; | |
234 | ||
235 | if (omap_crtc_channel(crtc) == channel) | |
236 | return true; | |
237 | } | |
238 | ||
239 | return false; | |
240 | } | |
cc823bdc AT |
241 | static void omap_disconnect_dssdevs(void) |
242 | { | |
243 | struct omap_dss_device *dssdev = NULL; | |
244 | ||
245 | for_each_dss_dev(dssdev) | |
246 | dssdev->driver->disconnect(dssdev); | |
247 | } | |
0d8f371f | 248 | |
3a01ab25 AT |
249 | static int omap_connect_dssdevs(void) |
250 | { | |
251 | int r; | |
252 | struct omap_dss_device *dssdev = NULL; | |
a09d2bc1 PU |
253 | |
254 | if (!omapdss_stack_is_ready()) | |
255 | return -EPROBE_DEFER; | |
3a01ab25 AT |
256 | |
257 | for_each_dss_dev(dssdev) { | |
258 | r = dssdev->driver->connect(dssdev); | |
259 | if (r == -EPROBE_DEFER) { | |
260 | omap_dss_put_device(dssdev); | |
261 | goto cleanup; | |
262 | } else if (r) { | |
263 | dev_warn(dssdev->dev, "could not connect display: %s\n", | |
264 | dssdev->name); | |
3a01ab25 AT |
265 | } |
266 | } | |
267 | ||
3a01ab25 AT |
268 | return 0; |
269 | ||
270 | cleanup: | |
271 | /* | |
272 | * if we are deferring probe, we disconnect the devices we previously | |
273 | * connected | |
274 | */ | |
cc823bdc | 275 | omap_disconnect_dssdevs(); |
3a01ab25 AT |
276 | |
277 | return r; | |
278 | } | |
0d8f371f | 279 | |
fb9a35f8 | 280 | static int omap_modeset_create_crtc(struct drm_device *dev, int id, |
e43f2c33 TV |
281 | enum omap_channel channel, |
282 | u32 possible_crtcs) | |
fb9a35f8 LP |
283 | { |
284 | struct omap_drm_private *priv = dev->dev_private; | |
285 | struct drm_plane *plane; | |
286 | struct drm_crtc *crtc; | |
287 | ||
e43f2c33 TV |
288 | plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY, |
289 | possible_crtcs); | |
fb9a35f8 LP |
290 | if (IS_ERR(plane)) |
291 | return PTR_ERR(plane); | |
292 | ||
293 | crtc = omap_crtc_init(dev, plane, channel, id); | |
294 | ||
295 | BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs)); | |
296 | priv->crtcs[id] = crtc; | |
297 | priv->num_crtcs++; | |
298 | ||
299 | priv->planes[id] = plane; | |
300 | priv->num_planes++; | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
e2cd09b2 LP |
305 | static int omap_modeset_init_properties(struct drm_device *dev) |
306 | { | |
307 | struct omap_drm_private *priv = dev->dev_private; | |
308 | ||
e2cd09b2 LP |
309 | priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3); |
310 | if (!priv->zorder_prop) | |
311 | return -ENOMEM; | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
f5f9454c | 316 | static int omap_modeset_init(struct drm_device *dev) |
cd5351f4 RC |
317 | { |
318 | struct omap_drm_private *priv = dev->dev_private; | |
f5f9454c | 319 | struct omap_dss_device *dssdev = NULL; |
9f759225 TV |
320 | int num_ovls = priv->dispc_ops->get_num_ovls(); |
321 | int num_mgrs = priv->dispc_ops->get_num_mgrs(); | |
0d8f371f AT |
322 | int num_crtcs; |
323 | int i, id = 0; | |
fb9a35f8 | 324 | int ret; |
e43f2c33 | 325 | u32 possible_crtcs; |
04b1fc02 | 326 | |
f5f9454c | 327 | drm_mode_config_init(dev); |
cd5351f4 | 328 | |
e2cd09b2 LP |
329 | ret = omap_modeset_init_properties(dev); |
330 | if (ret < 0) | |
331 | return ret; | |
332 | ||
f5f9454c | 333 | /* |
0d8f371f AT |
334 | * We usually don't want to create a CRTC for each manager, at least |
335 | * not until we have a way to expose private planes to userspace. | |
336 | * Otherwise there would not be enough video pipes left for drm planes. | |
337 | * We use the num_crtc argument to limit the number of crtcs we create. | |
f5f9454c | 338 | */ |
0d8f371f | 339 | num_crtcs = min3(num_crtc, num_mgrs, num_ovls); |
e43f2c33 | 340 | possible_crtcs = (1 << num_crtcs) - 1; |
cd5351f4 | 341 | |
0d8f371f | 342 | dssdev = NULL; |
cd5351f4 | 343 | |
f5f9454c RC |
344 | for_each_dss_dev(dssdev) { |
345 | struct drm_connector *connector; | |
346 | struct drm_encoder *encoder; | |
0d8f371f | 347 | enum omap_channel channel; |
179df15f | 348 | struct omap_dss_device *out; |
c7f904b3 | 349 | |
3a01ab25 | 350 | if (!omapdss_device_is_connected(dssdev)) |
581382e3 | 351 | continue; |
a7e71e7f | 352 | |
f5f9454c | 353 | encoder = omap_encoder_init(dev, dssdev); |
cd5351f4 | 354 | |
f5f9454c RC |
355 | if (!encoder) { |
356 | dev_err(dev->dev, "could not create encoder: %s\n", | |
357 | dssdev->name); | |
358 | return -ENOMEM; | |
cd5351f4 RC |
359 | } |
360 | ||
f5f9454c RC |
361 | connector = omap_connector_init(dev, |
362 | get_connector_type(dssdev), dssdev, encoder); | |
cd5351f4 | 363 | |
f5f9454c RC |
364 | if (!connector) { |
365 | dev_err(dev->dev, "could not create connector: %s\n", | |
366 | dssdev->name); | |
367 | return -ENOMEM; | |
cd5351f4 | 368 | } |
bb5c2d9a | 369 | |
f5f9454c RC |
370 | BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders)); |
371 | BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors)); | |
cd5351f4 | 372 | |
f5f9454c RC |
373 | priv->encoders[priv->num_encoders++] = encoder; |
374 | priv->connectors[priv->num_connectors++] = connector; | |
cd5351f4 | 375 | |
f5f9454c | 376 | drm_mode_connector_attach_encoder(connector, encoder); |
cd5351f4 | 377 | |
0d8f371f AT |
378 | /* |
379 | * if we have reached the limit of the crtcs we are allowed to | |
380 | * create, let's not try to look for a crtc for this | |
381 | * panel/encoder and onwards, we will, of course, populate the | |
382 | * the possible_crtcs field for all the encoders with the final | |
383 | * set of crtcs we create | |
384 | */ | |
385 | if (id == num_crtcs) | |
386 | continue; | |
387 | ||
388 | /* | |
389 | * get the recommended DISPC channel for this encoder. For now, | |
390 | * we only try to get create a crtc out of the recommended, the | |
391 | * other possible channels to which the encoder can connect are | |
392 | * not considered. | |
393 | */ | |
0d8f371f | 394 | |
179df15f TV |
395 | out = omapdss_find_output_from_display(dssdev); |
396 | channel = out->dispc_channel; | |
397 | omap_dss_put_device(out); | |
398 | ||
0d8f371f AT |
399 | /* |
400 | * if this channel hasn't already been taken by a previously | |
401 | * allocated crtc, we create a new crtc for it | |
402 | */ | |
403 | if (!channel_used(dev, channel)) { | |
e43f2c33 TV |
404 | ret = omap_modeset_create_crtc(dev, id, channel, |
405 | possible_crtcs); | |
fb9a35f8 LP |
406 | if (ret < 0) { |
407 | dev_err(dev->dev, | |
408 | "could not create CRTC (channel %u)\n", | |
409 | channel); | |
410 | return ret; | |
411 | } | |
0d8f371f AT |
412 | |
413 | id++; | |
414 | } | |
415 | } | |
416 | ||
417 | /* | |
418 | * we have allocated crtcs according to the need of the panels/encoders, | |
419 | * adding more crtcs here if needed | |
420 | */ | |
421 | for (; id < num_crtcs; id++) { | |
422 | ||
423 | /* find a free manager for this crtc */ | |
424 | for (i = 0; i < num_mgrs; i++) { | |
fb9a35f8 | 425 | if (!channel_used(dev, i)) |
0d8f371f | 426 | break; |
0d8f371f AT |
427 | } |
428 | ||
429 | if (i == num_mgrs) { | |
430 | /* this shouldn't really happen */ | |
431 | dev_err(dev->dev, "no managers left for crtc\n"); | |
432 | return -ENOMEM; | |
433 | } | |
fb9a35f8 | 434 | |
e43f2c33 TV |
435 | ret = omap_modeset_create_crtc(dev, id, i, |
436 | possible_crtcs); | |
fb9a35f8 LP |
437 | if (ret < 0) { |
438 | dev_err(dev->dev, | |
439 | "could not create CRTC (channel %u)\n", i); | |
440 | return ret; | |
441 | } | |
0d8f371f AT |
442 | } |
443 | ||
444 | /* | |
445 | * Create normal planes for the remaining overlays: | |
446 | */ | |
447 | for (; id < num_ovls; id++) { | |
fb9a35f8 LP |
448 | struct drm_plane *plane; |
449 | ||
e43f2c33 TV |
450 | plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY, |
451 | possible_crtcs); | |
fb9a35f8 LP |
452 | if (IS_ERR(plane)) |
453 | return PTR_ERR(plane); | |
0d8f371f AT |
454 | |
455 | BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)); | |
456 | priv->planes[priv->num_planes++] = plane; | |
457 | } | |
458 | ||
459 | for (i = 0; i < priv->num_encoders; i++) { | |
460 | struct drm_encoder *encoder = priv->encoders[i]; | |
461 | struct omap_dss_device *dssdev = | |
462 | omap_encoder_get_dssdev(encoder); | |
1f68d9c4 | 463 | struct omap_dss_device *output; |
be8e8e1c TV |
464 | |
465 | output = omapdss_find_output_from_display(dssdev); | |
0d8f371f | 466 | |
f5f9454c RC |
467 | /* figure out which crtc's we can connect the encoder to: */ |
468 | encoder->possible_crtcs = 0; | |
469 | for (id = 0; id < priv->num_crtcs; id++) { | |
0d8f371f AT |
470 | struct drm_crtc *crtc = priv->crtcs[id]; |
471 | enum omap_channel crtc_channel; | |
0d8f371f AT |
472 | |
473 | crtc_channel = omap_crtc_channel(crtc); | |
0d8f371f | 474 | |
17337297 | 475 | if (output->dispc_channel == crtc_channel) { |
f5f9454c | 476 | encoder->possible_crtcs |= (1 << id); |
17337297 TV |
477 | break; |
478 | } | |
bb5c2d9a | 479 | } |
820caabf TV |
480 | |
481 | omap_dss_put_device(output); | |
cd5351f4 RC |
482 | } |
483 | ||
0d8f371f AT |
484 | DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n", |
485 | priv->num_planes, priv->num_crtcs, priv->num_encoders, | |
486 | priv->num_connectors); | |
487 | ||
1e90711d TV |
488 | dev->mode_config.min_width = 8; |
489 | dev->mode_config.min_height = 2; | |
cd5351f4 RC |
490 | |
491 | /* note: eventually will need some cpu_is_omapXYZ() type stuff here | |
492 | * to fill in these limits properly on different OMAP generations.. | |
493 | */ | |
494 | dev->mode_config.max_width = 2048; | |
495 | dev->mode_config.max_height = 2048; | |
496 | ||
497 | dev->mode_config.funcs = &omap_mode_config_funcs; | |
498 | ||
69a12263 LP |
499 | drm_mode_config_reset(dev); |
500 | ||
728ae8dd LP |
501 | omap_drm_irq_install(dev); |
502 | ||
cd5351f4 RC |
503 | return 0; |
504 | } | |
505 | ||
cd5351f4 RC |
506 | /* |
507 | * drm ioctl funcs | |
508 | */ | |
509 | ||
510 | ||
511 | static int ioctl_get_param(struct drm_device *dev, void *data, | |
512 | struct drm_file *file_priv) | |
513 | { | |
5e3b0874 | 514 | struct omap_drm_private *priv = dev->dev_private; |
cd5351f4 RC |
515 | struct drm_omap_param *args = data; |
516 | ||
517 | DBG("%p: param=%llu", dev, args->param); | |
518 | ||
519 | switch (args->param) { | |
520 | case OMAP_PARAM_CHIPSET_ID: | |
5e3b0874 | 521 | args->value = priv->omaprev; |
cd5351f4 RC |
522 | break; |
523 | default: | |
524 | DBG("unknown parameter %lld", args->param); | |
525 | return -EINVAL; | |
526 | } | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
531 | static int ioctl_set_param(struct drm_device *dev, void *data, | |
532 | struct drm_file *file_priv) | |
533 | { | |
534 | struct drm_omap_param *args = data; | |
535 | ||
536 | switch (args->param) { | |
537 | default: | |
538 | DBG("unknown parameter %lld", args->param); | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
ef3f4e99 LP |
545 | #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */ |
546 | ||
cd5351f4 RC |
547 | static int ioctl_gem_new(struct drm_device *dev, void *data, |
548 | struct drm_file *file_priv) | |
549 | { | |
550 | struct drm_omap_gem_new *args = data; | |
ef3f4e99 LP |
551 | u32 flags = args->flags & OMAP_BO_USER_MASK; |
552 | ||
f5f9454c | 553 | VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, |
ef3f4e99 LP |
554 | args->size.bytes, flags); |
555 | ||
556 | return omap_gem_new_handle(dev, file_priv, args->size, flags, | |
557 | &args->handle); | |
cd5351f4 RC |
558 | } |
559 | ||
560 | static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
561 | struct drm_file *file_priv) | |
562 | { | |
563 | struct drm_omap_gem_cpu_prep *args = data; | |
564 | struct drm_gem_object *obj; | |
565 | int ret; | |
566 | ||
567 | VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op); | |
568 | ||
a8ad0bd8 | 569 | obj = drm_gem_object_lookup(file_priv, args->handle); |
c7f904b3 | 570 | if (!obj) |
cd5351f4 | 571 | return -ENOENT; |
cd5351f4 RC |
572 | |
573 | ret = omap_gem_op_sync(obj, args->op); | |
574 | ||
c7f904b3 | 575 | if (!ret) |
cd5351f4 | 576 | ret = omap_gem_op_start(obj, args->op); |
cd5351f4 RC |
577 | |
578 | drm_gem_object_unreference_unlocked(obj); | |
579 | ||
580 | return ret; | |
581 | } | |
582 | ||
583 | static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
584 | struct drm_file *file_priv) | |
585 | { | |
586 | struct drm_omap_gem_cpu_fini *args = data; | |
587 | struct drm_gem_object *obj; | |
588 | int ret; | |
589 | ||
590 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); | |
591 | ||
a8ad0bd8 | 592 | obj = drm_gem_object_lookup(file_priv, args->handle); |
c7f904b3 | 593 | if (!obj) |
cd5351f4 | 594 | return -ENOENT; |
cd5351f4 RC |
595 | |
596 | /* XXX flushy, flushy */ | |
597 | ret = 0; | |
598 | ||
c7f904b3 | 599 | if (!ret) |
cd5351f4 | 600 | ret = omap_gem_op_finish(obj, args->op); |
cd5351f4 RC |
601 | |
602 | drm_gem_object_unreference_unlocked(obj); | |
603 | ||
604 | return ret; | |
605 | } | |
606 | ||
607 | static int ioctl_gem_info(struct drm_device *dev, void *data, | |
608 | struct drm_file *file_priv) | |
609 | { | |
610 | struct drm_omap_gem_info *args = data; | |
611 | struct drm_gem_object *obj; | |
612 | int ret = 0; | |
613 | ||
f5f9454c | 614 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); |
cd5351f4 | 615 | |
a8ad0bd8 | 616 | obj = drm_gem_object_lookup(file_priv, args->handle); |
c7f904b3 | 617 | if (!obj) |
cd5351f4 | 618 | return -ENOENT; |
cd5351f4 | 619 | |
f7f9f453 | 620 | args->size = omap_gem_mmap_size(obj); |
cd5351f4 RC |
621 | args->offset = omap_gem_mmap_offset(obj); |
622 | ||
623 | drm_gem_object_unreference_unlocked(obj); | |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
baa70943 | 628 | static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { |
5f6ab8ca HH |
629 | DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, |
630 | DRM_AUTH | DRM_RENDER_ALLOW), | |
631 | DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, | |
632 | DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY), | |
633 | DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, | |
634 | DRM_AUTH | DRM_RENDER_ALLOW), | |
635 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, | |
636 | DRM_AUTH | DRM_RENDER_ALLOW), | |
637 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, | |
638 | DRM_AUTH | DRM_RENDER_ALLOW), | |
639 | DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, | |
640 | DRM_AUTH | DRM_RENDER_ALLOW), | |
cd5351f4 RC |
641 | }; |
642 | ||
643 | /* | |
644 | * drm driver funcs | |
645 | */ | |
646 | ||
cd5351f4 RC |
647 | static int dev_open(struct drm_device *dev, struct drm_file *file) |
648 | { | |
649 | file->driver_priv = NULL; | |
650 | ||
651 | DBG("open: dev=%p, file=%p", dev, file); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
cd5351f4 RC |
656 | /** |
657 | * lastclose - clean up after all DRM clients have exited | |
658 | * @dev: DRM device | |
659 | * | |
660 | * Take care of cleaning up after all DRM clients have exited. In the | |
661 | * mode setting case, we want to restore the kernel's initial mode (just | |
662 | * in case the last client left us in a bad state). | |
663 | */ | |
664 | static void dev_lastclose(struct drm_device *dev) | |
665 | { | |
3c810c61 RC |
666 | int i; |
667 | ||
f15a66e6 | 668 | /* we don't support vga_switcheroo.. so just make sure the fbdev |
cd5351f4 RC |
669 | * mode is active |
670 | */ | |
671 | struct omap_drm_private *priv = dev->dev_private; | |
672 | int ret; | |
673 | ||
674 | DBG("lastclose: dev=%p", dev); | |
675 | ||
0da88db1 VS |
676 | /* need to restore default rotation state.. not sure |
677 | * if there is a cleaner way to restore properties to | |
678 | * default state? Maybe a flag that properties should | |
679 | * automatically be restored to default state on | |
680 | * lastclose? | |
681 | */ | |
682 | for (i = 0; i < priv->num_crtcs; i++) { | |
683 | struct drm_crtc *crtc = priv->crtcs[i]; | |
3c810c61 | 684 | |
0da88db1 VS |
685 | if (!crtc->primary->rotation_property) |
686 | continue; | |
687 | ||
688 | drm_object_property_set_value(&crtc->base, | |
689 | crtc->primary->rotation_property, | |
690 | DRM_ROTATE_0); | |
691 | } | |
692 | ||
693 | for (i = 0; i < priv->num_planes; i++) { | |
694 | struct drm_plane *plane = priv->planes[i]; | |
695 | ||
696 | if (!plane->rotation_property) | |
697 | continue; | |
698 | ||
699 | drm_object_property_set_value(&plane->base, | |
700 | plane->rotation_property, | |
701 | DRM_ROTATE_0); | |
3c810c61 RC |
702 | } |
703 | ||
c7c1aecd TV |
704 | if (priv->fbdev) { |
705 | ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
706 | if (ret) | |
707 | DBG("failed to restore crtc mode"); | |
708 | } | |
cd5351f4 RC |
709 | } |
710 | ||
78b68556 | 711 | static const struct vm_operations_struct omap_gem_vm_ops = { |
cd5351f4 RC |
712 | .fault = omap_gem_fault, |
713 | .open = drm_gem_vm_open, | |
714 | .close = drm_gem_vm_close, | |
715 | }; | |
716 | ||
ff4f3876 | 717 | static const struct file_operations omapdriver_fops = { |
222025e4 LP |
718 | .owner = THIS_MODULE, |
719 | .open = drm_open, | |
720 | .unlocked_ioctl = drm_ioctl, | |
721 | .release = drm_release, | |
722 | .mmap = omap_gem_mmap, | |
723 | .poll = drm_poll, | |
724 | .read = drm_read, | |
725 | .llseek = noop_llseek, | |
ff4f3876 RC |
726 | }; |
727 | ||
cd5351f4 | 728 | static struct drm_driver omap_drm_driver = { |
728fea77 | 729 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
5f6ab8ca | 730 | DRIVER_ATOMIC | DRIVER_RENDER, |
222025e4 LP |
731 | .open = dev_open, |
732 | .lastclose = dev_lastclose, | |
6169a148 | 733 | #ifdef CONFIG_DEBUG_FS |
222025e4 | 734 | .debugfs_init = omap_debugfs_init, |
6169a148 | 735 | #endif |
222025e4 LP |
736 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
737 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
738 | .gem_prime_export = omap_gem_prime_export, | |
739 | .gem_prime_import = omap_gem_prime_import, | |
740 | .gem_free_object = omap_gem_free_object, | |
741 | .gem_vm_ops = &omap_gem_vm_ops, | |
742 | .dumb_create = omap_gem_dumb_create, | |
743 | .dumb_map_offset = omap_gem_dumb_map_offset, | |
744 | .dumb_destroy = drm_gem_dumb_destroy, | |
745 | .ioctls = ioctls, | |
746 | .num_ioctls = DRM_OMAP_NUM_IOCTLS, | |
747 | .fops = &omapdriver_fops, | |
748 | .name = DRIVER_NAME, | |
749 | .desc = DRIVER_DESC, | |
750 | .date = DRIVER_DATE, | |
751 | .major = DRIVER_MAJOR, | |
752 | .minor = DRIVER_MINOR, | |
753 | .patchlevel = DRIVER_PATCHLEVEL, | |
cd5351f4 RC |
754 | }; |
755 | ||
2f95bc6d | 756 | static int pdev_probe(struct platform_device *pdev) |
cd5351f4 | 757 | { |
2f95bc6d LP |
758 | struct omap_drm_platform_data *pdata = pdev->dev.platform_data; |
759 | struct omap_drm_private *priv; | |
760 | struct drm_device *ddev; | |
761 | unsigned int i; | |
762 | int ret; | |
763 | ||
764 | DBG("%s", pdev->name); | |
3a01ab25 | 765 | |
591a0ac7 TV |
766 | if (omapdss_is_initialized() == false) |
767 | return -EPROBE_DEFER; | |
768 | ||
3a01ab25 AT |
769 | omap_crtc_pre_init(); |
770 | ||
2f95bc6d LP |
771 | ret = omap_connect_dssdevs(); |
772 | if (ret) | |
773 | goto err_crtc_uninit; | |
774 | ||
775 | /* Allocate and initialize the driver private structure. */ | |
776 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
777 | if (!priv) { | |
778 | ret = -ENOMEM; | |
779 | goto err_disconnect_dssdevs; | |
780 | } | |
781 | ||
9f759225 TV |
782 | priv->dispc_ops = dispc_get_ops(); |
783 | ||
2f95bc6d LP |
784 | priv->omaprev = pdata->omaprev; |
785 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); | |
786 | ||
787 | init_waitqueue_head(&priv->commit.wait); | |
788 | spin_lock_init(&priv->commit.lock); | |
789 | spin_lock_init(&priv->list_lock); | |
790 | INIT_LIST_HEAD(&priv->obj_list); | |
791 | ||
792 | /* Allocate and initialize the DRM device. */ | |
793 | ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev); | |
794 | if (IS_ERR(ddev)) { | |
795 | ret = PTR_ERR(ddev); | |
796 | goto err_free_priv; | |
797 | } | |
798 | ||
799 | ddev->dev_private = priv; | |
800 | platform_set_drvdata(pdev, ddev); | |
801 | ||
802 | omap_gem_init(ddev); | |
803 | ||
804 | ret = omap_modeset_init(ddev); | |
805 | if (ret) { | |
806 | dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret); | |
807 | goto err_free_drm_dev; | |
808 | } | |
809 | ||
810 | /* Initialize vblank handling, start with all CRTCs disabled. */ | |
811 | ret = drm_vblank_init(ddev, priv->num_crtcs); | |
812 | if (ret) { | |
813 | dev_err(&pdev->dev, "could not init vblank\n"); | |
814 | goto err_cleanup_modeset; | |
3a01ab25 AT |
815 | } |
816 | ||
2f95bc6d LP |
817 | for (i = 0; i < priv->num_crtcs; i++) |
818 | drm_crtc_vblank_off(priv->crtcs[i]); | |
819 | ||
820 | priv->fbdev = omap_fbdev_init(ddev); | |
821 | ||
822 | drm_kms_helper_poll_init(ddev); | |
823 | ||
824 | /* | |
825 | * Register the DRM device with the core and the connectors with | |
826 | * sysfs. | |
827 | */ | |
828 | ret = drm_dev_register(ddev, 0); | |
829 | if (ret) | |
830 | goto err_cleanup_helpers; | |
831 | ||
832 | return 0; | |
833 | ||
834 | err_cleanup_helpers: | |
835 | drm_kms_helper_poll_fini(ddev); | |
836 | if (priv->fbdev) | |
837 | omap_fbdev_free(ddev); | |
838 | err_cleanup_modeset: | |
839 | drm_mode_config_cleanup(ddev); | |
840 | omap_drm_irq_uninstall(ddev); | |
841 | err_free_drm_dev: | |
842 | omap_gem_deinit(ddev); | |
843 | drm_dev_unref(ddev); | |
844 | err_free_priv: | |
845 | destroy_workqueue(priv->wq); | |
846 | kfree(priv); | |
847 | err_disconnect_dssdevs: | |
848 | omap_disconnect_dssdevs(); | |
849 | err_crtc_uninit: | |
850 | omap_crtc_pre_uninit(); | |
851 | return ret; | |
cd5351f4 RC |
852 | } |
853 | ||
2f95bc6d | 854 | static int pdev_remove(struct platform_device *pdev) |
cd5351f4 | 855 | { |
2f95bc6d LP |
856 | struct drm_device *ddev = platform_get_drvdata(pdev); |
857 | struct omap_drm_private *priv = ddev->dev_private; | |
858 | ||
cd5351f4 | 859 | DBG(""); |
5c137797 | 860 | |
2f95bc6d LP |
861 | drm_dev_unregister(ddev); |
862 | ||
863 | drm_kms_helper_poll_fini(ddev); | |
864 | ||
865 | if (priv->fbdev) | |
866 | omap_fbdev_free(ddev); | |
867 | ||
8a54aa92 TV |
868 | drm_atomic_helper_shutdown(ddev); |
869 | ||
2f95bc6d LP |
870 | drm_mode_config_cleanup(ddev); |
871 | ||
872 | omap_drm_irq_uninstall(ddev); | |
873 | omap_gem_deinit(ddev); | |
874 | ||
875 | drm_dev_unref(ddev); | |
876 | ||
877 | destroy_workqueue(priv->wq); | |
878 | kfree(priv); | |
707cf58a | 879 | |
cc823bdc AT |
880 | omap_disconnect_dssdevs(); |
881 | omap_crtc_pre_uninit(); | |
fd3c0253 | 882 | |
cd5351f4 RC |
883 | return 0; |
884 | } | |
885 | ||
8450c8d0 | 886 | #ifdef CONFIG_PM_SLEEP |
92bf0f9e TV |
887 | static int omap_drm_suspend_all_displays(void) |
888 | { | |
889 | struct omap_dss_device *dssdev = NULL; | |
890 | ||
891 | for_each_dss_dev(dssdev) { | |
892 | if (!dssdev->driver) | |
893 | continue; | |
894 | ||
895 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
896 | dssdev->driver->disable(dssdev); | |
897 | dssdev->activate_after_resume = true; | |
898 | } else { | |
899 | dssdev->activate_after_resume = false; | |
900 | } | |
901 | } | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | static int omap_drm_resume_all_displays(void) | |
907 | { | |
908 | struct omap_dss_device *dssdev = NULL; | |
909 | ||
910 | for_each_dss_dev(dssdev) { | |
911 | if (!dssdev->driver) | |
912 | continue; | |
913 | ||
914 | if (dssdev->activate_after_resume) { | |
915 | dssdev->driver->enable(dssdev); | |
916 | dssdev->activate_after_resume = false; | |
917 | } | |
918 | } | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
ccd7b5ed TV |
923 | static int omap_drm_suspend(struct device *dev) |
924 | { | |
925 | struct drm_device *drm_dev = dev_get_drvdata(dev); | |
926 | ||
927 | drm_kms_helper_poll_disable(drm_dev); | |
928 | ||
92bf0f9e TV |
929 | drm_modeset_lock_all(drm_dev); |
930 | omap_drm_suspend_all_displays(); | |
931 | drm_modeset_unlock_all(drm_dev); | |
932 | ||
ccd7b5ed TV |
933 | return 0; |
934 | } | |
935 | ||
936 | static int omap_drm_resume(struct device *dev) | |
937 | { | |
938 | struct drm_device *drm_dev = dev_get_drvdata(dev); | |
939 | ||
92bf0f9e TV |
940 | drm_modeset_lock_all(drm_dev); |
941 | omap_drm_resume_all_displays(); | |
942 | drm_modeset_unlock_all(drm_dev); | |
943 | ||
ccd7b5ed TV |
944 | drm_kms_helper_poll_enable(drm_dev); |
945 | ||
946 | return omap_gem_resume(dev); | |
947 | } | |
e78edba1 AG |
948 | #endif |
949 | ||
8450c8d0 GS |
950 | static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume); |
951 | ||
6717cd29 | 952 | static struct platform_driver pdev = { |
222025e4 LP |
953 | .driver = { |
954 | .name = DRIVER_NAME, | |
222025e4 | 955 | .pm = &omapdrm_pm_ops, |
222025e4 LP |
956 | }, |
957 | .probe = pdev_probe, | |
958 | .remove = pdev_remove, | |
cd5351f4 RC |
959 | }; |
960 | ||
e1c49bdc TR |
961 | static struct platform_driver * const drivers[] = { |
962 | &omap_dmm_driver, | |
963 | &pdev, | |
964 | }; | |
965 | ||
cd5351f4 RC |
966 | static int __init omap_drm_init(void) |
967 | { | |
968 | DBG("init"); | |
ea7e3a66 | 969 | |
e1c49bdc | 970 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
cd5351f4 RC |
971 | } |
972 | ||
973 | static void __exit omap_drm_fini(void) | |
974 | { | |
975 | DBG("fini"); | |
ea7e3a66 | 976 | |
e1c49bdc | 977 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
cd5351f4 RC |
978 | } |
979 | ||
980 | /* need late_initcall() so we load after dss_driver's are loaded */ | |
981 | late_initcall(omap_drm_init); | |
982 | module_exit(omap_drm_fini); | |
983 | ||
984 | MODULE_AUTHOR("Rob Clark <rob@ti.com>"); | |
985 | MODULE_DESCRIPTION("OMAP DRM Display Driver"); | |
986 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
987 | MODULE_LICENSE("GPL v2"); |