]>
Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
bb5cdf8d | 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
cd5351f4 RC |
3 | * Author: Rob Clark <rob@ti.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
6e471fab LP |
18 | #include <linux/sys_soc.h> |
19 | ||
748471a5 | 20 | #include <drm/drm_atomic.h> |
cef77d40 | 21 | #include <drm/drm_atomic_helper.h> |
2d278f54 LP |
22 | #include <drm/drm_crtc_helper.h> |
23 | #include <drm/drm_fb_helper.h> | |
cd5351f4 | 24 | |
5c137797 | 25 | #include "omap_dmm_tiler.h" |
2d278f54 | 26 | #include "omap_drv.h" |
cd5351f4 RC |
27 | |
28 | #define DRIVER_NAME MODULE_NAME | |
29 | #define DRIVER_DESC "OMAP DRM" | |
30 | #define DRIVER_DATE "20110917" | |
31 | #define DRIVER_MAJOR 1 | |
32 | #define DRIVER_MINOR 0 | |
33 | #define DRIVER_PATCHLEVEL 0 | |
34 | ||
cd5351f4 RC |
35 | /* |
36 | * mode config funcs | |
37 | */ | |
38 | ||
39 | /* Notes about mapping DSS and DRM entities: | |
40 | * CRTC: overlay | |
41 | * encoder: manager.. with some extension to allow one primary CRTC | |
42 | * and zero or more video CRTC's to be mapped to one encoder? | |
43 | * connector: dssdev.. manager can be attached/detached from different | |
44 | * devices | |
45 | */ | |
46 | ||
5f741b39 TV |
47 | static void omap_atomic_wait_for_completion(struct drm_device *dev, |
48 | struct drm_atomic_state *old_state) | |
49 | { | |
34d88237 | 50 | struct drm_crtc_state *new_crtc_state; |
5f741b39 TV |
51 | struct drm_crtc *crtc; |
52 | unsigned int i; | |
53 | int ret; | |
54 | ||
34d88237 ML |
55 | for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) { |
56 | if (!new_crtc_state->active) | |
5f741b39 TV |
57 | continue; |
58 | ||
59 | ret = omap_crtc_wait_pending(crtc); | |
60 | ||
61 | if (!ret) | |
62 | dev_warn(dev->dev, | |
63 | "atomic complete timeout (pipe %u)!\n", i); | |
64 | } | |
65 | } | |
66 | ||
a9e6f9f7 | 67 | static void omap_atomic_commit_tail(struct drm_atomic_state *old_state) |
748471a5 | 68 | { |
a9e6f9f7 | 69 | struct drm_device *dev = old_state->dev; |
748471a5 | 70 | struct omap_drm_private *priv = dev->dev_private; |
748471a5 | 71 | |
50638ae5 | 72 | priv->dispc_ops->runtime_get(priv->dispc); |
69fb7c85 | 73 | |
a9e6f9f7 | 74 | /* Apply the atomic update. */ |
748471a5 | 75 | drm_atomic_helper_commit_modeset_disables(dev, old_state); |
897145d0 | 76 | |
fc5cc967 TV |
77 | if (priv->omaprev != 0x3430) { |
78 | /* With the current dss dispc implementation we have to enable | |
79 | * the new modeset before we can commit planes. The dispc ovl | |
80 | * configuration relies on the video mode configuration been | |
81 | * written into the HW when the ovl configuration is | |
82 | * calculated. | |
83 | * | |
84 | * This approach is not ideal because after a mode change the | |
85 | * plane update is executed only after the first vblank | |
86 | * interrupt. The dispc implementation should be fixed so that | |
87 | * it is able use uncommitted drm state information. | |
88 | */ | |
89 | drm_atomic_helper_commit_modeset_enables(dev, old_state); | |
90 | omap_atomic_wait_for_completion(dev, old_state); | |
91 | ||
92 | drm_atomic_helper_commit_planes(dev, old_state, 0); | |
93 | ||
94 | drm_atomic_helper_commit_hw_done(old_state); | |
95 | } else { | |
96 | /* | |
97 | * OMAP3 DSS seems to have issues with the work-around above, | |
98 | * resulting in endless sync losts if a crtc is enabled without | |
99 | * a plane. For now, skip the WA for OMAP3. | |
100 | */ | |
101 | drm_atomic_helper_commit_planes(dev, old_state, 0); | |
102 | ||
103 | drm_atomic_helper_commit_modeset_enables(dev, old_state); | |
104 | ||
105 | drm_atomic_helper_commit_hw_done(old_state); | |
106 | } | |
a9e6f9f7 LP |
107 | |
108 | /* | |
109 | * Wait for completion of the page flips to ensure that old buffers | |
110 | * can't be touched by the hardware anymore before cleaning up planes. | |
111 | */ | |
5f741b39 | 112 | omap_atomic_wait_for_completion(dev, old_state); |
748471a5 LP |
113 | |
114 | drm_atomic_helper_cleanup_planes(dev, old_state); | |
115 | ||
50638ae5 | 116 | priv->dispc_ops->runtime_put(priv->dispc); |
748471a5 LP |
117 | } |
118 | ||
a9e6f9f7 LP |
119 | static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = { |
120 | .atomic_commit_tail = omap_atomic_commit_tail, | |
121 | }; | |
748471a5 | 122 | |
e6ecefaa | 123 | static const struct drm_mode_config_funcs omap_mode_config_funcs = { |
cd5351f4 | 124 | .fb_create = omap_framebuffer_create, |
ef62d308 | 125 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
cef77d40 | 126 | .atomic_check = drm_atomic_helper_check, |
a9e6f9f7 | 127 | .atomic_commit = drm_atomic_helper_commit, |
cd5351f4 RC |
128 | }; |
129 | ||
130 | static int get_connector_type(struct omap_dss_device *dssdev) | |
131 | { | |
132 | switch (dssdev->type) { | |
133 | case OMAP_DISPLAY_TYPE_HDMI: | |
134 | return DRM_MODE_CONNECTOR_HDMIA; | |
4635c17d TV |
135 | case OMAP_DISPLAY_TYPE_DVI: |
136 | return DRM_MODE_CONNECTOR_DVID; | |
4a64b908 SR |
137 | case OMAP_DISPLAY_TYPE_DSI: |
138 | return DRM_MODE_CONNECTOR_DSI; | |
564f88c1 TV |
139 | case OMAP_DISPLAY_TYPE_DPI: |
140 | case OMAP_DISPLAY_TYPE_DBI: | |
141 | return DRM_MODE_CONNECTOR_DPI; | |
142 | case OMAP_DISPLAY_TYPE_VENC: | |
143 | /* TODO: This could also be composite */ | |
144 | return DRM_MODE_CONNECTOR_SVIDEO; | |
145 | case OMAP_DISPLAY_TYPE_SDI: | |
146 | return DRM_MODE_CONNECTOR_LVDS; | |
cd5351f4 RC |
147 | default: |
148 | return DRM_MODE_CONNECTOR_Unknown; | |
149 | } | |
150 | } | |
151 | ||
cc823bdc AT |
152 | static void omap_disconnect_dssdevs(void) |
153 | { | |
154 | struct omap_dss_device *dssdev = NULL; | |
155 | ||
156 | for_each_dss_dev(dssdev) | |
157 | dssdev->driver->disconnect(dssdev); | |
158 | } | |
0d8f371f | 159 | |
3a01ab25 AT |
160 | static int omap_connect_dssdevs(void) |
161 | { | |
162 | int r; | |
163 | struct omap_dss_device *dssdev = NULL; | |
a09d2bc1 PU |
164 | |
165 | if (!omapdss_stack_is_ready()) | |
166 | return -EPROBE_DEFER; | |
3a01ab25 AT |
167 | |
168 | for_each_dss_dev(dssdev) { | |
169 | r = dssdev->driver->connect(dssdev); | |
170 | if (r == -EPROBE_DEFER) { | |
171 | omap_dss_put_device(dssdev); | |
172 | goto cleanup; | |
173 | } else if (r) { | |
174 | dev_warn(dssdev->dev, "could not connect display: %s\n", | |
175 | dssdev->name); | |
3a01ab25 AT |
176 | } |
177 | } | |
178 | ||
3a01ab25 AT |
179 | return 0; |
180 | ||
181 | cleanup: | |
182 | /* | |
183 | * if we are deferring probe, we disconnect the devices we previously | |
184 | * connected | |
185 | */ | |
cc823bdc | 186 | omap_disconnect_dssdevs(); |
3a01ab25 AT |
187 | |
188 | return r; | |
189 | } | |
0d8f371f | 190 | |
e2cd09b2 LP |
191 | static int omap_modeset_init_properties(struct drm_device *dev) |
192 | { | |
193 | struct omap_drm_private *priv = dev->dev_private; | |
50638ae5 | 194 | unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); |
e2cd09b2 | 195 | |
dff6c246 LP |
196 | priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, |
197 | num_planes - 1); | |
e2cd09b2 LP |
198 | if (!priv->zorder_prop) |
199 | return -ENOMEM; | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
f5f9454c | 204 | static int omap_modeset_init(struct drm_device *dev) |
cd5351f4 RC |
205 | { |
206 | struct omap_drm_private *priv = dev->dev_private; | |
f5f9454c | 207 | struct omap_dss_device *dssdev = NULL; |
50638ae5 LP |
208 | int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc); |
209 | int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); | |
e8e13b15 | 210 | int num_crtcs, crtc_idx, plane_idx; |
fb9a35f8 | 211 | int ret; |
e8e13b15 | 212 | u32 plane_crtc_mask; |
04b1fc02 | 213 | |
f5f9454c | 214 | drm_mode_config_init(dev); |
cd5351f4 | 215 | |
e2cd09b2 LP |
216 | ret = omap_modeset_init_properties(dev); |
217 | if (ret < 0) | |
218 | return ret; | |
219 | ||
f5f9454c | 220 | /* |
e8e13b15 JS |
221 | * This function creates exactly one connector, encoder, crtc, |
222 | * and primary plane per each connected dss-device. Each | |
223 | * connector->encoder->crtc chain is expected to be separate | |
224 | * and each crtc is connect to a single dss-channel. If the | |
225 | * configuration does not match the expectations or exceeds | |
226 | * the available resources, the configuration is rejected. | |
f5f9454c | 227 | */ |
e8e13b15 | 228 | num_crtcs = 0; |
f1118b89 JS |
229 | for_each_dss_dev(dssdev) |
230 | if (omapdss_device_is_connected(dssdev)) | |
231 | num_crtcs++; | |
232 | ||
e8e13b15 JS |
233 | if (num_crtcs > num_mgrs || num_crtcs > num_ovls || |
234 | num_crtcs > ARRAY_SIZE(priv->crtcs) || | |
235 | num_crtcs > ARRAY_SIZE(priv->planes) || | |
236 | num_crtcs > ARRAY_SIZE(priv->encoders) || | |
237 | num_crtcs > ARRAY_SIZE(priv->connectors)) { | |
238 | dev_err(dev->dev, "%s(): Too many connected displays\n", | |
239 | __func__); | |
240 | return -EINVAL; | |
241 | } | |
242 | ||
243 | /* All planes can be put to any CRTC */ | |
244 | plane_crtc_mask = (1 << num_crtcs) - 1; | |
cd5351f4 | 245 | |
0d8f371f | 246 | dssdev = NULL; |
cd5351f4 | 247 | |
e8e13b15 JS |
248 | crtc_idx = 0; |
249 | plane_idx = 0; | |
f5f9454c RC |
250 | for_each_dss_dev(dssdev) { |
251 | struct drm_connector *connector; | |
252 | struct drm_encoder *encoder; | |
e8e13b15 JS |
253 | struct drm_plane *plane; |
254 | struct drm_crtc *crtc; | |
c7f904b3 | 255 | |
3a01ab25 | 256 | if (!omapdss_device_is_connected(dssdev)) |
581382e3 | 257 | continue; |
a7e71e7f | 258 | |
f5f9454c | 259 | encoder = omap_encoder_init(dev, dssdev); |
e8e13b15 | 260 | if (!encoder) |
f5f9454c | 261 | return -ENOMEM; |
cd5351f4 | 262 | |
f5f9454c RC |
263 | connector = omap_connector_init(dev, |
264 | get_connector_type(dssdev), dssdev, encoder); | |
e8e13b15 | 265 | if (!connector) |
f5f9454c | 266 | return -ENOMEM; |
bb5c2d9a | 267 | |
e8e13b15 JS |
268 | plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY, |
269 | plane_crtc_mask); | |
270 | if (IS_ERR(plane)) | |
271 | return PTR_ERR(plane); | |
cd5351f4 | 272 | |
e8e13b15 JS |
273 | crtc = omap_crtc_init(dev, plane, dssdev); |
274 | if (IS_ERR(crtc)) | |
275 | return PTR_ERR(crtc); | |
cd5351f4 | 276 | |
cde4c44d | 277 | drm_connector_attach_encoder(connector, encoder); |
e8e13b15 | 278 | encoder->possible_crtcs = (1 << crtc_idx); |
cd5351f4 | 279 | |
e8e13b15 JS |
280 | priv->crtcs[priv->num_crtcs++] = crtc; |
281 | priv->planes[priv->num_planes++] = plane; | |
282 | priv->encoders[priv->num_encoders++] = encoder; | |
283 | priv->connectors[priv->num_connectors++] = connector; | |
0d8f371f | 284 | |
e8e13b15 JS |
285 | plane_idx++; |
286 | crtc_idx++; | |
0d8f371f AT |
287 | } |
288 | ||
0d8f371f AT |
289 | /* |
290 | * Create normal planes for the remaining overlays: | |
291 | */ | |
e8e13b15 | 292 | for (; plane_idx < num_ovls; plane_idx++) { |
fb9a35f8 LP |
293 | struct drm_plane *plane; |
294 | ||
e8e13b15 JS |
295 | if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes))) |
296 | return -EINVAL; | |
297 | ||
298 | plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY, | |
299 | plane_crtc_mask); | |
fb9a35f8 LP |
300 | if (IS_ERR(plane)) |
301 | return PTR_ERR(plane); | |
0d8f371f | 302 | |
0d8f371f AT |
303 | priv->planes[priv->num_planes++] = plane; |
304 | } | |
305 | ||
0d8f371f AT |
306 | DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n", |
307 | priv->num_planes, priv->num_crtcs, priv->num_encoders, | |
308 | priv->num_connectors); | |
309 | ||
1e90711d TV |
310 | dev->mode_config.min_width = 8; |
311 | dev->mode_config.min_height = 2; | |
cd5351f4 | 312 | |
1915d7fa TV |
313 | /* |
314 | * Note: these values are used for multiple independent things: | |
315 | * connector mode filtering, buffer sizes, crtc sizes... | |
316 | * Use big enough values here to cover all use cases, and do more | |
317 | * specific checking in the respective code paths. | |
cd5351f4 | 318 | */ |
1915d7fa TV |
319 | dev->mode_config.max_width = 8192; |
320 | dev->mode_config.max_height = 8192; | |
cd5351f4 | 321 | |
23936ba9 PU |
322 | /* We want the zpos to be normalized */ |
323 | dev->mode_config.normalize_zpos = true; | |
324 | ||
cd5351f4 | 325 | dev->mode_config.funcs = &omap_mode_config_funcs; |
a9e6f9f7 | 326 | dev->mode_config.helper_private = &omap_mode_config_helper_funcs; |
cd5351f4 | 327 | |
69a12263 LP |
328 | drm_mode_config_reset(dev); |
329 | ||
728ae8dd LP |
330 | omap_drm_irq_install(dev); |
331 | ||
cd5351f4 RC |
332 | return 0; |
333 | } | |
334 | ||
3c596800 PU |
335 | /* |
336 | * Enable the HPD in external components if supported | |
337 | */ | |
338 | static void omap_modeset_enable_external_hpd(void) | |
339 | { | |
340 | struct omap_dss_device *dssdev = NULL; | |
341 | ||
342 | for_each_dss_dev(dssdev) { | |
343 | if (dssdev->driver->enable_hpd) | |
344 | dssdev->driver->enable_hpd(dssdev); | |
345 | } | |
346 | } | |
347 | ||
348 | /* | |
349 | * Disable the HPD in external components if supported | |
350 | */ | |
351 | static void omap_modeset_disable_external_hpd(void) | |
352 | { | |
353 | struct omap_dss_device *dssdev = NULL; | |
354 | ||
355 | for_each_dss_dev(dssdev) { | |
356 | if (dssdev->driver->disable_hpd) | |
357 | dssdev->driver->disable_hpd(dssdev); | |
358 | } | |
359 | } | |
360 | ||
cd5351f4 RC |
361 | /* |
362 | * drm ioctl funcs | |
363 | */ | |
364 | ||
365 | ||
366 | static int ioctl_get_param(struct drm_device *dev, void *data, | |
367 | struct drm_file *file_priv) | |
368 | { | |
5e3b0874 | 369 | struct omap_drm_private *priv = dev->dev_private; |
cd5351f4 RC |
370 | struct drm_omap_param *args = data; |
371 | ||
372 | DBG("%p: param=%llu", dev, args->param); | |
373 | ||
374 | switch (args->param) { | |
375 | case OMAP_PARAM_CHIPSET_ID: | |
5e3b0874 | 376 | args->value = priv->omaprev; |
cd5351f4 RC |
377 | break; |
378 | default: | |
379 | DBG("unknown parameter %lld", args->param); | |
380 | return -EINVAL; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static int ioctl_set_param(struct drm_device *dev, void *data, | |
387 | struct drm_file *file_priv) | |
388 | { | |
389 | struct drm_omap_param *args = data; | |
390 | ||
391 | switch (args->param) { | |
392 | default: | |
393 | DBG("unknown parameter %lld", args->param); | |
394 | return -EINVAL; | |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
ef3f4e99 LP |
400 | #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */ |
401 | ||
cd5351f4 RC |
402 | static int ioctl_gem_new(struct drm_device *dev, void *data, |
403 | struct drm_file *file_priv) | |
404 | { | |
405 | struct drm_omap_gem_new *args = data; | |
ef3f4e99 LP |
406 | u32 flags = args->flags & OMAP_BO_USER_MASK; |
407 | ||
f5f9454c | 408 | VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, |
ef3f4e99 LP |
409 | args->size.bytes, flags); |
410 | ||
411 | return omap_gem_new_handle(dev, file_priv, args->size, flags, | |
412 | &args->handle); | |
cd5351f4 RC |
413 | } |
414 | ||
cd5351f4 RC |
415 | static int ioctl_gem_info(struct drm_device *dev, void *data, |
416 | struct drm_file *file_priv) | |
417 | { | |
418 | struct drm_omap_gem_info *args = data; | |
419 | struct drm_gem_object *obj; | |
420 | int ret = 0; | |
421 | ||
f5f9454c | 422 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); |
cd5351f4 | 423 | |
a8ad0bd8 | 424 | obj = drm_gem_object_lookup(file_priv, args->handle); |
c7f904b3 | 425 | if (!obj) |
cd5351f4 | 426 | return -ENOENT; |
cd5351f4 | 427 | |
f7f9f453 | 428 | args->size = omap_gem_mmap_size(obj); |
cd5351f4 RC |
429 | args->offset = omap_gem_mmap_offset(obj); |
430 | ||
431 | drm_gem_object_unreference_unlocked(obj); | |
432 | ||
433 | return ret; | |
434 | } | |
435 | ||
baa70943 | 436 | static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { |
5f6ab8ca HH |
437 | DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, |
438 | DRM_AUTH | DRM_RENDER_ALLOW), | |
439 | DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, | |
440 | DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY), | |
441 | DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, | |
442 | DRM_AUTH | DRM_RENDER_ALLOW), | |
d6f544f6 LP |
443 | /* Deprecated, to be removed. */ |
444 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop, | |
5f6ab8ca | 445 | DRM_AUTH | DRM_RENDER_ALLOW), |
d6f544f6 LP |
446 | /* Deprecated, to be removed. */ |
447 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop, | |
5f6ab8ca HH |
448 | DRM_AUTH | DRM_RENDER_ALLOW), |
449 | DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, | |
450 | DRM_AUTH | DRM_RENDER_ALLOW), | |
cd5351f4 RC |
451 | }; |
452 | ||
453 | /* | |
454 | * drm driver funcs | |
455 | */ | |
456 | ||
cd5351f4 RC |
457 | static int dev_open(struct drm_device *dev, struct drm_file *file) |
458 | { | |
459 | file->driver_priv = NULL; | |
460 | ||
461 | DBG("open: dev=%p, file=%p", dev, file); | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
78b68556 | 466 | static const struct vm_operations_struct omap_gem_vm_ops = { |
cd5351f4 RC |
467 | .fault = omap_gem_fault, |
468 | .open = drm_gem_vm_open, | |
469 | .close = drm_gem_vm_close, | |
470 | }; | |
471 | ||
ff4f3876 | 472 | static const struct file_operations omapdriver_fops = { |
222025e4 LP |
473 | .owner = THIS_MODULE, |
474 | .open = drm_open, | |
475 | .unlocked_ioctl = drm_ioctl, | |
9d24159a | 476 | .compat_ioctl = drm_compat_ioctl, |
222025e4 LP |
477 | .release = drm_release, |
478 | .mmap = omap_gem_mmap, | |
479 | .poll = drm_poll, | |
480 | .read = drm_read, | |
481 | .llseek = noop_llseek, | |
ff4f3876 RC |
482 | }; |
483 | ||
cd5351f4 | 484 | static struct drm_driver omap_drm_driver = { |
728fea77 | 485 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
5f6ab8ca | 486 | DRIVER_ATOMIC | DRIVER_RENDER, |
222025e4 | 487 | .open = dev_open, |
ef62d308 | 488 | .lastclose = drm_fb_helper_lastclose, |
6169a148 | 489 | #ifdef CONFIG_DEBUG_FS |
222025e4 | 490 | .debugfs_init = omap_debugfs_init, |
6169a148 | 491 | #endif |
222025e4 LP |
492 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
493 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
494 | .gem_prime_export = omap_gem_prime_export, | |
495 | .gem_prime_import = omap_gem_prime_import, | |
f8466184 | 496 | .gem_free_object_unlocked = omap_gem_free_object, |
222025e4 LP |
497 | .gem_vm_ops = &omap_gem_vm_ops, |
498 | .dumb_create = omap_gem_dumb_create, | |
499 | .dumb_map_offset = omap_gem_dumb_map_offset, | |
222025e4 LP |
500 | .ioctls = ioctls, |
501 | .num_ioctls = DRM_OMAP_NUM_IOCTLS, | |
502 | .fops = &omapdriver_fops, | |
503 | .name = DRIVER_NAME, | |
504 | .desc = DRIVER_DESC, | |
505 | .date = DRIVER_DATE, | |
506 | .major = DRIVER_MAJOR, | |
507 | .minor = DRIVER_MINOR, | |
508 | .patchlevel = DRIVER_PATCHLEVEL, | |
cd5351f4 RC |
509 | }; |
510 | ||
6e471fab LP |
511 | static const struct soc_device_attribute omapdrm_soc_devices[] = { |
512 | { .family = "OMAP3", .data = (void *)0x3430 }, | |
513 | { .family = "OMAP4", .data = (void *)0x4430 }, | |
514 | { .family = "OMAP5", .data = (void *)0x5430 }, | |
515 | { .family = "DRA7", .data = (void *)0x0752 }, | |
516 | { /* sentinel */ } | |
517 | }; | |
518 | ||
a82f0347 | 519 | static int omapdrm_init(struct omap_drm_private *priv, struct device *dev) |
cd5351f4 | 520 | { |
6e471fab | 521 | const struct soc_device_attribute *soc; |
2f95bc6d LP |
522 | struct drm_device *ddev; |
523 | unsigned int i; | |
524 | int ret; | |
525 | ||
a82f0347 | 526 | DBG("%s", dev_name(dev)); |
591a0ac7 | 527 | |
a82f0347 | 528 | priv->dev = dev; |
d3541ca8 | 529 | priv->dss = omapdss_get_dss(); |
50638ae5 | 530 | priv->dispc = dispc_get_dispc(priv->dss); |
d3541ca8 | 531 | priv->dispc_ops = dispc_get_ops(priv->dss); |
510c74c5 | 532 | |
64cb8179 | 533 | omap_crtc_pre_init(priv); |
3a01ab25 | 534 | |
2f95bc6d LP |
535 | ret = omap_connect_dssdevs(); |
536 | if (ret) | |
537 | goto err_crtc_uninit; | |
538 | ||
6e471fab LP |
539 | soc = soc_device_match(omapdrm_soc_devices); |
540 | priv->omaprev = soc ? (unsigned int)soc->data : 0; | |
2f95bc6d LP |
541 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); |
542 | ||
5117bd89 | 543 | mutex_init(&priv->list_lock); |
2f95bc6d LP |
544 | INIT_LIST_HEAD(&priv->obj_list); |
545 | ||
546 | /* Allocate and initialize the DRM device. */ | |
a82f0347 | 547 | ddev = drm_dev_alloc(&omap_drm_driver, priv->dev); |
2f95bc6d LP |
548 | if (IS_ERR(ddev)) { |
549 | ret = PTR_ERR(ddev); | |
a82f0347 | 550 | goto err_destroy_wq; |
2f95bc6d LP |
551 | } |
552 | ||
a82f0347 | 553 | priv->ddev = ddev; |
2f95bc6d | 554 | ddev->dev_private = priv; |
2f95bc6d | 555 | |
a7631c4b PU |
556 | /* Get memory bandwidth limits */ |
557 | if (priv->dispc_ops->get_memory_bandwidth_limit) | |
558 | priv->max_bandwidth = | |
50638ae5 | 559 | priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc); |
a7631c4b | 560 | |
2f95bc6d LP |
561 | omap_gem_init(ddev); |
562 | ||
563 | ret = omap_modeset_init(ddev); | |
564 | if (ret) { | |
a82f0347 | 565 | dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret); |
2f95bc6d LP |
566 | goto err_free_drm_dev; |
567 | } | |
568 | ||
569 | /* Initialize vblank handling, start with all CRTCs disabled. */ | |
570 | ret = drm_vblank_init(ddev, priv->num_crtcs); | |
571 | if (ret) { | |
a82f0347 | 572 | dev_err(priv->dev, "could not init vblank\n"); |
2f95bc6d | 573 | goto err_cleanup_modeset; |
3a01ab25 AT |
574 | } |
575 | ||
2f95bc6d LP |
576 | for (i = 0; i < priv->num_crtcs; i++) |
577 | drm_crtc_vblank_off(priv->crtcs[i]); | |
578 | ||
efd1f06b | 579 | omap_fbdev_init(ddev); |
2f95bc6d LP |
580 | |
581 | drm_kms_helper_poll_init(ddev); | |
3c596800 | 582 | omap_modeset_enable_external_hpd(); |
2f95bc6d LP |
583 | |
584 | /* | |
585 | * Register the DRM device with the core and the connectors with | |
586 | * sysfs. | |
587 | */ | |
588 | ret = drm_dev_register(ddev, 0); | |
589 | if (ret) | |
590 | goto err_cleanup_helpers; | |
591 | ||
592 | return 0; | |
593 | ||
594 | err_cleanup_helpers: | |
3c596800 | 595 | omap_modeset_disable_external_hpd(); |
2f95bc6d | 596 | drm_kms_helper_poll_fini(ddev); |
efd1f06b TV |
597 | |
598 | omap_fbdev_fini(ddev); | |
2f95bc6d LP |
599 | err_cleanup_modeset: |
600 | drm_mode_config_cleanup(ddev); | |
601 | omap_drm_irq_uninstall(ddev); | |
602 | err_free_drm_dev: | |
603 | omap_gem_deinit(ddev); | |
604 | drm_dev_unref(ddev); | |
a82f0347 | 605 | err_destroy_wq: |
2f95bc6d | 606 | destroy_workqueue(priv->wq); |
2f95bc6d LP |
607 | omap_disconnect_dssdevs(); |
608 | err_crtc_uninit: | |
609 | omap_crtc_pre_uninit(); | |
610 | return ret; | |
cd5351f4 RC |
611 | } |
612 | ||
a82f0347 | 613 | static void omapdrm_cleanup(struct omap_drm_private *priv) |
cd5351f4 | 614 | { |
a82f0347 | 615 | struct drm_device *ddev = priv->ddev; |
2f95bc6d | 616 | |
cd5351f4 | 617 | DBG(""); |
5c137797 | 618 | |
2f95bc6d LP |
619 | drm_dev_unregister(ddev); |
620 | ||
3c596800 | 621 | omap_modeset_disable_external_hpd(); |
2f95bc6d LP |
622 | drm_kms_helper_poll_fini(ddev); |
623 | ||
efd1f06b | 624 | omap_fbdev_fini(ddev); |
2f95bc6d | 625 | |
8a54aa92 TV |
626 | drm_atomic_helper_shutdown(ddev); |
627 | ||
2f95bc6d LP |
628 | drm_mode_config_cleanup(ddev); |
629 | ||
630 | omap_drm_irq_uninstall(ddev); | |
631 | omap_gem_deinit(ddev); | |
632 | ||
633 | drm_dev_unref(ddev); | |
634 | ||
635 | destroy_workqueue(priv->wq); | |
707cf58a | 636 | |
cc823bdc AT |
637 | omap_disconnect_dssdevs(); |
638 | omap_crtc_pre_uninit(); | |
a82f0347 LP |
639 | } |
640 | ||
641 | static int pdev_probe(struct platform_device *pdev) | |
642 | { | |
643 | struct omap_drm_private *priv; | |
644 | int ret; | |
645 | ||
646 | if (omapdss_is_initialized() == false) | |
647 | return -EPROBE_DEFER; | |
648 | ||
649 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
650 | if (ret) { | |
651 | dev_err(&pdev->dev, "Failed to set the DMA mask\n"); | |
652 | return ret; | |
653 | } | |
654 | ||
655 | /* Allocate and initialize the driver private structure. */ | |
656 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
657 | if (!priv) | |
658 | return -ENOMEM; | |
659 | ||
660 | platform_set_drvdata(pdev, priv); | |
661 | ||
662 | ret = omapdrm_init(priv, &pdev->dev); | |
663 | if (ret < 0) | |
664 | kfree(priv); | |
665 | ||
666 | return ret; | |
667 | } | |
668 | ||
669 | static int pdev_remove(struct platform_device *pdev) | |
670 | { | |
671 | struct omap_drm_private *priv = platform_get_drvdata(pdev); | |
672 | ||
673 | omapdrm_cleanup(priv); | |
674 | kfree(priv); | |
fd3c0253 | 675 | |
cd5351f4 RC |
676 | return 0; |
677 | } | |
678 | ||
8450c8d0 | 679 | #ifdef CONFIG_PM_SLEEP |
92bf0f9e TV |
680 | static int omap_drm_suspend_all_displays(void) |
681 | { | |
682 | struct omap_dss_device *dssdev = NULL; | |
683 | ||
684 | for_each_dss_dev(dssdev) { | |
685 | if (!dssdev->driver) | |
686 | continue; | |
687 | ||
688 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { | |
689 | dssdev->driver->disable(dssdev); | |
690 | dssdev->activate_after_resume = true; | |
691 | } else { | |
692 | dssdev->activate_after_resume = false; | |
693 | } | |
694 | } | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | static int omap_drm_resume_all_displays(void) | |
700 | { | |
701 | struct omap_dss_device *dssdev = NULL; | |
702 | ||
703 | for_each_dss_dev(dssdev) { | |
704 | if (!dssdev->driver) | |
705 | continue; | |
706 | ||
707 | if (dssdev->activate_after_resume) { | |
708 | dssdev->driver->enable(dssdev); | |
709 | dssdev->activate_after_resume = false; | |
710 | } | |
711 | } | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
ccd7b5ed TV |
716 | static int omap_drm_suspend(struct device *dev) |
717 | { | |
a82f0347 LP |
718 | struct omap_drm_private *priv = dev_get_drvdata(dev); |
719 | struct drm_device *drm_dev = priv->ddev; | |
ccd7b5ed TV |
720 | |
721 | drm_kms_helper_poll_disable(drm_dev); | |
722 | ||
92bf0f9e TV |
723 | drm_modeset_lock_all(drm_dev); |
724 | omap_drm_suspend_all_displays(); | |
725 | drm_modeset_unlock_all(drm_dev); | |
726 | ||
ccd7b5ed TV |
727 | return 0; |
728 | } | |
729 | ||
730 | static int omap_drm_resume(struct device *dev) | |
731 | { | |
a82f0347 LP |
732 | struct omap_drm_private *priv = dev_get_drvdata(dev); |
733 | struct drm_device *drm_dev = priv->ddev; | |
ccd7b5ed | 734 | |
92bf0f9e TV |
735 | drm_modeset_lock_all(drm_dev); |
736 | omap_drm_resume_all_displays(); | |
737 | drm_modeset_unlock_all(drm_dev); | |
738 | ||
ccd7b5ed TV |
739 | drm_kms_helper_poll_enable(drm_dev); |
740 | ||
7fb15c48 | 741 | return omap_gem_resume(drm_dev); |
ccd7b5ed | 742 | } |
e78edba1 AG |
743 | #endif |
744 | ||
8450c8d0 GS |
745 | static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume); |
746 | ||
6717cd29 | 747 | static struct platform_driver pdev = { |
222025e4 | 748 | .driver = { |
f64eafa0 | 749 | .name = "omapdrm", |
222025e4 | 750 | .pm = &omapdrm_pm_ops, |
222025e4 LP |
751 | }, |
752 | .probe = pdev_probe, | |
753 | .remove = pdev_remove, | |
cd5351f4 RC |
754 | }; |
755 | ||
e1c49bdc TR |
756 | static struct platform_driver * const drivers[] = { |
757 | &omap_dmm_driver, | |
758 | &pdev, | |
759 | }; | |
760 | ||
cd5351f4 RC |
761 | static int __init omap_drm_init(void) |
762 | { | |
763 | DBG("init"); | |
ea7e3a66 | 764 | |
e1c49bdc | 765 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
cd5351f4 RC |
766 | } |
767 | ||
768 | static void __exit omap_drm_fini(void) | |
769 | { | |
770 | DBG("fini"); | |
ea7e3a66 | 771 | |
e1c49bdc | 772 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
cd5351f4 RC |
773 | } |
774 | ||
775 | /* need late_initcall() so we load after dss_driver's are loaded */ | |
776 | late_initcall(omap_drm_init); | |
777 | module_exit(omap_drm_fini); | |
778 | ||
779 | MODULE_AUTHOR("Rob Clark <rob@ti.com>"); | |
780 | MODULE_DESCRIPTION("OMAP DRM Display Driver"); | |
781 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
782 | MODULE_LICENSE("GPL v2"); |