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drm: omapdrm: Remove custom plane state
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cd5351f4 1/*
8bb0daff 2 * drivers/gpu/drm/omapdrm/omap_drv.c
cd5351f4
RC
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Rob Clark <rob@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
748471a5 20#include <drm/drm_atomic.h>
cef77d40 21#include <drm/drm_atomic_helper.h>
2d278f54
LP
22#include <drm/drm_crtc_helper.h>
23#include <drm/drm_fb_helper.h>
cd5351f4 24
5c137797 25#include "omap_dmm_tiler.h"
2d278f54 26#include "omap_drv.h"
cd5351f4
RC
27
28#define DRIVER_NAME MODULE_NAME
29#define DRIVER_DESC "OMAP DRM"
30#define DRIVER_DATE "20110917"
31#define DRIVER_MAJOR 1
32#define DRIVER_MINOR 0
33#define DRIVER_PATCHLEVEL 0
34
cd5351f4
RC
35/*
36 * mode config funcs
37 */
38
39/* Notes about mapping DSS and DRM entities:
40 * CRTC: overlay
41 * encoder: manager.. with some extension to allow one primary CRTC
42 * and zero or more video CRTC's to be mapped to one encoder?
43 * connector: dssdev.. manager can be attached/detached from different
44 * devices
45 */
46
47static void omap_fb_output_poll_changed(struct drm_device *dev)
48{
49 struct omap_drm_private *priv = dev->dev_private;
50 DBG("dev=%p", dev);
c7f904b3 51 if (priv->fbdev)
cd5351f4 52 drm_fb_helper_hotplug_event(priv->fbdev);
cd5351f4
RC
53}
54
5f741b39
TV
55static void omap_atomic_wait_for_completion(struct drm_device *dev,
56 struct drm_atomic_state *old_state)
57{
58 struct drm_crtc_state *old_crtc_state;
59 struct drm_crtc *crtc;
60 unsigned int i;
61 int ret;
62
63 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
64 if (!crtc->state->enable)
65 continue;
66
67 ret = omap_crtc_wait_pending(crtc);
68
69 if (!ret)
70 dev_warn(dev->dev,
71 "atomic complete timeout (pipe %u)!\n", i);
72 }
73}
74
a9e6f9f7 75static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
748471a5 76{
a9e6f9f7 77 struct drm_device *dev = old_state->dev;
748471a5 78 struct omap_drm_private *priv = dev->dev_private;
748471a5 79
9f759225 80 priv->dispc_ops->runtime_get();
69fb7c85 81
a9e6f9f7 82 /* Apply the atomic update. */
748471a5 83 drm_atomic_helper_commit_modeset_disables(dev, old_state);
897145d0
JS
84
85 /* With the current dss dispc implementation we have to enable
86 * the new modeset before we can commit planes. The dispc ovl
87 * configuration relies on the video mode configuration been
88 * written into the HW when the ovl configuration is
89 * calculated.
90 *
91 * This approach is not ideal because after a mode change the
92 * plane update is executed only after the first vblank
93 * interrupt. The dispc implementation should be fixed so that
94 * it is able use uncommitted drm state information.
95 */
748471a5 96 drm_atomic_helper_commit_modeset_enables(dev, old_state);
897145d0
JS
97 omap_atomic_wait_for_completion(dev, old_state);
98
99 drm_atomic_helper_commit_planes(dev, old_state, 0);
748471a5 100
a9e6f9f7
LP
101 drm_atomic_helper_commit_hw_done(old_state);
102
103 /*
104 * Wait for completion of the page flips to ensure that old buffers
105 * can't be touched by the hardware anymore before cleaning up planes.
106 */
5f741b39 107 omap_atomic_wait_for_completion(dev, old_state);
748471a5
LP
108
109 drm_atomic_helper_cleanup_planes(dev, old_state);
110
9f759225 111 priv->dispc_ops->runtime_put();
748471a5
LP
112}
113
a9e6f9f7
LP
114static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
115 .atomic_commit_tail = omap_atomic_commit_tail,
116};
748471a5 117
e6ecefaa 118static const struct drm_mode_config_funcs omap_mode_config_funcs = {
cd5351f4
RC
119 .fb_create = omap_framebuffer_create,
120 .output_poll_changed = omap_fb_output_poll_changed,
cef77d40 121 .atomic_check = drm_atomic_helper_check,
a9e6f9f7 122 .atomic_commit = drm_atomic_helper_commit,
cd5351f4
RC
123};
124
125static int get_connector_type(struct omap_dss_device *dssdev)
126{
127 switch (dssdev->type) {
128 case OMAP_DISPLAY_TYPE_HDMI:
129 return DRM_MODE_CONNECTOR_HDMIA;
4635c17d
TV
130 case OMAP_DISPLAY_TYPE_DVI:
131 return DRM_MODE_CONNECTOR_DVID;
4a64b908
SR
132 case OMAP_DISPLAY_TYPE_DSI:
133 return DRM_MODE_CONNECTOR_DSI;
cd5351f4
RC
134 default:
135 return DRM_MODE_CONNECTOR_Unknown;
136 }
137}
138
cc823bdc
AT
139static void omap_disconnect_dssdevs(void)
140{
141 struct omap_dss_device *dssdev = NULL;
142
143 for_each_dss_dev(dssdev)
144 dssdev->driver->disconnect(dssdev);
145}
0d8f371f 146
3a01ab25
AT
147static int omap_connect_dssdevs(void)
148{
149 int r;
150 struct omap_dss_device *dssdev = NULL;
a09d2bc1
PU
151
152 if (!omapdss_stack_is_ready())
153 return -EPROBE_DEFER;
3a01ab25
AT
154
155 for_each_dss_dev(dssdev) {
156 r = dssdev->driver->connect(dssdev);
157 if (r == -EPROBE_DEFER) {
158 omap_dss_put_device(dssdev);
159 goto cleanup;
160 } else if (r) {
161 dev_warn(dssdev->dev, "could not connect display: %s\n",
162 dssdev->name);
3a01ab25
AT
163 }
164 }
165
3a01ab25
AT
166 return 0;
167
168cleanup:
169 /*
170 * if we are deferring probe, we disconnect the devices we previously
171 * connected
172 */
cc823bdc 173 omap_disconnect_dssdevs();
3a01ab25
AT
174
175 return r;
176}
0d8f371f 177
e2cd09b2
LP
178static int omap_modeset_init_properties(struct drm_device *dev)
179{
180 struct omap_drm_private *priv = dev->dev_private;
181
e2cd09b2
LP
182 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
183 if (!priv->zorder_prop)
184 return -ENOMEM;
185
186 return 0;
187}
188
f5f9454c 189static int omap_modeset_init(struct drm_device *dev)
cd5351f4
RC
190{
191 struct omap_drm_private *priv = dev->dev_private;
f5f9454c 192 struct omap_dss_device *dssdev = NULL;
9f759225
TV
193 int num_ovls = priv->dispc_ops->get_num_ovls();
194 int num_mgrs = priv->dispc_ops->get_num_mgrs();
e8e13b15 195 int num_crtcs, crtc_idx, plane_idx;
fb9a35f8 196 int ret;
e8e13b15 197 u32 plane_crtc_mask;
04b1fc02 198
f5f9454c 199 drm_mode_config_init(dev);
cd5351f4 200
e2cd09b2
LP
201 ret = omap_modeset_init_properties(dev);
202 if (ret < 0)
203 return ret;
204
f5f9454c 205 /*
e8e13b15
JS
206 * This function creates exactly one connector, encoder, crtc,
207 * and primary plane per each connected dss-device. Each
208 * connector->encoder->crtc chain is expected to be separate
209 * and each crtc is connect to a single dss-channel. If the
210 * configuration does not match the expectations or exceeds
211 * the available resources, the configuration is rejected.
f5f9454c 212 */
e8e13b15 213 num_crtcs = 0;
f1118b89
JS
214 for_each_dss_dev(dssdev)
215 if (omapdss_device_is_connected(dssdev))
216 num_crtcs++;
217
e8e13b15
JS
218 if (num_crtcs > num_mgrs || num_crtcs > num_ovls ||
219 num_crtcs > ARRAY_SIZE(priv->crtcs) ||
220 num_crtcs > ARRAY_SIZE(priv->planes) ||
221 num_crtcs > ARRAY_SIZE(priv->encoders) ||
222 num_crtcs > ARRAY_SIZE(priv->connectors)) {
223 dev_err(dev->dev, "%s(): Too many connected displays\n",
224 __func__);
225 return -EINVAL;
226 }
227
228 /* All planes can be put to any CRTC */
229 plane_crtc_mask = (1 << num_crtcs) - 1;
cd5351f4 230
0d8f371f 231 dssdev = NULL;
cd5351f4 232
e8e13b15
JS
233 crtc_idx = 0;
234 plane_idx = 0;
f5f9454c
RC
235 for_each_dss_dev(dssdev) {
236 struct drm_connector *connector;
237 struct drm_encoder *encoder;
e8e13b15
JS
238 struct drm_plane *plane;
239 struct drm_crtc *crtc;
c7f904b3 240
3a01ab25 241 if (!omapdss_device_is_connected(dssdev))
581382e3 242 continue;
a7e71e7f 243
f5f9454c 244 encoder = omap_encoder_init(dev, dssdev);
e8e13b15 245 if (!encoder)
f5f9454c 246 return -ENOMEM;
cd5351f4 247
f5f9454c
RC
248 connector = omap_connector_init(dev,
249 get_connector_type(dssdev), dssdev, encoder);
e8e13b15 250 if (!connector)
f5f9454c 251 return -ENOMEM;
bb5c2d9a 252
e8e13b15
JS
253 plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY,
254 plane_crtc_mask);
255 if (IS_ERR(plane))
256 return PTR_ERR(plane);
cd5351f4 257
e8e13b15
JS
258 crtc = omap_crtc_init(dev, plane, dssdev);
259 if (IS_ERR(crtc))
260 return PTR_ERR(crtc);
cd5351f4 261
f5f9454c 262 drm_mode_connector_attach_encoder(connector, encoder);
e8e13b15 263 encoder->possible_crtcs = (1 << crtc_idx);
cd5351f4 264
e8e13b15
JS
265 priv->crtcs[priv->num_crtcs++] = crtc;
266 priv->planes[priv->num_planes++] = plane;
267 priv->encoders[priv->num_encoders++] = encoder;
268 priv->connectors[priv->num_connectors++] = connector;
0d8f371f 269
e8e13b15
JS
270 plane_idx++;
271 crtc_idx++;
0d8f371f
AT
272 }
273
0d8f371f
AT
274 /*
275 * Create normal planes for the remaining overlays:
276 */
e8e13b15 277 for (; plane_idx < num_ovls; plane_idx++) {
fb9a35f8
LP
278 struct drm_plane *plane;
279
e8e13b15
JS
280 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
281 return -EINVAL;
282
283 plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY,
284 plane_crtc_mask);
fb9a35f8
LP
285 if (IS_ERR(plane))
286 return PTR_ERR(plane);
0d8f371f 287
0d8f371f
AT
288 priv->planes[priv->num_planes++] = plane;
289 }
290
0d8f371f
AT
291 DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
292 priv->num_planes, priv->num_crtcs, priv->num_encoders,
293 priv->num_connectors);
294
1e90711d
TV
295 dev->mode_config.min_width = 8;
296 dev->mode_config.min_height = 2;
cd5351f4
RC
297
298 /* note: eventually will need some cpu_is_omapXYZ() type stuff here
299 * to fill in these limits properly on different OMAP generations..
300 */
301 dev->mode_config.max_width = 2048;
302 dev->mode_config.max_height = 2048;
303
304 dev->mode_config.funcs = &omap_mode_config_funcs;
a9e6f9f7 305 dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
cd5351f4 306
69a12263
LP
307 drm_mode_config_reset(dev);
308
728ae8dd
LP
309 omap_drm_irq_install(dev);
310
cd5351f4
RC
311 return 0;
312}
313
cd5351f4
RC
314/*
315 * drm ioctl funcs
316 */
317
318
319static int ioctl_get_param(struct drm_device *dev, void *data,
320 struct drm_file *file_priv)
321{
5e3b0874 322 struct omap_drm_private *priv = dev->dev_private;
cd5351f4
RC
323 struct drm_omap_param *args = data;
324
325 DBG("%p: param=%llu", dev, args->param);
326
327 switch (args->param) {
328 case OMAP_PARAM_CHIPSET_ID:
5e3b0874 329 args->value = priv->omaprev;
cd5351f4
RC
330 break;
331 default:
332 DBG("unknown parameter %lld", args->param);
333 return -EINVAL;
334 }
335
336 return 0;
337}
338
339static int ioctl_set_param(struct drm_device *dev, void *data,
340 struct drm_file *file_priv)
341{
342 struct drm_omap_param *args = data;
343
344 switch (args->param) {
345 default:
346 DBG("unknown parameter %lld", args->param);
347 return -EINVAL;
348 }
349
350 return 0;
351}
352
ef3f4e99
LP
353#define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
354
cd5351f4
RC
355static int ioctl_gem_new(struct drm_device *dev, void *data,
356 struct drm_file *file_priv)
357{
358 struct drm_omap_gem_new *args = data;
ef3f4e99
LP
359 u32 flags = args->flags & OMAP_BO_USER_MASK;
360
f5f9454c 361 VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
ef3f4e99
LP
362 args->size.bytes, flags);
363
364 return omap_gem_new_handle(dev, file_priv, args->size, flags,
365 &args->handle);
cd5351f4
RC
366}
367
cd5351f4
RC
368static int ioctl_gem_info(struct drm_device *dev, void *data,
369 struct drm_file *file_priv)
370{
371 struct drm_omap_gem_info *args = data;
372 struct drm_gem_object *obj;
373 int ret = 0;
374
f5f9454c 375 VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
cd5351f4 376
a8ad0bd8 377 obj = drm_gem_object_lookup(file_priv, args->handle);
c7f904b3 378 if (!obj)
cd5351f4 379 return -ENOENT;
cd5351f4 380
f7f9f453 381 args->size = omap_gem_mmap_size(obj);
cd5351f4
RC
382 args->offset = omap_gem_mmap_offset(obj);
383
384 drm_gem_object_unreference_unlocked(obj);
385
386 return ret;
387}
388
baa70943 389static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
5f6ab8ca
HH
390 DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
391 DRM_AUTH | DRM_RENDER_ALLOW),
392 DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
393 DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
394 DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
395 DRM_AUTH | DRM_RENDER_ALLOW),
d6f544f6
LP
396 /* Deprecated, to be removed. */
397 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
5f6ab8ca 398 DRM_AUTH | DRM_RENDER_ALLOW),
d6f544f6
LP
399 /* Deprecated, to be removed. */
400 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
5f6ab8ca
HH
401 DRM_AUTH | DRM_RENDER_ALLOW),
402 DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
403 DRM_AUTH | DRM_RENDER_ALLOW),
cd5351f4
RC
404};
405
406/*
407 * drm driver funcs
408 */
409
cd5351f4
RC
410static int dev_open(struct drm_device *dev, struct drm_file *file)
411{
412 file->driver_priv = NULL;
413
414 DBG("open: dev=%p, file=%p", dev, file);
415
416 return 0;
417}
418
cd5351f4
RC
419/**
420 * lastclose - clean up after all DRM clients have exited
421 * @dev: DRM device
422 *
423 * Take care of cleaning up after all DRM clients have exited. In the
424 * mode setting case, we want to restore the kernel's initial mode (just
425 * in case the last client left us in a bad state).
426 */
427static void dev_lastclose(struct drm_device *dev)
428{
3c810c61
RC
429 int i;
430
f15a66e6 431 /* we don't support vga_switcheroo.. so just make sure the fbdev
cd5351f4
RC
432 * mode is active
433 */
434 struct omap_drm_private *priv = dev->dev_private;
435 int ret;
436
437 DBG("lastclose: dev=%p", dev);
438
0da88db1
VS
439 /* need to restore default rotation state.. not sure
440 * if there is a cleaner way to restore properties to
441 * default state? Maybe a flag that properties should
442 * automatically be restored to default state on
443 * lastclose?
444 */
445 for (i = 0; i < priv->num_crtcs; i++) {
446 struct drm_crtc *crtc = priv->crtcs[i];
3c810c61 447
0da88db1
VS
448 if (!crtc->primary->rotation_property)
449 continue;
450
451 drm_object_property_set_value(&crtc->base,
452 crtc->primary->rotation_property,
c2c446ad 453 DRM_MODE_ROTATE_0);
0da88db1
VS
454 }
455
456 for (i = 0; i < priv->num_planes; i++) {
457 struct drm_plane *plane = priv->planes[i];
458
459 if (!plane->rotation_property)
460 continue;
461
462 drm_object_property_set_value(&plane->base,
463 plane->rotation_property,
c2c446ad 464 DRM_MODE_ROTATE_0);
3c810c61
RC
465 }
466
c7c1aecd
TV
467 if (priv->fbdev) {
468 ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
469 if (ret)
470 DBG("failed to restore crtc mode");
471 }
cd5351f4
RC
472}
473
78b68556 474static const struct vm_operations_struct omap_gem_vm_ops = {
cd5351f4
RC
475 .fault = omap_gem_fault,
476 .open = drm_gem_vm_open,
477 .close = drm_gem_vm_close,
478};
479
ff4f3876 480static const struct file_operations omapdriver_fops = {
222025e4
LP
481 .owner = THIS_MODULE,
482 .open = drm_open,
483 .unlocked_ioctl = drm_ioctl,
484 .release = drm_release,
485 .mmap = omap_gem_mmap,
486 .poll = drm_poll,
487 .read = drm_read,
488 .llseek = noop_llseek,
ff4f3876
RC
489};
490
cd5351f4 491static struct drm_driver omap_drm_driver = {
728fea77 492 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
5f6ab8ca 493 DRIVER_ATOMIC | DRIVER_RENDER,
222025e4
LP
494 .open = dev_open,
495 .lastclose = dev_lastclose,
6169a148 496#ifdef CONFIG_DEBUG_FS
222025e4 497 .debugfs_init = omap_debugfs_init,
6169a148 498#endif
222025e4
LP
499 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
500 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
501 .gem_prime_export = omap_gem_prime_export,
502 .gem_prime_import = omap_gem_prime_import,
503 .gem_free_object = omap_gem_free_object,
504 .gem_vm_ops = &omap_gem_vm_ops,
505 .dumb_create = omap_gem_dumb_create,
506 .dumb_map_offset = omap_gem_dumb_map_offset,
507 .dumb_destroy = drm_gem_dumb_destroy,
508 .ioctls = ioctls,
509 .num_ioctls = DRM_OMAP_NUM_IOCTLS,
510 .fops = &omapdriver_fops,
511 .name = DRIVER_NAME,
512 .desc = DRIVER_DESC,
513 .date = DRIVER_DATE,
514 .major = DRIVER_MAJOR,
515 .minor = DRIVER_MINOR,
516 .patchlevel = DRIVER_PATCHLEVEL,
cd5351f4
RC
517};
518
2f95bc6d 519static int pdev_probe(struct platform_device *pdev)
cd5351f4 520{
2f95bc6d
LP
521 struct omap_drm_platform_data *pdata = pdev->dev.platform_data;
522 struct omap_drm_private *priv;
523 struct drm_device *ddev;
524 unsigned int i;
525 int ret;
526
527 DBG("%s", pdev->name);
3a01ab25 528
591a0ac7
TV
529 if (omapdss_is_initialized() == false)
530 return -EPROBE_DEFER;
531
3a01ab25
AT
532 omap_crtc_pre_init();
533
2f95bc6d
LP
534 ret = omap_connect_dssdevs();
535 if (ret)
536 goto err_crtc_uninit;
537
538 /* Allocate and initialize the driver private structure. */
539 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
540 if (!priv) {
541 ret = -ENOMEM;
542 goto err_disconnect_dssdevs;
543 }
544
9f759225
TV
545 priv->dispc_ops = dispc_get_ops();
546
2f95bc6d
LP
547 priv->omaprev = pdata->omaprev;
548 priv->wq = alloc_ordered_workqueue("omapdrm", 0);
549
2f95bc6d
LP
550 spin_lock_init(&priv->list_lock);
551 INIT_LIST_HEAD(&priv->obj_list);
552
553 /* Allocate and initialize the DRM device. */
554 ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev);
555 if (IS_ERR(ddev)) {
556 ret = PTR_ERR(ddev);
557 goto err_free_priv;
558 }
559
560 ddev->dev_private = priv;
561 platform_set_drvdata(pdev, ddev);
562
563 omap_gem_init(ddev);
564
565 ret = omap_modeset_init(ddev);
566 if (ret) {
567 dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret);
568 goto err_free_drm_dev;
569 }
570
571 /* Initialize vblank handling, start with all CRTCs disabled. */
572 ret = drm_vblank_init(ddev, priv->num_crtcs);
573 if (ret) {
574 dev_err(&pdev->dev, "could not init vblank\n");
575 goto err_cleanup_modeset;
3a01ab25
AT
576 }
577
2f95bc6d
LP
578 for (i = 0; i < priv->num_crtcs; i++)
579 drm_crtc_vblank_off(priv->crtcs[i]);
580
581 priv->fbdev = omap_fbdev_init(ddev);
582
583 drm_kms_helper_poll_init(ddev);
584
585 /*
586 * Register the DRM device with the core and the connectors with
587 * sysfs.
588 */
589 ret = drm_dev_register(ddev, 0);
590 if (ret)
591 goto err_cleanup_helpers;
592
593 return 0;
594
595err_cleanup_helpers:
596 drm_kms_helper_poll_fini(ddev);
597 if (priv->fbdev)
598 omap_fbdev_free(ddev);
599err_cleanup_modeset:
600 drm_mode_config_cleanup(ddev);
601 omap_drm_irq_uninstall(ddev);
602err_free_drm_dev:
603 omap_gem_deinit(ddev);
604 drm_dev_unref(ddev);
605err_free_priv:
606 destroy_workqueue(priv->wq);
607 kfree(priv);
608err_disconnect_dssdevs:
609 omap_disconnect_dssdevs();
610err_crtc_uninit:
611 omap_crtc_pre_uninit();
612 return ret;
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613}
614
2f95bc6d 615static int pdev_remove(struct platform_device *pdev)
cd5351f4 616{
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617 struct drm_device *ddev = platform_get_drvdata(pdev);
618 struct omap_drm_private *priv = ddev->dev_private;
619
cd5351f4 620 DBG("");
5c137797 621
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LP
622 drm_dev_unregister(ddev);
623
624 drm_kms_helper_poll_fini(ddev);
625
626 if (priv->fbdev)
627 omap_fbdev_free(ddev);
628
8a54aa92
TV
629 drm_atomic_helper_shutdown(ddev);
630
2f95bc6d
LP
631 drm_mode_config_cleanup(ddev);
632
633 omap_drm_irq_uninstall(ddev);
634 omap_gem_deinit(ddev);
635
636 drm_dev_unref(ddev);
637
638 destroy_workqueue(priv->wq);
639 kfree(priv);
707cf58a 640
cc823bdc
AT
641 omap_disconnect_dssdevs();
642 omap_crtc_pre_uninit();
fd3c0253 643
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644 return 0;
645}
646
8450c8d0 647#ifdef CONFIG_PM_SLEEP
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648static int omap_drm_suspend_all_displays(void)
649{
650 struct omap_dss_device *dssdev = NULL;
651
652 for_each_dss_dev(dssdev) {
653 if (!dssdev->driver)
654 continue;
655
656 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
657 dssdev->driver->disable(dssdev);
658 dssdev->activate_after_resume = true;
659 } else {
660 dssdev->activate_after_resume = false;
661 }
662 }
663
664 return 0;
665}
666
667static int omap_drm_resume_all_displays(void)
668{
669 struct omap_dss_device *dssdev = NULL;
670
671 for_each_dss_dev(dssdev) {
672 if (!dssdev->driver)
673 continue;
674
675 if (dssdev->activate_after_resume) {
676 dssdev->driver->enable(dssdev);
677 dssdev->activate_after_resume = false;
678 }
679 }
680
681 return 0;
682}
683
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TV
684static int omap_drm_suspend(struct device *dev)
685{
686 struct drm_device *drm_dev = dev_get_drvdata(dev);
687
688 drm_kms_helper_poll_disable(drm_dev);
689
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690 drm_modeset_lock_all(drm_dev);
691 omap_drm_suspend_all_displays();
692 drm_modeset_unlock_all(drm_dev);
693
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694 return 0;
695}
696
697static int omap_drm_resume(struct device *dev)
698{
699 struct drm_device *drm_dev = dev_get_drvdata(dev);
700
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701 drm_modeset_lock_all(drm_dev);
702 omap_drm_resume_all_displays();
703 drm_modeset_unlock_all(drm_dev);
704
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705 drm_kms_helper_poll_enable(drm_dev);
706
707 return omap_gem_resume(dev);
708}
e78edba1
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709#endif
710
8450c8d0
GS
711static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
712
6717cd29 713static struct platform_driver pdev = {
222025e4
LP
714 .driver = {
715 .name = DRIVER_NAME,
222025e4 716 .pm = &omapdrm_pm_ops,
222025e4
LP
717 },
718 .probe = pdev_probe,
719 .remove = pdev_remove,
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720};
721
e1c49bdc
TR
722static struct platform_driver * const drivers[] = {
723 &omap_dmm_driver,
724 &pdev,
725};
726
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727static int __init omap_drm_init(void)
728{
729 DBG("init");
ea7e3a66 730
e1c49bdc 731 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
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732}
733
734static void __exit omap_drm_fini(void)
735{
736 DBG("fini");
ea7e3a66 737
e1c49bdc 738 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
cd5351f4
RC
739}
740
741/* need late_initcall() so we load after dss_driver's are loaded */
742late_initcall(omap_drm_init);
743module_exit(omap_drm_fini);
744
745MODULE_AUTHOR("Rob Clark <rob@ti.com>");
746MODULE_DESCRIPTION("OMAP DRM Display Driver");
747MODULE_ALIAS("platform:" DRIVER_NAME);
748MODULE_LICENSE("GPL v2");