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Commit | Line | Data |
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cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_drv.h |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef __OMAP_DRV_H__ | |
21 | #define __OMAP_DRV_H__ | |
22 | ||
cd5351f4 | 23 | #include <linux/module.h> |
2d278f54 | 24 | #include <linux/platform_data/omap_drm.h> |
cd5351f4 | 25 | #include <linux/types.h> |
748471a5 | 26 | #include <linux/wait.h> |
2d278f54 LP |
27 | #include <video/omapdss.h> |
28 | ||
cd5351f4 | 29 | #include <drm/drmP.h> |
ae43d7ca | 30 | #include <drm/drm_crtc_helper.h> |
d9fc9413 | 31 | #include <drm/drm_gem.h> |
2d278f54 | 32 | #include <drm/omap_drm.h> |
f5f9454c | 33 | |
cd5351f4 RC |
34 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
35 | #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt, ##__VA_ARGS__) /* verbose debug */ | |
36 | ||
37 | #define MODULE_NAME "omapdrm" | |
38 | ||
f4302747 LP |
39 | struct omap_drm_usergart; |
40 | ||
f5f9454c RC |
41 | /* parameters which describe (unrotated) coordinates of scanout within a fb: */ |
42 | struct omap_drm_window { | |
43 | uint32_t rotation; | |
44 | int32_t crtc_x, crtc_y; /* signed because can be offscreen */ | |
45 | uint32_t crtc_w, crtc_h; | |
46 | uint32_t src_x, src_y; | |
47 | uint32_t src_w, src_h; | |
48 | }; | |
49 | ||
f5f9454c RC |
50 | /* For transiently registering for different DSS irqs that various parts |
51 | * of the KMS code need during setup/configuration. We these are not | |
52 | * necessarily the same as what drm_vblank_get/put() are requesting, and | |
53 | * the hysteresis in drm_vblank_put() is not necessarily desirable for | |
54 | * internal housekeeping related irq usage. | |
55 | */ | |
56 | struct omap_drm_irq { | |
57 | struct list_head node; | |
58 | uint32_t irqmask; | |
59 | bool registered; | |
60 | void (*irq)(struct omap_drm_irq *irq, uint32_t irqstatus); | |
61 | }; | |
62 | ||
63 | /* For KMS code that needs to wait for a certain # of IRQs: | |
64 | */ | |
65 | struct omap_irq_wait; | |
66 | struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, | |
67 | uint32_t irqmask, int count); | |
68 | int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, | |
69 | unsigned long timeout); | |
70 | ||
cd5351f4 | 71 | struct omap_drm_private { |
5e3b0874 RC |
72 | uint32_t omaprev; |
73 | ||
cd5351f4 RC |
74 | unsigned int num_crtcs; |
75 | struct drm_crtc *crtcs[8]; | |
f6b6036e | 76 | |
bb5c2d9a RC |
77 | unsigned int num_planes; |
78 | struct drm_plane *planes[8]; | |
f6b6036e | 79 | |
cd5351f4 RC |
80 | unsigned int num_encoders; |
81 | struct drm_encoder *encoders[8]; | |
f6b6036e | 82 | |
cd5351f4 RC |
83 | unsigned int num_connectors; |
84 | struct drm_connector *connectors[8]; | |
85 | ||
86 | struct drm_fb_helper *fbdev; | |
a6a91827 | 87 | |
5609f7fe RC |
88 | struct workqueue_struct *wq; |
89 | ||
76c4055f TV |
90 | /* lock for obj_list below */ |
91 | spinlock_t list_lock; | |
92 | ||
f5f9454c | 93 | /* list of GEM objects: */ |
f6b6036e RC |
94 | struct list_head obj_list; |
95 | ||
f4302747 | 96 | struct omap_drm_usergart *usergart; |
a6a91827 | 97 | bool has_dmm; |
3c810c61 RC |
98 | |
99 | /* properties: */ | |
8451b5ad | 100 | struct drm_property *zorder_prop; |
f5f9454c RC |
101 | |
102 | /* irq handling: */ | |
103 | struct list_head irq_list; /* list of omap_drm_irq */ | |
104 | uint32_t vblank_mask; /* irq bits set for userspace vblank */ | |
105 | struct omap_drm_irq error_handler; | |
748471a5 LP |
106 | |
107 | /* atomic commit */ | |
108 | struct { | |
1cfe19aa | 109 | struct list_head events; |
748471a5 LP |
110 | wait_queue_head_t wait; |
111 | u32 pending; | |
112 | spinlock_t lock; /* Protects commit.pending */ | |
113 | } commit; | |
3c810c61 RC |
114 | }; |
115 | ||
3c810c61 | 116 | |
6169a148 AG |
117 | #ifdef CONFIG_DEBUG_FS |
118 | int omap_debugfs_init(struct drm_minor *minor); | |
119 | void omap_debugfs_cleanup(struct drm_minor *minor); | |
f6b6036e RC |
120 | void omap_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); |
121 | void omap_gem_describe(struct drm_gem_object *obj, struct seq_file *m); | |
122 | void omap_gem_describe_objects(struct list_head *list, struct seq_file *m); | |
6169a148 AG |
123 | #endif |
124 | ||
4836d157 AG |
125 | #ifdef CONFIG_PM |
126 | int omap_gem_resume(struct device *dev); | |
127 | #endif | |
128 | ||
88e72717 TR |
129 | int omap_irq_enable_vblank(struct drm_device *dev, unsigned int pipe); |
130 | void omap_irq_disable_vblank(struct drm_device *dev, unsigned int pipe); | |
6da9f891 TV |
131 | void __omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); |
132 | void __omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq); | |
f5f9454c RC |
133 | void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); |
134 | void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq); | |
f13ab005 | 135 | void omap_drm_irq_uninstall(struct drm_device *dev); |
f5f9454c RC |
136 | int omap_drm_irq_install(struct drm_device *dev); |
137 | ||
e1c1174f | 138 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
cd5351f4 RC |
139 | struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev); |
140 | void omap_fbdev_free(struct drm_device *dev); | |
e1c1174f LP |
141 | #else |
142 | static inline struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev) | |
143 | { | |
144 | return NULL; | |
145 | } | |
146 | static inline void omap_fbdev_free(struct drm_device *dev) | |
147 | { | |
148 | } | |
149 | #endif | |
cd5351f4 | 150 | |
4029755e | 151 | struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc); |
f5f9454c | 152 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc); |
04b1fc02 | 153 | void omap_crtc_pre_init(void); |
3a01ab25 | 154 | void omap_crtc_pre_uninit(void); |
cd5351f4 | 155 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, |
f5f9454c | 156 | struct drm_plane *plane, enum omap_channel channel, int id); |
5f741b39 | 157 | int omap_crtc_wait_pending(struct drm_crtc *crtc); |
bb5c2d9a RC |
158 | |
159 | struct drm_plane *omap_plane_init(struct drm_device *dev, | |
ef6b0e02 | 160 | int id, enum drm_plane_type type); |
3c810c61 RC |
161 | void omap_plane_install_properties(struct drm_plane *plane, |
162 | struct drm_mode_object *obj); | |
cd5351f4 RC |
163 | |
164 | struct drm_encoder *omap_encoder_init(struct drm_device *dev, | |
f5f9454c | 165 | struct omap_dss_device *dssdev); |
f5f9454c RC |
166 | |
167 | struct drm_connector *omap_connector_init(struct drm_device *dev, | |
168 | int connector_type, struct omap_dss_device *dssdev, | |
cd5351f4 RC |
169 | struct drm_encoder *encoder); |
170 | struct drm_encoder *omap_connector_attached_encoder( | |
171 | struct drm_connector *connector); | |
4f930c0f | 172 | bool omap_connector_get_hdmi_mode(struct drm_connector *connector); |
cd5351f4 | 173 | |
f5f9454c RC |
174 | void copy_timings_omap_to_drm(struct drm_display_mode *mode, |
175 | struct omap_video_timings *timings); | |
176 | void copy_timings_drm_to_omap(struct omap_video_timings *timings, | |
177 | struct drm_display_mode *mode); | |
178 | ||
a890e662 RC |
179 | uint32_t omap_framebuffer_get_formats(uint32_t *pixel_formats, |
180 | uint32_t max_formats, enum omap_color_mode supported_modes); | |
cd5351f4 | 181 | struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, |
1eb83451 | 182 | struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); |
cd5351f4 | 183 | struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, |
1eb83451 | 184 | const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); |
9a0774e0 | 185 | struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p); |
5833bd2f | 186 | int omap_framebuffer_pin(struct drm_framebuffer *fb); |
9c368506 | 187 | void omap_framebuffer_unpin(struct drm_framebuffer *fb); |
3c810c61 RC |
188 | void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, |
189 | struct omap_drm_window *win, struct omap_overlay_info *info); | |
cd5351f4 RC |
190 | struct drm_connector *omap_framebuffer_get_next_connector( |
191 | struct drm_framebuffer *fb, struct drm_connector *from); | |
cd5351f4 | 192 | |
f7f9f453 RC |
193 | void omap_gem_init(struct drm_device *dev); |
194 | void omap_gem_deinit(struct drm_device *dev); | |
cd5351f4 RC |
195 | |
196 | struct drm_gem_object *omap_gem_new(struct drm_device *dev, | |
197 | union omap_gem_size gsize, uint32_t flags); | |
b22e6690 LP |
198 | struct drm_gem_object *omap_gem_new_dmabuf(struct drm_device *dev, size_t size, |
199 | struct sg_table *sgt); | |
cd5351f4 RC |
200 | int omap_gem_new_handle(struct drm_device *dev, struct drm_file *file, |
201 | union omap_gem_size gsize, uint32_t flags, uint32_t *handle); | |
202 | void omap_gem_free_object(struct drm_gem_object *obj); | |
cd5351f4 RC |
203 | void *omap_gem_vaddr(struct drm_gem_object *obj); |
204 | int omap_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, | |
205 | uint32_t handle, uint64_t *offset); | |
cd5351f4 RC |
206 | int omap_gem_dumb_create(struct drm_file *file, struct drm_device *dev, |
207 | struct drm_mode_create_dumb *args); | |
208 | int omap_gem_mmap(struct file *filp, struct vm_area_struct *vma); | |
8b6b569e RC |
209 | int omap_gem_mmap_obj(struct drm_gem_object *obj, |
210 | struct vm_area_struct *vma); | |
cd5351f4 RC |
211 | int omap_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
212 | int omap_gem_op_start(struct drm_gem_object *obj, enum omap_gem_op op); | |
213 | int omap_gem_op_finish(struct drm_gem_object *obj, enum omap_gem_op op); | |
214 | int omap_gem_op_sync(struct drm_gem_object *obj, enum omap_gem_op op); | |
215 | int omap_gem_op_async(struct drm_gem_object *obj, enum omap_gem_op op, | |
216 | void (*fxn)(void *arg), void *arg); | |
a6a91827 | 217 | int omap_gem_roll(struct drm_gem_object *obj, uint32_t roll); |
8b6b569e RC |
218 | void omap_gem_cpu_sync(struct drm_gem_object *obj, int pgoff); |
219 | void omap_gem_dma_sync(struct drm_gem_object *obj, | |
220 | enum dma_data_direction dir); | |
cd5351f4 RC |
221 | int omap_gem_get_paddr(struct drm_gem_object *obj, |
222 | dma_addr_t *paddr, bool remap); | |
393a949f | 223 | void omap_gem_put_paddr(struct drm_gem_object *obj); |
6ad11bc3 RC |
224 | int omap_gem_get_pages(struct drm_gem_object *obj, struct page ***pages, |
225 | bool remap); | |
226 | int omap_gem_put_pages(struct drm_gem_object *obj); | |
227 | uint32_t omap_gem_flags(struct drm_gem_object *obj); | |
3c810c61 RC |
228 | int omap_gem_rotated_paddr(struct drm_gem_object *obj, uint32_t orient, |
229 | int x, int y, dma_addr_t *paddr); | |
cd5351f4 | 230 | uint64_t omap_gem_mmap_offset(struct drm_gem_object *obj); |
f7f9f453 | 231 | size_t omap_gem_mmap_size(struct drm_gem_object *obj); |
3c810c61 RC |
232 | int omap_gem_tiled_size(struct drm_gem_object *obj, uint16_t *w, uint16_t *h); |
233 | int omap_gem_tiled_stride(struct drm_gem_object *obj, uint32_t orient); | |
cd5351f4 | 234 | |
7ced63cf | 235 | struct dma_buf *omap_gem_prime_export(struct drm_device *dev, |
6ad11bc3 | 236 | struct drm_gem_object *obj, int flags); |
7ced63cf | 237 | struct drm_gem_object *omap_gem_prime_import(struct drm_device *dev, |
3080b838 | 238 | struct dma_buf *buffer); |
6ad11bc3 | 239 | |
cd5351f4 RC |
240 | static inline int align_pitch(int pitch, int width, int bpp) |
241 | { | |
242 | int bytespp = (bpp + 7) / 8; | |
243 | /* in case someone tries to feed us a completely bogus stride: */ | |
244 | pitch = max(pitch, width * bytespp); | |
245 | /* PVR needs alignment to 8 pixels.. right now that is the most | |
246 | * restrictive stride requirement.. | |
247 | */ | |
d642d3ac | 248 | return roundup(pitch, 8 * bytespp); |
cd5351f4 RC |
249 | } |
250 | ||
f5f9454c | 251 | /* map crtc to vblank mask */ |
0d8f371f AT |
252 | uint32_t pipe2vbl(struct drm_crtc *crtc); |
253 | struct omap_dss_device *omap_encoder_get_dssdev(struct drm_encoder *encoder); | |
f5f9454c | 254 | |
ae43d7ca RC |
255 | /* should these be made into common util helpers? |
256 | */ | |
257 | ||
258 | static inline int objects_lookup(struct drm_device *dev, | |
259 | struct drm_file *filp, uint32_t pixel_format, | |
1eb83451 | 260 | struct drm_gem_object **bos, const uint32_t *handles) |
ae43d7ca RC |
261 | { |
262 | int i, n = drm_format_num_planes(pixel_format); | |
263 | ||
264 | for (i = 0; i < n; i++) { | |
265 | bos[i] = drm_gem_object_lookup(dev, filp, handles[i]); | |
bc1e1581 | 266 | if (!bos[i]) |
ae43d7ca | 267 | goto fail; |
bc1e1581 | 268 | |
ae43d7ca RC |
269 | } |
270 | ||
271 | return 0; | |
272 | ||
273 | fail: | |
bc1e1581 | 274 | while (--i > 0) |
ae43d7ca | 275 | drm_gem_object_unreference_unlocked(bos[i]); |
bc1e1581 | 276 | |
ae43d7ca RC |
277 | return -ENOENT; |
278 | } | |
279 | ||
cd5351f4 | 280 | #endif /* __OMAP_DRV_H__ */ |