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Commit | Line | Data |
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f5f9454c | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_irq.c |
f5f9454c RC |
3 | * |
4 | * Copyright (C) 2012 Texas Instruments | |
5 | * Author: Rob Clark <rob.clark@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
80f91bff LP |
22 | struct omap_irq_wait { |
23 | struct list_head node; | |
84e1d457 | 24 | wait_queue_head_t wq; |
80f91bff LP |
25 | uint32_t irqmask; |
26 | int count; | |
27 | }; | |
28 | ||
84e1d457 | 29 | /* call with wait_lock and dispc runtime held */ |
f5f9454c RC |
30 | static void omap_irq_update(struct drm_device *dev) |
31 | { | |
32 | struct omap_drm_private *priv = dev->dev_private; | |
80f91bff | 33 | struct omap_irq_wait *wait; |
728ae8dd | 34 | uint32_t irqmask = priv->irq_mask; |
f5f9454c | 35 | |
84e1d457 | 36 | assert_spin_locked(&priv->wait_lock); |
f5f9454c | 37 | |
80f91bff LP |
38 | list_for_each_entry(wait, &priv->wait_list, node) |
39 | irqmask |= wait->irqmask; | |
f5f9454c RC |
40 | |
41 | DBG("irqmask=%08x", irqmask); | |
42 | ||
9f759225 | 43 | priv->dispc_ops->write_irqenable(irqmask); |
f5f9454c RC |
44 | } |
45 | ||
80f91bff | 46 | static void omap_irq_wait_handler(struct omap_irq_wait *wait) |
f5f9454c | 47 | { |
f5f9454c | 48 | wait->count--; |
84e1d457 | 49 | wake_up(&wait->wq); |
f5f9454c RC |
50 | } |
51 | ||
52 | struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, | |
53 | uint32_t irqmask, int count) | |
54 | { | |
80f91bff | 55 | struct omap_drm_private *priv = dev->dev_private; |
f5f9454c | 56 | struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL); |
80f91bff LP |
57 | unsigned long flags; |
58 | ||
84e1d457 | 59 | init_waitqueue_head(&wait->wq); |
80f91bff | 60 | wait->irqmask = irqmask; |
f5f9454c | 61 | wait->count = count; |
80f91bff | 62 | |
84e1d457 | 63 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
64 | list_add(&wait->node, &priv->wait_list); |
65 | omap_irq_update(dev); | |
84e1d457 | 66 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
80f91bff | 67 | |
f5f9454c RC |
68 | return wait; |
69 | } | |
70 | ||
71 | int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, | |
72 | unsigned long timeout) | |
73 | { | |
84e1d457 | 74 | struct omap_drm_private *priv = dev->dev_private; |
80f91bff | 75 | unsigned long flags; |
84e1d457 LP |
76 | int ret; |
77 | ||
78 | ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout); | |
80f91bff | 79 | |
84e1d457 | 80 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
81 | list_del(&wait->node); |
82 | omap_irq_update(dev); | |
84e1d457 | 83 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
80f91bff | 84 | |
f5f9454c | 85 | kfree(wait); |
80f91bff LP |
86 | |
87 | return ret == 0 ? -1 : 0; | |
f5f9454c RC |
88 | } |
89 | ||
90 | /** | |
91 | * enable_vblank - enable vblank interrupt events | |
92 | * @dev: DRM device | |
88e72717 | 93 | * @pipe: which irq to enable |
f5f9454c RC |
94 | * |
95 | * Enable vblank interrupts for @crtc. If the device doesn't have | |
96 | * a hardware vblank counter, this routine should be a no-op, since | |
97 | * interrupts will have to stay on to keep the count accurate. | |
98 | * | |
99 | * RETURNS | |
100 | * Zero on success, appropriate errno if the given @crtc's vblank | |
101 | * interrupt cannot be enabled. | |
102 | */ | |
0396162a | 103 | int omap_irq_enable_vblank(struct drm_crtc *crtc) |
f5f9454c | 104 | { |
0396162a | 105 | struct drm_device *dev = crtc->dev; |
f5f9454c RC |
106 | struct omap_drm_private *priv = dev->dev_private; |
107 | unsigned long flags; | |
0396162a | 108 | enum omap_channel channel = omap_crtc_channel(crtc); |
f5f9454c | 109 | |
0396162a | 110 | DBG("dev=%p, crtc=%u", dev, channel); |
f5f9454c | 111 | |
84e1d457 | 112 | spin_lock_irqsave(&priv->wait_lock, flags); |
9f759225 | 113 | priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(channel); |
f5f9454c | 114 | omap_irq_update(dev); |
84e1d457 | 115 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
116 | |
117 | return 0; | |
118 | } | |
119 | ||
120 | /** | |
121 | * disable_vblank - disable vblank interrupt events | |
122 | * @dev: DRM device | |
88e72717 | 123 | * @pipe: which irq to enable |
f5f9454c RC |
124 | * |
125 | * Disable vblank interrupts for @crtc. If the device doesn't have | |
126 | * a hardware vblank counter, this routine should be a no-op, since | |
127 | * interrupts will have to stay on to keep the count accurate. | |
128 | */ | |
0396162a | 129 | void omap_irq_disable_vblank(struct drm_crtc *crtc) |
f5f9454c | 130 | { |
0396162a | 131 | struct drm_device *dev = crtc->dev; |
f5f9454c RC |
132 | struct omap_drm_private *priv = dev->dev_private; |
133 | unsigned long flags; | |
0396162a | 134 | enum omap_channel channel = omap_crtc_channel(crtc); |
f5f9454c | 135 | |
0396162a | 136 | DBG("dev=%p, crtc=%u", dev, channel); |
f5f9454c | 137 | |
84e1d457 | 138 | spin_lock_irqsave(&priv->wait_lock, flags); |
9f759225 | 139 | priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(channel); |
f5f9454c | 140 | omap_irq_update(dev); |
84e1d457 | 141 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
142 | } |
143 | ||
728ae8dd LP |
144 | static void omap_irq_fifo_underflow(struct omap_drm_private *priv, |
145 | u32 irqstatus) | |
146 | { | |
147 | static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, | |
148 | DEFAULT_RATELIMIT_BURST); | |
149 | static const struct { | |
150 | const char *name; | |
151 | u32 mask; | |
152 | } sources[] = { | |
153 | { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, | |
154 | { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW }, | |
155 | { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW }, | |
156 | { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW }, | |
157 | }; | |
158 | ||
159 | const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW | |
160 | | DISPC_IRQ_VID1_FIFO_UNDERFLOW | |
161 | | DISPC_IRQ_VID2_FIFO_UNDERFLOW | |
162 | | DISPC_IRQ_VID3_FIFO_UNDERFLOW; | |
163 | unsigned int i; | |
164 | ||
84e1d457 | 165 | spin_lock(&priv->wait_lock); |
728ae8dd | 166 | irqstatus &= priv->irq_mask & mask; |
84e1d457 | 167 | spin_unlock(&priv->wait_lock); |
728ae8dd LP |
168 | |
169 | if (!irqstatus) | |
170 | return; | |
171 | ||
172 | if (!__ratelimit(&_rs)) | |
173 | return; | |
174 | ||
175 | DRM_ERROR("FIFO underflow on "); | |
176 | ||
177 | for (i = 0; i < ARRAY_SIZE(sources); ++i) { | |
178 | if (sources[i].mask & irqstatus) | |
179 | pr_cont("%s ", sources[i].name); | |
180 | } | |
181 | ||
182 | pr_cont("(0x%08x)\n", irqstatus); | |
183 | } | |
184 | ||
6b5538d4 LP |
185 | static void omap_irq_ocp_error_handler(u32 irqstatus) |
186 | { | |
187 | if (!(irqstatus & DISPC_IRQ_OCP_ERR)) | |
188 | return; | |
189 | ||
190 | DRM_ERROR("OCP error\n"); | |
191 | } | |
192 | ||
f13ab005 | 193 | static irqreturn_t omap_irq_handler(int irq, void *arg) |
f5f9454c RC |
194 | { |
195 | struct drm_device *dev = (struct drm_device *) arg; | |
196 | struct omap_drm_private *priv = dev->dev_private; | |
80f91bff | 197 | struct omap_irq_wait *wait, *n; |
f5f9454c RC |
198 | unsigned long flags; |
199 | unsigned int id; | |
200 | u32 irqstatus; | |
201 | ||
9f759225 TV |
202 | irqstatus = priv->dispc_ops->read_irqstatus(); |
203 | priv->dispc_ops->clear_irqstatus(irqstatus); | |
204 | priv->dispc_ops->read_irqstatus(); /* flush posted write */ | |
f5f9454c RC |
205 | |
206 | VERB("irqs: %08x", irqstatus); | |
207 | ||
0d8f371f AT |
208 | for (id = 0; id < priv->num_crtcs; id++) { |
209 | struct drm_crtc *crtc = priv->crtcs[id]; | |
e0519af7 | 210 | enum omap_channel channel = omap_crtc_channel(crtc); |
0d8f371f | 211 | |
9f759225 | 212 | if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(channel)) { |
f5f9454c | 213 | drm_handle_vblank(dev, id); |
14389a37 LP |
214 | omap_crtc_vblank_irq(crtc); |
215 | } | |
e0519af7 | 216 | |
9f759225 | 217 | if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(channel)) |
e0519af7 | 218 | omap_crtc_error_irq(crtc, irqstatus); |
0d8f371f | 219 | } |
f5f9454c | 220 | |
6b5538d4 | 221 | omap_irq_ocp_error_handler(irqstatus); |
728ae8dd LP |
222 | omap_irq_fifo_underflow(priv, irqstatus); |
223 | ||
84e1d457 | 224 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
225 | list_for_each_entry_safe(wait, n, &priv->wait_list, node) { |
226 | if (wait->irqmask & irqstatus) | |
227 | omap_irq_wait_handler(wait); | |
f5f9454c | 228 | } |
84e1d457 | 229 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
230 | |
231 | return IRQ_HANDLED; | |
232 | } | |
233 | ||
728ae8dd LP |
234 | static const u32 omap_underflow_irqs[] = { |
235 | [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW, | |
236 | [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW, | |
237 | [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW, | |
238 | [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW, | |
239 | }; | |
240 | ||
f13ab005 LP |
241 | /* |
242 | * We need a special version, instead of just using drm_irq_install(), | |
243 | * because we need to register the irq via omapdss. Once omapdss and | |
244 | * omapdrm are merged together we can assign the dispc hwmod data to | |
245 | * ourselves and drop these and just use drm_irq_{install,uninstall}() | |
246 | */ | |
f5f9454c | 247 | |
f13ab005 | 248 | int omap_drm_irq_install(struct drm_device *dev) |
f5f9454c RC |
249 | { |
250 | struct omap_drm_private *priv = dev->dev_private; | |
9f759225 | 251 | unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(); |
728ae8dd LP |
252 | unsigned int max_planes; |
253 | unsigned int i; | |
f13ab005 | 254 | int ret; |
f5f9454c | 255 | |
84e1d457 | 256 | spin_lock_init(&priv->wait_lock); |
80f91bff | 257 | INIT_LIST_HEAD(&priv->wait_list); |
f5f9454c | 258 | |
6b5538d4 | 259 | priv->irq_mask = DISPC_IRQ_OCP_ERR; |
728ae8dd LP |
260 | |
261 | max_planes = min(ARRAY_SIZE(priv->planes), | |
262 | ARRAY_SIZE(omap_underflow_irqs)); | |
263 | for (i = 0; i < max_planes; ++i) { | |
264 | if (priv->planes[i]) | |
265 | priv->irq_mask |= omap_underflow_irqs[i]; | |
266 | } | |
267 | ||
e0519af7 | 268 | for (i = 0; i < num_mgrs; ++i) |
9f759225 | 269 | priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(i); |
e0519af7 | 270 | |
9f759225 TV |
271 | priv->dispc_ops->runtime_get(); |
272 | priv->dispc_ops->clear_irqstatus(0xffffffff); | |
273 | priv->dispc_ops->runtime_put(); | |
f13ab005 | 274 | |
9f759225 | 275 | ret = priv->dispc_ops->request_irq(omap_irq_handler, dev); |
f13ab005 LP |
276 | if (ret < 0) |
277 | return ret; | |
278 | ||
4423843c | 279 | dev->irq_enabled = true; |
f5f9454c | 280 | |
f13ab005 | 281 | return 0; |
f5f9454c RC |
282 | } |
283 | ||
f13ab005 | 284 | void omap_drm_irq_uninstall(struct drm_device *dev) |
f5f9454c | 285 | { |
9f759225 | 286 | struct omap_drm_private *priv = dev->dev_private; |
f5f9454c | 287 | |
f13ab005 LP |
288 | if (!dev->irq_enabled) |
289 | return; | |
290 | ||
4423843c | 291 | dev->irq_enabled = false; |
f5f9454c | 292 | |
9f759225 | 293 | priv->dispc_ops->free_irq(dev); |
f5f9454c | 294 | } |