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Commit | Line | Data |
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f5f9454c | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_irq.c |
f5f9454c RC |
3 | * |
4 | * Copyright (C) 2012 Texas Instruments | |
5 | * Author: Rob Clark <rob.clark@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
80f91bff LP |
22 | struct omap_irq_wait { |
23 | struct list_head node; | |
84e1d457 | 24 | wait_queue_head_t wq; |
80f91bff LP |
25 | uint32_t irqmask; |
26 | int count; | |
27 | }; | |
28 | ||
84e1d457 | 29 | /* call with wait_lock and dispc runtime held */ |
f5f9454c RC |
30 | static void omap_irq_update(struct drm_device *dev) |
31 | { | |
32 | struct omap_drm_private *priv = dev->dev_private; | |
80f91bff | 33 | struct omap_irq_wait *wait; |
728ae8dd | 34 | uint32_t irqmask = priv->irq_mask; |
f5f9454c | 35 | |
84e1d457 | 36 | assert_spin_locked(&priv->wait_lock); |
f5f9454c | 37 | |
80f91bff LP |
38 | list_for_each_entry(wait, &priv->wait_list, node) |
39 | irqmask |= wait->irqmask; | |
f5f9454c RC |
40 | |
41 | DBG("irqmask=%08x", irqmask); | |
42 | ||
43 | dispc_write_irqenable(irqmask); | |
44 | dispc_read_irqenable(); /* flush posted write */ | |
45 | } | |
46 | ||
80f91bff | 47 | static void omap_irq_wait_handler(struct omap_irq_wait *wait) |
f5f9454c | 48 | { |
f5f9454c | 49 | wait->count--; |
84e1d457 | 50 | wake_up(&wait->wq); |
f5f9454c RC |
51 | } |
52 | ||
53 | struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, | |
54 | uint32_t irqmask, int count) | |
55 | { | |
80f91bff | 56 | struct omap_drm_private *priv = dev->dev_private; |
f5f9454c | 57 | struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL); |
80f91bff LP |
58 | unsigned long flags; |
59 | ||
84e1d457 | 60 | init_waitqueue_head(&wait->wq); |
80f91bff | 61 | wait->irqmask = irqmask; |
f5f9454c | 62 | wait->count = count; |
80f91bff | 63 | |
84e1d457 | 64 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
65 | list_add(&wait->node, &priv->wait_list); |
66 | omap_irq_update(dev); | |
84e1d457 | 67 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
80f91bff | 68 | |
f5f9454c RC |
69 | return wait; |
70 | } | |
71 | ||
72 | int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, | |
73 | unsigned long timeout) | |
74 | { | |
84e1d457 | 75 | struct omap_drm_private *priv = dev->dev_private; |
80f91bff | 76 | unsigned long flags; |
84e1d457 LP |
77 | int ret; |
78 | ||
79 | ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout); | |
80f91bff | 80 | |
84e1d457 | 81 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
82 | list_del(&wait->node); |
83 | omap_irq_update(dev); | |
84e1d457 | 84 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
80f91bff | 85 | |
f5f9454c | 86 | kfree(wait); |
80f91bff LP |
87 | |
88 | return ret == 0 ? -1 : 0; | |
f5f9454c RC |
89 | } |
90 | ||
91 | /** | |
92 | * enable_vblank - enable vblank interrupt events | |
93 | * @dev: DRM device | |
88e72717 | 94 | * @pipe: which irq to enable |
f5f9454c RC |
95 | * |
96 | * Enable vblank interrupts for @crtc. If the device doesn't have | |
97 | * a hardware vblank counter, this routine should be a no-op, since | |
98 | * interrupts will have to stay on to keep the count accurate. | |
99 | * | |
100 | * RETURNS | |
101 | * Zero on success, appropriate errno if the given @crtc's vblank | |
102 | * interrupt cannot be enabled. | |
103 | */ | |
88e72717 | 104 | int omap_irq_enable_vblank(struct drm_device *dev, unsigned int pipe) |
f5f9454c RC |
105 | { |
106 | struct omap_drm_private *priv = dev->dev_private; | |
88e72717 | 107 | struct drm_crtc *crtc = priv->crtcs[pipe]; |
f5f9454c RC |
108 | unsigned long flags; |
109 | ||
88e72717 | 110 | DBG("dev=%p, crtc=%u", dev, pipe); |
f5f9454c | 111 | |
84e1d457 | 112 | spin_lock_irqsave(&priv->wait_lock, flags); |
ca52d2f3 | 113 | priv->irq_mask |= dispc_mgr_get_vsync_irq(omap_crtc_channel(crtc)); |
f5f9454c | 114 | omap_irq_update(dev); |
84e1d457 | 115 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
116 | |
117 | return 0; | |
118 | } | |
119 | ||
120 | /** | |
121 | * disable_vblank - disable vblank interrupt events | |
122 | * @dev: DRM device | |
88e72717 | 123 | * @pipe: which irq to enable |
f5f9454c RC |
124 | * |
125 | * Disable vblank interrupts for @crtc. If the device doesn't have | |
126 | * a hardware vblank counter, this routine should be a no-op, since | |
127 | * interrupts will have to stay on to keep the count accurate. | |
128 | */ | |
88e72717 | 129 | void omap_irq_disable_vblank(struct drm_device *dev, unsigned int pipe) |
f5f9454c RC |
130 | { |
131 | struct omap_drm_private *priv = dev->dev_private; | |
88e72717 | 132 | struct drm_crtc *crtc = priv->crtcs[pipe]; |
f5f9454c RC |
133 | unsigned long flags; |
134 | ||
88e72717 | 135 | DBG("dev=%p, crtc=%u", dev, pipe); |
f5f9454c | 136 | |
84e1d457 | 137 | spin_lock_irqsave(&priv->wait_lock, flags); |
ca52d2f3 | 138 | priv->irq_mask &= ~dispc_mgr_get_vsync_irq(omap_crtc_channel(crtc)); |
f5f9454c | 139 | omap_irq_update(dev); |
84e1d457 | 140 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
141 | } |
142 | ||
728ae8dd LP |
143 | static void omap_irq_fifo_underflow(struct omap_drm_private *priv, |
144 | u32 irqstatus) | |
145 | { | |
146 | static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, | |
147 | DEFAULT_RATELIMIT_BURST); | |
148 | static const struct { | |
149 | const char *name; | |
150 | u32 mask; | |
151 | } sources[] = { | |
152 | { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, | |
153 | { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW }, | |
154 | { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW }, | |
155 | { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW }, | |
156 | }; | |
157 | ||
158 | const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW | |
159 | | DISPC_IRQ_VID1_FIFO_UNDERFLOW | |
160 | | DISPC_IRQ_VID2_FIFO_UNDERFLOW | |
161 | | DISPC_IRQ_VID3_FIFO_UNDERFLOW; | |
162 | unsigned int i; | |
163 | ||
84e1d457 | 164 | spin_lock(&priv->wait_lock); |
728ae8dd | 165 | irqstatus &= priv->irq_mask & mask; |
84e1d457 | 166 | spin_unlock(&priv->wait_lock); |
728ae8dd LP |
167 | |
168 | if (!irqstatus) | |
169 | return; | |
170 | ||
171 | if (!__ratelimit(&_rs)) | |
172 | return; | |
173 | ||
174 | DRM_ERROR("FIFO underflow on "); | |
175 | ||
176 | for (i = 0; i < ARRAY_SIZE(sources); ++i) { | |
177 | if (sources[i].mask & irqstatus) | |
178 | pr_cont("%s ", sources[i].name); | |
179 | } | |
180 | ||
181 | pr_cont("(0x%08x)\n", irqstatus); | |
182 | } | |
183 | ||
6b5538d4 LP |
184 | static void omap_irq_ocp_error_handler(u32 irqstatus) |
185 | { | |
186 | if (!(irqstatus & DISPC_IRQ_OCP_ERR)) | |
187 | return; | |
188 | ||
189 | DRM_ERROR("OCP error\n"); | |
190 | } | |
191 | ||
f13ab005 | 192 | static irqreturn_t omap_irq_handler(int irq, void *arg) |
f5f9454c RC |
193 | { |
194 | struct drm_device *dev = (struct drm_device *) arg; | |
195 | struct omap_drm_private *priv = dev->dev_private; | |
80f91bff | 196 | struct omap_irq_wait *wait, *n; |
f5f9454c RC |
197 | unsigned long flags; |
198 | unsigned int id; | |
199 | u32 irqstatus; | |
200 | ||
201 | irqstatus = dispc_read_irqstatus(); | |
202 | dispc_clear_irqstatus(irqstatus); | |
203 | dispc_read_irqstatus(); /* flush posted write */ | |
204 | ||
205 | VERB("irqs: %08x", irqstatus); | |
206 | ||
0d8f371f AT |
207 | for (id = 0; id < priv->num_crtcs; id++) { |
208 | struct drm_crtc *crtc = priv->crtcs[id]; | |
e0519af7 | 209 | enum omap_channel channel = omap_crtc_channel(crtc); |
0d8f371f | 210 | |
ca52d2f3 | 211 | if (irqstatus & dispc_mgr_get_vsync_irq(channel)) { |
f5f9454c | 212 | drm_handle_vblank(dev, id); |
14389a37 LP |
213 | omap_crtc_vblank_irq(crtc); |
214 | } | |
e0519af7 LP |
215 | |
216 | if (irqstatus & dispc_mgr_get_sync_lost_irq(channel)) | |
217 | omap_crtc_error_irq(crtc, irqstatus); | |
0d8f371f | 218 | } |
f5f9454c | 219 | |
6b5538d4 | 220 | omap_irq_ocp_error_handler(irqstatus); |
728ae8dd LP |
221 | omap_irq_fifo_underflow(priv, irqstatus); |
222 | ||
84e1d457 | 223 | spin_lock_irqsave(&priv->wait_lock, flags); |
80f91bff LP |
224 | list_for_each_entry_safe(wait, n, &priv->wait_list, node) { |
225 | if (wait->irqmask & irqstatus) | |
226 | omap_irq_wait_handler(wait); | |
f5f9454c | 227 | } |
84e1d457 | 228 | spin_unlock_irqrestore(&priv->wait_lock, flags); |
f5f9454c RC |
229 | |
230 | return IRQ_HANDLED; | |
231 | } | |
232 | ||
728ae8dd LP |
233 | static const u32 omap_underflow_irqs[] = { |
234 | [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW, | |
235 | [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW, | |
236 | [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW, | |
237 | [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW, | |
238 | }; | |
239 | ||
f13ab005 LP |
240 | /* |
241 | * We need a special version, instead of just using drm_irq_install(), | |
242 | * because we need to register the irq via omapdss. Once omapdss and | |
243 | * omapdrm are merged together we can assign the dispc hwmod data to | |
244 | * ourselves and drop these and just use drm_irq_{install,uninstall}() | |
245 | */ | |
f5f9454c | 246 | |
f13ab005 | 247 | int omap_drm_irq_install(struct drm_device *dev) |
f5f9454c RC |
248 | { |
249 | struct omap_drm_private *priv = dev->dev_private; | |
e0519af7 | 250 | unsigned int num_mgrs = dss_feat_get_num_mgrs(); |
728ae8dd LP |
251 | unsigned int max_planes; |
252 | unsigned int i; | |
f13ab005 | 253 | int ret; |
f5f9454c | 254 | |
84e1d457 | 255 | spin_lock_init(&priv->wait_lock); |
80f91bff | 256 | INIT_LIST_HEAD(&priv->wait_list); |
f5f9454c | 257 | |
6b5538d4 | 258 | priv->irq_mask = DISPC_IRQ_OCP_ERR; |
728ae8dd LP |
259 | |
260 | max_planes = min(ARRAY_SIZE(priv->planes), | |
261 | ARRAY_SIZE(omap_underflow_irqs)); | |
262 | for (i = 0; i < max_planes; ++i) { | |
263 | if (priv->planes[i]) | |
264 | priv->irq_mask |= omap_underflow_irqs[i]; | |
265 | } | |
266 | ||
e0519af7 LP |
267 | for (i = 0; i < num_mgrs; ++i) |
268 | priv->irq_mask |= dispc_mgr_get_sync_lost_irq(i); | |
269 | ||
f13ab005 LP |
270 | dispc_runtime_get(); |
271 | dispc_clear_irqstatus(0xffffffff); | |
272 | dispc_runtime_put(); | |
273 | ||
274 | ret = dispc_request_irq(omap_irq_handler, dev); | |
275 | if (ret < 0) | |
276 | return ret; | |
277 | ||
4423843c | 278 | dev->irq_enabled = true; |
f5f9454c | 279 | |
f13ab005 | 280 | return 0; |
f5f9454c RC |
281 | } |
282 | ||
f13ab005 | 283 | void omap_drm_irq_uninstall(struct drm_device *dev) |
f5f9454c RC |
284 | { |
285 | unsigned long irqflags; | |
4423843c | 286 | int i; |
f5f9454c | 287 | |
f13ab005 LP |
288 | if (!dev->irq_enabled) |
289 | return; | |
290 | ||
4423843c | 291 | dev->irq_enabled = false; |
f5f9454c | 292 | |
f13ab005 | 293 | /* Wake up any waiters so they don't hang. */ |
f5f9454c RC |
294 | if (dev->num_crtcs) { |
295 | spin_lock_irqsave(&dev->vbl_lock, irqflags); | |
296 | for (i = 0; i < dev->num_crtcs; i++) { | |
57ed0f7b | 297 | wake_up(&dev->vblank[i].queue); |
5380e929 VS |
298 | dev->vblank[i].enabled = false; |
299 | dev->vblank[i].last = | |
f5f9454c RC |
300 | dev->driver->get_vblank_counter(dev, i); |
301 | } | |
302 | spin_unlock_irqrestore(&dev->vbl_lock, irqflags); | |
303 | } | |
304 | ||
f5f9454c | 305 | dispc_free_irq(dev); |
f5f9454c | 306 | } |