]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc_helper.h> | |
28 | #include <drm/radeon_drm.h> | |
68adac5e | 29 | #include <drm/drm_fixed.h> |
771fe6b9 JG |
30 | #include "radeon.h" |
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
33 | ||
c93bb85b JG |
34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
35 | struct drm_display_mode *mode, | |
36 | struct drm_display_mode *adjusted_mode) | |
37 | { | |
38 | struct drm_device *dev = crtc->dev; | |
39 | struct radeon_device *rdev = dev->dev_private; | |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; | |
42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); | |
43 | int a1, a2; | |
44 | ||
45 | memset(&args, 0, sizeof(args)); | |
46 | ||
c93bb85b JG |
47 | args.ucCRTC = radeon_crtc->crtc_id; |
48 | ||
49 | switch (radeon_crtc->rmx_type) { | |
50 | case RMX_CENTER: | |
4589433c CC |
51 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
52 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); | |
53 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); | |
54 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); | |
c93bb85b JG |
55 | break; |
56 | case RMX_ASPECT: | |
57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; | |
58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; | |
59 | ||
60 | if (a1 > a2) { | |
4589433c CC |
61 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
62 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); | |
c93bb85b | 63 | } else if (a2 > a1) { |
942b0e95 AD |
64 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
65 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); | |
c93bb85b | 66 | } |
c93bb85b JG |
67 | break; |
68 | case RMX_FULL: | |
69 | default: | |
4589433c CC |
70 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
71 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); | |
72 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); | |
73 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); | |
c93bb85b JG |
74 | break; |
75 | } | |
5b1714d3 | 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
c93bb85b JG |
77 | } |
78 | ||
79 | static void atombios_scaler_setup(struct drm_crtc *crtc) | |
80 | { | |
81 | struct drm_device *dev = crtc->dev; | |
82 | struct radeon_device *rdev = dev->dev_private; | |
83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
84 | ENABLE_SCALER_PS_ALLOCATION args; | |
85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); | |
4ce001ab | 86 | |
c93bb85b JG |
87 | /* fixme - fill in enc_priv for atom dac */ |
88 | enum radeon_tv_std tv_std = TV_STD_NTSC; | |
4ce001ab DA |
89 | bool is_tv = false, is_cv = false; |
90 | struct drm_encoder *encoder; | |
c93bb85b JG |
91 | |
92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) | |
93 | return; | |
94 | ||
4ce001ab DA |
95 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
96 | /* find tv std */ | |
97 | if (encoder->crtc == crtc) { | |
98 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
99 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { | |
100 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; | |
101 | tv_std = tv_dac->tv_std; | |
102 | is_tv = true; | |
103 | } | |
104 | } | |
105 | } | |
106 | ||
c93bb85b JG |
107 | memset(&args, 0, sizeof(args)); |
108 | ||
109 | args.ucScaler = radeon_crtc->crtc_id; | |
110 | ||
4ce001ab | 111 | if (is_tv) { |
c93bb85b JG |
112 | switch (tv_std) { |
113 | case TV_STD_NTSC: | |
114 | default: | |
115 | args.ucTVStandard = ATOM_TV_NTSC; | |
116 | break; | |
117 | case TV_STD_PAL: | |
118 | args.ucTVStandard = ATOM_TV_PAL; | |
119 | break; | |
120 | case TV_STD_PAL_M: | |
121 | args.ucTVStandard = ATOM_TV_PALM; | |
122 | break; | |
123 | case TV_STD_PAL_60: | |
124 | args.ucTVStandard = ATOM_TV_PAL60; | |
125 | break; | |
126 | case TV_STD_NTSC_J: | |
127 | args.ucTVStandard = ATOM_TV_NTSCJ; | |
128 | break; | |
129 | case TV_STD_SCART_PAL: | |
130 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ | |
131 | break; | |
132 | case TV_STD_SECAM: | |
133 | args.ucTVStandard = ATOM_TV_SECAM; | |
134 | break; | |
135 | case TV_STD_PAL_CN: | |
136 | args.ucTVStandard = ATOM_TV_PALCN; | |
137 | break; | |
138 | } | |
139 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | |
4ce001ab | 140 | } else if (is_cv) { |
c93bb85b JG |
141 | args.ucTVStandard = ATOM_TV_CV; |
142 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | |
143 | } else { | |
144 | switch (radeon_crtc->rmx_type) { | |
145 | case RMX_FULL: | |
146 | args.ucEnable = ATOM_SCALER_EXPANSION; | |
147 | break; | |
148 | case RMX_CENTER: | |
149 | args.ucEnable = ATOM_SCALER_CENTER; | |
150 | break; | |
151 | case RMX_ASPECT: | |
152 | args.ucEnable = ATOM_SCALER_EXPANSION; | |
153 | break; | |
154 | default: | |
155 | if (ASIC_IS_AVIVO(rdev)) | |
156 | args.ucEnable = ATOM_SCALER_DISABLE; | |
157 | else | |
158 | args.ucEnable = ATOM_SCALER_CENTER; | |
159 | break; | |
160 | } | |
161 | } | |
162 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
4ce001ab DA |
163 | if ((is_tv || is_cv) |
164 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { | |
165 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); | |
c93bb85b JG |
166 | } |
167 | } | |
168 | ||
771fe6b9 JG |
169 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
170 | { | |
171 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
172 | struct drm_device *dev = crtc->dev; | |
173 | struct radeon_device *rdev = dev->dev_private; | |
174 | int index = | |
175 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); | |
176 | ENABLE_CRTC_PS_ALLOCATION args; | |
177 | ||
178 | memset(&args, 0, sizeof(args)); | |
179 | ||
180 | args.ucCRTC = radeon_crtc->crtc_id; | |
181 | args.ucEnable = lock; | |
182 | ||
183 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
184 | } | |
185 | ||
186 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) | |
187 | { | |
188 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
189 | struct drm_device *dev = crtc->dev; | |
190 | struct radeon_device *rdev = dev->dev_private; | |
191 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); | |
192 | ENABLE_CRTC_PS_ALLOCATION args; | |
193 | ||
194 | memset(&args, 0, sizeof(args)); | |
195 | ||
196 | args.ucCRTC = radeon_crtc->crtc_id; | |
197 | args.ucEnable = state; | |
198 | ||
199 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
200 | } | |
201 | ||
202 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) | |
203 | { | |
204 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
205 | struct drm_device *dev = crtc->dev; | |
206 | struct radeon_device *rdev = dev->dev_private; | |
207 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); | |
208 | ENABLE_CRTC_PS_ALLOCATION args; | |
209 | ||
210 | memset(&args, 0, sizeof(args)); | |
211 | ||
212 | args.ucCRTC = radeon_crtc->crtc_id; | |
213 | args.ucEnable = state; | |
214 | ||
215 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
216 | } | |
217 | ||
218 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) | |
219 | { | |
220 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
221 | struct drm_device *dev = crtc->dev; | |
222 | struct radeon_device *rdev = dev->dev_private; | |
223 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); | |
224 | BLANK_CRTC_PS_ALLOCATION args; | |
225 | ||
226 | memset(&args, 0, sizeof(args)); | |
227 | ||
228 | args.ucCRTC = radeon_crtc->crtc_id; | |
229 | args.ucBlanking = state; | |
230 | ||
231 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
232 | } | |
233 | ||
fef9f91f AD |
234 | static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) |
235 | { | |
236 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
237 | struct drm_device *dev = crtc->dev; | |
238 | struct radeon_device *rdev = dev->dev_private; | |
239 | int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); | |
240 | ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; | |
241 | ||
242 | memset(&args, 0, sizeof(args)); | |
243 | ||
244 | args.ucDispPipeId = radeon_crtc->crtc_id; | |
245 | args.ucEnable = state; | |
246 | ||
247 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
248 | } | |
249 | ||
771fe6b9 JG |
250 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
251 | { | |
252 | struct drm_device *dev = crtc->dev; | |
253 | struct radeon_device *rdev = dev->dev_private; | |
500b7587 | 254 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
255 | |
256 | switch (mode) { | |
257 | case DRM_MODE_DPMS_ON: | |
d7311171 AD |
258 | radeon_crtc->enabled = true; |
259 | /* adjust pm to dpms changes BEFORE enabling crtcs */ | |
260 | radeon_pm_compute_clocks(rdev); | |
6c0ae2ab | 261 | if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) |
fef9f91f | 262 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
37b4390e | 263 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
79f17c64 | 264 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
37b4390e AD |
265 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
266 | atombios_blank_crtc(crtc, ATOM_DISABLE); | |
45f9a39b | 267 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
500b7587 | 268 | radeon_crtc_load_lut(crtc); |
771fe6b9 JG |
269 | break; |
270 | case DRM_MODE_DPMS_STANDBY: | |
271 | case DRM_MODE_DPMS_SUSPEND: | |
272 | case DRM_MODE_DPMS_OFF: | |
45f9a39b | 273 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
a93f344d AD |
274 | if (radeon_crtc->enabled) |
275 | atombios_blank_crtc(crtc, ATOM_ENABLE); | |
79f17c64 | 276 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
37b4390e AD |
277 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
278 | atombios_enable_crtc(crtc, ATOM_DISABLE); | |
a48b9b4e | 279 | radeon_crtc->enabled = false; |
c205b232 AD |
280 | if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) |
281 | atombios_powergate_crtc(crtc, ATOM_ENABLE); | |
d7311171 AD |
282 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
283 | radeon_pm_compute_clocks(rdev); | |
771fe6b9 JG |
284 | break; |
285 | } | |
771fe6b9 JG |
286 | } |
287 | ||
288 | static void | |
289 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, | |
5a9bcacc | 290 | struct drm_display_mode *mode) |
771fe6b9 | 291 | { |
5a9bcacc | 292 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
293 | struct drm_device *dev = crtc->dev; |
294 | struct radeon_device *rdev = dev->dev_private; | |
5a9bcacc | 295 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
771fe6b9 | 296 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
5a9bcacc | 297 | u16 misc = 0; |
771fe6b9 | 298 | |
5a9bcacc | 299 | memset(&args, 0, sizeof(args)); |
5b1714d3 | 300 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
5a9bcacc | 301 | args.usH_Blanking_Time = |
5b1714d3 AD |
302 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
303 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); | |
5a9bcacc | 304 | args.usV_Blanking_Time = |
5b1714d3 | 305 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
5a9bcacc | 306 | args.usH_SyncOffset = |
5b1714d3 | 307 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
5a9bcacc AD |
308 | args.usH_SyncWidth = |
309 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); | |
310 | args.usV_SyncOffset = | |
5b1714d3 | 311 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
5a9bcacc AD |
312 | args.usV_SyncWidth = |
313 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); | |
5b1714d3 AD |
314 | args.ucH_Border = radeon_crtc->h_border; |
315 | args.ucV_Border = radeon_crtc->v_border; | |
5a9bcacc AD |
316 | |
317 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
318 | misc |= ATOM_VSYNC_POLARITY; | |
319 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
320 | misc |= ATOM_HSYNC_POLARITY; | |
321 | if (mode->flags & DRM_MODE_FLAG_CSYNC) | |
322 | misc |= ATOM_COMPOSITESYNC; | |
323 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
324 | misc |= ATOM_INTERLACE; | |
325 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
326 | misc |= ATOM_DOUBLE_CLOCK_MODE; | |
327 | ||
328 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); | |
329 | args.ucCRTC = radeon_crtc->crtc_id; | |
771fe6b9 | 330 | |
5a9bcacc | 331 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
771fe6b9 JG |
332 | } |
333 | ||
5a9bcacc AD |
334 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
335 | struct drm_display_mode *mode) | |
771fe6b9 | 336 | { |
5a9bcacc | 337 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
338 | struct drm_device *dev = crtc->dev; |
339 | struct radeon_device *rdev = dev->dev_private; | |
5a9bcacc | 340 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
771fe6b9 | 341 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
5a9bcacc | 342 | u16 misc = 0; |
771fe6b9 | 343 | |
5a9bcacc AD |
344 | memset(&args, 0, sizeof(args)); |
345 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); | |
346 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); | |
347 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); | |
348 | args.usH_SyncWidth = | |
349 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); | |
350 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); | |
351 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); | |
352 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); | |
353 | args.usV_SyncWidth = | |
354 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); | |
355 | ||
54bfe496 AD |
356 | args.ucOverscanRight = radeon_crtc->h_border; |
357 | args.ucOverscanLeft = radeon_crtc->h_border; | |
358 | args.ucOverscanBottom = radeon_crtc->v_border; | |
359 | args.ucOverscanTop = radeon_crtc->v_border; | |
360 | ||
5a9bcacc AD |
361 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
362 | misc |= ATOM_VSYNC_POLARITY; | |
363 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
364 | misc |= ATOM_HSYNC_POLARITY; | |
365 | if (mode->flags & DRM_MODE_FLAG_CSYNC) | |
366 | misc |= ATOM_COMPOSITESYNC; | |
367 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
368 | misc |= ATOM_INTERLACE; | |
369 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
370 | misc |= ATOM_DOUBLE_CLOCK_MODE; | |
371 | ||
372 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); | |
373 | args.ucCRTC = radeon_crtc->crtc_id; | |
771fe6b9 | 374 | |
5a9bcacc | 375 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
771fe6b9 JG |
376 | } |
377 | ||
3fa47d9e | 378 | static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) |
b792210e | 379 | { |
b792210e AD |
380 | u32 ss_cntl; |
381 | ||
382 | if (ASIC_IS_DCE4(rdev)) { | |
3fa47d9e | 383 | switch (pll_id) { |
b792210e AD |
384 | case ATOM_PPLL1: |
385 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); | |
386 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; | |
387 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); | |
388 | break; | |
389 | case ATOM_PPLL2: | |
390 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); | |
391 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; | |
392 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); | |
393 | break; | |
394 | case ATOM_DCPLL: | |
395 | case ATOM_PPLL_INVALID: | |
396 | return; | |
397 | } | |
398 | } else if (ASIC_IS_AVIVO(rdev)) { | |
3fa47d9e | 399 | switch (pll_id) { |
b792210e AD |
400 | case ATOM_PPLL1: |
401 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); | |
402 | ss_cntl &= ~1; | |
403 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); | |
404 | break; | |
405 | case ATOM_PPLL2: | |
406 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); | |
407 | ss_cntl &= ~1; | |
408 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); | |
409 | break; | |
410 | case ATOM_DCPLL: | |
411 | case ATOM_PPLL_INVALID: | |
412 | return; | |
413 | } | |
414 | } | |
415 | } | |
416 | ||
417 | ||
26b9fc3a | 418 | union atom_enable_ss { |
ba032a58 AD |
419 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
420 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; | |
26b9fc3a | 421 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
ba032a58 | 422 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
a572eaa3 | 423 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
26b9fc3a AD |
424 | }; |
425 | ||
3fa47d9e | 426 | static void atombios_crtc_program_ss(struct radeon_device *rdev, |
ba032a58 AD |
427 | int enable, |
428 | int pll_id, | |
5efcc76c | 429 | int crtc_id, |
ba032a58 | 430 | struct radeon_atom_ss *ss) |
ebbe1cb9 | 431 | { |
5efcc76c | 432 | unsigned i; |
ebbe1cb9 | 433 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
26b9fc3a | 434 | union atom_enable_ss args; |
ebbe1cb9 | 435 | |
5efcc76c | 436 | if (!enable) { |
53176706 | 437 | for (i = 0; i < rdev->num_crtc; i++) { |
5efcc76c JG |
438 | if (rdev->mode_info.crtcs[i] && |
439 | rdev->mode_info.crtcs[i]->enabled && | |
440 | i != crtc_id && | |
441 | pll_id == rdev->mode_info.crtcs[i]->pll_id) { | |
442 | /* one other crtc is using this pll don't turn | |
443 | * off spread spectrum as it might turn off | |
444 | * display on active crtc | |
445 | */ | |
446 | return; | |
447 | } | |
448 | } | |
449 | } | |
450 | ||
ba032a58 | 451 | memset(&args, 0, sizeof(args)); |
bcc1c2a1 | 452 | |
a572eaa3 | 453 | if (ASIC_IS_DCE5(rdev)) { |
4589433c | 454 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
8e8e523d | 455 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
a572eaa3 AD |
456 | switch (pll_id) { |
457 | case ATOM_PPLL1: | |
458 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; | |
a572eaa3 AD |
459 | break; |
460 | case ATOM_PPLL2: | |
461 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; | |
a572eaa3 AD |
462 | break; |
463 | case ATOM_DCPLL: | |
464 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; | |
a572eaa3 AD |
465 | break; |
466 | case ATOM_PPLL_INVALID: | |
467 | return; | |
468 | } | |
f312f093 AD |
469 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
470 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
d0ae3e89 | 471 | args.v3.ucEnable = enable; |
0671bdd7 | 472 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) |
8e8e523d | 473 | args.v3.ucEnable = ATOM_DISABLE; |
a572eaa3 | 474 | } else if (ASIC_IS_DCE4(rdev)) { |
ba032a58 | 475 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
8e8e523d | 476 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
477 | switch (pll_id) { |
478 | case ATOM_PPLL1: | |
479 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; | |
ba032a58 AD |
480 | break; |
481 | case ATOM_PPLL2: | |
482 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; | |
ebbe1cb9 | 483 | break; |
ba032a58 AD |
484 | case ATOM_DCPLL: |
485 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; | |
ba032a58 AD |
486 | break; |
487 | case ATOM_PPLL_INVALID: | |
488 | return; | |
ebbe1cb9 | 489 | } |
f312f093 AD |
490 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
491 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
ba032a58 | 492 | args.v2.ucEnable = enable; |
09cc6506 | 493 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) |
8e8e523d | 494 | args.v2.ucEnable = ATOM_DISABLE; |
ba032a58 AD |
495 | } else if (ASIC_IS_DCE3(rdev)) { |
496 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 497 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
498 | args.v1.ucSpreadSpectrumStep = ss->step; |
499 | args.v1.ucSpreadSpectrumDelay = ss->delay; | |
500 | args.v1.ucSpreadSpectrumRange = ss->range; | |
501 | args.v1.ucPpll = pll_id; | |
502 | args.v1.ucEnable = enable; | |
503 | } else if (ASIC_IS_AVIVO(rdev)) { | |
8e8e523d AD |
504 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
505 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { | |
3fa47d9e | 506 | atombios_disable_ss(rdev, pll_id); |
ba032a58 AD |
507 | return; |
508 | } | |
509 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 510 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
511 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
512 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; | |
513 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; | |
514 | args.lvds_ss_2.ucEnable = enable; | |
ebbe1cb9 | 515 | } else { |
8e8e523d AD |
516 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
517 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { | |
3fa47d9e | 518 | atombios_disable_ss(rdev, pll_id); |
ba032a58 AD |
519 | return; |
520 | } | |
521 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 522 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
523 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
524 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; | |
525 | args.lvds_ss.ucEnable = enable; | |
ebbe1cb9 | 526 | } |
26b9fc3a | 527 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
ebbe1cb9 AD |
528 | } |
529 | ||
4eaeca33 AD |
530 | union adjust_pixel_clock { |
531 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; | |
bcc1c2a1 | 532 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
4eaeca33 AD |
533 | }; |
534 | ||
535 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |
19eca43e | 536 | struct drm_display_mode *mode) |
771fe6b9 | 537 | { |
19eca43e | 538 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
539 | struct drm_device *dev = crtc->dev; |
540 | struct radeon_device *rdev = dev->dev_private; | |
541 | struct drm_encoder *encoder = NULL; | |
542 | struct radeon_encoder *radeon_encoder = NULL; | |
df271bec | 543 | struct drm_connector *connector = NULL; |
4eaeca33 | 544 | u32 adjusted_clock = mode->clock; |
bcc1c2a1 | 545 | int encoder_mode = 0; |
fbee67a6 AD |
546 | u32 dp_clock = mode->clock; |
547 | int bpc = 8; | |
9aa59993 | 548 | bool is_duallink = false; |
fc10332b | 549 | |
4eaeca33 | 550 | /* reset the pll flags */ |
19eca43e | 551 | radeon_crtc->pll_flags = 0; |
771fe6b9 JG |
552 | |
553 | if (ASIC_IS_AVIVO(rdev)) { | |
eb1300bc AD |
554 | if ((rdev->family == CHIP_RS600) || |
555 | (rdev->family == CHIP_RS690) || | |
556 | (rdev->family == CHIP_RS740)) | |
19eca43e AD |
557 | radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
558 | RADEON_PLL_PREFER_CLOSEST_LOWER); | |
5480f727 DA |
559 | |
560 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ | |
19eca43e | 561 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
5480f727 | 562 | else |
19eca43e | 563 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
9bb09fa1 | 564 | |
5785e53f | 565 | if (rdev->family < CHIP_RV770) |
19eca43e | 566 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
37d4174d AD |
567 | /* use frac fb div on APUs */ |
568 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) | |
19eca43e | 569 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
5480f727 | 570 | } else { |
19eca43e | 571 | radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; |
771fe6b9 | 572 | |
5480f727 | 573 | if (mode->clock > 200000) /* range limits??? */ |
19eca43e | 574 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
5480f727 | 575 | else |
19eca43e | 576 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
5480f727 DA |
577 | } |
578 | ||
771fe6b9 JG |
579 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
580 | if (encoder->crtc == crtc) { | |
4eaeca33 | 581 | radeon_encoder = to_radeon_encoder(encoder); |
df271bec | 582 | connector = radeon_get_connector_for_encoder(encoder); |
eccea792 | 583 | bpc = radeon_get_monitor_bpc(connector); |
bcc1c2a1 | 584 | encoder_mode = atombios_get_encoder_mode(encoder); |
9aa59993 | 585 | is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
eac4dff6 | 586 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
1d33e1fc | 587 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
fbee67a6 AD |
588 | if (connector) { |
589 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
590 | struct radeon_connector_atom_dig *dig_connector = | |
591 | radeon_connector->con_priv; | |
592 | ||
593 | dp_clock = dig_connector->dp_clock; | |
594 | } | |
595 | } | |
5b40ddf8 | 596 | |
ba032a58 AD |
597 | /* use recommended ref_div for ss */ |
598 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
19eca43e AD |
599 | if (radeon_crtc->ss_enabled) { |
600 | if (radeon_crtc->ss.refdiv) { | |
601 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | |
602 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; | |
5b40ddf8 | 603 | if (ASIC_IS_AVIVO(rdev)) |
19eca43e | 604 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
ba032a58 AD |
605 | } |
606 | } | |
607 | } | |
5b40ddf8 | 608 | |
4eaeca33 AD |
609 | if (ASIC_IS_AVIVO(rdev)) { |
610 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ | |
611 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) | |
612 | adjusted_clock = mode->clock * 2; | |
48dfaaeb | 613 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
19eca43e | 614 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
5b40ddf8 | 615 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
19eca43e | 616 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; |
4eaeca33 AD |
617 | } else { |
618 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) | |
19eca43e | 619 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
4eaeca33 | 620 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
19eca43e | 621 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; |
771fe6b9 | 622 | } |
3ce0a23d | 623 | break; |
771fe6b9 JG |
624 | } |
625 | } | |
626 | ||
2606c886 AD |
627 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
628 | * accordingly based on the encoder/transmitter to work around | |
629 | * special hw requirements. | |
630 | */ | |
631 | if (ASIC_IS_DCE3(rdev)) { | |
4eaeca33 | 632 | union adjust_pixel_clock args; |
4eaeca33 AD |
633 | u8 frev, crev; |
634 | int index; | |
2606c886 | 635 | |
2606c886 | 636 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
a084e6ee AD |
637 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
638 | &crev)) | |
639 | return adjusted_clock; | |
4eaeca33 AD |
640 | |
641 | memset(&args, 0, sizeof(args)); | |
642 | ||
643 | switch (frev) { | |
644 | case 1: | |
645 | switch (crev) { | |
646 | case 1: | |
647 | case 2: | |
648 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); | |
649 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; | |
bcc1c2a1 | 650 | args.v1.ucEncodeMode = encoder_mode; |
19eca43e | 651 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
fbee67a6 AD |
652 | args.v1.ucConfig |= |
653 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; | |
4eaeca33 AD |
654 | |
655 | atom_execute_table(rdev->mode_info.atom_context, | |
656 | index, (uint32_t *)&args); | |
657 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; | |
658 | break; | |
bcc1c2a1 AD |
659 | case 3: |
660 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); | |
661 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; | |
662 | args.v3.sInput.ucEncodeMode = encoder_mode; | |
663 | args.v3.sInput.ucDispPllConfig = 0; | |
19eca43e | 664 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
b526ce22 AD |
665 | args.v3.sInput.ucDispPllConfig |= |
666 | DISPPLL_CONFIG_SS_ENABLE; | |
996d5c59 | 667 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
b4f15f80 AD |
668 | args.v3.sInput.ucDispPllConfig |= |
669 | DISPPLL_CONFIG_COHERENT_MODE; | |
670 | /* 16200 or 27000 */ | |
671 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | |
672 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
bcc1c2a1 | 673 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
b4f15f80 AD |
674 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
675 | /* deep color support */ | |
676 | args.v3.sInput.usPixelClock = | |
677 | cpu_to_le16((mode->clock * bpc / 8) / 10); | |
678 | if (dig->coherent_mode) | |
bcc1c2a1 AD |
679 | args.v3.sInput.ucDispPllConfig |= |
680 | DISPPLL_CONFIG_COHERENT_MODE; | |
9aa59993 | 681 | if (is_duallink) |
bcc1c2a1 | 682 | args.v3.sInput.ucDispPllConfig |= |
b4f15f80 | 683 | DISPPLL_CONFIG_DUAL_LINK; |
bcc1c2a1 | 684 | } |
1d33e1fc AD |
685 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
686 | ENCODER_OBJECT_ID_NONE) | |
687 | args.v3.sInput.ucExtTransmitterID = | |
688 | radeon_encoder_get_dp_bridge_encoder_id(encoder); | |
689 | else | |
cc9f67a0 AD |
690 | args.v3.sInput.ucExtTransmitterID = 0; |
691 | ||
bcc1c2a1 AD |
692 | atom_execute_table(rdev->mode_info.atom_context, |
693 | index, (uint32_t *)&args); | |
694 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; | |
695 | if (args.v3.sOutput.ucRefDiv) { | |
19eca43e AD |
696 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
697 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | |
698 | radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; | |
bcc1c2a1 AD |
699 | } |
700 | if (args.v3.sOutput.ucPostDiv) { | |
19eca43e AD |
701 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
702 | radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; | |
703 | radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; | |
bcc1c2a1 AD |
704 | } |
705 | break; | |
4eaeca33 AD |
706 | default: |
707 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
708 | return adjusted_clock; | |
709 | } | |
710 | break; | |
711 | default: | |
712 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
713 | return adjusted_clock; | |
714 | } | |
d56ef9c8 | 715 | } |
4eaeca33 AD |
716 | return adjusted_clock; |
717 | } | |
718 | ||
719 | union set_pixel_clock { | |
720 | SET_PIXEL_CLOCK_PS_ALLOCATION base; | |
721 | PIXEL_CLOCK_PARAMETERS v1; | |
722 | PIXEL_CLOCK_PARAMETERS_V2 v2; | |
723 | PIXEL_CLOCK_PARAMETERS_V3 v3; | |
bcc1c2a1 | 724 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
f82b3ddc | 725 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
4eaeca33 AD |
726 | }; |
727 | ||
f82b3ddc AD |
728 | /* on DCE5, make sure the voltage is high enough to support the |
729 | * required disp clk. | |
730 | */ | |
f3f1f03e | 731 | static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, |
f82b3ddc | 732 | u32 dispclk) |
bcc1c2a1 | 733 | { |
bcc1c2a1 AD |
734 | u8 frev, crev; |
735 | int index; | |
736 | union set_pixel_clock args; | |
737 | ||
738 | memset(&args, 0, sizeof(args)); | |
739 | ||
740 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); | |
a084e6ee AD |
741 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
742 | &crev)) | |
743 | return; | |
bcc1c2a1 AD |
744 | |
745 | switch (frev) { | |
746 | case 1: | |
747 | switch (crev) { | |
748 | case 5: | |
749 | /* if the default dcpll clock is specified, | |
750 | * SetPixelClock provides the dividers | |
751 | */ | |
752 | args.v5.ucCRTC = ATOM_CRTC_INVALID; | |
4589433c | 753 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
bcc1c2a1 AD |
754 | args.v5.ucPpll = ATOM_DCPLL; |
755 | break; | |
f82b3ddc AD |
756 | case 6: |
757 | /* if the default dcpll clock is specified, | |
758 | * SetPixelClock provides the dividers | |
759 | */ | |
265aa6c8 | 760 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
729b95ef AD |
761 | if (ASIC_IS_DCE61(rdev)) |
762 | args.v6.ucPpll = ATOM_EXT_PLL1; | |
763 | else if (ASIC_IS_DCE6(rdev)) | |
f3f1f03e AD |
764 | args.v6.ucPpll = ATOM_PPLL0; |
765 | else | |
766 | args.v6.ucPpll = ATOM_DCPLL; | |
f82b3ddc | 767 | break; |
bcc1c2a1 AD |
768 | default: |
769 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
770 | return; | |
771 | } | |
772 | break; | |
773 | default: | |
774 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
775 | return; | |
776 | } | |
777 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
778 | } | |
779 | ||
37f9003b | 780 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
f1bece7f | 781 | u32 crtc_id, |
37f9003b AD |
782 | int pll_id, |
783 | u32 encoder_mode, | |
784 | u32 encoder_id, | |
785 | u32 clock, | |
786 | u32 ref_div, | |
787 | u32 fb_div, | |
788 | u32 frac_fb_div, | |
df271bec | 789 | u32 post_div, |
8e8e523d AD |
790 | int bpc, |
791 | bool ss_enabled, | |
792 | struct radeon_atom_ss *ss) | |
4eaeca33 | 793 | { |
4eaeca33 AD |
794 | struct drm_device *dev = crtc->dev; |
795 | struct radeon_device *rdev = dev->dev_private; | |
4eaeca33 | 796 | u8 frev, crev; |
37f9003b | 797 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
4eaeca33 | 798 | union set_pixel_clock args; |
4eaeca33 AD |
799 | |
800 | memset(&args, 0, sizeof(args)); | |
801 | ||
a084e6ee AD |
802 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
803 | &crev)) | |
804 | return; | |
771fe6b9 JG |
805 | |
806 | switch (frev) { | |
807 | case 1: | |
808 | switch (crev) { | |
809 | case 1: | |
37f9003b AD |
810 | if (clock == ATOM_DISABLE) |
811 | return; | |
812 | args.v1.usPixelClock = cpu_to_le16(clock / 10); | |
4eaeca33 AD |
813 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
814 | args.v1.usFbDiv = cpu_to_le16(fb_div); | |
815 | args.v1.ucFracFbDiv = frac_fb_div; | |
816 | args.v1.ucPostDiv = post_div; | |
37f9003b AD |
817 | args.v1.ucPpll = pll_id; |
818 | args.v1.ucCRTC = crtc_id; | |
4eaeca33 | 819 | args.v1.ucRefDivSrc = 1; |
771fe6b9 JG |
820 | break; |
821 | case 2: | |
37f9003b | 822 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
4eaeca33 AD |
823 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
824 | args.v2.usFbDiv = cpu_to_le16(fb_div); | |
825 | args.v2.ucFracFbDiv = frac_fb_div; | |
826 | args.v2.ucPostDiv = post_div; | |
37f9003b AD |
827 | args.v2.ucPpll = pll_id; |
828 | args.v2.ucCRTC = crtc_id; | |
4eaeca33 | 829 | args.v2.ucRefDivSrc = 1; |
771fe6b9 JG |
830 | break; |
831 | case 3: | |
37f9003b | 832 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
4eaeca33 AD |
833 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
834 | args.v3.usFbDiv = cpu_to_le16(fb_div); | |
835 | args.v3.ucFracFbDiv = frac_fb_div; | |
836 | args.v3.ucPostDiv = post_div; | |
37f9003b | 837 | args.v3.ucPpll = pll_id; |
e729586e AD |
838 | if (crtc_id == ATOM_CRTC2) |
839 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; | |
840 | else | |
841 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; | |
6f15c506 AD |
842 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
843 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; | |
37f9003b | 844 | args.v3.ucTransmitterId = encoder_id; |
bcc1c2a1 AD |
845 | args.v3.ucEncoderMode = encoder_mode; |
846 | break; | |
847 | case 5: | |
37f9003b AD |
848 | args.v5.ucCRTC = crtc_id; |
849 | args.v5.usPixelClock = cpu_to_le16(clock / 10); | |
bcc1c2a1 AD |
850 | args.v5.ucRefDiv = ref_div; |
851 | args.v5.usFbDiv = cpu_to_le16(fb_div); | |
852 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); | |
853 | args.v5.ucPostDiv = post_div; | |
854 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ | |
8e8e523d AD |
855 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
856 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; | |
df271bec AD |
857 | switch (bpc) { |
858 | case 8: | |
859 | default: | |
860 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; | |
861 | break; | |
862 | case 10: | |
863 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; | |
864 | break; | |
865 | } | |
37f9003b | 866 | args.v5.ucTransmitterID = encoder_id; |
bcc1c2a1 | 867 | args.v5.ucEncoderMode = encoder_mode; |
37f9003b | 868 | args.v5.ucPpll = pll_id; |
771fe6b9 | 869 | break; |
f82b3ddc | 870 | case 6: |
f1bece7f | 871 | args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); |
f82b3ddc AD |
872 | args.v6.ucRefDiv = ref_div; |
873 | args.v6.usFbDiv = cpu_to_le16(fb_div); | |
874 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); | |
875 | args.v6.ucPostDiv = post_div; | |
876 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ | |
8e8e523d AD |
877 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
878 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; | |
df271bec AD |
879 | switch (bpc) { |
880 | case 8: | |
881 | default: | |
882 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; | |
883 | break; | |
884 | case 10: | |
885 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; | |
886 | break; | |
887 | case 12: | |
888 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; | |
889 | break; | |
890 | case 16: | |
891 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; | |
892 | break; | |
893 | } | |
f82b3ddc AD |
894 | args.v6.ucTransmitterID = encoder_id; |
895 | args.v6.ucEncoderMode = encoder_mode; | |
896 | args.v6.ucPpll = pll_id; | |
897 | break; | |
771fe6b9 JG |
898 | default: |
899 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
900 | return; | |
901 | } | |
902 | break; | |
903 | default: | |
904 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
905 | return; | |
906 | } | |
907 | ||
771fe6b9 JG |
908 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
909 | } | |
910 | ||
19eca43e | 911 | static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
37f9003b AD |
912 | { |
913 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
914 | struct drm_device *dev = crtc->dev; | |
915 | struct radeon_device *rdev = dev->dev_private; | |
916 | struct drm_encoder *encoder = NULL; | |
917 | struct radeon_encoder *radeon_encoder = NULL; | |
37f9003b | 918 | int encoder_mode = 0; |
19eca43e AD |
919 | |
920 | radeon_crtc->bpc = 8; | |
921 | radeon_crtc->ss_enabled = false; | |
37f9003b AD |
922 | |
923 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
924 | if (encoder->crtc == crtc) { | |
925 | radeon_encoder = to_radeon_encoder(encoder); | |
926 | encoder_mode = atombios_get_encoder_mode(encoder); | |
927 | break; | |
928 | } | |
929 | } | |
930 | ||
931 | if (!radeon_encoder) | |
19eca43e | 932 | return false; |
37f9003b | 933 | |
700698e7 AD |
934 | if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
935 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { | |
ba032a58 AD |
936 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
937 | struct drm_connector *connector = | |
938 | radeon_get_connector_for_encoder(encoder); | |
939 | struct radeon_connector *radeon_connector = | |
940 | to_radeon_connector(connector); | |
941 | struct radeon_connector_atom_dig *dig_connector = | |
942 | radeon_connector->con_priv; | |
943 | int dp_clock; | |
19eca43e | 944 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
ba032a58 AD |
945 | |
946 | switch (encoder_mode) { | |
996d5c59 | 947 | case ATOM_ENCODER_MODE_DP_MST: |
ba032a58 AD |
948 | case ATOM_ENCODER_MODE_DP: |
949 | /* DP/eDP */ | |
950 | dp_clock = dig_connector->dp_clock / 10; | |
2307790f | 951 | if (ASIC_IS_DCE4(rdev)) |
19eca43e AD |
952 | radeon_crtc->ss_enabled = |
953 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, | |
2307790f AD |
954 | ASIC_INTERNAL_SS_ON_DP, |
955 | dp_clock); | |
956 | else { | |
957 | if (dp_clock == 16200) { | |
19eca43e AD |
958 | radeon_crtc->ss_enabled = |
959 | radeon_atombios_get_ppll_ss_info(rdev, | |
960 | &radeon_crtc->ss, | |
2307790f | 961 | ATOM_DP_SS_ID2); |
19eca43e AD |
962 | if (!radeon_crtc->ss_enabled) |
963 | radeon_crtc->ss_enabled = | |
964 | radeon_atombios_get_ppll_ss_info(rdev, | |
965 | &radeon_crtc->ss, | |
2307790f | 966 | ATOM_DP_SS_ID1); |
8e8e523d | 967 | } else |
19eca43e AD |
968 | radeon_crtc->ss_enabled = |
969 | radeon_atombios_get_ppll_ss_info(rdev, | |
970 | &radeon_crtc->ss, | |
2307790f | 971 | ATOM_DP_SS_ID1); |
ba032a58 AD |
972 | } |
973 | break; | |
974 | case ATOM_ENCODER_MODE_LVDS: | |
975 | if (ASIC_IS_DCE4(rdev)) | |
19eca43e AD |
976 | radeon_crtc->ss_enabled = |
977 | radeon_atombios_get_asic_ss_info(rdev, | |
978 | &radeon_crtc->ss, | |
979 | dig->lcd_ss_id, | |
980 | mode->clock / 10); | |
ba032a58 | 981 | else |
19eca43e AD |
982 | radeon_crtc->ss_enabled = |
983 | radeon_atombios_get_ppll_ss_info(rdev, | |
984 | &radeon_crtc->ss, | |
985 | dig->lcd_ss_id); | |
ba032a58 AD |
986 | break; |
987 | case ATOM_ENCODER_MODE_DVI: | |
988 | if (ASIC_IS_DCE4(rdev)) | |
19eca43e AD |
989 | radeon_crtc->ss_enabled = |
990 | radeon_atombios_get_asic_ss_info(rdev, | |
991 | &radeon_crtc->ss, | |
ba032a58 AD |
992 | ASIC_INTERNAL_SS_ON_TMDS, |
993 | mode->clock / 10); | |
994 | break; | |
995 | case ATOM_ENCODER_MODE_HDMI: | |
996 | if (ASIC_IS_DCE4(rdev)) | |
19eca43e AD |
997 | radeon_crtc->ss_enabled = |
998 | radeon_atombios_get_asic_ss_info(rdev, | |
999 | &radeon_crtc->ss, | |
ba032a58 AD |
1000 | ASIC_INTERNAL_SS_ON_HDMI, |
1001 | mode->clock / 10); | |
1002 | break; | |
1003 | default: | |
1004 | break; | |
1005 | } | |
1006 | } | |
1007 | ||
37f9003b | 1008 | /* adjust pixel clock as needed */ |
19eca43e AD |
1009 | radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); |
1010 | ||
1011 | return true; | |
1012 | } | |
1013 | ||
1014 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) | |
1015 | { | |
1016 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1017 | struct drm_device *dev = crtc->dev; | |
1018 | struct radeon_device *rdev = dev->dev_private; | |
1019 | struct drm_encoder *encoder = NULL; | |
1020 | struct radeon_encoder *radeon_encoder = NULL; | |
1021 | u32 pll_clock = mode->clock; | |
1022 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; | |
1023 | struct radeon_pll *pll; | |
1024 | int encoder_mode = 0; | |
1025 | ||
1026 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1027 | if (encoder->crtc == crtc) { | |
1028 | radeon_encoder = to_radeon_encoder(encoder); | |
1029 | encoder_mode = atombios_get_encoder_mode(encoder); | |
1030 | break; | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | if (!radeon_encoder) | |
1035 | return; | |
1036 | ||
1037 | switch (radeon_crtc->pll_id) { | |
1038 | case ATOM_PPLL1: | |
1039 | pll = &rdev->clock.p1pll; | |
1040 | break; | |
1041 | case ATOM_PPLL2: | |
1042 | pll = &rdev->clock.p2pll; | |
1043 | break; | |
1044 | case ATOM_DCPLL: | |
1045 | case ATOM_PPLL_INVALID: | |
1046 | default: | |
1047 | pll = &rdev->clock.dcpll; | |
1048 | break; | |
1049 | } | |
1050 | ||
1051 | /* update pll params */ | |
1052 | pll->flags = radeon_crtc->pll_flags; | |
1053 | pll->reference_div = radeon_crtc->pll_reference_div; | |
1054 | pll->post_div = radeon_crtc->pll_post_div; | |
37f9003b | 1055 | |
64146f8b AD |
1056 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1057 | /* TV seems to prefer the legacy algo on some boards */ | |
19eca43e AD |
1058 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1059 | &fb_div, &frac_fb_div, &ref_div, &post_div); | |
64146f8b | 1060 | else if (ASIC_IS_AVIVO(rdev)) |
19eca43e AD |
1061 | radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1062 | &fb_div, &frac_fb_div, &ref_div, &post_div); | |
619efb10 | 1063 | else |
19eca43e AD |
1064 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1065 | &fb_div, &frac_fb_div, &ref_div, &post_div); | |
37f9003b | 1066 | |
19eca43e AD |
1067 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
1068 | radeon_crtc->crtc_id, &radeon_crtc->ss); | |
ba032a58 | 1069 | |
37f9003b AD |
1070 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1071 | encoder_mode, radeon_encoder->encoder_id, mode->clock, | |
19eca43e AD |
1072 | ref_div, fb_div, frac_fb_div, post_div, |
1073 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); | |
37f9003b | 1074 | |
19eca43e | 1075 | if (radeon_crtc->ss_enabled) { |
ba032a58 AD |
1076 | /* calculate ss amount and step size */ |
1077 | if (ASIC_IS_DCE4(rdev)) { | |
1078 | u32 step_size; | |
19eca43e AD |
1079 | u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; |
1080 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; | |
1081 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & | |
ba032a58 | 1082 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
19eca43e AD |
1083 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1084 | step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / | |
ba032a58 AD |
1085 | (125 * 25 * pll->reference_freq / 100); |
1086 | else | |
19eca43e | 1087 | step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / |
ba032a58 | 1088 | (125 * 25 * pll->reference_freq / 100); |
19eca43e | 1089 | radeon_crtc->ss.step = step_size; |
ba032a58 AD |
1090 | } |
1091 | ||
19eca43e AD |
1092 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, |
1093 | radeon_crtc->crtc_id, &radeon_crtc->ss); | |
ba032a58 | 1094 | } |
37f9003b AD |
1095 | } |
1096 | ||
c9417bdd AD |
1097 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
1098 | struct drm_framebuffer *fb, | |
1099 | int x, int y, int atomic) | |
bcc1c2a1 AD |
1100 | { |
1101 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1102 | struct drm_device *dev = crtc->dev; | |
1103 | struct radeon_device *rdev = dev->dev_private; | |
1104 | struct radeon_framebuffer *radeon_fb; | |
4dd19b0d | 1105 | struct drm_framebuffer *target_fb; |
bcc1c2a1 AD |
1106 | struct drm_gem_object *obj; |
1107 | struct radeon_bo *rbo; | |
1108 | uint64_t fb_location; | |
1109 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; | |
285484e2 | 1110 | unsigned bankw, bankh, mtaspect, tile_split; |
fa6bee46 | 1111 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
adcfde51 | 1112 | u32 tmp, viewport_w, viewport_h; |
bcc1c2a1 AD |
1113 | int r; |
1114 | ||
1115 | /* no fb bound */ | |
4dd19b0d | 1116 | if (!atomic && !crtc->fb) { |
d9fdaafb | 1117 | DRM_DEBUG_KMS("No FB bound\n"); |
bcc1c2a1 AD |
1118 | return 0; |
1119 | } | |
1120 | ||
4dd19b0d CB |
1121 | if (atomic) { |
1122 | radeon_fb = to_radeon_framebuffer(fb); | |
1123 | target_fb = fb; | |
1124 | } | |
1125 | else { | |
1126 | radeon_fb = to_radeon_framebuffer(crtc->fb); | |
1127 | target_fb = crtc->fb; | |
1128 | } | |
bcc1c2a1 | 1129 | |
4dd19b0d CB |
1130 | /* If atomic, assume fb object is pinned & idle & fenced and |
1131 | * just update base pointers | |
1132 | */ | |
bcc1c2a1 | 1133 | obj = radeon_fb->obj; |
7e4d15d9 | 1134 | rbo = gem_to_radeon_bo(obj); |
bcc1c2a1 AD |
1135 | r = radeon_bo_reserve(rbo, false); |
1136 | if (unlikely(r != 0)) | |
1137 | return r; | |
4dd19b0d CB |
1138 | |
1139 | if (atomic) | |
1140 | fb_location = radeon_bo_gpu_offset(rbo); | |
1141 | else { | |
1142 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); | |
1143 | if (unlikely(r != 0)) { | |
1144 | radeon_bo_unreserve(rbo); | |
1145 | return -EINVAL; | |
1146 | } | |
bcc1c2a1 | 1147 | } |
4dd19b0d | 1148 | |
bcc1c2a1 AD |
1149 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1150 | radeon_bo_unreserve(rbo); | |
1151 | ||
4dd19b0d | 1152 | switch (target_fb->bits_per_pixel) { |
bcc1c2a1 AD |
1153 | case 8: |
1154 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | | |
1155 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); | |
1156 | break; | |
1157 | case 15: | |
1158 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | |
1159 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); | |
1160 | break; | |
1161 | case 16: | |
1162 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | |
1163 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); | |
fa6bee46 AD |
1164 | #ifdef __BIG_ENDIAN |
1165 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); | |
1166 | #endif | |
bcc1c2a1 AD |
1167 | break; |
1168 | case 24: | |
1169 | case 32: | |
1170 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | | |
1171 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); | |
fa6bee46 AD |
1172 | #ifdef __BIG_ENDIAN |
1173 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); | |
1174 | #endif | |
bcc1c2a1 AD |
1175 | break; |
1176 | default: | |
1177 | DRM_ERROR("Unsupported screen depth %d\n", | |
4dd19b0d | 1178 | target_fb->bits_per_pixel); |
bcc1c2a1 AD |
1179 | return -EINVAL; |
1180 | } | |
1181 | ||
392e3722 | 1182 | if (tiling_flags & RADEON_TILING_MACRO) { |
b7019b2f AD |
1183 | if (rdev->family >= CHIP_TAHITI) |
1184 | tmp = rdev->config.si.tile_config; | |
1185 | else if (rdev->family >= CHIP_CAYMAN) | |
392e3722 AD |
1186 | tmp = rdev->config.cayman.tile_config; |
1187 | else | |
1188 | tmp = rdev->config.evergreen.tile_config; | |
1189 | ||
1190 | switch ((tmp & 0xf0) >> 4) { | |
1191 | case 0: /* 4 banks */ | |
1192 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); | |
1193 | break; | |
1194 | case 1: /* 8 banks */ | |
1195 | default: | |
1196 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); | |
1197 | break; | |
1198 | case 2: /* 16 banks */ | |
1199 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); | |
1200 | break; | |
1201 | } | |
1202 | ||
97d66328 | 1203 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
285484e2 JG |
1204 | |
1205 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); | |
1206 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); | |
1207 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); | |
1208 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); | |
1209 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); | |
392e3722 | 1210 | } else if (tiling_flags & RADEON_TILING_MICRO) |
97d66328 AD |
1211 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
1212 | ||
b7019b2f AD |
1213 | if ((rdev->family == CHIP_TAHITI) || |
1214 | (rdev->family == CHIP_PITCAIRN)) | |
1215 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); | |
1216 | else if (rdev->family == CHIP_VERDE) | |
1217 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); | |
1218 | ||
bcc1c2a1 AD |
1219 | switch (radeon_crtc->crtc_id) { |
1220 | case 0: | |
1221 | WREG32(AVIVO_D1VGA_CONTROL, 0); | |
1222 | break; | |
1223 | case 1: | |
1224 | WREG32(AVIVO_D2VGA_CONTROL, 0); | |
1225 | break; | |
1226 | case 2: | |
1227 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); | |
1228 | break; | |
1229 | case 3: | |
1230 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); | |
1231 | break; | |
1232 | case 4: | |
1233 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); | |
1234 | break; | |
1235 | case 5: | |
1236 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); | |
1237 | break; | |
1238 | default: | |
1239 | break; | |
1240 | } | |
1241 | ||
1242 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
1243 | upper_32_bits(fb_location)); | |
1244 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
1245 | upper_32_bits(fb_location)); | |
1246 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
1247 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); | |
1248 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
1249 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); | |
1250 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); | |
fa6bee46 | 1251 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
bcc1c2a1 AD |
1252 | |
1253 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | |
1254 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | |
1255 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); | |
1256 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); | |
4dd19b0d CB |
1257 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1258 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); | |
bcc1c2a1 | 1259 | |
01f2c773 | 1260 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
bcc1c2a1 AD |
1261 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1262 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); | |
1263 | ||
1264 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, | |
1b619250 | 1265 | target_fb->height); |
bcc1c2a1 AD |
1266 | x &= ~3; |
1267 | y &= ~1; | |
1268 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, | |
1269 | (x << 16) | y); | |
adcfde51 AD |
1270 | viewport_w = crtc->mode.hdisplay; |
1271 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; | |
bcc1c2a1 | 1272 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
adcfde51 | 1273 | (viewport_w << 16) | viewport_h); |
bcc1c2a1 | 1274 | |
fb9674bd AD |
1275 | /* pageflip setup */ |
1276 | /* make sure flip is at vb rather than hb */ | |
1277 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); | |
1278 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; | |
1279 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); | |
1280 | ||
1281 | /* set pageflip to happen anywhere in vblank interval */ | |
1282 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); | |
1283 | ||
4dd19b0d CB |
1284 | if (!atomic && fb && fb != crtc->fb) { |
1285 | radeon_fb = to_radeon_framebuffer(fb); | |
7e4d15d9 | 1286 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
bcc1c2a1 AD |
1287 | r = radeon_bo_reserve(rbo, false); |
1288 | if (unlikely(r != 0)) | |
1289 | return r; | |
1290 | radeon_bo_unpin(rbo); | |
1291 | radeon_bo_unreserve(rbo); | |
1292 | } | |
1293 | ||
1294 | /* Bytes per pixel may have changed */ | |
1295 | radeon_bandwidth_update(rdev); | |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
4dd19b0d CB |
1300 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
1301 | struct drm_framebuffer *fb, | |
1302 | int x, int y, int atomic) | |
771fe6b9 JG |
1303 | { |
1304 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1305 | struct drm_device *dev = crtc->dev; | |
1306 | struct radeon_device *rdev = dev->dev_private; | |
1307 | struct radeon_framebuffer *radeon_fb; | |
1308 | struct drm_gem_object *obj; | |
4c788679 | 1309 | struct radeon_bo *rbo; |
4dd19b0d | 1310 | struct drm_framebuffer *target_fb; |
771fe6b9 | 1311 | uint64_t fb_location; |
e024e110 | 1312 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
fa6bee46 | 1313 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
adcfde51 | 1314 | u32 tmp, viewport_w, viewport_h; |
4c788679 | 1315 | int r; |
771fe6b9 | 1316 | |
2de3b484 | 1317 | /* no fb bound */ |
4dd19b0d | 1318 | if (!atomic && !crtc->fb) { |
d9fdaafb | 1319 | DRM_DEBUG_KMS("No FB bound\n"); |
2de3b484 JG |
1320 | return 0; |
1321 | } | |
771fe6b9 | 1322 | |
4dd19b0d CB |
1323 | if (atomic) { |
1324 | radeon_fb = to_radeon_framebuffer(fb); | |
1325 | target_fb = fb; | |
1326 | } | |
1327 | else { | |
1328 | radeon_fb = to_radeon_framebuffer(crtc->fb); | |
1329 | target_fb = crtc->fb; | |
1330 | } | |
771fe6b9 JG |
1331 | |
1332 | obj = radeon_fb->obj; | |
7e4d15d9 | 1333 | rbo = gem_to_radeon_bo(obj); |
4c788679 JG |
1334 | r = radeon_bo_reserve(rbo, false); |
1335 | if (unlikely(r != 0)) | |
1336 | return r; | |
4dd19b0d CB |
1337 | |
1338 | /* If atomic, assume fb object is pinned & idle & fenced and | |
1339 | * just update base pointers | |
1340 | */ | |
1341 | if (atomic) | |
1342 | fb_location = radeon_bo_gpu_offset(rbo); | |
1343 | else { | |
1344 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); | |
1345 | if (unlikely(r != 0)) { | |
1346 | radeon_bo_unreserve(rbo); | |
1347 | return -EINVAL; | |
1348 | } | |
771fe6b9 | 1349 | } |
4c788679 JG |
1350 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1351 | radeon_bo_unreserve(rbo); | |
771fe6b9 | 1352 | |
4dd19b0d | 1353 | switch (target_fb->bits_per_pixel) { |
41456df2 DA |
1354 | case 8: |
1355 | fb_format = | |
1356 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | | |
1357 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; | |
1358 | break; | |
771fe6b9 JG |
1359 | case 15: |
1360 | fb_format = | |
1361 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | |
1362 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; | |
1363 | break; | |
1364 | case 16: | |
1365 | fb_format = | |
1366 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | |
1367 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; | |
fa6bee46 AD |
1368 | #ifdef __BIG_ENDIAN |
1369 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; | |
1370 | #endif | |
771fe6b9 JG |
1371 | break; |
1372 | case 24: | |
1373 | case 32: | |
1374 | fb_format = | |
1375 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | | |
1376 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; | |
fa6bee46 AD |
1377 | #ifdef __BIG_ENDIAN |
1378 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; | |
1379 | #endif | |
771fe6b9 JG |
1380 | break; |
1381 | default: | |
1382 | DRM_ERROR("Unsupported screen depth %d\n", | |
4dd19b0d | 1383 | target_fb->bits_per_pixel); |
771fe6b9 JG |
1384 | return -EINVAL; |
1385 | } | |
1386 | ||
40c4ac1c AD |
1387 | if (rdev->family >= CHIP_R600) { |
1388 | if (tiling_flags & RADEON_TILING_MACRO) | |
1389 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; | |
1390 | else if (tiling_flags & RADEON_TILING_MICRO) | |
1391 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; | |
1392 | } else { | |
1393 | if (tiling_flags & RADEON_TILING_MACRO) | |
1394 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; | |
cf2f05d3 | 1395 | |
40c4ac1c AD |
1396 | if (tiling_flags & RADEON_TILING_MICRO) |
1397 | fb_format |= AVIVO_D1GRPH_TILED; | |
1398 | } | |
e024e110 | 1399 | |
771fe6b9 JG |
1400 | if (radeon_crtc->crtc_id == 0) |
1401 | WREG32(AVIVO_D1VGA_CONTROL, 0); | |
1402 | else | |
1403 | WREG32(AVIVO_D2VGA_CONTROL, 0); | |
c290dadf AD |
1404 | |
1405 | if (rdev->family >= CHIP_RV770) { | |
1406 | if (radeon_crtc->crtc_id) { | |
95347871 AD |
1407 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1408 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); | |
c290dadf | 1409 | } else { |
95347871 AD |
1410 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1411 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); | |
c290dadf AD |
1412 | } |
1413 | } | |
771fe6b9 JG |
1414 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1415 | (u32) fb_location); | |
1416 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + | |
1417 | radeon_crtc->crtc_offset, (u32) fb_location); | |
1418 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); | |
fa6bee46 AD |
1419 | if (rdev->family >= CHIP_R600) |
1420 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); | |
771fe6b9 JG |
1421 | |
1422 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | |
1423 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | |
1424 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); | |
1425 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); | |
4dd19b0d CB |
1426 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1427 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); | |
771fe6b9 | 1428 | |
01f2c773 | 1429 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
771fe6b9 JG |
1430 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1431 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); | |
1432 | ||
1433 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, | |
1b619250 | 1434 | target_fb->height); |
771fe6b9 JG |
1435 | x &= ~3; |
1436 | y &= ~1; | |
1437 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, | |
1438 | (x << 16) | y); | |
adcfde51 AD |
1439 | viewport_w = crtc->mode.hdisplay; |
1440 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; | |
771fe6b9 | 1441 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
adcfde51 | 1442 | (viewport_w << 16) | viewport_h); |
771fe6b9 | 1443 | |
fb9674bd AD |
1444 | /* pageflip setup */ |
1445 | /* make sure flip is at vb rather than hb */ | |
1446 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); | |
1447 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; | |
1448 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); | |
1449 | ||
1450 | /* set pageflip to happen anywhere in vblank interval */ | |
1451 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); | |
1452 | ||
4dd19b0d CB |
1453 | if (!atomic && fb && fb != crtc->fb) { |
1454 | radeon_fb = to_radeon_framebuffer(fb); | |
7e4d15d9 | 1455 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
4c788679 JG |
1456 | r = radeon_bo_reserve(rbo, false); |
1457 | if (unlikely(r != 0)) | |
1458 | return r; | |
1459 | radeon_bo_unpin(rbo); | |
1460 | radeon_bo_unreserve(rbo); | |
771fe6b9 | 1461 | } |
f30f37de MD |
1462 | |
1463 | /* Bytes per pixel may have changed */ | |
1464 | radeon_bandwidth_update(rdev); | |
1465 | ||
771fe6b9 JG |
1466 | return 0; |
1467 | } | |
1468 | ||
54f088a9 AD |
1469 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
1470 | struct drm_framebuffer *old_fb) | |
1471 | { | |
1472 | struct drm_device *dev = crtc->dev; | |
1473 | struct radeon_device *rdev = dev->dev_private; | |
1474 | ||
bcc1c2a1 | 1475 | if (ASIC_IS_DCE4(rdev)) |
c9417bdd | 1476 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
4dd19b0d CB |
1477 | else if (ASIC_IS_AVIVO(rdev)) |
1478 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
1479 | else | |
1480 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
1481 | } | |
1482 | ||
1483 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, | |
1484 | struct drm_framebuffer *fb, | |
21c74a8e | 1485 | int x, int y, enum mode_set_atomic state) |
4dd19b0d CB |
1486 | { |
1487 | struct drm_device *dev = crtc->dev; | |
1488 | struct radeon_device *rdev = dev->dev_private; | |
1489 | ||
1490 | if (ASIC_IS_DCE4(rdev)) | |
c9417bdd | 1491 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
bcc1c2a1 | 1492 | else if (ASIC_IS_AVIVO(rdev)) |
4dd19b0d | 1493 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
54f088a9 | 1494 | else |
4dd19b0d | 1495 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
54f088a9 AD |
1496 | } |
1497 | ||
615e0cb6 AD |
1498 | /* properly set additional regs when using atombios */ |
1499 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) | |
1500 | { | |
1501 | struct drm_device *dev = crtc->dev; | |
1502 | struct radeon_device *rdev = dev->dev_private; | |
1503 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1504 | u32 disp_merge_cntl; | |
1505 | ||
1506 | switch (radeon_crtc->crtc_id) { | |
1507 | case 0: | |
1508 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); | |
1509 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; | |
1510 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); | |
1511 | break; | |
1512 | case 1: | |
1513 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); | |
1514 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; | |
1515 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); | |
1516 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); | |
1517 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); | |
1518 | break; | |
1519 | } | |
1520 | } | |
1521 | ||
f3dd8508 AD |
1522 | /** |
1523 | * radeon_get_pll_use_mask - look up a mask of which pplls are in use | |
1524 | * | |
1525 | * @crtc: drm crtc | |
1526 | * | |
1527 | * Returns the mask of which PPLLs (Pixel PLLs) are in use. | |
1528 | */ | |
1529 | static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) | |
1530 | { | |
1531 | struct drm_device *dev = crtc->dev; | |
1532 | struct drm_crtc *test_crtc; | |
1533 | struct radeon_crtc *radeon_test_crtc; | |
1534 | u32 pll_in_use = 0; | |
1535 | ||
1536 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { | |
1537 | if (crtc == test_crtc) | |
1538 | continue; | |
1539 | ||
1540 | radeon_test_crtc = to_radeon_crtc(test_crtc); | |
1541 | if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID) | |
1542 | pll_in_use |= (1 << radeon_test_crtc->pll_id); | |
1543 | } | |
1544 | return pll_in_use; | |
1545 | } | |
1546 | ||
1547 | /** | |
1548 | * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP | |
1549 | * | |
1550 | * @crtc: drm crtc | |
1551 | * | |
1552 | * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is | |
1553 | * also in DP mode. For DP, a single PPLL can be used for all DP | |
1554 | * crtcs/encoders. | |
1555 | */ | |
1556 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) | |
1557 | { | |
1558 | struct drm_device *dev = crtc->dev; | |
1559 | struct drm_encoder *test_encoder; | |
1560 | struct radeon_crtc *radeon_test_crtc; | |
1561 | ||
1562 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
1563 | if (test_encoder->crtc && (test_encoder->crtc != crtc)) { | |
1564 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | |
1565 | /* for DP use the same PLL for all */ | |
1566 | radeon_test_crtc = to_radeon_crtc(test_encoder->crtc); | |
1567 | if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID) | |
1568 | return radeon_test_crtc->pll_id; | |
1569 | } | |
1570 | } | |
1571 | } | |
1572 | return ATOM_PPLL_INVALID; | |
1573 | } | |
1574 | ||
2f454cf1 AD |
1575 | /** |
1576 | * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc | |
1577 | * | |
1578 | * @crtc: drm crtc | |
1579 | * @encoder: drm encoder | |
1580 | * | |
1581 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can | |
1582 | * be shared (i.e., same clock). | |
1583 | */ | |
1584 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc, | |
1585 | struct drm_encoder *encoder) | |
1586 | { | |
1587 | struct drm_device *dev = crtc->dev; | |
1588 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1589 | struct drm_encoder *test_encoder; | |
1590 | struct radeon_crtc *radeon_test_crtc; | |
1591 | struct radeon_encoder *test_radeon_encoder; | |
1592 | u32 target_clock, test_clock; | |
1593 | ||
1594 | if (radeon_encoder->native_mode.clock) | |
1595 | target_clock = radeon_encoder->native_mode.clock; | |
1596 | else | |
1597 | target_clock = crtc->mode.clock; | |
1598 | ||
1599 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
1600 | if (test_encoder->crtc && (test_encoder->crtc != crtc)) { | |
1601 | if (!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | |
1602 | test_radeon_encoder = to_radeon_encoder(test_encoder); | |
1603 | radeon_test_crtc = to_radeon_crtc(test_encoder->crtc); | |
1604 | /* for non-DP check the clock */ | |
1605 | if (test_radeon_encoder->native_mode.clock) | |
1606 | test_clock = test_radeon_encoder->native_mode.clock; | |
1607 | else | |
1608 | test_clock = test_encoder->crtc->mode.clock; | |
1609 | if ((target_clock == test_clock) && | |
1610 | (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)) | |
1611 | return radeon_test_crtc->pll_id; | |
1612 | } | |
1613 | } | |
1614 | } | |
1615 | return ATOM_PPLL_INVALID; | |
1616 | } | |
1617 | ||
f3dd8508 AD |
1618 | /** |
1619 | * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. | |
1620 | * | |
1621 | * @crtc: drm crtc | |
1622 | * | |
1623 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors | |
1624 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP | |
1625 | * monitors a dedicated PPLL must be used. If a particular board has | |
1626 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming | |
1627 | * as there is no need to program the PLL itself. If we are not able to | |
1628 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to | |
1629 | * avoid messing up an existing monitor. | |
1630 | * | |
1631 | * Asic specific PLL information | |
1632 | * | |
1633 | * DCE 6.1 | |
1634 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) | |
1635 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) | |
1636 | * | |
1637 | * DCE 6.0 | |
1638 | * - PPLL0 is available to all UNIPHY (DP only) | |
1639 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
1640 | * | |
1641 | * DCE 5.0 | |
1642 | * - DCPLL is available to all UNIPHY (DP only) | |
1643 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
1644 | * | |
1645 | * DCE 3.0/4.0/4.1 | |
1646 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
1647 | * | |
1648 | */ | |
bcc1c2a1 AD |
1649 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1650 | { | |
bcc1c2a1 AD |
1651 | struct drm_device *dev = crtc->dev; |
1652 | struct radeon_device *rdev = dev->dev_private; | |
1653 | struct drm_encoder *test_encoder; | |
f3dd8508 AD |
1654 | u32 pll_in_use; |
1655 | int pll; | |
bcc1c2a1 | 1656 | |
24e1f794 AD |
1657 | if (ASIC_IS_DCE61(rdev)) { |
1658 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
1659 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { | |
1660 | struct radeon_encoder *test_radeon_encoder = | |
1661 | to_radeon_encoder(test_encoder); | |
1662 | struct radeon_encoder_atom_dig *dig = | |
1663 | test_radeon_encoder->enc_priv; | |
1664 | ||
1665 | if ((test_radeon_encoder->encoder_id == | |
1666 | ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && | |
f3dd8508 AD |
1667 | (dig->linkb == false)) |
1668 | /* UNIPHY A uses PPLL2 */ | |
24e1f794 | 1669 | return ATOM_PPLL2; |
f3dd8508 AD |
1670 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { |
1671 | /* UNIPHY B/C/D/E/F */ | |
1672 | if (rdev->clock.dp_extclk) | |
1673 | /* skip PPLL programming if using ext clock */ | |
1674 | return ATOM_PPLL_INVALID; | |
1675 | else { | |
1676 | /* use the same PPLL for all DP monitors */ | |
1677 | pll = radeon_get_shared_dp_ppll(crtc); | |
1678 | if (pll != ATOM_PPLL_INVALID) | |
1679 | return pll; | |
1680 | } | |
2f454cf1 AD |
1681 | } else { |
1682 | /* use the same PPLL for all monitors with the same clock */ | |
1683 | pll = radeon_get_shared_nondp_ppll(crtc, test_encoder); | |
1684 | if (pll != ATOM_PPLL_INVALID) | |
1685 | return pll; | |
f3dd8508 AD |
1686 | } |
1687 | break; | |
24e1f794 AD |
1688 | } |
1689 | } | |
1690 | /* UNIPHY B/C/D/E/F */ | |
f3dd8508 AD |
1691 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1692 | if (!(pll_in_use & (1 << ATOM_PPLL0))) | |
24e1f794 | 1693 | return ATOM_PPLL0; |
f3dd8508 AD |
1694 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1695 | return ATOM_PPLL1; | |
1696 | DRM_ERROR("unable to allocate a PPLL\n"); | |
1697 | return ATOM_PPLL_INVALID; | |
24e1f794 | 1698 | } else if (ASIC_IS_DCE4(rdev)) { |
bcc1c2a1 AD |
1699 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1700 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { | |
86a94def AD |
1701 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1702 | * depending on the asic: | |
1703 | * DCE4: PPLL or ext clock | |
f3dd8508 AD |
1704 | * DCE5: PPLL, DCPLL, or ext clock |
1705 | * DCE6: PPLL, PPLL0, or ext clock | |
86a94def AD |
1706 | * |
1707 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip | |
1708 | * PPLL/DCPLL programming and only program the DP DTO for the | |
1709 | * crtc virtual pixel clock. | |
1710 | */ | |
996d5c59 | 1711 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { |
ecd67955 | 1712 | if (rdev->clock.dp_extclk) |
f3dd8508 | 1713 | /* skip PPLL programming if using ext clock */ |
ecd67955 | 1714 | return ATOM_PPLL_INVALID; |
26fe45a0 | 1715 | else if (ASIC_IS_DCE6(rdev)) |
f3dd8508 | 1716 | /* use PPLL0 for all DP */ |
26fe45a0 | 1717 | return ATOM_PPLL0; |
ecd67955 | 1718 | else if (ASIC_IS_DCE5(rdev)) |
f3dd8508 | 1719 | /* use DCPLL for all DP */ |
ecd67955 | 1720 | return ATOM_DCPLL; |
f3dd8508 AD |
1721 | else { |
1722 | /* use the same PPLL for all DP monitors */ | |
1723 | pll = radeon_get_shared_dp_ppll(crtc); | |
1724 | if (pll != ATOM_PPLL_INVALID) | |
1725 | return pll; | |
1726 | } | |
2f454cf1 AD |
1727 | } else { |
1728 | /* use the same PPLL for all monitors with the same clock */ | |
1729 | pll = radeon_get_shared_nondp_ppll(crtc, test_encoder); | |
1730 | if (pll != ATOM_PPLL_INVALID) | |
1731 | return pll; | |
bcc1c2a1 | 1732 | } |
f3dd8508 | 1733 | break; |
bcc1c2a1 AD |
1734 | } |
1735 | } | |
f3dd8508 AD |
1736 | /* all other cases */ |
1737 | pll_in_use = radeon_get_pll_use_mask(crtc); | |
1738 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | |
1739 | return ATOM_PPLL2; | |
1740 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | |
bcc1c2a1 | 1741 | return ATOM_PPLL1; |
f3dd8508 AD |
1742 | DRM_ERROR("unable to allocate a PPLL\n"); |
1743 | return ATOM_PPLL_INVALID; | |
2f454cf1 AD |
1744 | } else { |
1745 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ | |
1746 | if (!ASIC_IS_AVIVO(rdev)) { | |
1747 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1748 | return radeon_crtc->crtc_id; | |
1749 | } | |
9dbbcfc6 AD |
1750 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1751 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { | |
1752 | /* in DP mode, the DP ref clock can come from either PPLL | |
1753 | * depending on the asic: | |
1754 | * DCE3: PPLL1 or PPLL2 | |
1755 | */ | |
1756 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { | |
1757 | /* use the same PPLL for all DP monitors */ | |
1758 | pll = radeon_get_shared_dp_ppll(crtc); | |
1759 | if (pll != ATOM_PPLL_INVALID) | |
1760 | return pll; | |
2f454cf1 AD |
1761 | } else { |
1762 | /* use the same PPLL for all monitors with the same clock */ | |
1763 | pll = radeon_get_shared_nondp_ppll(crtc, test_encoder); | |
1764 | if (pll != ATOM_PPLL_INVALID) | |
1765 | return pll; | |
9dbbcfc6 AD |
1766 | } |
1767 | break; | |
1768 | } | |
1769 | } | |
1770 | /* all other cases */ | |
1771 | pll_in_use = radeon_get_pll_use_mask(crtc); | |
1772 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | |
1773 | return ATOM_PPLL2; | |
1774 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | |
1775 | return ATOM_PPLL1; | |
1776 | DRM_ERROR("unable to allocate a PPLL\n"); | |
1777 | return ATOM_PPLL_INVALID; | |
2f454cf1 | 1778 | } |
bcc1c2a1 AD |
1779 | } |
1780 | ||
f3f1f03e | 1781 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
3fa47d9e AD |
1782 | { |
1783 | /* always set DCPLL */ | |
f3f1f03e AD |
1784 | if (ASIC_IS_DCE6(rdev)) |
1785 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); | |
1786 | else if (ASIC_IS_DCE4(rdev)) { | |
3fa47d9e AD |
1787 | struct radeon_atom_ss ss; |
1788 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, | |
1789 | ASIC_INTERNAL_SS_ON_DCPLL, | |
1790 | rdev->clock.default_dispclk); | |
1791 | if (ss_enabled) | |
5efcc76c | 1792 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); |
3fa47d9e | 1793 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
f3f1f03e | 1794 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
3fa47d9e | 1795 | if (ss_enabled) |
5efcc76c | 1796 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); |
3fa47d9e AD |
1797 | } |
1798 | ||
1799 | } | |
1800 | ||
771fe6b9 JG |
1801 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
1802 | struct drm_display_mode *mode, | |
1803 | struct drm_display_mode *adjusted_mode, | |
1804 | int x, int y, struct drm_framebuffer *old_fb) | |
1805 | { | |
1806 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1807 | struct drm_device *dev = crtc->dev; | |
1808 | struct radeon_device *rdev = dev->dev_private; | |
54bfe496 AD |
1809 | struct drm_encoder *encoder; |
1810 | bool is_tvcv = false; | |
771fe6b9 | 1811 | |
54bfe496 AD |
1812 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1813 | /* find tv std */ | |
1814 | if (encoder->crtc == crtc) { | |
1815 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1816 | if (radeon_encoder->active_device & | |
1817 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
1818 | is_tvcv = true; | |
1819 | } | |
1820 | } | |
771fe6b9 JG |
1821 | |
1822 | atombios_crtc_set_pll(crtc, adjusted_mode); | |
771fe6b9 | 1823 | |
54bfe496 | 1824 | if (ASIC_IS_DCE4(rdev)) |
bcc1c2a1 | 1825 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
54bfe496 AD |
1826 | else if (ASIC_IS_AVIVO(rdev)) { |
1827 | if (is_tvcv) | |
1828 | atombios_crtc_set_timing(crtc, adjusted_mode); | |
1829 | else | |
1830 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | |
1831 | } else { | |
bcc1c2a1 | 1832 | atombios_crtc_set_timing(crtc, adjusted_mode); |
5a9bcacc AD |
1833 | if (radeon_crtc->crtc_id == 0) |
1834 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | |
615e0cb6 | 1835 | radeon_legacy_atom_fixup(crtc); |
771fe6b9 | 1836 | } |
bcc1c2a1 | 1837 | atombios_crtc_set_base(crtc, x, y, old_fb); |
c93bb85b JG |
1838 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
1839 | atombios_scaler_setup(crtc); | |
771fe6b9 JG |
1840 | return 0; |
1841 | } | |
1842 | ||
1843 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, | |
e811f5ae | 1844 | const struct drm_display_mode *mode, |
771fe6b9 JG |
1845 | struct drm_display_mode *adjusted_mode) |
1846 | { | |
c93bb85b JG |
1847 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1848 | return false; | |
19eca43e AD |
1849 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
1850 | return false; | |
771fe6b9 JG |
1851 | return true; |
1852 | } | |
1853 | ||
1854 | static void atombios_crtc_prepare(struct drm_crtc *crtc) | |
1855 | { | |
267364ac | 1856 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
6c0ae2ab AD |
1857 | struct drm_device *dev = crtc->dev; |
1858 | struct radeon_device *rdev = dev->dev_private; | |
267364ac | 1859 | |
6c0ae2ab | 1860 | radeon_crtc->in_mode_set = true; |
267364ac AD |
1861 | /* pick pll */ |
1862 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); | |
1863 | ||
6c0ae2ab AD |
1864 | /* disable crtc pair power gating before programming */ |
1865 | if (ASIC_IS_DCE6(rdev)) | |
1866 | atombios_powergate_crtc(crtc, ATOM_DISABLE); | |
1867 | ||
37b4390e | 1868 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
a348c84d | 1869 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
771fe6b9 JG |
1870 | } |
1871 | ||
1872 | static void atombios_crtc_commit(struct drm_crtc *crtc) | |
1873 | { | |
6c0ae2ab AD |
1874 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1875 | ||
771fe6b9 | 1876 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
37b4390e | 1877 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
6c0ae2ab | 1878 | radeon_crtc->in_mode_set = false; |
771fe6b9 JG |
1879 | } |
1880 | ||
37f9003b AD |
1881 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
1882 | { | |
1883 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
64199870 AD |
1884 | struct drm_device *dev = crtc->dev; |
1885 | struct radeon_device *rdev = dev->dev_private; | |
8e8e523d | 1886 | struct radeon_atom_ss ss; |
4e58591c | 1887 | int i; |
8e8e523d | 1888 | |
37f9003b AD |
1889 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1890 | ||
4e58591c AD |
1891 | for (i = 0; i < rdev->num_crtc; i++) { |
1892 | if (rdev->mode_info.crtcs[i] && | |
1893 | rdev->mode_info.crtcs[i]->enabled && | |
1894 | i != radeon_crtc->crtc_id && | |
1895 | radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { | |
1896 | /* one other crtc is using this pll don't turn | |
1897 | * off the pll | |
1898 | */ | |
1899 | goto done; | |
1900 | } | |
1901 | } | |
1902 | ||
37f9003b AD |
1903 | switch (radeon_crtc->pll_id) { |
1904 | case ATOM_PPLL1: | |
1905 | case ATOM_PPLL2: | |
1906 | /* disable the ppll */ | |
1907 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, | |
8e8e523d | 1908 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
37f9003b | 1909 | break; |
64199870 AD |
1910 | case ATOM_PPLL0: |
1911 | /* disable the ppll */ | |
1912 | if (ASIC_IS_DCE61(rdev)) | |
1913 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, | |
1914 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); | |
1915 | break; | |
37f9003b AD |
1916 | default: |
1917 | break; | |
1918 | } | |
4e58591c | 1919 | done: |
f3dd8508 | 1920 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
37f9003b AD |
1921 | } |
1922 | ||
771fe6b9 JG |
1923 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
1924 | .dpms = atombios_crtc_dpms, | |
1925 | .mode_fixup = atombios_crtc_mode_fixup, | |
1926 | .mode_set = atombios_crtc_mode_set, | |
1927 | .mode_set_base = atombios_crtc_set_base, | |
4dd19b0d | 1928 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
771fe6b9 JG |
1929 | .prepare = atombios_crtc_prepare, |
1930 | .commit = atombios_crtc_commit, | |
068143d3 | 1931 | .load_lut = radeon_crtc_load_lut, |
37f9003b | 1932 | .disable = atombios_crtc_disable, |
771fe6b9 JG |
1933 | }; |
1934 | ||
1935 | void radeon_atombios_init_crtc(struct drm_device *dev, | |
1936 | struct radeon_crtc *radeon_crtc) | |
1937 | { | |
bcc1c2a1 AD |
1938 | struct radeon_device *rdev = dev->dev_private; |
1939 | ||
1940 | if (ASIC_IS_DCE4(rdev)) { | |
1941 | switch (radeon_crtc->crtc_id) { | |
1942 | case 0: | |
1943 | default: | |
12d7798f | 1944 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
bcc1c2a1 AD |
1945 | break; |
1946 | case 1: | |
12d7798f | 1947 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
bcc1c2a1 AD |
1948 | break; |
1949 | case 2: | |
12d7798f | 1950 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
bcc1c2a1 AD |
1951 | break; |
1952 | case 3: | |
12d7798f | 1953 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
bcc1c2a1 AD |
1954 | break; |
1955 | case 4: | |
12d7798f | 1956 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
bcc1c2a1 AD |
1957 | break; |
1958 | case 5: | |
12d7798f | 1959 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
bcc1c2a1 AD |
1960 | break; |
1961 | } | |
1962 | } else { | |
1963 | if (radeon_crtc->crtc_id == 1) | |
1964 | radeon_crtc->crtc_offset = | |
1965 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; | |
1966 | else | |
1967 | radeon_crtc->crtc_offset = 0; | |
1968 | } | |
f3dd8508 | 1969 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
771fe6b9 JG |
1970 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
1971 | } |