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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc_helper.h> | |
28 | #include <drm/radeon_drm.h> | |
68adac5e | 29 | #include <drm/drm_fixed.h> |
771fe6b9 JG |
30 | #include "radeon.h" |
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
33 | ||
c93bb85b JG |
34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
35 | struct drm_display_mode *mode, | |
36 | struct drm_display_mode *adjusted_mode) | |
37 | { | |
38 | struct drm_device *dev = crtc->dev; | |
39 | struct radeon_device *rdev = dev->dev_private; | |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; | |
42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); | |
43 | int a1, a2; | |
44 | ||
45 | memset(&args, 0, sizeof(args)); | |
46 | ||
c93bb85b JG |
47 | args.ucCRTC = radeon_crtc->crtc_id; |
48 | ||
49 | switch (radeon_crtc->rmx_type) { | |
50 | case RMX_CENTER: | |
4589433c CC |
51 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
52 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); | |
53 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); | |
54 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); | |
c93bb85b JG |
55 | break; |
56 | case RMX_ASPECT: | |
57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; | |
58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; | |
59 | ||
60 | if (a1 > a2) { | |
4589433c CC |
61 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
62 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); | |
c93bb85b | 63 | } else if (a2 > a1) { |
942b0e95 AD |
64 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
65 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); | |
c93bb85b | 66 | } |
c93bb85b JG |
67 | break; |
68 | case RMX_FULL: | |
69 | default: | |
4589433c CC |
70 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
71 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); | |
72 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); | |
73 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); | |
c93bb85b JG |
74 | break; |
75 | } | |
5b1714d3 | 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
c93bb85b JG |
77 | } |
78 | ||
79 | static void atombios_scaler_setup(struct drm_crtc *crtc) | |
80 | { | |
81 | struct drm_device *dev = crtc->dev; | |
82 | struct radeon_device *rdev = dev->dev_private; | |
83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
84 | ENABLE_SCALER_PS_ALLOCATION args; | |
85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); | |
4ce001ab | 86 | |
c93bb85b JG |
87 | /* fixme - fill in enc_priv for atom dac */ |
88 | enum radeon_tv_std tv_std = TV_STD_NTSC; | |
4ce001ab DA |
89 | bool is_tv = false, is_cv = false; |
90 | struct drm_encoder *encoder; | |
c93bb85b JG |
91 | |
92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) | |
93 | return; | |
94 | ||
4ce001ab DA |
95 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
96 | /* find tv std */ | |
97 | if (encoder->crtc == crtc) { | |
98 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
99 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { | |
100 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; | |
101 | tv_std = tv_dac->tv_std; | |
102 | is_tv = true; | |
103 | } | |
104 | } | |
105 | } | |
106 | ||
c93bb85b JG |
107 | memset(&args, 0, sizeof(args)); |
108 | ||
109 | args.ucScaler = radeon_crtc->crtc_id; | |
110 | ||
4ce001ab | 111 | if (is_tv) { |
c93bb85b JG |
112 | switch (tv_std) { |
113 | case TV_STD_NTSC: | |
114 | default: | |
115 | args.ucTVStandard = ATOM_TV_NTSC; | |
116 | break; | |
117 | case TV_STD_PAL: | |
118 | args.ucTVStandard = ATOM_TV_PAL; | |
119 | break; | |
120 | case TV_STD_PAL_M: | |
121 | args.ucTVStandard = ATOM_TV_PALM; | |
122 | break; | |
123 | case TV_STD_PAL_60: | |
124 | args.ucTVStandard = ATOM_TV_PAL60; | |
125 | break; | |
126 | case TV_STD_NTSC_J: | |
127 | args.ucTVStandard = ATOM_TV_NTSCJ; | |
128 | break; | |
129 | case TV_STD_SCART_PAL: | |
130 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ | |
131 | break; | |
132 | case TV_STD_SECAM: | |
133 | args.ucTVStandard = ATOM_TV_SECAM; | |
134 | break; | |
135 | case TV_STD_PAL_CN: | |
136 | args.ucTVStandard = ATOM_TV_PALCN; | |
137 | break; | |
138 | } | |
139 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | |
4ce001ab | 140 | } else if (is_cv) { |
c93bb85b JG |
141 | args.ucTVStandard = ATOM_TV_CV; |
142 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | |
143 | } else { | |
144 | switch (radeon_crtc->rmx_type) { | |
145 | case RMX_FULL: | |
146 | args.ucEnable = ATOM_SCALER_EXPANSION; | |
147 | break; | |
148 | case RMX_CENTER: | |
149 | args.ucEnable = ATOM_SCALER_CENTER; | |
150 | break; | |
151 | case RMX_ASPECT: | |
152 | args.ucEnable = ATOM_SCALER_EXPANSION; | |
153 | break; | |
154 | default: | |
155 | if (ASIC_IS_AVIVO(rdev)) | |
156 | args.ucEnable = ATOM_SCALER_DISABLE; | |
157 | else | |
158 | args.ucEnable = ATOM_SCALER_CENTER; | |
159 | break; | |
160 | } | |
161 | } | |
162 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
4ce001ab DA |
163 | if ((is_tv || is_cv) |
164 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { | |
165 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); | |
c93bb85b JG |
166 | } |
167 | } | |
168 | ||
771fe6b9 JG |
169 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
170 | { | |
171 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
172 | struct drm_device *dev = crtc->dev; | |
173 | struct radeon_device *rdev = dev->dev_private; | |
174 | int index = | |
175 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); | |
176 | ENABLE_CRTC_PS_ALLOCATION args; | |
177 | ||
178 | memset(&args, 0, sizeof(args)); | |
179 | ||
180 | args.ucCRTC = radeon_crtc->crtc_id; | |
181 | args.ucEnable = lock; | |
182 | ||
183 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
184 | } | |
185 | ||
186 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) | |
187 | { | |
188 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
189 | struct drm_device *dev = crtc->dev; | |
190 | struct radeon_device *rdev = dev->dev_private; | |
191 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); | |
192 | ENABLE_CRTC_PS_ALLOCATION args; | |
193 | ||
194 | memset(&args, 0, sizeof(args)); | |
195 | ||
196 | args.ucCRTC = radeon_crtc->crtc_id; | |
197 | args.ucEnable = state; | |
198 | ||
199 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
200 | } | |
201 | ||
202 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) | |
203 | { | |
204 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
205 | struct drm_device *dev = crtc->dev; | |
206 | struct radeon_device *rdev = dev->dev_private; | |
207 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); | |
208 | ENABLE_CRTC_PS_ALLOCATION args; | |
209 | ||
210 | memset(&args, 0, sizeof(args)); | |
211 | ||
212 | args.ucCRTC = radeon_crtc->crtc_id; | |
213 | args.ucEnable = state; | |
214 | ||
215 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
216 | } | |
217 | ||
218 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) | |
219 | { | |
220 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
221 | struct drm_device *dev = crtc->dev; | |
222 | struct radeon_device *rdev = dev->dev_private; | |
223 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); | |
224 | BLANK_CRTC_PS_ALLOCATION args; | |
225 | ||
226 | memset(&args, 0, sizeof(args)); | |
227 | ||
228 | args.ucCRTC = radeon_crtc->crtc_id; | |
229 | args.ucBlanking = state; | |
230 | ||
231 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
232 | } | |
233 | ||
234 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) | |
235 | { | |
236 | struct drm_device *dev = crtc->dev; | |
237 | struct radeon_device *rdev = dev->dev_private; | |
500b7587 | 238 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
239 | |
240 | switch (mode) { | |
241 | case DRM_MODE_DPMS_ON: | |
d7311171 AD |
242 | radeon_crtc->enabled = true; |
243 | /* adjust pm to dpms changes BEFORE enabling crtcs */ | |
244 | radeon_pm_compute_clocks(rdev); | |
37b4390e | 245 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
771fe6b9 | 246 | if (ASIC_IS_DCE3(rdev)) |
37b4390e AD |
247 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
248 | atombios_blank_crtc(crtc, ATOM_DISABLE); | |
45f9a39b | 249 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
500b7587 | 250 | radeon_crtc_load_lut(crtc); |
771fe6b9 JG |
251 | break; |
252 | case DRM_MODE_DPMS_STANDBY: | |
253 | case DRM_MODE_DPMS_SUSPEND: | |
254 | case DRM_MODE_DPMS_OFF: | |
45f9a39b | 255 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
a93f344d AD |
256 | if (radeon_crtc->enabled) |
257 | atombios_blank_crtc(crtc, ATOM_ENABLE); | |
771fe6b9 | 258 | if (ASIC_IS_DCE3(rdev)) |
37b4390e AD |
259 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
260 | atombios_enable_crtc(crtc, ATOM_DISABLE); | |
a48b9b4e | 261 | radeon_crtc->enabled = false; |
d7311171 AD |
262 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
263 | radeon_pm_compute_clocks(rdev); | |
771fe6b9 JG |
264 | break; |
265 | } | |
771fe6b9 JG |
266 | } |
267 | ||
268 | static void | |
269 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, | |
5a9bcacc | 270 | struct drm_display_mode *mode) |
771fe6b9 | 271 | { |
5a9bcacc | 272 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
273 | struct drm_device *dev = crtc->dev; |
274 | struct radeon_device *rdev = dev->dev_private; | |
5a9bcacc | 275 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
771fe6b9 | 276 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
5a9bcacc | 277 | u16 misc = 0; |
771fe6b9 | 278 | |
5a9bcacc | 279 | memset(&args, 0, sizeof(args)); |
5b1714d3 | 280 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
5a9bcacc | 281 | args.usH_Blanking_Time = |
5b1714d3 AD |
282 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
283 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); | |
5a9bcacc | 284 | args.usV_Blanking_Time = |
5b1714d3 | 285 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
5a9bcacc | 286 | args.usH_SyncOffset = |
5b1714d3 | 287 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
5a9bcacc AD |
288 | args.usH_SyncWidth = |
289 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); | |
290 | args.usV_SyncOffset = | |
5b1714d3 | 291 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
5a9bcacc AD |
292 | args.usV_SyncWidth = |
293 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); | |
5b1714d3 AD |
294 | args.ucH_Border = radeon_crtc->h_border; |
295 | args.ucV_Border = radeon_crtc->v_border; | |
5a9bcacc AD |
296 | |
297 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
298 | misc |= ATOM_VSYNC_POLARITY; | |
299 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
300 | misc |= ATOM_HSYNC_POLARITY; | |
301 | if (mode->flags & DRM_MODE_FLAG_CSYNC) | |
302 | misc |= ATOM_COMPOSITESYNC; | |
303 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
304 | misc |= ATOM_INTERLACE; | |
305 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
306 | misc |= ATOM_DOUBLE_CLOCK_MODE; | |
307 | ||
308 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); | |
309 | args.ucCRTC = radeon_crtc->crtc_id; | |
771fe6b9 | 310 | |
5a9bcacc | 311 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
771fe6b9 JG |
312 | } |
313 | ||
5a9bcacc AD |
314 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
315 | struct drm_display_mode *mode) | |
771fe6b9 | 316 | { |
5a9bcacc | 317 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
318 | struct drm_device *dev = crtc->dev; |
319 | struct radeon_device *rdev = dev->dev_private; | |
5a9bcacc | 320 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
771fe6b9 | 321 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
5a9bcacc | 322 | u16 misc = 0; |
771fe6b9 | 323 | |
5a9bcacc AD |
324 | memset(&args, 0, sizeof(args)); |
325 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); | |
326 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); | |
327 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); | |
328 | args.usH_SyncWidth = | |
329 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); | |
330 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); | |
331 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); | |
332 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); | |
333 | args.usV_SyncWidth = | |
334 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); | |
335 | ||
54bfe496 AD |
336 | args.ucOverscanRight = radeon_crtc->h_border; |
337 | args.ucOverscanLeft = radeon_crtc->h_border; | |
338 | args.ucOverscanBottom = radeon_crtc->v_border; | |
339 | args.ucOverscanTop = radeon_crtc->v_border; | |
340 | ||
5a9bcacc AD |
341 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
342 | misc |= ATOM_VSYNC_POLARITY; | |
343 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
344 | misc |= ATOM_HSYNC_POLARITY; | |
345 | if (mode->flags & DRM_MODE_FLAG_CSYNC) | |
346 | misc |= ATOM_COMPOSITESYNC; | |
347 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
348 | misc |= ATOM_INTERLACE; | |
349 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
350 | misc |= ATOM_DOUBLE_CLOCK_MODE; | |
351 | ||
352 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); | |
353 | args.ucCRTC = radeon_crtc->crtc_id; | |
771fe6b9 | 354 | |
5a9bcacc | 355 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
771fe6b9 JG |
356 | } |
357 | ||
b792210e AD |
358 | static void atombios_disable_ss(struct drm_crtc *crtc) |
359 | { | |
360 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
361 | struct drm_device *dev = crtc->dev; | |
362 | struct radeon_device *rdev = dev->dev_private; | |
363 | u32 ss_cntl; | |
364 | ||
365 | if (ASIC_IS_DCE4(rdev)) { | |
366 | switch (radeon_crtc->pll_id) { | |
367 | case ATOM_PPLL1: | |
368 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); | |
369 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; | |
370 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); | |
371 | break; | |
372 | case ATOM_PPLL2: | |
373 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); | |
374 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; | |
375 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); | |
376 | break; | |
377 | case ATOM_DCPLL: | |
378 | case ATOM_PPLL_INVALID: | |
379 | return; | |
380 | } | |
381 | } else if (ASIC_IS_AVIVO(rdev)) { | |
382 | switch (radeon_crtc->pll_id) { | |
383 | case ATOM_PPLL1: | |
384 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); | |
385 | ss_cntl &= ~1; | |
386 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); | |
387 | break; | |
388 | case ATOM_PPLL2: | |
389 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); | |
390 | ss_cntl &= ~1; | |
391 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); | |
392 | break; | |
393 | case ATOM_DCPLL: | |
394 | case ATOM_PPLL_INVALID: | |
395 | return; | |
396 | } | |
397 | } | |
398 | } | |
399 | ||
400 | ||
26b9fc3a | 401 | union atom_enable_ss { |
ba032a58 AD |
402 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
403 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; | |
26b9fc3a | 404 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
ba032a58 | 405 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
a572eaa3 | 406 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
26b9fc3a AD |
407 | }; |
408 | ||
ba032a58 AD |
409 | static void atombios_crtc_program_ss(struct drm_crtc *crtc, |
410 | int enable, | |
411 | int pll_id, | |
412 | struct radeon_atom_ss *ss) | |
ebbe1cb9 | 413 | { |
ebbe1cb9 AD |
414 | struct drm_device *dev = crtc->dev; |
415 | struct radeon_device *rdev = dev->dev_private; | |
ebbe1cb9 | 416 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
26b9fc3a | 417 | union atom_enable_ss args; |
ebbe1cb9 | 418 | |
ba032a58 | 419 | memset(&args, 0, sizeof(args)); |
bcc1c2a1 | 420 | |
a572eaa3 | 421 | if (ASIC_IS_DCE5(rdev)) { |
4589433c | 422 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
8e8e523d | 423 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
a572eaa3 AD |
424 | switch (pll_id) { |
425 | case ATOM_PPLL1: | |
426 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; | |
4589433c CC |
427 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
428 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
a572eaa3 AD |
429 | break; |
430 | case ATOM_PPLL2: | |
431 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; | |
4589433c CC |
432 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
433 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
a572eaa3 AD |
434 | break; |
435 | case ATOM_DCPLL: | |
436 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; | |
4589433c CC |
437 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(0); |
438 | args.v3.usSpreadSpectrumStep = cpu_to_le16(0); | |
a572eaa3 AD |
439 | break; |
440 | case ATOM_PPLL_INVALID: | |
441 | return; | |
442 | } | |
d0ae3e89 | 443 | args.v3.ucEnable = enable; |
8e8e523d AD |
444 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) |
445 | args.v3.ucEnable = ATOM_DISABLE; | |
a572eaa3 | 446 | } else if (ASIC_IS_DCE4(rdev)) { |
ba032a58 | 447 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
8e8e523d | 448 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
449 | switch (pll_id) { |
450 | case ATOM_PPLL1: | |
451 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; | |
4589433c CC |
452 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
453 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
ba032a58 AD |
454 | break; |
455 | case ATOM_PPLL2: | |
456 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; | |
4589433c CC |
457 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
458 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
ebbe1cb9 | 459 | break; |
ba032a58 AD |
460 | case ATOM_DCPLL: |
461 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; | |
4589433c CC |
462 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(0); |
463 | args.v2.usSpreadSpectrumStep = cpu_to_le16(0); | |
ba032a58 AD |
464 | break; |
465 | case ATOM_PPLL_INVALID: | |
466 | return; | |
ebbe1cb9 | 467 | } |
ba032a58 | 468 | args.v2.ucEnable = enable; |
8e8e523d AD |
469 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) |
470 | args.v2.ucEnable = ATOM_DISABLE; | |
ba032a58 AD |
471 | } else if (ASIC_IS_DCE3(rdev)) { |
472 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 473 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
474 | args.v1.ucSpreadSpectrumStep = ss->step; |
475 | args.v1.ucSpreadSpectrumDelay = ss->delay; | |
476 | args.v1.ucSpreadSpectrumRange = ss->range; | |
477 | args.v1.ucPpll = pll_id; | |
478 | args.v1.ucEnable = enable; | |
479 | } else if (ASIC_IS_AVIVO(rdev)) { | |
8e8e523d AD |
480 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
481 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { | |
ba032a58 AD |
482 | atombios_disable_ss(crtc); |
483 | return; | |
484 | } | |
485 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 486 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
487 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
488 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; | |
489 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; | |
490 | args.lvds_ss_2.ucEnable = enable; | |
ebbe1cb9 | 491 | } else { |
8e8e523d AD |
492 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
493 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { | |
ba032a58 AD |
494 | atombios_disable_ss(crtc); |
495 | return; | |
496 | } | |
497 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 498 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
499 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
500 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; | |
501 | args.lvds_ss.ucEnable = enable; | |
ebbe1cb9 | 502 | } |
26b9fc3a | 503 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
ebbe1cb9 AD |
504 | } |
505 | ||
4eaeca33 AD |
506 | union adjust_pixel_clock { |
507 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; | |
bcc1c2a1 | 508 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
4eaeca33 AD |
509 | }; |
510 | ||
511 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |
512 | struct drm_display_mode *mode, | |
ba032a58 AD |
513 | struct radeon_pll *pll, |
514 | bool ss_enabled, | |
515 | struct radeon_atom_ss *ss) | |
771fe6b9 | 516 | { |
771fe6b9 JG |
517 | struct drm_device *dev = crtc->dev; |
518 | struct radeon_device *rdev = dev->dev_private; | |
519 | struct drm_encoder *encoder = NULL; | |
520 | struct radeon_encoder *radeon_encoder = NULL; | |
df271bec | 521 | struct drm_connector *connector = NULL; |
4eaeca33 | 522 | u32 adjusted_clock = mode->clock; |
bcc1c2a1 | 523 | int encoder_mode = 0; |
fbee67a6 AD |
524 | u32 dp_clock = mode->clock; |
525 | int bpc = 8; | |
fc10332b | 526 | |
4eaeca33 AD |
527 | /* reset the pll flags */ |
528 | pll->flags = 0; | |
771fe6b9 JG |
529 | |
530 | if (ASIC_IS_AVIVO(rdev)) { | |
eb1300bc AD |
531 | if ((rdev->family == CHIP_RS600) || |
532 | (rdev->family == CHIP_RS690) || | |
533 | (rdev->family == CHIP_RS740)) | |
2ff776cf | 534 | pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
fc10332b | 535 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
5480f727 DA |
536 | |
537 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ | |
538 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; | |
539 | else | |
540 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; | |
9bb09fa1 | 541 | |
5785e53f | 542 | if (rdev->family < CHIP_RV770) |
9bb09fa1 | 543 | pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
5480f727 | 544 | } else { |
fc10332b | 545 | pll->flags |= RADEON_PLL_LEGACY; |
771fe6b9 | 546 | |
5480f727 DA |
547 | if (mode->clock > 200000) /* range limits??? */ |
548 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; | |
549 | else | |
550 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; | |
5480f727 DA |
551 | } |
552 | ||
771fe6b9 JG |
553 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
554 | if (encoder->crtc == crtc) { | |
4eaeca33 | 555 | radeon_encoder = to_radeon_encoder(encoder); |
df271bec AD |
556 | connector = radeon_get_connector_for_encoder(encoder); |
557 | if (connector) | |
558 | bpc = connector->display_info.bpc; | |
bcc1c2a1 | 559 | encoder_mode = atombios_get_encoder_mode(encoder); |
eac4dff6 AD |
560 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
561 | radeon_encoder_is_dp_bridge(encoder)) { | |
fbee67a6 AD |
562 | if (connector) { |
563 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
564 | struct radeon_connector_atom_dig *dig_connector = | |
565 | radeon_connector->con_priv; | |
566 | ||
567 | dp_clock = dig_connector->dp_clock; | |
568 | } | |
569 | } | |
5b40ddf8 | 570 | |
ba032a58 AD |
571 | /* use recommended ref_div for ss */ |
572 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
573 | if (ss_enabled) { | |
574 | if (ss->refdiv) { | |
575 | pll->flags |= RADEON_PLL_USE_REF_DIV; | |
576 | pll->reference_div = ss->refdiv; | |
5b40ddf8 AD |
577 | if (ASIC_IS_AVIVO(rdev)) |
578 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; | |
ba032a58 AD |
579 | } |
580 | } | |
581 | } | |
5b40ddf8 | 582 | |
4eaeca33 AD |
583 | if (ASIC_IS_AVIVO(rdev)) { |
584 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ | |
585 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) | |
586 | adjusted_clock = mode->clock * 2; | |
48dfaaeb | 587 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
a1a4b23b | 588 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
5b40ddf8 AD |
589 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
590 | pll->flags |= RADEON_PLL_IS_LCD; | |
4eaeca33 AD |
591 | } else { |
592 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) | |
fc10332b | 593 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
4eaeca33 | 594 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
fc10332b | 595 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
771fe6b9 | 596 | } |
3ce0a23d | 597 | break; |
771fe6b9 JG |
598 | } |
599 | } | |
600 | ||
2606c886 AD |
601 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
602 | * accordingly based on the encoder/transmitter to work around | |
603 | * special hw requirements. | |
604 | */ | |
605 | if (ASIC_IS_DCE3(rdev)) { | |
4eaeca33 | 606 | union adjust_pixel_clock args; |
4eaeca33 AD |
607 | u8 frev, crev; |
608 | int index; | |
2606c886 | 609 | |
2606c886 | 610 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
a084e6ee AD |
611 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
612 | &crev)) | |
613 | return adjusted_clock; | |
4eaeca33 AD |
614 | |
615 | memset(&args, 0, sizeof(args)); | |
616 | ||
617 | switch (frev) { | |
618 | case 1: | |
619 | switch (crev) { | |
620 | case 1: | |
621 | case 2: | |
622 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); | |
623 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; | |
bcc1c2a1 | 624 | args.v1.ucEncodeMode = encoder_mode; |
8e8e523d | 625 | if (ss_enabled && ss->percentage) |
fbee67a6 AD |
626 | args.v1.ucConfig |= |
627 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; | |
4eaeca33 AD |
628 | |
629 | atom_execute_table(rdev->mode_info.atom_context, | |
630 | index, (uint32_t *)&args); | |
631 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; | |
632 | break; | |
bcc1c2a1 AD |
633 | case 3: |
634 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); | |
635 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; | |
636 | args.v3.sInput.ucEncodeMode = encoder_mode; | |
637 | args.v3.sInput.ucDispPllConfig = 0; | |
8e8e523d | 638 | if (ss_enabled && ss->percentage) |
b526ce22 AD |
639 | args.v3.sInput.ucDispPllConfig |= |
640 | DISPPLL_CONFIG_SS_ENABLE; | |
eac4dff6 AD |
641 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) || |
642 | radeon_encoder_is_dp_bridge(encoder)) { | |
bcc1c2a1 | 643 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
fbee67a6 | 644 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { |
bcc1c2a1 AD |
645 | args.v3.sInput.ucDispPllConfig |= |
646 | DISPPLL_CONFIG_COHERENT_MODE; | |
fbee67a6 AD |
647 | /* 16200 or 27000 */ |
648 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | |
649 | } else { | |
650 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { | |
651 | /* deep color support */ | |
652 | args.v3.sInput.usPixelClock = | |
653 | cpu_to_le16((mode->clock * bpc / 8) / 10); | |
654 | } | |
bcc1c2a1 AD |
655 | if (dig->coherent_mode) |
656 | args.v3.sInput.ucDispPllConfig |= | |
657 | DISPPLL_CONFIG_COHERENT_MODE; | |
658 | if (mode->clock > 165000) | |
659 | args.v3.sInput.ucDispPllConfig |= | |
660 | DISPPLL_CONFIG_DUAL_LINK; | |
661 | } | |
662 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
fbee67a6 | 663 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { |
bcc1c2a1 | 664 | args.v3.sInput.ucDispPllConfig |= |
9f998ad7 | 665 | DISPPLL_CONFIG_COHERENT_MODE; |
fbee67a6 AD |
666 | /* 16200 or 27000 */ |
667 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | |
b526ce22 | 668 | } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) { |
9f998ad7 AD |
669 | if (mode->clock > 165000) |
670 | args.v3.sInput.ucDispPllConfig |= | |
671 | DISPPLL_CONFIG_DUAL_LINK; | |
672 | } | |
bcc1c2a1 AD |
673 | } |
674 | atom_execute_table(rdev->mode_info.atom_context, | |
675 | index, (uint32_t *)&args); | |
676 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; | |
677 | if (args.v3.sOutput.ucRefDiv) { | |
9f4283f4 | 678 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
bcc1c2a1 AD |
679 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
680 | pll->reference_div = args.v3.sOutput.ucRefDiv; | |
681 | } | |
682 | if (args.v3.sOutput.ucPostDiv) { | |
9f4283f4 | 683 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
bcc1c2a1 AD |
684 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
685 | pll->post_div = args.v3.sOutput.ucPostDiv; | |
686 | } | |
687 | break; | |
4eaeca33 AD |
688 | default: |
689 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
690 | return adjusted_clock; | |
691 | } | |
692 | break; | |
693 | default: | |
694 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
695 | return adjusted_clock; | |
696 | } | |
d56ef9c8 | 697 | } |
4eaeca33 AD |
698 | return adjusted_clock; |
699 | } | |
700 | ||
701 | union set_pixel_clock { | |
702 | SET_PIXEL_CLOCK_PS_ALLOCATION base; | |
703 | PIXEL_CLOCK_PARAMETERS v1; | |
704 | PIXEL_CLOCK_PARAMETERS_V2 v2; | |
705 | PIXEL_CLOCK_PARAMETERS_V3 v3; | |
bcc1c2a1 | 706 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
f82b3ddc | 707 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
4eaeca33 AD |
708 | }; |
709 | ||
f82b3ddc AD |
710 | /* on DCE5, make sure the voltage is high enough to support the |
711 | * required disp clk. | |
712 | */ | |
713 | static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, | |
714 | u32 dispclk) | |
bcc1c2a1 AD |
715 | { |
716 | struct drm_device *dev = crtc->dev; | |
717 | struct radeon_device *rdev = dev->dev_private; | |
718 | u8 frev, crev; | |
719 | int index; | |
720 | union set_pixel_clock args; | |
721 | ||
722 | memset(&args, 0, sizeof(args)); | |
723 | ||
724 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); | |
a084e6ee AD |
725 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
726 | &crev)) | |
727 | return; | |
bcc1c2a1 AD |
728 | |
729 | switch (frev) { | |
730 | case 1: | |
731 | switch (crev) { | |
732 | case 5: | |
733 | /* if the default dcpll clock is specified, | |
734 | * SetPixelClock provides the dividers | |
735 | */ | |
736 | args.v5.ucCRTC = ATOM_CRTC_INVALID; | |
4589433c | 737 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
bcc1c2a1 AD |
738 | args.v5.ucPpll = ATOM_DCPLL; |
739 | break; | |
f82b3ddc AD |
740 | case 6: |
741 | /* if the default dcpll clock is specified, | |
742 | * SetPixelClock provides the dividers | |
743 | */ | |
265aa6c8 | 744 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
f82b3ddc AD |
745 | args.v6.ucPpll = ATOM_DCPLL; |
746 | break; | |
bcc1c2a1 AD |
747 | default: |
748 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
749 | return; | |
750 | } | |
751 | break; | |
752 | default: | |
753 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
754 | return; | |
755 | } | |
756 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
757 | } | |
758 | ||
37f9003b AD |
759 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
760 | int crtc_id, | |
761 | int pll_id, | |
762 | u32 encoder_mode, | |
763 | u32 encoder_id, | |
764 | u32 clock, | |
765 | u32 ref_div, | |
766 | u32 fb_div, | |
767 | u32 frac_fb_div, | |
df271bec | 768 | u32 post_div, |
8e8e523d AD |
769 | int bpc, |
770 | bool ss_enabled, | |
771 | struct radeon_atom_ss *ss) | |
4eaeca33 | 772 | { |
4eaeca33 AD |
773 | struct drm_device *dev = crtc->dev; |
774 | struct radeon_device *rdev = dev->dev_private; | |
4eaeca33 | 775 | u8 frev, crev; |
37f9003b | 776 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
4eaeca33 | 777 | union set_pixel_clock args; |
4eaeca33 AD |
778 | |
779 | memset(&args, 0, sizeof(args)); | |
780 | ||
a084e6ee AD |
781 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
782 | &crev)) | |
783 | return; | |
771fe6b9 JG |
784 | |
785 | switch (frev) { | |
786 | case 1: | |
787 | switch (crev) { | |
788 | case 1: | |
37f9003b AD |
789 | if (clock == ATOM_DISABLE) |
790 | return; | |
791 | args.v1.usPixelClock = cpu_to_le16(clock / 10); | |
4eaeca33 AD |
792 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
793 | args.v1.usFbDiv = cpu_to_le16(fb_div); | |
794 | args.v1.ucFracFbDiv = frac_fb_div; | |
795 | args.v1.ucPostDiv = post_div; | |
37f9003b AD |
796 | args.v1.ucPpll = pll_id; |
797 | args.v1.ucCRTC = crtc_id; | |
4eaeca33 | 798 | args.v1.ucRefDivSrc = 1; |
771fe6b9 JG |
799 | break; |
800 | case 2: | |
37f9003b | 801 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
4eaeca33 AD |
802 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
803 | args.v2.usFbDiv = cpu_to_le16(fb_div); | |
804 | args.v2.ucFracFbDiv = frac_fb_div; | |
805 | args.v2.ucPostDiv = post_div; | |
37f9003b AD |
806 | args.v2.ucPpll = pll_id; |
807 | args.v2.ucCRTC = crtc_id; | |
4eaeca33 | 808 | args.v2.ucRefDivSrc = 1; |
771fe6b9 JG |
809 | break; |
810 | case 3: | |
37f9003b | 811 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
4eaeca33 AD |
812 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
813 | args.v3.usFbDiv = cpu_to_le16(fb_div); | |
814 | args.v3.ucFracFbDiv = frac_fb_div; | |
815 | args.v3.ucPostDiv = post_div; | |
37f9003b AD |
816 | args.v3.ucPpll = pll_id; |
817 | args.v3.ucMiscInfo = (pll_id << 2); | |
6f15c506 AD |
818 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
819 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; | |
37f9003b | 820 | args.v3.ucTransmitterId = encoder_id; |
bcc1c2a1 AD |
821 | args.v3.ucEncoderMode = encoder_mode; |
822 | break; | |
823 | case 5: | |
37f9003b AD |
824 | args.v5.ucCRTC = crtc_id; |
825 | args.v5.usPixelClock = cpu_to_le16(clock / 10); | |
bcc1c2a1 AD |
826 | args.v5.ucRefDiv = ref_div; |
827 | args.v5.usFbDiv = cpu_to_le16(fb_div); | |
828 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); | |
829 | args.v5.ucPostDiv = post_div; | |
830 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ | |
8e8e523d AD |
831 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
832 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; | |
df271bec AD |
833 | switch (bpc) { |
834 | case 8: | |
835 | default: | |
836 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; | |
837 | break; | |
838 | case 10: | |
839 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; | |
840 | break; | |
841 | } | |
37f9003b | 842 | args.v5.ucTransmitterID = encoder_id; |
bcc1c2a1 | 843 | args.v5.ucEncoderMode = encoder_mode; |
37f9003b | 844 | args.v5.ucPpll = pll_id; |
771fe6b9 | 845 | break; |
f82b3ddc AD |
846 | case 6: |
847 | args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id; | |
848 | args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); | |
849 | args.v6.ucRefDiv = ref_div; | |
850 | args.v6.usFbDiv = cpu_to_le16(fb_div); | |
851 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); | |
852 | args.v6.ucPostDiv = post_div; | |
853 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ | |
8e8e523d AD |
854 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
855 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; | |
df271bec AD |
856 | switch (bpc) { |
857 | case 8: | |
858 | default: | |
859 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; | |
860 | break; | |
861 | case 10: | |
862 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; | |
863 | break; | |
864 | case 12: | |
865 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; | |
866 | break; | |
867 | case 16: | |
868 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; | |
869 | break; | |
870 | } | |
f82b3ddc AD |
871 | args.v6.ucTransmitterID = encoder_id; |
872 | args.v6.ucEncoderMode = encoder_mode; | |
873 | args.v6.ucPpll = pll_id; | |
874 | break; | |
771fe6b9 JG |
875 | default: |
876 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
877 | return; | |
878 | } | |
879 | break; | |
880 | default: | |
881 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
882 | return; | |
883 | } | |
884 | ||
771fe6b9 JG |
885 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
886 | } | |
887 | ||
37f9003b AD |
888 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
889 | { | |
890 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
891 | struct drm_device *dev = crtc->dev; | |
892 | struct radeon_device *rdev = dev->dev_private; | |
893 | struct drm_encoder *encoder = NULL; | |
894 | struct radeon_encoder *radeon_encoder = NULL; | |
895 | u32 pll_clock = mode->clock; | |
896 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; | |
897 | struct radeon_pll *pll; | |
898 | u32 adjusted_clock; | |
899 | int encoder_mode = 0; | |
ba032a58 AD |
900 | struct radeon_atom_ss ss; |
901 | bool ss_enabled = false; | |
df271bec | 902 | int bpc = 8; |
37f9003b AD |
903 | |
904 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
905 | if (encoder->crtc == crtc) { | |
906 | radeon_encoder = to_radeon_encoder(encoder); | |
907 | encoder_mode = atombios_get_encoder_mode(encoder); | |
908 | break; | |
909 | } | |
910 | } | |
911 | ||
912 | if (!radeon_encoder) | |
913 | return; | |
914 | ||
915 | switch (radeon_crtc->pll_id) { | |
916 | case ATOM_PPLL1: | |
917 | pll = &rdev->clock.p1pll; | |
918 | break; | |
919 | case ATOM_PPLL2: | |
920 | pll = &rdev->clock.p2pll; | |
921 | break; | |
922 | case ATOM_DCPLL: | |
923 | case ATOM_PPLL_INVALID: | |
924 | default: | |
925 | pll = &rdev->clock.dcpll; | |
926 | break; | |
927 | } | |
928 | ||
ba032a58 AD |
929 | if (radeon_encoder->active_device & |
930 | (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { | |
931 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
932 | struct drm_connector *connector = | |
933 | radeon_get_connector_for_encoder(encoder); | |
934 | struct radeon_connector *radeon_connector = | |
935 | to_radeon_connector(connector); | |
936 | struct radeon_connector_atom_dig *dig_connector = | |
937 | radeon_connector->con_priv; | |
938 | int dp_clock; | |
df271bec | 939 | bpc = connector->display_info.bpc; |
ba032a58 AD |
940 | |
941 | switch (encoder_mode) { | |
942 | case ATOM_ENCODER_MODE_DP: | |
943 | /* DP/eDP */ | |
944 | dp_clock = dig_connector->dp_clock / 10; | |
2307790f AD |
945 | if (ASIC_IS_DCE4(rdev)) |
946 | ss_enabled = | |
947 | radeon_atombios_get_asic_ss_info(rdev, &ss, | |
948 | ASIC_INTERNAL_SS_ON_DP, | |
949 | dp_clock); | |
950 | else { | |
951 | if (dp_clock == 16200) { | |
ba032a58 | 952 | ss_enabled = |
2307790f AD |
953 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
954 | ATOM_DP_SS_ID2); | |
8e8e523d AD |
955 | if (!ss_enabled) |
956 | ss_enabled = | |
2307790f AD |
957 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
958 | ATOM_DP_SS_ID1); | |
8e8e523d | 959 | } else |
ba032a58 AD |
960 | ss_enabled = |
961 | radeon_atombios_get_ppll_ss_info(rdev, &ss, | |
2307790f | 962 | ATOM_DP_SS_ID1); |
ba032a58 AD |
963 | } |
964 | break; | |
965 | case ATOM_ENCODER_MODE_LVDS: | |
966 | if (ASIC_IS_DCE4(rdev)) | |
967 | ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, | |
968 | dig->lcd_ss_id, | |
969 | mode->clock / 10); | |
970 | else | |
971 | ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss, | |
972 | dig->lcd_ss_id); | |
973 | break; | |
974 | case ATOM_ENCODER_MODE_DVI: | |
975 | if (ASIC_IS_DCE4(rdev)) | |
976 | ss_enabled = | |
977 | radeon_atombios_get_asic_ss_info(rdev, &ss, | |
978 | ASIC_INTERNAL_SS_ON_TMDS, | |
979 | mode->clock / 10); | |
980 | break; | |
981 | case ATOM_ENCODER_MODE_HDMI: | |
982 | if (ASIC_IS_DCE4(rdev)) | |
983 | ss_enabled = | |
984 | radeon_atombios_get_asic_ss_info(rdev, &ss, | |
985 | ASIC_INTERNAL_SS_ON_HDMI, | |
986 | mode->clock / 10); | |
987 | break; | |
988 | default: | |
989 | break; | |
990 | } | |
991 | } | |
992 | ||
37f9003b | 993 | /* adjust pixel clock as needed */ |
ba032a58 | 994 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); |
37f9003b | 995 | |
64146f8b AD |
996 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
997 | /* TV seems to prefer the legacy algo on some boards */ | |
998 | radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, | |
999 | &ref_div, &post_div); | |
1000 | else if (ASIC_IS_AVIVO(rdev)) | |
619efb10 AD |
1001 | radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
1002 | &ref_div, &post_div); | |
1003 | else | |
1004 | radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, | |
1005 | &ref_div, &post_div); | |
37f9003b | 1006 | |
ba032a58 AD |
1007 | atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss); |
1008 | ||
37f9003b AD |
1009 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1010 | encoder_mode, radeon_encoder->encoder_id, mode->clock, | |
8e8e523d | 1011 | ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss); |
37f9003b | 1012 | |
ba032a58 AD |
1013 | if (ss_enabled) { |
1014 | /* calculate ss amount and step size */ | |
1015 | if (ASIC_IS_DCE4(rdev)) { | |
1016 | u32 step_size; | |
1017 | u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000; | |
1018 | ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; | |
8e8e523d | 1019 | ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
ba032a58 AD |
1020 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
1021 | if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) | |
1022 | step_size = (4 * amount * ref_div * (ss.rate * 2048)) / | |
1023 | (125 * 25 * pll->reference_freq / 100); | |
1024 | else | |
1025 | step_size = (2 * amount * ref_div * (ss.rate * 2048)) / | |
1026 | (125 * 25 * pll->reference_freq / 100); | |
1027 | ss.step = step_size; | |
1028 | } | |
1029 | ||
1030 | atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss); | |
1031 | } | |
37f9003b AD |
1032 | } |
1033 | ||
c9417bdd AD |
1034 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
1035 | struct drm_framebuffer *fb, | |
1036 | int x, int y, int atomic) | |
bcc1c2a1 AD |
1037 | { |
1038 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1039 | struct drm_device *dev = crtc->dev; | |
1040 | struct radeon_device *rdev = dev->dev_private; | |
1041 | struct radeon_framebuffer *radeon_fb; | |
4dd19b0d | 1042 | struct drm_framebuffer *target_fb; |
bcc1c2a1 AD |
1043 | struct drm_gem_object *obj; |
1044 | struct radeon_bo *rbo; | |
1045 | uint64_t fb_location; | |
1046 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; | |
fa6bee46 | 1047 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
fb9674bd | 1048 | u32 tmp; |
bcc1c2a1 AD |
1049 | int r; |
1050 | ||
1051 | /* no fb bound */ | |
4dd19b0d | 1052 | if (!atomic && !crtc->fb) { |
d9fdaafb | 1053 | DRM_DEBUG_KMS("No FB bound\n"); |
bcc1c2a1 AD |
1054 | return 0; |
1055 | } | |
1056 | ||
4dd19b0d CB |
1057 | if (atomic) { |
1058 | radeon_fb = to_radeon_framebuffer(fb); | |
1059 | target_fb = fb; | |
1060 | } | |
1061 | else { | |
1062 | radeon_fb = to_radeon_framebuffer(crtc->fb); | |
1063 | target_fb = crtc->fb; | |
1064 | } | |
bcc1c2a1 | 1065 | |
4dd19b0d CB |
1066 | /* If atomic, assume fb object is pinned & idle & fenced and |
1067 | * just update base pointers | |
1068 | */ | |
bcc1c2a1 | 1069 | obj = radeon_fb->obj; |
7e4d15d9 | 1070 | rbo = gem_to_radeon_bo(obj); |
bcc1c2a1 AD |
1071 | r = radeon_bo_reserve(rbo, false); |
1072 | if (unlikely(r != 0)) | |
1073 | return r; | |
4dd19b0d CB |
1074 | |
1075 | if (atomic) | |
1076 | fb_location = radeon_bo_gpu_offset(rbo); | |
1077 | else { | |
1078 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); | |
1079 | if (unlikely(r != 0)) { | |
1080 | radeon_bo_unreserve(rbo); | |
1081 | return -EINVAL; | |
1082 | } | |
bcc1c2a1 | 1083 | } |
4dd19b0d | 1084 | |
bcc1c2a1 AD |
1085 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1086 | radeon_bo_unreserve(rbo); | |
1087 | ||
4dd19b0d | 1088 | switch (target_fb->bits_per_pixel) { |
bcc1c2a1 AD |
1089 | case 8: |
1090 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | | |
1091 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); | |
1092 | break; | |
1093 | case 15: | |
1094 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | |
1095 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); | |
1096 | break; | |
1097 | case 16: | |
1098 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | |
1099 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); | |
fa6bee46 AD |
1100 | #ifdef __BIG_ENDIAN |
1101 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); | |
1102 | #endif | |
bcc1c2a1 AD |
1103 | break; |
1104 | case 24: | |
1105 | case 32: | |
1106 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | | |
1107 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); | |
fa6bee46 AD |
1108 | #ifdef __BIG_ENDIAN |
1109 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); | |
1110 | #endif | |
bcc1c2a1 AD |
1111 | break; |
1112 | default: | |
1113 | DRM_ERROR("Unsupported screen depth %d\n", | |
4dd19b0d | 1114 | target_fb->bits_per_pixel); |
bcc1c2a1 AD |
1115 | return -EINVAL; |
1116 | } | |
1117 | ||
97d66328 AD |
1118 | if (tiling_flags & RADEON_TILING_MACRO) |
1119 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); | |
1120 | else if (tiling_flags & RADEON_TILING_MICRO) | |
1121 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); | |
1122 | ||
bcc1c2a1 AD |
1123 | switch (radeon_crtc->crtc_id) { |
1124 | case 0: | |
1125 | WREG32(AVIVO_D1VGA_CONTROL, 0); | |
1126 | break; | |
1127 | case 1: | |
1128 | WREG32(AVIVO_D2VGA_CONTROL, 0); | |
1129 | break; | |
1130 | case 2: | |
1131 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); | |
1132 | break; | |
1133 | case 3: | |
1134 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); | |
1135 | break; | |
1136 | case 4: | |
1137 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); | |
1138 | break; | |
1139 | case 5: | |
1140 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); | |
1141 | break; | |
1142 | default: | |
1143 | break; | |
1144 | } | |
1145 | ||
1146 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
1147 | upper_32_bits(fb_location)); | |
1148 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
1149 | upper_32_bits(fb_location)); | |
1150 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
1151 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); | |
1152 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
1153 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); | |
1154 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); | |
fa6bee46 | 1155 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
bcc1c2a1 AD |
1156 | |
1157 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | |
1158 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | |
1159 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); | |
1160 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); | |
4dd19b0d CB |
1161 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1162 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); | |
bcc1c2a1 | 1163 | |
4dd19b0d | 1164 | fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); |
bcc1c2a1 AD |
1165 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1166 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); | |
1167 | ||
1168 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, | |
1169 | crtc->mode.vdisplay); | |
1170 | x &= ~3; | |
1171 | y &= ~1; | |
1172 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, | |
1173 | (x << 16) | y); | |
1174 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, | |
1175 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); | |
1176 | ||
fb9674bd AD |
1177 | /* pageflip setup */ |
1178 | /* make sure flip is at vb rather than hb */ | |
1179 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); | |
1180 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; | |
1181 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); | |
1182 | ||
1183 | /* set pageflip to happen anywhere in vblank interval */ | |
1184 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); | |
1185 | ||
4dd19b0d CB |
1186 | if (!atomic && fb && fb != crtc->fb) { |
1187 | radeon_fb = to_radeon_framebuffer(fb); | |
7e4d15d9 | 1188 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
bcc1c2a1 AD |
1189 | r = radeon_bo_reserve(rbo, false); |
1190 | if (unlikely(r != 0)) | |
1191 | return r; | |
1192 | radeon_bo_unpin(rbo); | |
1193 | radeon_bo_unreserve(rbo); | |
1194 | } | |
1195 | ||
1196 | /* Bytes per pixel may have changed */ | |
1197 | radeon_bandwidth_update(rdev); | |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
4dd19b0d CB |
1202 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
1203 | struct drm_framebuffer *fb, | |
1204 | int x, int y, int atomic) | |
771fe6b9 JG |
1205 | { |
1206 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1207 | struct drm_device *dev = crtc->dev; | |
1208 | struct radeon_device *rdev = dev->dev_private; | |
1209 | struct radeon_framebuffer *radeon_fb; | |
1210 | struct drm_gem_object *obj; | |
4c788679 | 1211 | struct radeon_bo *rbo; |
4dd19b0d | 1212 | struct drm_framebuffer *target_fb; |
771fe6b9 | 1213 | uint64_t fb_location; |
e024e110 | 1214 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
fa6bee46 | 1215 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
fb9674bd | 1216 | u32 tmp; |
4c788679 | 1217 | int r; |
771fe6b9 | 1218 | |
2de3b484 | 1219 | /* no fb bound */ |
4dd19b0d | 1220 | if (!atomic && !crtc->fb) { |
d9fdaafb | 1221 | DRM_DEBUG_KMS("No FB bound\n"); |
2de3b484 JG |
1222 | return 0; |
1223 | } | |
771fe6b9 | 1224 | |
4dd19b0d CB |
1225 | if (atomic) { |
1226 | radeon_fb = to_radeon_framebuffer(fb); | |
1227 | target_fb = fb; | |
1228 | } | |
1229 | else { | |
1230 | radeon_fb = to_radeon_framebuffer(crtc->fb); | |
1231 | target_fb = crtc->fb; | |
1232 | } | |
771fe6b9 JG |
1233 | |
1234 | obj = radeon_fb->obj; | |
7e4d15d9 | 1235 | rbo = gem_to_radeon_bo(obj); |
4c788679 JG |
1236 | r = radeon_bo_reserve(rbo, false); |
1237 | if (unlikely(r != 0)) | |
1238 | return r; | |
4dd19b0d CB |
1239 | |
1240 | /* If atomic, assume fb object is pinned & idle & fenced and | |
1241 | * just update base pointers | |
1242 | */ | |
1243 | if (atomic) | |
1244 | fb_location = radeon_bo_gpu_offset(rbo); | |
1245 | else { | |
1246 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); | |
1247 | if (unlikely(r != 0)) { | |
1248 | radeon_bo_unreserve(rbo); | |
1249 | return -EINVAL; | |
1250 | } | |
771fe6b9 | 1251 | } |
4c788679 JG |
1252 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1253 | radeon_bo_unreserve(rbo); | |
771fe6b9 | 1254 | |
4dd19b0d | 1255 | switch (target_fb->bits_per_pixel) { |
41456df2 DA |
1256 | case 8: |
1257 | fb_format = | |
1258 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | | |
1259 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; | |
1260 | break; | |
771fe6b9 JG |
1261 | case 15: |
1262 | fb_format = | |
1263 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | |
1264 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; | |
1265 | break; | |
1266 | case 16: | |
1267 | fb_format = | |
1268 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | |
1269 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; | |
fa6bee46 AD |
1270 | #ifdef __BIG_ENDIAN |
1271 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; | |
1272 | #endif | |
771fe6b9 JG |
1273 | break; |
1274 | case 24: | |
1275 | case 32: | |
1276 | fb_format = | |
1277 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | | |
1278 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; | |
fa6bee46 AD |
1279 | #ifdef __BIG_ENDIAN |
1280 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; | |
1281 | #endif | |
771fe6b9 JG |
1282 | break; |
1283 | default: | |
1284 | DRM_ERROR("Unsupported screen depth %d\n", | |
4dd19b0d | 1285 | target_fb->bits_per_pixel); |
771fe6b9 JG |
1286 | return -EINVAL; |
1287 | } | |
1288 | ||
40c4ac1c AD |
1289 | if (rdev->family >= CHIP_R600) { |
1290 | if (tiling_flags & RADEON_TILING_MACRO) | |
1291 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; | |
1292 | else if (tiling_flags & RADEON_TILING_MICRO) | |
1293 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; | |
1294 | } else { | |
1295 | if (tiling_flags & RADEON_TILING_MACRO) | |
1296 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; | |
cf2f05d3 | 1297 | |
40c4ac1c AD |
1298 | if (tiling_flags & RADEON_TILING_MICRO) |
1299 | fb_format |= AVIVO_D1GRPH_TILED; | |
1300 | } | |
e024e110 | 1301 | |
771fe6b9 JG |
1302 | if (radeon_crtc->crtc_id == 0) |
1303 | WREG32(AVIVO_D1VGA_CONTROL, 0); | |
1304 | else | |
1305 | WREG32(AVIVO_D2VGA_CONTROL, 0); | |
c290dadf AD |
1306 | |
1307 | if (rdev->family >= CHIP_RV770) { | |
1308 | if (radeon_crtc->crtc_id) { | |
95347871 AD |
1309 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1310 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); | |
c290dadf | 1311 | } else { |
95347871 AD |
1312 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1313 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); | |
c290dadf AD |
1314 | } |
1315 | } | |
771fe6b9 JG |
1316 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1317 | (u32) fb_location); | |
1318 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + | |
1319 | radeon_crtc->crtc_offset, (u32) fb_location); | |
1320 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); | |
fa6bee46 AD |
1321 | if (rdev->family >= CHIP_R600) |
1322 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); | |
771fe6b9 JG |
1323 | |
1324 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | |
1325 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | |
1326 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); | |
1327 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); | |
4dd19b0d CB |
1328 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1329 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); | |
771fe6b9 | 1330 | |
4dd19b0d | 1331 | fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); |
771fe6b9 JG |
1332 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1333 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); | |
1334 | ||
1335 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, | |
1336 | crtc->mode.vdisplay); | |
1337 | x &= ~3; | |
1338 | y &= ~1; | |
1339 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, | |
1340 | (x << 16) | y); | |
1341 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, | |
1342 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); | |
1343 | ||
fb9674bd AD |
1344 | /* pageflip setup */ |
1345 | /* make sure flip is at vb rather than hb */ | |
1346 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); | |
1347 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; | |
1348 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); | |
1349 | ||
1350 | /* set pageflip to happen anywhere in vblank interval */ | |
1351 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); | |
1352 | ||
4dd19b0d CB |
1353 | if (!atomic && fb && fb != crtc->fb) { |
1354 | radeon_fb = to_radeon_framebuffer(fb); | |
7e4d15d9 | 1355 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
4c788679 JG |
1356 | r = radeon_bo_reserve(rbo, false); |
1357 | if (unlikely(r != 0)) | |
1358 | return r; | |
1359 | radeon_bo_unpin(rbo); | |
1360 | radeon_bo_unreserve(rbo); | |
771fe6b9 | 1361 | } |
f30f37de MD |
1362 | |
1363 | /* Bytes per pixel may have changed */ | |
1364 | radeon_bandwidth_update(rdev); | |
1365 | ||
771fe6b9 JG |
1366 | return 0; |
1367 | } | |
1368 | ||
54f088a9 AD |
1369 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
1370 | struct drm_framebuffer *old_fb) | |
1371 | { | |
1372 | struct drm_device *dev = crtc->dev; | |
1373 | struct radeon_device *rdev = dev->dev_private; | |
1374 | ||
bcc1c2a1 | 1375 | if (ASIC_IS_DCE4(rdev)) |
c9417bdd | 1376 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
4dd19b0d CB |
1377 | else if (ASIC_IS_AVIVO(rdev)) |
1378 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
1379 | else | |
1380 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
1381 | } | |
1382 | ||
1383 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, | |
1384 | struct drm_framebuffer *fb, | |
21c74a8e | 1385 | int x, int y, enum mode_set_atomic state) |
4dd19b0d CB |
1386 | { |
1387 | struct drm_device *dev = crtc->dev; | |
1388 | struct radeon_device *rdev = dev->dev_private; | |
1389 | ||
1390 | if (ASIC_IS_DCE4(rdev)) | |
c9417bdd | 1391 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
bcc1c2a1 | 1392 | else if (ASIC_IS_AVIVO(rdev)) |
4dd19b0d | 1393 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
54f088a9 | 1394 | else |
4dd19b0d | 1395 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
54f088a9 AD |
1396 | } |
1397 | ||
615e0cb6 AD |
1398 | /* properly set additional regs when using atombios */ |
1399 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) | |
1400 | { | |
1401 | struct drm_device *dev = crtc->dev; | |
1402 | struct radeon_device *rdev = dev->dev_private; | |
1403 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1404 | u32 disp_merge_cntl; | |
1405 | ||
1406 | switch (radeon_crtc->crtc_id) { | |
1407 | case 0: | |
1408 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); | |
1409 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; | |
1410 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); | |
1411 | break; | |
1412 | case 1: | |
1413 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); | |
1414 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; | |
1415 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); | |
1416 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); | |
1417 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); | |
1418 | break; | |
1419 | } | |
1420 | } | |
1421 | ||
bcc1c2a1 AD |
1422 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1423 | { | |
1424 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1425 | struct drm_device *dev = crtc->dev; | |
1426 | struct radeon_device *rdev = dev->dev_private; | |
1427 | struct drm_encoder *test_encoder; | |
1428 | struct drm_crtc *test_crtc; | |
1429 | uint32_t pll_in_use = 0; | |
1430 | ||
1431 | if (ASIC_IS_DCE4(rdev)) { | |
bcc1c2a1 AD |
1432 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
1433 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { | |
86a94def AD |
1434 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1435 | * depending on the asic: | |
1436 | * DCE4: PPLL or ext clock | |
1437 | * DCE5: DCPLL or ext clock | |
1438 | * | |
1439 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip | |
1440 | * PPLL/DCPLL programming and only program the DP DTO for the | |
1441 | * crtc virtual pixel clock. | |
1442 | */ | |
bcc1c2a1 | 1443 | if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { |
86a94def | 1444 | if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) |
bcc1c2a1 AD |
1445 | return ATOM_PPLL_INVALID; |
1446 | } | |
1447 | } | |
1448 | } | |
1449 | ||
1450 | /* otherwise, pick one of the plls */ | |
1451 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { | |
1452 | struct radeon_crtc *radeon_test_crtc; | |
1453 | ||
1454 | if (crtc == test_crtc) | |
1455 | continue; | |
1456 | ||
1457 | radeon_test_crtc = to_radeon_crtc(test_crtc); | |
1458 | if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && | |
1459 | (radeon_test_crtc->pll_id <= ATOM_PPLL2)) | |
1460 | pll_in_use |= (1 << radeon_test_crtc->pll_id); | |
1461 | } | |
1462 | if (!(pll_in_use & 1)) | |
1463 | return ATOM_PPLL1; | |
1464 | return ATOM_PPLL2; | |
1465 | } else | |
1466 | return radeon_crtc->crtc_id; | |
1467 | ||
1468 | } | |
1469 | ||
771fe6b9 JG |
1470 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
1471 | struct drm_display_mode *mode, | |
1472 | struct drm_display_mode *adjusted_mode, | |
1473 | int x, int y, struct drm_framebuffer *old_fb) | |
1474 | { | |
1475 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1476 | struct drm_device *dev = crtc->dev; | |
1477 | struct radeon_device *rdev = dev->dev_private; | |
54bfe496 AD |
1478 | struct drm_encoder *encoder; |
1479 | bool is_tvcv = false; | |
771fe6b9 | 1480 | |
54bfe496 AD |
1481 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1482 | /* find tv std */ | |
1483 | if (encoder->crtc == crtc) { | |
1484 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1485 | if (radeon_encoder->active_device & | |
1486 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
1487 | is_tvcv = true; | |
1488 | } | |
1489 | } | |
771fe6b9 | 1490 | |
bcc1c2a1 | 1491 | /* always set DCPLL */ |
ba032a58 AD |
1492 | if (ASIC_IS_DCE4(rdev)) { |
1493 | struct radeon_atom_ss ss; | |
1494 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, | |
1495 | ASIC_INTERNAL_SS_ON_DCPLL, | |
1496 | rdev->clock.default_dispclk); | |
1497 | if (ss_enabled) | |
1498 | atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss); | |
f82b3ddc AD |
1499 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
1500 | atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk); | |
ba032a58 AD |
1501 | if (ss_enabled) |
1502 | atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss); | |
1503 | } | |
771fe6b9 | 1504 | atombios_crtc_set_pll(crtc, adjusted_mode); |
771fe6b9 | 1505 | |
54bfe496 | 1506 | if (ASIC_IS_DCE4(rdev)) |
bcc1c2a1 | 1507 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
54bfe496 AD |
1508 | else if (ASIC_IS_AVIVO(rdev)) { |
1509 | if (is_tvcv) | |
1510 | atombios_crtc_set_timing(crtc, adjusted_mode); | |
1511 | else | |
1512 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | |
1513 | } else { | |
bcc1c2a1 | 1514 | atombios_crtc_set_timing(crtc, adjusted_mode); |
5a9bcacc AD |
1515 | if (radeon_crtc->crtc_id == 0) |
1516 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | |
615e0cb6 | 1517 | radeon_legacy_atom_fixup(crtc); |
771fe6b9 | 1518 | } |
bcc1c2a1 | 1519 | atombios_crtc_set_base(crtc, x, y, old_fb); |
c93bb85b JG |
1520 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
1521 | atombios_scaler_setup(crtc); | |
771fe6b9 JG |
1522 | return 0; |
1523 | } | |
1524 | ||
1525 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, | |
1526 | struct drm_display_mode *mode, | |
1527 | struct drm_display_mode *adjusted_mode) | |
1528 | { | |
03214bd5 AD |
1529 | struct drm_device *dev = crtc->dev; |
1530 | struct radeon_device *rdev = dev->dev_private; | |
1531 | ||
1532 | /* adjust pm to upcoming mode change */ | |
1533 | radeon_pm_compute_clocks(rdev); | |
1534 | ||
c93bb85b JG |
1535 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1536 | return false; | |
771fe6b9 JG |
1537 | return true; |
1538 | } | |
1539 | ||
1540 | static void atombios_crtc_prepare(struct drm_crtc *crtc) | |
1541 | { | |
267364ac AD |
1542 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1543 | ||
1544 | /* pick pll */ | |
1545 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); | |
1546 | ||
37b4390e | 1547 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
a348c84d | 1548 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
771fe6b9 JG |
1549 | } |
1550 | ||
1551 | static void atombios_crtc_commit(struct drm_crtc *crtc) | |
1552 | { | |
1553 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); | |
37b4390e | 1554 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
771fe6b9 JG |
1555 | } |
1556 | ||
37f9003b AD |
1557 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
1558 | { | |
1559 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
8e8e523d AD |
1560 | struct radeon_atom_ss ss; |
1561 | ||
37f9003b AD |
1562 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
1563 | ||
1564 | switch (radeon_crtc->pll_id) { | |
1565 | case ATOM_PPLL1: | |
1566 | case ATOM_PPLL2: | |
1567 | /* disable the ppll */ | |
1568 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, | |
8e8e523d | 1569 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
37f9003b AD |
1570 | break; |
1571 | default: | |
1572 | break; | |
1573 | } | |
1574 | radeon_crtc->pll_id = -1; | |
1575 | } | |
1576 | ||
771fe6b9 JG |
1577 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
1578 | .dpms = atombios_crtc_dpms, | |
1579 | .mode_fixup = atombios_crtc_mode_fixup, | |
1580 | .mode_set = atombios_crtc_mode_set, | |
1581 | .mode_set_base = atombios_crtc_set_base, | |
4dd19b0d | 1582 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
771fe6b9 JG |
1583 | .prepare = atombios_crtc_prepare, |
1584 | .commit = atombios_crtc_commit, | |
068143d3 | 1585 | .load_lut = radeon_crtc_load_lut, |
37f9003b | 1586 | .disable = atombios_crtc_disable, |
771fe6b9 JG |
1587 | }; |
1588 | ||
1589 | void radeon_atombios_init_crtc(struct drm_device *dev, | |
1590 | struct radeon_crtc *radeon_crtc) | |
1591 | { | |
bcc1c2a1 AD |
1592 | struct radeon_device *rdev = dev->dev_private; |
1593 | ||
1594 | if (ASIC_IS_DCE4(rdev)) { | |
1595 | switch (radeon_crtc->crtc_id) { | |
1596 | case 0: | |
1597 | default: | |
12d7798f | 1598 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
bcc1c2a1 AD |
1599 | break; |
1600 | case 1: | |
12d7798f | 1601 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
bcc1c2a1 AD |
1602 | break; |
1603 | case 2: | |
12d7798f | 1604 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
bcc1c2a1 AD |
1605 | break; |
1606 | case 3: | |
12d7798f | 1607 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
bcc1c2a1 AD |
1608 | break; |
1609 | case 4: | |
12d7798f | 1610 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
bcc1c2a1 AD |
1611 | break; |
1612 | case 5: | |
12d7798f | 1613 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
bcc1c2a1 AD |
1614 | break; |
1615 | } | |
1616 | } else { | |
1617 | if (radeon_crtc->crtc_id == 1) | |
1618 | radeon_crtc->crtc_offset = | |
1619 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; | |
1620 | else | |
1621 | radeon_crtc->crtc_offset = 0; | |
1622 | } | |
1623 | radeon_crtc->pll_id = -1; | |
771fe6b9 JG |
1624 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
1625 | } |