]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/radeon/atombios_crtc.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: pll tweaks for rv6xx
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
942b0e95
AD		 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 258 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 261 radeon_crtc->enabled = false;
d7311171
AD		 262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 264 break;
265 }
771fe6b9
JG		 266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 270 struct drm_display_mode *mode)
771fe6b9 271{
5a9bcacc 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 277 u16 misc = 0;
771fe6b9 278
5a9bcacc 279 memset(&args, 0, sizeof(args));
5b1714d3 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 281 args.usH_Blanking_Time =
5b1714d3
AD		 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 284 args.usV_Blanking_Time =
5b1714d3 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 286 args.usH_SyncOffset =
5b1714d3 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
5b1714d3 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 310
5a9bcacc 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 312}
313
5a9bcacc
AD		 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
771fe6b9 316{
5a9bcacc 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 322 u16 misc = 0;
771fe6b9 323
5a9bcacc
AD		 324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
54bfe496
AD		 336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
5a9bcacc
AD		 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 354
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
b792210e
AD		 358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
26b9fc3a 401union atom_enable_ss {
ba032a58
AD		 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 407};
408
ba032a58
AD		 409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
ebbe1cb9 413{
ebbe1cb9
AD		 414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
ebbe1cb9 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 417 union atom_enable_ss args;
ebbe1cb9 418
ba032a58 419 memset(&args, 0, sizeof(args));
bcc1c2a1 420
a572eaa3 421 if (ASIC_IS_DCE5(rdev)) {
4589433c 422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
a572eaa3
AD		 423 args.v3.ucSpreadSpectrumType = ss->type;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
4589433c
CC		 427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
4589433c
CC		 432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
4589433c
CC		 437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
a572eaa3
AD		 439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v2.ucEnable = enable;
444 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58
AD		 445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446 args.v2.ucSpreadSpectrumType = ss->type;
447 switch (pll_id) {
448 case ATOM_PPLL1:
449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
4589433c
CC		 450 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
451 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 452 break;
453 case ATOM_PPLL2:
454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
4589433c
CC		 455 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
456 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ebbe1cb9 457 break;
ba032a58
AD		 458 case ATOM_DCPLL:
459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
4589433c
CC		 460 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
461 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
ba032a58
AD		 462 break;
463 case ATOM_PPLL_INVALID:
464 return;
ebbe1cb9 465 }
ba032a58
AD		 466 args.v2.ucEnable = enable;
467 } else if (ASIC_IS_DCE3(rdev)) {
468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469 args.v1.ucSpreadSpectrumType = ss->type;
470 args.v1.ucSpreadSpectrumStep = ss->step;
471 args.v1.ucSpreadSpectrumDelay = ss->delay;
472 args.v1.ucSpreadSpectrumRange = ss->range;
473 args.v1.ucPpll = pll_id;
474 args.v1.ucEnable = enable;
475 } else if (ASIC_IS_AVIVO(rdev)) {
476 if (enable == ATOM_DISABLE) {
477 atombios_disable_ss(crtc);
478 return;
479 }
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 486 } else {
ba032a58
AD		 487 if (enable == ATOM_DISABLE) {
488 atombios_disable_ss(crtc);
489 return;
490 }
491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.lvds_ss.ucSpreadSpectrumType = ss->type;
493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495 args.lvds_ss.ucEnable = enable;
ebbe1cb9 496 }
26b9fc3a 497 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 498}
499
4eaeca33
AD		 500union adjust_pixel_clock {
501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 503};
504
505static u32 atombios_adjust_pll(struct drm_crtc *crtc,
506 struct drm_display_mode *mode,
ba032a58
AD		 507 struct radeon_pll *pll,
508 bool ss_enabled,
509 struct radeon_atom_ss *ss)
771fe6b9 510{
771fe6b9
JG		 511 struct drm_device *dev = crtc->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct drm_encoder *encoder = NULL;
514 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 515 u32 adjusted_clock = mode->clock;
bcc1c2a1 516 int encoder_mode = 0;
fbee67a6
AD		 517 u32 dp_clock = mode->clock;
518 int bpc = 8;
fc10332b 519
4eaeca33
AD		 520 /* reset the pll flags */
521 pll->flags = 0;
771fe6b9
JG		 522
523 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 524 if ((rdev->family == CHIP_RS600) ||
525 (rdev->family == CHIP_RS690) ||
526 (rdev->family == CHIP_RS740))
2ff776cf 527 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 528 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 529
530 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
532 else
533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
9bb09fa1
AD		 534
535 if ((rdev->family == CHIP_R600) ||
536 (rdev->family == CHIP_RV610) ||
537 (rdev->family == CHIP_RV630) ||
538 (rdev->family == CHIP_RV670))
539 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
5480f727 540 } else {
fc10332b 541 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 542
5480f727
DA		 543 if (mode->clock > 200000) /* range limits??? */
544 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
545 else
546 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
5480f727
DA		 547 }
548
771fe6b9
JG		 549 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
550 if (encoder->crtc == crtc) {
4eaeca33 551 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 552 encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6
AD		 553 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
554 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
555 if (connector) {
556 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
557 struct radeon_connector_atom_dig *dig_connector =
558 radeon_connector->con_priv;
559
560 dp_clock = dig_connector->dp_clock;
561 }
562 }
5b40ddf8 563
ba032a58
AD		 564 /* use recommended ref_div for ss */
565 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
566 if (ss_enabled) {
567 if (ss->refdiv) {
9f4283f4 568 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
ba032a58
AD		 569 pll->flags |= RADEON_PLL_USE_REF_DIV;
570 pll->reference_div = ss->refdiv;
5b40ddf8
AD		 571 if (ASIC_IS_AVIVO(rdev))
572 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
ba032a58
AD		 573 }
574 }
575 }
5b40ddf8 576
4eaeca33
AD		 577 if (ASIC_IS_AVIVO(rdev)) {
578 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
579 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
580 adjusted_clock = mode->clock * 2;
48dfaaeb 581 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 582 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
5b40ddf8
AD		 583 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
584 pll->flags |= RADEON_PLL_IS_LCD;
4eaeca33
AD		 585 } else {
586 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 587 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 588 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 589 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 590 }
3ce0a23d 591 break;
771fe6b9
JG		 592 }
593 }
594
2606c886
AD		 595 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
596 * accordingly based on the encoder/transmitter to work around
597 * special hw requirements.
598 */
599 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 600 union adjust_pixel_clock args;
4eaeca33
AD		 601 u8 frev, crev;
602 int index;
2606c886 603
2606c886 604 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 605 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
606 &crev))
607 return adjusted_clock;
4eaeca33
AD		 608
609 memset(&args, 0, sizeof(args));
610
611 switch (frev) {
612 case 1:
613 switch (crev) {
614 case 1:
615 case 2:
616 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
617 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 618 args.v1.ucEncodeMode = encoder_mode;
b526ce22 619 if (ss_enabled)
fbee67a6
AD		 620 args.v1.ucConfig |=
621 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 622
623 atom_execute_table(rdev->mode_info.atom_context,
624 index, (uint32_t *)&args);
625 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
626 break;
bcc1c2a1
AD		 627 case 3:
628 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
629 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
630 args.v3.sInput.ucEncodeMode = encoder_mode;
631 args.v3.sInput.ucDispPllConfig = 0;
b526ce22
AD		 632 if (ss_enabled)
633 args.v3.sInput.ucDispPllConfig |=
634 DISPPLL_CONFIG_SS_ENABLE;
bcc1c2a1
AD		 635 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
636 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
fbee67a6 637 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1
AD		 638 args.v3.sInput.ucDispPllConfig |=
639 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 640 /* 16200 or 27000 */
641 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
642 } else {
643 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
644 /* deep color support */
645 args.v3.sInput.usPixelClock =
646 cpu_to_le16((mode->clock * bpc / 8) / 10);
647 }
bcc1c2a1
AD		 648 if (dig->coherent_mode)
649 args.v3.sInput.ucDispPllConfig |=
650 DISPPLL_CONFIG_COHERENT_MODE;
651 if (mode->clock > 165000)
652 args.v3.sInput.ucDispPllConfig |=
653 DISPPLL_CONFIG_DUAL_LINK;
654 }
655 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
fbee67a6 656 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1 657 args.v3.sInput.ucDispPllConfig |=
9f998ad7 658 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 659 /* 16200 or 27000 */
660 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
b526ce22 661 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
9f998ad7
AD		 662 if (mode->clock > 165000)
663 args.v3.sInput.ucDispPllConfig |=
664 DISPPLL_CONFIG_DUAL_LINK;
665 }
bcc1c2a1
AD		 666 }
667 atom_execute_table(rdev->mode_info.atom_context,
668 index, (uint32_t *)&args);
669 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
670 if (args.v3.sOutput.ucRefDiv) {
9f4283f4 671 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 672 pll->flags |= RADEON_PLL_USE_REF_DIV;
673 pll->reference_div = args.v3.sOutput.ucRefDiv;
674 }
675 if (args.v3.sOutput.ucPostDiv) {
9f4283f4 676 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 677 pll->flags |= RADEON_PLL_USE_POST_DIV;
678 pll->post_div = args.v3.sOutput.ucPostDiv;
679 }
680 break;
4eaeca33
AD		 681 default:
682 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
683 return adjusted_clock;
684 }
685 break;
686 default:
687 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
688 return adjusted_clock;
689 }
d56ef9c8 690 }
4eaeca33
AD		 691 return adjusted_clock;
692}
693
694union set_pixel_clock {
695 SET_PIXEL_CLOCK_PS_ALLOCATION base;
696 PIXEL_CLOCK_PARAMETERS v1;
697 PIXEL_CLOCK_PARAMETERS_V2 v2;
698 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 699 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 700 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 701};
702
f82b3ddc
AD		 703/* on DCE5, make sure the voltage is high enough to support the
704 * required disp clk.
705 */
706static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
707 u32 dispclk)
bcc1c2a1
AD		 708{
709 struct drm_device *dev = crtc->dev;
710 struct radeon_device *rdev = dev->dev_private;
711 u8 frev, crev;
712 int index;
713 union set_pixel_clock args;
714
715 memset(&args, 0, sizeof(args));
716
717 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 718 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
719 &crev))
720 return;
bcc1c2a1
AD		 721
722 switch (frev) {
723 case 1:
724 switch (crev) {
725 case 5:
726 /* if the default dcpll clock is specified,
727 * SetPixelClock provides the dividers
728 */
729 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 730 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 731 args.v5.ucPpll = ATOM_DCPLL;
732 break;
f82b3ddc
AD		 733 case 6:
734 /* if the default dcpll clock is specified,
735 * SetPixelClock provides the dividers
736 */
265aa6c8 737 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
f82b3ddc
AD		 738 args.v6.ucPpll = ATOM_DCPLL;
739 break;
bcc1c2a1
AD		 740 default:
741 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
742 return;
743 }
744 break;
745 default:
746 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
747 return;
748 }
749 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
750}
751
37f9003b
AD		 752static void atombios_crtc_program_pll(struct drm_crtc *crtc,
753 int crtc_id,
754 int pll_id,
755 u32 encoder_mode,
756 u32 encoder_id,
757 u32 clock,
758 u32 ref_div,
759 u32 fb_div,
760 u32 frac_fb_div,
761 u32 post_div)
4eaeca33 762{
4eaeca33
AD		 763 struct drm_device *dev = crtc->dev;
764 struct radeon_device *rdev = dev->dev_private;
4eaeca33 765 u8 frev, crev;
37f9003b 766 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 767 union set_pixel_clock args;
4eaeca33
AD		 768
769 memset(&args, 0, sizeof(args));
770
a084e6ee
AD		 771 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
772 &crev))
773 return;
771fe6b9
JG		 774
775 switch (frev) {
776 case 1:
777 switch (crev) {
778 case 1:
37f9003b
AD		 779 if (clock == ATOM_DISABLE)
780 return;
781 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 782 args.v1.usRefDiv = cpu_to_le16(ref_div);
783 args.v1.usFbDiv = cpu_to_le16(fb_div);
784 args.v1.ucFracFbDiv = frac_fb_div;
785 args.v1.ucPostDiv = post_div;
37f9003b
AD		 786 args.v1.ucPpll = pll_id;
787 args.v1.ucCRTC = crtc_id;
4eaeca33 788 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 789 break;
790 case 2:
37f9003b 791 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 792 args.v2.usRefDiv = cpu_to_le16(ref_div);
793 args.v2.usFbDiv = cpu_to_le16(fb_div);
794 args.v2.ucFracFbDiv = frac_fb_div;
795 args.v2.ucPostDiv = post_div;
37f9003b
AD		 796 args.v2.ucPpll = pll_id;
797 args.v2.ucCRTC = crtc_id;
4eaeca33 798 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 799 break;
800 case 3:
37f9003b 801 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 802 args.v3.usRefDiv = cpu_to_le16(ref_div);
803 args.v3.usFbDiv = cpu_to_le16(fb_div);
804 args.v3.ucFracFbDiv = frac_fb_div;
805 args.v3.ucPostDiv = post_div;
37f9003b
AD		 806 args.v3.ucPpll = pll_id;
807 args.v3.ucMiscInfo = (pll_id << 2);
808 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 809 args.v3.ucEncoderMode = encoder_mode;
810 break;
811 case 5:
37f9003b
AD		 812 args.v5.ucCRTC = crtc_id;
813 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 814 args.v5.ucRefDiv = ref_div;
815 args.v5.usFbDiv = cpu_to_le16(fb_div);
816 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
817 args.v5.ucPostDiv = post_div;
818 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
37f9003b 819 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 820 args.v5.ucEncoderMode = encoder_mode;
37f9003b 821 args.v5.ucPpll = pll_id;
771fe6b9 822 break;
f82b3ddc
AD		 823 case 6:
824 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
825 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
826 args.v6.ucRefDiv = ref_div;
827 args.v6.usFbDiv = cpu_to_le16(fb_div);
828 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
829 args.v6.ucPostDiv = post_div;
830 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
831 args.v6.ucTransmitterID = encoder_id;
832 args.v6.ucEncoderMode = encoder_mode;
833 args.v6.ucPpll = pll_id;
834 break;
771fe6b9
JG		 835 default:
836 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
837 return;
838 }
839 break;
840 default:
841 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
842 return;
843 }
844
771fe6b9
JG		 845 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
846}
847
37f9003b
AD		 848static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
849{
850 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
851 struct drm_device *dev = crtc->dev;
852 struct radeon_device *rdev = dev->dev_private;
853 struct drm_encoder *encoder = NULL;
854 struct radeon_encoder *radeon_encoder = NULL;
855 u32 pll_clock = mode->clock;
856 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
857 struct radeon_pll *pll;
858 u32 adjusted_clock;
859 int encoder_mode = 0;
ba032a58
AD		 860 struct radeon_atom_ss ss;
861 bool ss_enabled = false;
37f9003b
AD		 862
863 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
864 if (encoder->crtc == crtc) {
865 radeon_encoder = to_radeon_encoder(encoder);
866 encoder_mode = atombios_get_encoder_mode(encoder);
867 break;
868 }
869 }
870
871 if (!radeon_encoder)
872 return;
873
874 switch (radeon_crtc->pll_id) {
875 case ATOM_PPLL1:
876 pll = &rdev->clock.p1pll;
877 break;
878 case ATOM_PPLL2:
879 pll = &rdev->clock.p2pll;
880 break;
881 case ATOM_DCPLL:
882 case ATOM_PPLL_INVALID:
883 default:
884 pll = &rdev->clock.dcpll;
885 break;
886 }
887
ba032a58
AD		 888 if (radeon_encoder->active_device &
889 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
890 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
891 struct drm_connector *connector =
892 radeon_get_connector_for_encoder(encoder);
893 struct radeon_connector *radeon_connector =
894 to_radeon_connector(connector);
895 struct radeon_connector_atom_dig *dig_connector =
896 radeon_connector->con_priv;
897 int dp_clock;
898
899 switch (encoder_mode) {
900 case ATOM_ENCODER_MODE_DP:
901 /* DP/eDP */
902 dp_clock = dig_connector->dp_clock / 10;
903 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
904 if (ASIC_IS_DCE4(rdev))
905 ss_enabled =
906 radeon_atombios_get_asic_ss_info(rdev, &ss,
907 dig->lcd_ss_id,
908 dp_clock);
909 else
910 ss_enabled =
911 radeon_atombios_get_ppll_ss_info(rdev, &ss,
912 dig->lcd_ss_id);
913 } else {
914 if (ASIC_IS_DCE4(rdev))
915 ss_enabled =
916 radeon_atombios_get_asic_ss_info(rdev, &ss,
917 ASIC_INTERNAL_SS_ON_DP,
918 dp_clock);
919 else {
920 if (dp_clock == 16200) {
921 ss_enabled =
922 radeon_atombios_get_ppll_ss_info(rdev, &ss,
923 ATOM_DP_SS_ID2);
924 if (!ss_enabled)
925 ss_enabled =
926 radeon_atombios_get_ppll_ss_info(rdev, &ss,
927 ATOM_DP_SS_ID1);
928 } else
929 ss_enabled =
930 radeon_atombios_get_ppll_ss_info(rdev, &ss,
931 ATOM_DP_SS_ID1);
932 }
933 }
934 break;
935 case ATOM_ENCODER_MODE_LVDS:
936 if (ASIC_IS_DCE4(rdev))
937 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
938 dig->lcd_ss_id,
939 mode->clock / 10);
940 else
941 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
942 dig->lcd_ss_id);
943 break;
944 case ATOM_ENCODER_MODE_DVI:
945 if (ASIC_IS_DCE4(rdev))
946 ss_enabled =
947 radeon_atombios_get_asic_ss_info(rdev, &ss,
948 ASIC_INTERNAL_SS_ON_TMDS,
949 mode->clock / 10);
950 break;
951 case ATOM_ENCODER_MODE_HDMI:
952 if (ASIC_IS_DCE4(rdev))
953 ss_enabled =
954 radeon_atombios_get_asic_ss_info(rdev, &ss,
955 ASIC_INTERNAL_SS_ON_HDMI,
956 mode->clock / 10);
957 break;
958 default:
959 break;
960 }
961 }
962
37f9003b 963 /* adjust pixel clock as needed */
ba032a58 964 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b 965
64146f8b
AD		 966 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
967 /* TV seems to prefer the legacy algo on some boards */
968 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
969 &ref_div, &post_div);
970 else if (ASIC_IS_AVIVO(rdev))
619efb10
AD		 971 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
972 &ref_div, &post_div);
973 else
974 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
975 &ref_div, &post_div);
37f9003b 976
ba032a58
AD		 977 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
978
37f9003b
AD		 979 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
980 encoder_mode, radeon_encoder->encoder_id, mode->clock,
981 ref_div, fb_div, frac_fb_div, post_div);
982
ba032a58
AD		 983 if (ss_enabled) {
984 /* calculate ss amount and step size */
985 if (ASIC_IS_DCE4(rdev)) {
986 u32 step_size;
987 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
988 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
989 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
990 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
991 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
992 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
993 (125 * 25 * pll->reference_freq / 100);
994 else
995 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
996 (125 * 25 * pll->reference_freq / 100);
997 ss.step = step_size;
998 }
999
1000 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1001 }
37f9003b
AD		 1002}
1003
c9417bdd
AD		 1004static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1005 struct drm_framebuffer *fb,
1006 int x, int y, int atomic)
bcc1c2a1
AD		 1007{
1008 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1009 struct drm_device *dev = crtc->dev;
1010 struct radeon_device *rdev = dev->dev_private;
1011 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1012 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1013 struct drm_gem_object *obj;
1014 struct radeon_bo *rbo;
1015 uint64_t fb_location;
1016 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1017 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
fb9674bd 1018 u32 tmp;
bcc1c2a1
AD		 1019 int r;
1020
1021 /* no fb bound */
4dd19b0d 1022 if (!atomic && !crtc->fb) {
d9fdaafb 1023 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1024 return 0;
1025 }
1026
4dd19b0d
CB		 1027 if (atomic) {
1028 radeon_fb = to_radeon_framebuffer(fb);
1029 target_fb = fb;
1030 }
1031 else {
1032 radeon_fb = to_radeon_framebuffer(crtc->fb);
1033 target_fb = crtc->fb;
1034 }
bcc1c2a1 1035
4dd19b0d
CB		 1036 /* If atomic, assume fb object is pinned & idle & fenced and
1037 * just update base pointers
1038 */
bcc1c2a1 1039 obj = radeon_fb->obj;
7e4d15d9 1040 rbo = gem_to_radeon_bo(obj);
bcc1c2a1
AD		 1041 r = radeon_bo_reserve(rbo, false);
1042 if (unlikely(r != 0))
1043 return r;
4dd19b0d
CB		 1044
1045 if (atomic)
1046 fb_location = radeon_bo_gpu_offset(rbo);
1047 else {
1048 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1049 if (unlikely(r != 0)) {
1050 radeon_bo_unreserve(rbo);
1051 return -EINVAL;
1052 }
bcc1c2a1 1053 }
4dd19b0d 1054
bcc1c2a1
AD		 1055 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1056 radeon_bo_unreserve(rbo);
1057
4dd19b0d 1058 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1059 case 8:
1060 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1061 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1062 break;
1063 case 15:
1064 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1065 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1066 break;
1067 case 16:
1068 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1069 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1070#ifdef __BIG_ENDIAN
1071 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1072#endif
bcc1c2a1
AD		 1073 break;
1074 case 24:
1075 case 32:
1076 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1077 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1078#ifdef __BIG_ENDIAN
1079 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1080#endif
bcc1c2a1
AD		 1081 break;
1082 default:
1083 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1084 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1085 return -EINVAL;
1086 }
1087
97d66328
AD		 1088 if (tiling_flags & RADEON_TILING_MACRO)
1089 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1090 else if (tiling_flags & RADEON_TILING_MICRO)
1091 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1092
bcc1c2a1
AD		 1093 switch (radeon_crtc->crtc_id) {
1094 case 0:
1095 WREG32(AVIVO_D1VGA_CONTROL, 0);
1096 break;
1097 case 1:
1098 WREG32(AVIVO_D2VGA_CONTROL, 0);
1099 break;
1100 case 2:
1101 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1102 break;
1103 case 3:
1104 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1105 break;
1106 case 4:
1107 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1108 break;
1109 case 5:
1110 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1111 break;
1112 default:
1113 break;
1114 }
1115
1116 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1117 upper_32_bits(fb_location));
1118 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1119 upper_32_bits(fb_location));
1120 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1121 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1122 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1123 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1124 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1125 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1
AD		 1126
1127 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1128 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1129 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1130 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1131 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1132 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1133
4dd19b0d 1134 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1135 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1136 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1137
1138 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1139 crtc->mode.vdisplay);
1140 x &= ~3;
1141 y &= ~1;
1142 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1143 (x << 16) | y);
1144 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1145 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1146
fb9674bd
AD		 1147 /* pageflip setup */
1148 /* make sure flip is at vb rather than hb */
1149 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1150 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1151 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1152
1153 /* set pageflip to happen anywhere in vblank interval */
1154 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1155
4dd19b0d
CB		 1156 if (!atomic && fb && fb != crtc->fb) {
1157 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1158 rbo = gem_to_radeon_bo(radeon_fb->obj);
bcc1c2a1
AD		 1159 r = radeon_bo_reserve(rbo, false);
1160 if (unlikely(r != 0))
1161 return r;
1162 radeon_bo_unpin(rbo);
1163 radeon_bo_unreserve(rbo);
1164 }
1165
1166 /* Bytes per pixel may have changed */
1167 radeon_bandwidth_update(rdev);
1168
1169 return 0;
1170}
1171
4dd19b0d
CB		 1172static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1173 struct drm_framebuffer *fb,
1174 int x, int y, int atomic)
771fe6b9
JG		 1175{
1176 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1177 struct drm_device *dev = crtc->dev;
1178 struct radeon_device *rdev = dev->dev_private;
1179 struct radeon_framebuffer *radeon_fb;
1180 struct drm_gem_object *obj;
4c788679 1181 struct radeon_bo *rbo;
4dd19b0d 1182 struct drm_framebuffer *target_fb;
771fe6b9 1183 uint64_t fb_location;
e024e110 1184 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1185 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
fb9674bd 1186 u32 tmp;
4c788679 1187 int r;
771fe6b9 1188
2de3b484 1189 /* no fb bound */
4dd19b0d 1190 if (!atomic && !crtc->fb) {
d9fdaafb 1191 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1192 return 0;
1193 }
771fe6b9 1194
4dd19b0d
CB		 1195 if (atomic) {
1196 radeon_fb = to_radeon_framebuffer(fb);
1197 target_fb = fb;
1198 }
1199 else {
1200 radeon_fb = to_radeon_framebuffer(crtc->fb);
1201 target_fb = crtc->fb;
1202 }
771fe6b9
JG		 1203
1204 obj = radeon_fb->obj;
7e4d15d9 1205 rbo = gem_to_radeon_bo(obj);
4c788679
JG		 1206 r = radeon_bo_reserve(rbo, false);
1207 if (unlikely(r != 0))
1208 return r;
4dd19b0d
CB		 1209
1210 /* If atomic, assume fb object is pinned & idle & fenced and
1211 * just update base pointers
1212 */
1213 if (atomic)
1214 fb_location = radeon_bo_gpu_offset(rbo);
1215 else {
1216 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1217 if (unlikely(r != 0)) {
1218 radeon_bo_unreserve(rbo);
1219 return -EINVAL;
1220 }
771fe6b9 1221 }
4c788679
JG		 1222 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1223 radeon_bo_unreserve(rbo);
771fe6b9 1224
4dd19b0d 1225 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1226 case 8:
1227 fb_format =
1228 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1229 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1230 break;
771fe6b9
JG		 1231 case 15:
1232 fb_format =
1233 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1234 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1235 break;
1236 case 16:
1237 fb_format =
1238 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1239 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1240#ifdef __BIG_ENDIAN
1241 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1242#endif
771fe6b9
JG		 1243 break;
1244 case 24:
1245 case 32:
1246 fb_format =
1247 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1248 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1249#ifdef __BIG_ENDIAN
1250 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1251#endif
771fe6b9
JG		 1252 break;
1253 default:
1254 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1255 target_fb->bits_per_pixel);
771fe6b9
JG		 1256 return -EINVAL;
1257 }
1258
40c4ac1c
AD		 1259 if (rdev->family >= CHIP_R600) {
1260 if (tiling_flags & RADEON_TILING_MACRO)
1261 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1262 else if (tiling_flags & RADEON_TILING_MICRO)
1263 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1264 } else {
1265 if (tiling_flags & RADEON_TILING_MACRO)
1266 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1267
40c4ac1c
AD		 1268 if (tiling_flags & RADEON_TILING_MICRO)
1269 fb_format |= AVIVO_D1GRPH_TILED;
1270 }
e024e110 1271
771fe6b9
JG		 1272 if (radeon_crtc->crtc_id == 0)
1273 WREG32(AVIVO_D1VGA_CONTROL, 0);
1274 else
1275 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1276
1277 if (rdev->family >= CHIP_RV770) {
1278 if (radeon_crtc->crtc_id) {
95347871
AD		 1279 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1280 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1281 } else {
95347871
AD		 1282 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1283 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1284 }
1285 }
771fe6b9
JG		 1286 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1287 (u32) fb_location);
1288 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1289 radeon_crtc->crtc_offset, (u32) fb_location);
1290 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1291 if (rdev->family >= CHIP_R600)
1292 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9
JG		 1293
1294 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1295 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1296 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1297 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1298 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1299 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1300
4dd19b0d 1301 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1302 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1303 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1304
1305 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1306 crtc->mode.vdisplay);
1307 x &= ~3;
1308 y &= ~1;
1309 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1310 (x << 16) | y);
1311 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1312 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1313
fb9674bd
AD		 1314 /* pageflip setup */
1315 /* make sure flip is at vb rather than hb */
1316 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1317 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1318 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1319
1320 /* set pageflip to happen anywhere in vblank interval */
1321 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1322
4dd19b0d
CB		 1323 if (!atomic && fb && fb != crtc->fb) {
1324 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1325 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 1326 r = radeon_bo_reserve(rbo, false);
1327 if (unlikely(r != 0))
1328 return r;
1329 radeon_bo_unpin(rbo);
1330 radeon_bo_unreserve(rbo);
771fe6b9 1331 }
f30f37de
MD		 1332
1333 /* Bytes per pixel may have changed */
1334 radeon_bandwidth_update(rdev);
1335
771fe6b9
JG		 1336 return 0;
1337}
1338
54f088a9
AD		 1339int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1340 struct drm_framebuffer *old_fb)
1341{
1342 struct drm_device *dev = crtc->dev;
1343 struct radeon_device *rdev = dev->dev_private;
1344
bcc1c2a1 1345 if (ASIC_IS_DCE4(rdev))
c9417bdd 1346 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1347 else if (ASIC_IS_AVIVO(rdev))
1348 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1349 else
1350 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1351}
1352
1353int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1354 struct drm_framebuffer *fb,
21c74a8e 1355 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1356{
1357 struct drm_device *dev = crtc->dev;
1358 struct radeon_device *rdev = dev->dev_private;
1359
1360 if (ASIC_IS_DCE4(rdev))
c9417bdd 1361 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1362 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1363 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1364 else
4dd19b0d 1365 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1366}
1367
615e0cb6
AD		 1368/* properly set additional regs when using atombios */
1369static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1370{
1371 struct drm_device *dev = crtc->dev;
1372 struct radeon_device *rdev = dev->dev_private;
1373 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1374 u32 disp_merge_cntl;
1375
1376 switch (radeon_crtc->crtc_id) {
1377 case 0:
1378 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1379 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1380 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1381 break;
1382 case 1:
1383 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1384 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1385 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1386 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1387 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1388 break;
1389 }
1390}
1391
bcc1c2a1
AD		 1392static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1393{
1394 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1395 struct drm_device *dev = crtc->dev;
1396 struct radeon_device *rdev = dev->dev_private;
1397 struct drm_encoder *test_encoder;
1398 struct drm_crtc *test_crtc;
1399 uint32_t pll_in_use = 0;
1400
1401 if (ASIC_IS_DCE4(rdev)) {
1402 /* if crtc is driving DP and we have an ext clock, use that */
1403 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1404 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1405 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1406 if (rdev->clock.dp_extclk)
1407 return ATOM_PPLL_INVALID;
1408 }
1409 }
1410 }
1411
1412 /* otherwise, pick one of the plls */
1413 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1414 struct radeon_crtc *radeon_test_crtc;
1415
1416 if (crtc == test_crtc)
1417 continue;
1418
1419 radeon_test_crtc = to_radeon_crtc(test_crtc);
1420 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1421 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1422 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1423 }
1424 if (!(pll_in_use & 1))
1425 return ATOM_PPLL1;
1426 return ATOM_PPLL2;
1427 } else
1428 return radeon_crtc->crtc_id;
1429
1430}
1431
771fe6b9
JG		 1432int atombios_crtc_mode_set(struct drm_crtc *crtc,
1433 struct drm_display_mode *mode,
1434 struct drm_display_mode *adjusted_mode,
1435 int x, int y, struct drm_framebuffer *old_fb)
1436{
1437 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1438 struct drm_device *dev = crtc->dev;
1439 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1440 struct drm_encoder *encoder;
1441 bool is_tvcv = false;
771fe6b9 1442
54bfe496
AD		 1443 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1444 /* find tv std */
1445 if (encoder->crtc == crtc) {
1446 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1447 if (radeon_encoder->active_device &
1448 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1449 is_tvcv = true;
1450 }
1451 }
771fe6b9 1452
bcc1c2a1 1453 /* always set DCPLL */
ba032a58
AD		 1454 if (ASIC_IS_DCE4(rdev)) {
1455 struct radeon_atom_ss ss;
1456 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1457 ASIC_INTERNAL_SS_ON_DCPLL,
1458 rdev->clock.default_dispclk);
1459 if (ss_enabled)
1460 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
f82b3ddc
AD		 1461 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1462 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
ba032a58
AD		 1463 if (ss_enabled)
1464 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1465 }
771fe6b9 1466 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1467
54bfe496 1468 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1469 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1470 else if (ASIC_IS_AVIVO(rdev)) {
1471 if (is_tvcv)
1472 atombios_crtc_set_timing(crtc, adjusted_mode);
1473 else
1474 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1475 } else {
bcc1c2a1 1476 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1477 if (radeon_crtc->crtc_id == 0)
1478 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1479 radeon_legacy_atom_fixup(crtc);
771fe6b9 1480 }
bcc1c2a1 1481 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1482 atombios_overscan_setup(crtc, mode, adjusted_mode);
1483 atombios_scaler_setup(crtc);
771fe6b9
JG		 1484 return 0;
1485}
1486
1487static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1488 struct drm_display_mode *mode,
1489 struct drm_display_mode *adjusted_mode)
1490{
03214bd5
AD		 1491 struct drm_device *dev = crtc->dev;
1492 struct radeon_device *rdev = dev->dev_private;
1493
1494 /* adjust pm to upcoming mode change */
1495 radeon_pm_compute_clocks(rdev);
1496
c93bb85b
JG		 1497 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1498 return false;
771fe6b9
JG		 1499 return true;
1500}
1501
1502static void atombios_crtc_prepare(struct drm_crtc *crtc)
1503{
267364ac
AD		 1504 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1505
1506 /* pick pll */
1507 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1508
37b4390e 1509 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1510 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1511}
1512
1513static void atombios_crtc_commit(struct drm_crtc *crtc)
1514{
1515 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1516 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1517}
1518
37f9003b
AD		 1519static void atombios_crtc_disable(struct drm_crtc *crtc)
1520{
1521 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1522 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1523
1524 switch (radeon_crtc->pll_id) {
1525 case ATOM_PPLL1:
1526 case ATOM_PPLL2:
1527 /* disable the ppll */
1528 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1529 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1530 break;
1531 default:
1532 break;
1533 }
1534 radeon_crtc->pll_id = -1;
1535}
1536
771fe6b9
JG		 1537static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1538 .dpms = atombios_crtc_dpms,
1539 .mode_fixup = atombios_crtc_mode_fixup,
1540 .mode_set = atombios_crtc_mode_set,
1541 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1542 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1543 .prepare = atombios_crtc_prepare,
1544 .commit = atombios_crtc_commit,
068143d3 1545 .load_lut = radeon_crtc_load_lut,
37f9003b 1546 .disable = atombios_crtc_disable,
771fe6b9
JG		 1547};
1548
1549void radeon_atombios_init_crtc(struct drm_device *dev,
1550 struct radeon_crtc *radeon_crtc)
1551{
bcc1c2a1
AD		 1552 struct radeon_device *rdev = dev->dev_private;
1553
1554 if (ASIC_IS_DCE4(rdev)) {
1555 switch (radeon_crtc->crtc_id) {
1556 case 0:
1557 default:
12d7798f 1558 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1559 break;
1560 case 1:
12d7798f 1561 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1562 break;
1563 case 2:
12d7798f 1564 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1565 break;
1566 case 3:
12d7798f 1567 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1568 break;
1569 case 4:
12d7798f 1570 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1571 break;
1572 case 5:
12d7798f 1573 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1574 break;
1575 }
1576 } else {
1577 if (radeon_crtc->crtc_id == 1)
1578 radeon_crtc->crtc_offset =
1579 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1580 else
1581 radeon_crtc->crtc_offset = 0;
1582 }
1583 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1584 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1585}
Ubuntu Artful kernel mirror