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drm/radeon/kms: clean up some magic numbers
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
63 } else if (a2 > a1) {
64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
5b1714d3
AD		 70 args.usOverscanRight = radeon_crtc->h_border;
71 args.usOverscanLeft = radeon_crtc->h_border;
72 args.usOverscanBottom = radeon_crtc->v_border;
73 args.usOverscanTop = radeon_crtc->v_border;
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 258 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 261 radeon_crtc->enabled = false;
d7311171
AD		 262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 264 break;
265 }
771fe6b9
JG		 266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 270 struct drm_display_mode *mode)
771fe6b9 271{
5a9bcacc 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 277 u16 misc = 0;
771fe6b9 278
5a9bcacc 279 memset(&args, 0, sizeof(args));
5b1714d3 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 281 args.usH_Blanking_Time =
5b1714d3
AD		 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 284 args.usV_Blanking_Time =
5b1714d3 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 286 args.usH_SyncOffset =
5b1714d3 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
5b1714d3 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 310
5a9bcacc 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 312}
313
5a9bcacc
AD		 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
771fe6b9 316{
5a9bcacc 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 322 u16 misc = 0;
771fe6b9 323
5a9bcacc
AD		 324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
54bfe496
AD		 336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
5a9bcacc
AD		 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 354
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
b792210e
AD		 358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
26b9fc3a 401union atom_enable_ss {
ba032a58
AD		 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 407};
408
ba032a58
AD		 409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
ebbe1cb9 413{
ebbe1cb9
AD		 414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
ebbe1cb9 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 417 union atom_enable_ss args;
ebbe1cb9 418
ba032a58 419 memset(&args, 0, sizeof(args));
bcc1c2a1 420
a572eaa3
AD		 421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = 0;
423 args.v3.ucSpreadSpectrumType = ss->type;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = ss->amount;
428 args.v3.usSpreadSpectrumStep = ss->step;
429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = ss->amount;
433 args.v3.usSpreadSpectrumStep = ss->step;
434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = 0;
438 args.v3.usSpreadSpectrumStep = 0;
439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v2.ucEnable = enable;
444 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58
AD		 445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446 args.v2.ucSpreadSpectrumType = ss->type;
447 switch (pll_id) {
448 case ATOM_PPLL1:
449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
450 args.v2.usSpreadSpectrumAmount = ss->amount;
451 args.v2.usSpreadSpectrumStep = ss->step;
452 break;
453 case ATOM_PPLL2:
454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
455 args.v2.usSpreadSpectrumAmount = ss->amount;
456 args.v2.usSpreadSpectrumStep = ss->step;
ebbe1cb9 457 break;
ba032a58
AD		 458 case ATOM_DCPLL:
459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
460 args.v2.usSpreadSpectrumAmount = 0;
461 args.v2.usSpreadSpectrumStep = 0;
462 break;
463 case ATOM_PPLL_INVALID:
464 return;
ebbe1cb9 465 }
ba032a58
AD		 466 args.v2.ucEnable = enable;
467 } else if (ASIC_IS_DCE3(rdev)) {
468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469 args.v1.ucSpreadSpectrumType = ss->type;
470 args.v1.ucSpreadSpectrumStep = ss->step;
471 args.v1.ucSpreadSpectrumDelay = ss->delay;
472 args.v1.ucSpreadSpectrumRange = ss->range;
473 args.v1.ucPpll = pll_id;
474 args.v1.ucEnable = enable;
475 } else if (ASIC_IS_AVIVO(rdev)) {
476 if (enable == ATOM_DISABLE) {
477 atombios_disable_ss(crtc);
478 return;
479 }
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 486 } else {
ba032a58
AD		 487 if (enable == ATOM_DISABLE) {
488 atombios_disable_ss(crtc);
489 return;
490 }
491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.lvds_ss.ucSpreadSpectrumType = ss->type;
493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495 args.lvds_ss.ucEnable = enable;
ebbe1cb9 496 }
26b9fc3a 497 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 498}
499
4eaeca33
AD		 500union adjust_pixel_clock {
501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 503};
504
505static u32 atombios_adjust_pll(struct drm_crtc *crtc,
506 struct drm_display_mode *mode,
ba032a58
AD		 507 struct radeon_pll *pll,
508 bool ss_enabled,
509 struct radeon_atom_ss *ss)
771fe6b9 510{
771fe6b9
JG		 511 struct drm_device *dev = crtc->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct drm_encoder *encoder = NULL;
514 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 515 u32 adjusted_clock = mode->clock;
bcc1c2a1 516 int encoder_mode = 0;
fbee67a6
AD		 517 u32 dp_clock = mode->clock;
518 int bpc = 8;
fc10332b 519
4eaeca33
AD		 520 /* reset the pll flags */
521 pll->flags = 0;
771fe6b9
JG		 522
523 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 524 if ((rdev->family == CHIP_RS600) ||
525 (rdev->family == CHIP_RS690) ||
526 (rdev->family == CHIP_RS740))
2ff776cf 527 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 528 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 529
530 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
532 else
533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
534 } else {
fc10332b 535 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 536
5480f727
DA		 537 if (mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
541
542 }
543
771fe6b9
JG		 544 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
545 if (encoder->crtc == crtc) {
4eaeca33 546 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 547 encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6
AD		 548 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
549 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
550 if (connector) {
551 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
552 struct radeon_connector_atom_dig *dig_connector =
553 radeon_connector->con_priv;
554
555 dp_clock = dig_connector->dp_clock;
556 }
557 }
e5fd205f 558#if 0 /* doesn't work properly on some laptops */
ba032a58
AD		 559 /* use recommended ref_div for ss */
560 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
561 if (ss_enabled) {
562 if (ss->refdiv) {
563 pll->flags |= RADEON_PLL_USE_REF_DIV;
564 pll->reference_div = ss->refdiv;
565 }
566 }
567 }
e5fd205f 568#endif
4eaeca33
AD		 569 if (ASIC_IS_AVIVO(rdev)) {
570 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
571 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
572 adjusted_clock = mode->clock * 2;
48dfaaeb 573 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 574 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
4eaeca33
AD		 575 } else {
576 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 577 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 578 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 579 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 580 }
3ce0a23d 581 break;
771fe6b9
JG		 582 }
583 }
584
2606c886
AD		 585 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
586 * accordingly based on the encoder/transmitter to work around
587 * special hw requirements.
588 */
589 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 590 union adjust_pixel_clock args;
4eaeca33
AD		 591 u8 frev, crev;
592 int index;
2606c886 593
2606c886 594 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 595 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
596 &crev))
597 return adjusted_clock;
4eaeca33
AD		 598
599 memset(&args, 0, sizeof(args));
600
601 switch (frev) {
602 case 1:
603 switch (crev) {
604 case 1:
605 case 2:
606 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
607 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 608 args.v1.ucEncodeMode = encoder_mode;
b526ce22 609 if (ss_enabled)
fbee67a6
AD		 610 args.v1.ucConfig |=
611 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 612
613 atom_execute_table(rdev->mode_info.atom_context,
614 index, (uint32_t *)&args);
615 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
616 break;
bcc1c2a1
AD		 617 case 3:
618 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
619 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
620 args.v3.sInput.ucEncodeMode = encoder_mode;
621 args.v3.sInput.ucDispPllConfig = 0;
b526ce22
AD		 622 if (ss_enabled)
623 args.v3.sInput.ucDispPllConfig |=
624 DISPPLL_CONFIG_SS_ENABLE;
bcc1c2a1
AD		 625 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
626 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
fbee67a6 627 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1
AD		 628 args.v3.sInput.ucDispPllConfig |=
629 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 630 /* 16200 or 27000 */
631 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
632 } else {
633 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
634 /* deep color support */
635 args.v3.sInput.usPixelClock =
636 cpu_to_le16((mode->clock * bpc / 8) / 10);
637 }
bcc1c2a1
AD		 638 if (dig->coherent_mode)
639 args.v3.sInput.ucDispPllConfig |=
640 DISPPLL_CONFIG_COHERENT_MODE;
641 if (mode->clock > 165000)
642 args.v3.sInput.ucDispPllConfig |=
643 DISPPLL_CONFIG_DUAL_LINK;
644 }
645 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
fbee67a6 646 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1 647 args.v3.sInput.ucDispPllConfig |=
9f998ad7 648 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 649 /* 16200 or 27000 */
650 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
b526ce22 651 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
9f998ad7
AD		 652 if (mode->clock > 165000)
653 args.v3.sInput.ucDispPllConfig |=
654 DISPPLL_CONFIG_DUAL_LINK;
655 }
bcc1c2a1
AD		 656 }
657 atom_execute_table(rdev->mode_info.atom_context,
658 index, (uint32_t *)&args);
659 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
660 if (args.v3.sOutput.ucRefDiv) {
661 pll->flags |= RADEON_PLL_USE_REF_DIV;
662 pll->reference_div = args.v3.sOutput.ucRefDiv;
663 }
664 if (args.v3.sOutput.ucPostDiv) {
665 pll->flags |= RADEON_PLL_USE_POST_DIV;
666 pll->post_div = args.v3.sOutput.ucPostDiv;
667 }
668 break;
4eaeca33
AD		 669 default:
670 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
671 return adjusted_clock;
672 }
673 break;
674 default:
675 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
676 return adjusted_clock;
677 }
d56ef9c8 678 }
4eaeca33
AD		 679 return adjusted_clock;
680}
681
682union set_pixel_clock {
683 SET_PIXEL_CLOCK_PS_ALLOCATION base;
684 PIXEL_CLOCK_PARAMETERS v1;
685 PIXEL_CLOCK_PARAMETERS_V2 v2;
686 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 687 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 688 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 689};
690
f82b3ddc
AD		 691/* on DCE5, make sure the voltage is high enough to support the
692 * required disp clk.
693 */
694static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
695 u32 dispclk)
bcc1c2a1
AD		 696{
697 struct drm_device *dev = crtc->dev;
698 struct radeon_device *rdev = dev->dev_private;
699 u8 frev, crev;
700 int index;
701 union set_pixel_clock args;
702
703 memset(&args, 0, sizeof(args));
704
705 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 706 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
707 &crev))
708 return;
bcc1c2a1
AD		 709
710 switch (frev) {
711 case 1:
712 switch (crev) {
713 case 5:
714 /* if the default dcpll clock is specified,
715 * SetPixelClock provides the dividers
716 */
717 args.v5.ucCRTC = ATOM_CRTC_INVALID;
f82b3ddc 718 args.v5.usPixelClock = dispclk;
bcc1c2a1
AD		 719 args.v5.ucPpll = ATOM_DCPLL;
720 break;
f82b3ddc
AD		 721 case 6:
722 /* if the default dcpll clock is specified,
723 * SetPixelClock provides the dividers
724 */
725 args.v6.ulDispEngClkFreq = dispclk;
726 args.v6.ucPpll = ATOM_DCPLL;
727 break;
bcc1c2a1
AD		 728 default:
729 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
730 return;
731 }
732 break;
733 default:
734 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
735 return;
736 }
737 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
738}
739
37f9003b
AD		 740static void atombios_crtc_program_pll(struct drm_crtc *crtc,
741 int crtc_id,
742 int pll_id,
743 u32 encoder_mode,
744 u32 encoder_id,
745 u32 clock,
746 u32 ref_div,
747 u32 fb_div,
748 u32 frac_fb_div,
749 u32 post_div)
4eaeca33 750{
4eaeca33
AD		 751 struct drm_device *dev = crtc->dev;
752 struct radeon_device *rdev = dev->dev_private;
4eaeca33 753 u8 frev, crev;
37f9003b 754 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 755 union set_pixel_clock args;
4eaeca33
AD		 756
757 memset(&args, 0, sizeof(args));
758
a084e6ee
AD		 759 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
760 &crev))
761 return;
771fe6b9
JG		 762
763 switch (frev) {
764 case 1:
765 switch (crev) {
766 case 1:
37f9003b
AD		 767 if (clock == ATOM_DISABLE)
768 return;
769 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 770 args.v1.usRefDiv = cpu_to_le16(ref_div);
771 args.v1.usFbDiv = cpu_to_le16(fb_div);
772 args.v1.ucFracFbDiv = frac_fb_div;
773 args.v1.ucPostDiv = post_div;
37f9003b
AD		 774 args.v1.ucPpll = pll_id;
775 args.v1.ucCRTC = crtc_id;
4eaeca33 776 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 777 break;
778 case 2:
37f9003b 779 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 780 args.v2.usRefDiv = cpu_to_le16(ref_div);
781 args.v2.usFbDiv = cpu_to_le16(fb_div);
782 args.v2.ucFracFbDiv = frac_fb_div;
783 args.v2.ucPostDiv = post_div;
37f9003b
AD		 784 args.v2.ucPpll = pll_id;
785 args.v2.ucCRTC = crtc_id;
4eaeca33 786 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 787 break;
788 case 3:
37f9003b 789 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 790 args.v3.usRefDiv = cpu_to_le16(ref_div);
791 args.v3.usFbDiv = cpu_to_le16(fb_div);
792 args.v3.ucFracFbDiv = frac_fb_div;
793 args.v3.ucPostDiv = post_div;
37f9003b
AD		 794 args.v3.ucPpll = pll_id;
795 args.v3.ucMiscInfo = (pll_id << 2);
796 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 797 args.v3.ucEncoderMode = encoder_mode;
798 break;
799 case 5:
37f9003b
AD		 800 args.v5.ucCRTC = crtc_id;
801 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 802 args.v5.ucRefDiv = ref_div;
803 args.v5.usFbDiv = cpu_to_le16(fb_div);
804 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
805 args.v5.ucPostDiv = post_div;
806 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
37f9003b 807 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 808 args.v5.ucEncoderMode = encoder_mode;
37f9003b 809 args.v5.ucPpll = pll_id;
771fe6b9 810 break;
f82b3ddc
AD		 811 case 6:
812 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
813 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
814 args.v6.ucRefDiv = ref_div;
815 args.v6.usFbDiv = cpu_to_le16(fb_div);
816 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
817 args.v6.ucPostDiv = post_div;
818 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
819 args.v6.ucTransmitterID = encoder_id;
820 args.v6.ucEncoderMode = encoder_mode;
821 args.v6.ucPpll = pll_id;
822 break;
771fe6b9
JG		 823 default:
824 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
825 return;
826 }
827 break;
828 default:
829 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
830 return;
831 }
832
771fe6b9
JG		 833 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
834}
835
37f9003b
AD		 836static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
837{
838 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
839 struct drm_device *dev = crtc->dev;
840 struct radeon_device *rdev = dev->dev_private;
841 struct drm_encoder *encoder = NULL;
842 struct radeon_encoder *radeon_encoder = NULL;
843 u32 pll_clock = mode->clock;
844 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
845 struct radeon_pll *pll;
846 u32 adjusted_clock;
847 int encoder_mode = 0;
ba032a58
AD		 848 struct radeon_atom_ss ss;
849 bool ss_enabled = false;
37f9003b
AD		 850
851 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
852 if (encoder->crtc == crtc) {
853 radeon_encoder = to_radeon_encoder(encoder);
854 encoder_mode = atombios_get_encoder_mode(encoder);
855 break;
856 }
857 }
858
859 if (!radeon_encoder)
860 return;
861
862 switch (radeon_crtc->pll_id) {
863 case ATOM_PPLL1:
864 pll = &rdev->clock.p1pll;
865 break;
866 case ATOM_PPLL2:
867 pll = &rdev->clock.p2pll;
868 break;
869 case ATOM_DCPLL:
870 case ATOM_PPLL_INVALID:
871 default:
872 pll = &rdev->clock.dcpll;
873 break;
874 }
875
ba032a58
AD		 876 if (radeon_encoder->active_device &
877 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
878 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
879 struct drm_connector *connector =
880 radeon_get_connector_for_encoder(encoder);
881 struct radeon_connector *radeon_connector =
882 to_radeon_connector(connector);
883 struct radeon_connector_atom_dig *dig_connector =
884 radeon_connector->con_priv;
885 int dp_clock;
886
887 switch (encoder_mode) {
888 case ATOM_ENCODER_MODE_DP:
889 /* DP/eDP */
890 dp_clock = dig_connector->dp_clock / 10;
891 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
892 if (ASIC_IS_DCE4(rdev))
893 ss_enabled =
894 radeon_atombios_get_asic_ss_info(rdev, &ss,
895 dig->lcd_ss_id,
896 dp_clock);
897 else
898 ss_enabled =
899 radeon_atombios_get_ppll_ss_info(rdev, &ss,
900 dig->lcd_ss_id);
901 } else {
902 if (ASIC_IS_DCE4(rdev))
903 ss_enabled =
904 radeon_atombios_get_asic_ss_info(rdev, &ss,
905 ASIC_INTERNAL_SS_ON_DP,
906 dp_clock);
907 else {
908 if (dp_clock == 16200) {
909 ss_enabled =
910 radeon_atombios_get_ppll_ss_info(rdev, &ss,
911 ATOM_DP_SS_ID2);
912 if (!ss_enabled)
913 ss_enabled =
914 radeon_atombios_get_ppll_ss_info(rdev, &ss,
915 ATOM_DP_SS_ID1);
916 } else
917 ss_enabled =
918 radeon_atombios_get_ppll_ss_info(rdev, &ss,
919 ATOM_DP_SS_ID1);
920 }
921 }
922 break;
923 case ATOM_ENCODER_MODE_LVDS:
924 if (ASIC_IS_DCE4(rdev))
925 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
926 dig->lcd_ss_id,
927 mode->clock / 10);
928 else
929 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
930 dig->lcd_ss_id);
931 break;
932 case ATOM_ENCODER_MODE_DVI:
933 if (ASIC_IS_DCE4(rdev))
934 ss_enabled =
935 radeon_atombios_get_asic_ss_info(rdev, &ss,
936 ASIC_INTERNAL_SS_ON_TMDS,
937 mode->clock / 10);
938 break;
939 case ATOM_ENCODER_MODE_HDMI:
940 if (ASIC_IS_DCE4(rdev))
941 ss_enabled =
942 radeon_atombios_get_asic_ss_info(rdev, &ss,
943 ASIC_INTERNAL_SS_ON_HDMI,
944 mode->clock / 10);
945 break;
946 default:
947 break;
948 }
949 }
950
37f9003b 951 /* adjust pixel clock as needed */
ba032a58 952 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b
AD		 953
954 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
955 &ref_div, &post_div);
956
ba032a58
AD		 957 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
958
37f9003b
AD		 959 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
960 encoder_mode, radeon_encoder->encoder_id, mode->clock,
961 ref_div, fb_div, frac_fb_div, post_div);
962
ba032a58
AD		 963 if (ss_enabled) {
964 /* calculate ss amount and step size */
965 if (ASIC_IS_DCE4(rdev)) {
966 u32 step_size;
967 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
968 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
969 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
970 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
971 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
972 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
973 (125 * 25 * pll->reference_freq / 100);
974 else
975 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
976 (125 * 25 * pll->reference_freq / 100);
977 ss.step = step_size;
978 }
979
980 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
981 }
37f9003b
AD		 982}
983
4dd19b0d
CB		 984static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
985 struct drm_framebuffer *fb,
986 int x, int y, int atomic)
bcc1c2a1
AD		 987{
988 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
989 struct drm_device *dev = crtc->dev;
990 struct radeon_device *rdev = dev->dev_private;
991 struct radeon_framebuffer *radeon_fb;
4dd19b0d 992 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 993 struct drm_gem_object *obj;
994 struct radeon_bo *rbo;
995 uint64_t fb_location;
996 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
997 int r;
998
999 /* no fb bound */
4dd19b0d 1000 if (!atomic && !crtc->fb) {
d9fdaafb 1001 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1002 return 0;
1003 }
1004
4dd19b0d
CB		 1005 if (atomic) {
1006 radeon_fb = to_radeon_framebuffer(fb);
1007 target_fb = fb;
1008 }
1009 else {
1010 radeon_fb = to_radeon_framebuffer(crtc->fb);
1011 target_fb = crtc->fb;
1012 }
bcc1c2a1 1013
4dd19b0d
CB		 1014 /* If atomic, assume fb object is pinned & idle & fenced and
1015 * just update base pointers
1016 */
bcc1c2a1
AD		 1017 obj = radeon_fb->obj;
1018 rbo = obj->driver_private;
1019 r = radeon_bo_reserve(rbo, false);
1020 if (unlikely(r != 0))
1021 return r;
4dd19b0d
CB		 1022
1023 if (atomic)
1024 fb_location = radeon_bo_gpu_offset(rbo);
1025 else {
1026 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1027 if (unlikely(r != 0)) {
1028 radeon_bo_unreserve(rbo);
1029 return -EINVAL;
1030 }
bcc1c2a1 1031 }
4dd19b0d 1032
bcc1c2a1
AD		 1033 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1034 radeon_bo_unreserve(rbo);
1035
4dd19b0d 1036 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1037 case 8:
1038 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1039 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1040 break;
1041 case 15:
1042 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1043 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1044 break;
1045 case 16:
1046 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1047 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1048 break;
1049 case 24:
1050 case 32:
1051 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1052 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1053 break;
1054 default:
1055 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1056 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1057 return -EINVAL;
1058 }
1059
97d66328
AD		 1060 if (tiling_flags & RADEON_TILING_MACRO)
1061 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1062 else if (tiling_flags & RADEON_TILING_MICRO)
1063 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1064
bcc1c2a1
AD		 1065 switch (radeon_crtc->crtc_id) {
1066 case 0:
1067 WREG32(AVIVO_D1VGA_CONTROL, 0);
1068 break;
1069 case 1:
1070 WREG32(AVIVO_D2VGA_CONTROL, 0);
1071 break;
1072 case 2:
1073 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1074 break;
1075 case 3:
1076 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1077 break;
1078 case 4:
1079 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1080 break;
1081 case 5:
1082 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1083 break;
1084 default:
1085 break;
1086 }
1087
1088 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1089 upper_32_bits(fb_location));
1090 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1091 upper_32_bits(fb_location));
1092 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1093 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1094 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1095 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1096 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1097
1098 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1099 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1100 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1101 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1102 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1103 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1104
4dd19b0d 1105 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1106 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1107 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1108
1109 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1110 crtc->mode.vdisplay);
1111 x &= ~3;
1112 y &= ~1;
1113 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1114 (x << 16) | y);
1115 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1116 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1117
1118 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1119 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1120 EVERGREEN_INTERLEAVE_EN);
1121 else
1122 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1123
4dd19b0d
CB		 1124 if (!atomic && fb && fb != crtc->fb) {
1125 radeon_fb = to_radeon_framebuffer(fb);
bcc1c2a1
AD		 1126 rbo = radeon_fb->obj->driver_private;
1127 r = radeon_bo_reserve(rbo, false);
1128 if (unlikely(r != 0))
1129 return r;
1130 radeon_bo_unpin(rbo);
1131 radeon_bo_unreserve(rbo);
1132 }
1133
1134 /* Bytes per pixel may have changed */
1135 radeon_bandwidth_update(rdev);
1136
1137 return 0;
1138}
1139
4dd19b0d
CB		 1140static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1141 struct drm_framebuffer *fb,
1142 int x, int y, int atomic)
771fe6b9
JG		 1143{
1144 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1145 struct drm_device *dev = crtc->dev;
1146 struct radeon_device *rdev = dev->dev_private;
1147 struct radeon_framebuffer *radeon_fb;
1148 struct drm_gem_object *obj;
4c788679 1149 struct radeon_bo *rbo;
4dd19b0d 1150 struct drm_framebuffer *target_fb;
771fe6b9 1151 uint64_t fb_location;
e024e110 1152 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 1153 int r;
771fe6b9 1154
2de3b484 1155 /* no fb bound */
4dd19b0d 1156 if (!atomic && !crtc->fb) {
d9fdaafb 1157 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1158 return 0;
1159 }
771fe6b9 1160
4dd19b0d
CB		 1161 if (atomic) {
1162 radeon_fb = to_radeon_framebuffer(fb);
1163 target_fb = fb;
1164 }
1165 else {
1166 radeon_fb = to_radeon_framebuffer(crtc->fb);
1167 target_fb = crtc->fb;
1168 }
771fe6b9
JG		 1169
1170 obj = radeon_fb->obj;
4c788679
JG		 1171 rbo = obj->driver_private;
1172 r = radeon_bo_reserve(rbo, false);
1173 if (unlikely(r != 0))
1174 return r;
4dd19b0d
CB		 1175
1176 /* If atomic, assume fb object is pinned & idle & fenced and
1177 * just update base pointers
1178 */
1179 if (atomic)
1180 fb_location = radeon_bo_gpu_offset(rbo);
1181 else {
1182 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1183 if (unlikely(r != 0)) {
1184 radeon_bo_unreserve(rbo);
1185 return -EINVAL;
1186 }
771fe6b9 1187 }
4c788679
JG		 1188 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1189 radeon_bo_unreserve(rbo);
771fe6b9 1190
4dd19b0d 1191 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1192 case 8:
1193 fb_format =
1194 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1195 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1196 break;
771fe6b9
JG		 1197 case 15:
1198 fb_format =
1199 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1200 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1201 break;
1202 case 16:
1203 fb_format =
1204 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1205 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1206 break;
1207 case 24:
1208 case 32:
1209 fb_format =
1210 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1211 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1212 break;
1213 default:
1214 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1215 target_fb->bits_per_pixel);
771fe6b9
JG		 1216 return -EINVAL;
1217 }
1218
40c4ac1c
AD		 1219 if (rdev->family >= CHIP_R600) {
1220 if (tiling_flags & RADEON_TILING_MACRO)
1221 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1222 else if (tiling_flags & RADEON_TILING_MICRO)
1223 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1224 } else {
1225 if (tiling_flags & RADEON_TILING_MACRO)
1226 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1227
40c4ac1c
AD		 1228 if (tiling_flags & RADEON_TILING_MICRO)
1229 fb_format |= AVIVO_D1GRPH_TILED;
1230 }
e024e110 1231
771fe6b9
JG		 1232 if (radeon_crtc->crtc_id == 0)
1233 WREG32(AVIVO_D1VGA_CONTROL, 0);
1234 else
1235 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1236
1237 if (rdev->family >= CHIP_RV770) {
1238 if (radeon_crtc->crtc_id) {
95347871
AD		 1239 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1240 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1241 } else {
95347871
AD		 1242 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1243 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1244 }
1245 }
771fe6b9
JG		 1246 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1247 (u32) fb_location);
1248 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1249 radeon_crtc->crtc_offset, (u32) fb_location);
1250 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1251
1252 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1253 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1254 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1255 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1256 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1257 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1258
4dd19b0d 1259 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1260 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1261 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1262
1263 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1264 crtc->mode.vdisplay);
1265 x &= ~3;
1266 y &= ~1;
1267 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1268 (x << 16) | y);
1269 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1270 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1271
1272 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1273 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1274 AVIVO_D1MODE_INTERLEAVE_EN);
1275 else
1276 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1277
4dd19b0d
CB		 1278 if (!atomic && fb && fb != crtc->fb) {
1279 radeon_fb = to_radeon_framebuffer(fb);
4c788679
JG		 1280 rbo = radeon_fb->obj->driver_private;
1281 r = radeon_bo_reserve(rbo, false);
1282 if (unlikely(r != 0))
1283 return r;
1284 radeon_bo_unpin(rbo);
1285 radeon_bo_unreserve(rbo);
771fe6b9 1286 }
f30f37de
MD		 1287
1288 /* Bytes per pixel may have changed */
1289 radeon_bandwidth_update(rdev);
1290
771fe6b9
JG		 1291 return 0;
1292}
1293
54f088a9
AD		 1294int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1295 struct drm_framebuffer *old_fb)
1296{
1297 struct drm_device *dev = crtc->dev;
1298 struct radeon_device *rdev = dev->dev_private;
1299
bcc1c2a1 1300 if (ASIC_IS_DCE4(rdev))
4dd19b0d
CB		 1301 return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
1302 else if (ASIC_IS_AVIVO(rdev))
1303 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1304 else
1305 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1306}
1307
1308int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1309 struct drm_framebuffer *fb,
21c74a8e 1310 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1311{
1312 struct drm_device *dev = crtc->dev;
1313 struct radeon_device *rdev = dev->dev_private;
1314
1315 if (ASIC_IS_DCE4(rdev))
1316 return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1317 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1318 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1319 else
4dd19b0d 1320 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1321}
1322
615e0cb6
AD		 1323/* properly set additional regs when using atombios */
1324static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1325{
1326 struct drm_device *dev = crtc->dev;
1327 struct radeon_device *rdev = dev->dev_private;
1328 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1329 u32 disp_merge_cntl;
1330
1331 switch (radeon_crtc->crtc_id) {
1332 case 0:
1333 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1334 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1335 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1336 break;
1337 case 1:
1338 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1339 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1340 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1341 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1342 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1343 break;
1344 }
1345}
1346
bcc1c2a1
AD		 1347static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1348{
1349 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1350 struct drm_device *dev = crtc->dev;
1351 struct radeon_device *rdev = dev->dev_private;
1352 struct drm_encoder *test_encoder;
1353 struct drm_crtc *test_crtc;
1354 uint32_t pll_in_use = 0;
1355
1356 if (ASIC_IS_DCE4(rdev)) {
1357 /* if crtc is driving DP and we have an ext clock, use that */
1358 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1359 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1360 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1361 if (rdev->clock.dp_extclk)
1362 return ATOM_PPLL_INVALID;
1363 }
1364 }
1365 }
1366
1367 /* otherwise, pick one of the plls */
1368 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1369 struct radeon_crtc *radeon_test_crtc;
1370
1371 if (crtc == test_crtc)
1372 continue;
1373
1374 radeon_test_crtc = to_radeon_crtc(test_crtc);
1375 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1376 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1377 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1378 }
1379 if (!(pll_in_use & 1))
1380 return ATOM_PPLL1;
1381 return ATOM_PPLL2;
1382 } else
1383 return radeon_crtc->crtc_id;
1384
1385}
1386
771fe6b9
JG		 1387int atombios_crtc_mode_set(struct drm_crtc *crtc,
1388 struct drm_display_mode *mode,
1389 struct drm_display_mode *adjusted_mode,
1390 int x, int y, struct drm_framebuffer *old_fb)
1391{
1392 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1393 struct drm_device *dev = crtc->dev;
1394 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1395 struct drm_encoder *encoder;
1396 bool is_tvcv = false;
771fe6b9 1397
54bfe496
AD		 1398 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1399 /* find tv std */
1400 if (encoder->crtc == crtc) {
1401 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1402 if (radeon_encoder->active_device &
1403 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1404 is_tvcv = true;
1405 }
1406 }
771fe6b9 1407
bcc1c2a1 1408 /* always set DCPLL */
ba032a58
AD		 1409 if (ASIC_IS_DCE4(rdev)) {
1410 struct radeon_atom_ss ss;
1411 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1412 ASIC_INTERNAL_SS_ON_DCPLL,
1413 rdev->clock.default_dispclk);
1414 if (ss_enabled)
1415 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
f82b3ddc
AD		 1416 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1417 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
ba032a58
AD		 1418 if (ss_enabled)
1419 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1420 }
771fe6b9 1421 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1422
54bfe496 1423 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1424 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1425 else if (ASIC_IS_AVIVO(rdev)) {
1426 if (is_tvcv)
1427 atombios_crtc_set_timing(crtc, adjusted_mode);
1428 else
1429 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1430 } else {
bcc1c2a1 1431 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1432 if (radeon_crtc->crtc_id == 0)
1433 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1434 radeon_legacy_atom_fixup(crtc);
771fe6b9 1435 }
bcc1c2a1 1436 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1437 atombios_overscan_setup(crtc, mode, adjusted_mode);
1438 atombios_scaler_setup(crtc);
771fe6b9
JG		 1439 return 0;
1440}
1441
1442static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1443 struct drm_display_mode *mode,
1444 struct drm_display_mode *adjusted_mode)
1445{
03214bd5
AD		 1446 struct drm_device *dev = crtc->dev;
1447 struct radeon_device *rdev = dev->dev_private;
1448
1449 /* adjust pm to upcoming mode change */
1450 radeon_pm_compute_clocks(rdev);
1451
c93bb85b
JG		 1452 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1453 return false;
771fe6b9
JG		 1454 return true;
1455}
1456
1457static void atombios_crtc_prepare(struct drm_crtc *crtc)
1458{
267364ac
AD		 1459 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1460
1461 /* pick pll */
1462 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1463
37b4390e 1464 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1465 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1466}
1467
1468static void atombios_crtc_commit(struct drm_crtc *crtc)
1469{
1470 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1471 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1472}
1473
37f9003b
AD		 1474static void atombios_crtc_disable(struct drm_crtc *crtc)
1475{
1476 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1477 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1478
1479 switch (radeon_crtc->pll_id) {
1480 case ATOM_PPLL1:
1481 case ATOM_PPLL2:
1482 /* disable the ppll */
1483 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1484 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1485 break;
1486 default:
1487 break;
1488 }
1489 radeon_crtc->pll_id = -1;
1490}
1491
771fe6b9
JG		 1492static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1493 .dpms = atombios_crtc_dpms,
1494 .mode_fixup = atombios_crtc_mode_fixup,
1495 .mode_set = atombios_crtc_mode_set,
1496 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1497 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1498 .prepare = atombios_crtc_prepare,
1499 .commit = atombios_crtc_commit,
068143d3 1500 .load_lut = radeon_crtc_load_lut,
37f9003b 1501 .disable = atombios_crtc_disable,
771fe6b9
JG		 1502};
1503
1504void radeon_atombios_init_crtc(struct drm_device *dev,
1505 struct radeon_crtc *radeon_crtc)
1506{
bcc1c2a1
AD		 1507 struct radeon_device *rdev = dev->dev_private;
1508
1509 if (ASIC_IS_DCE4(rdev)) {
1510 switch (radeon_crtc->crtc_id) {
1511 case 0:
1512 default:
12d7798f 1513 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1514 break;
1515 case 1:
12d7798f 1516 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1517 break;
1518 case 2:
12d7798f 1519 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1520 break;
1521 case 3:
12d7798f 1522 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1523 break;
1524 case 4:
12d7798f 1525 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1526 break;
1527 case 5:
12d7798f 1528 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1529 break;
1530 }
1531 } else {
1532 if (radeon_crtc->crtc_id == 1)
1533 radeon_crtc->crtc_offset =
1534 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1535 else
1536 radeon_crtc->crtc_offset = 0;
1537 }
1538 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1539 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1540}
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