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drm/radeon/kms: properly handle bpc >8 in atom command tables
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
942b0e95
AD		 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 258 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 261 radeon_crtc->enabled = false;
d7311171
AD		 262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 264 break;
265 }
771fe6b9
JG		 266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 270 struct drm_display_mode *mode)
771fe6b9 271{
5a9bcacc 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 277 u16 misc = 0;
771fe6b9 278
5a9bcacc 279 memset(&args, 0, sizeof(args));
5b1714d3 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 281 args.usH_Blanking_Time =
5b1714d3
AD		 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 284 args.usV_Blanking_Time =
5b1714d3 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 286 args.usH_SyncOffset =
5b1714d3 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
5b1714d3 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 310
5a9bcacc 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 312}
313
5a9bcacc
AD		 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
771fe6b9 316{
5a9bcacc 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 322 u16 misc = 0;
771fe6b9 323
5a9bcacc
AD		 324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
54bfe496
AD		 336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
5a9bcacc
AD		 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 354
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
b792210e
AD		 358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
26b9fc3a 401union atom_enable_ss {
ba032a58
AD		 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 407};
408
ba032a58
AD		 409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
ebbe1cb9 413{
ebbe1cb9
AD		 414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
ebbe1cb9 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 417 union atom_enable_ss args;
ebbe1cb9 418
ba032a58 419 memset(&args, 0, sizeof(args));
bcc1c2a1 420
a572eaa3 421 if (ASIC_IS_DCE5(rdev)) {
4589433c 422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
a572eaa3
AD		 423 args.v3.ucSpreadSpectrumType = ss->type;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
4589433c
CC		 427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
4589433c
CC		 432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
4589433c
CC		 437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
a572eaa3
AD		 439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v2.ucEnable = enable;
444 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58
AD		 445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446 args.v2.ucSpreadSpectrumType = ss->type;
447 switch (pll_id) {
448 case ATOM_PPLL1:
449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
4589433c
CC		 450 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
451 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 452 break;
453 case ATOM_PPLL2:
454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
4589433c
CC		 455 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
456 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ebbe1cb9 457 break;
ba032a58
AD		 458 case ATOM_DCPLL:
459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
4589433c
CC		 460 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
461 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
ba032a58
AD		 462 break;
463 case ATOM_PPLL_INVALID:
464 return;
ebbe1cb9 465 }
ba032a58
AD		 466 args.v2.ucEnable = enable;
467 } else if (ASIC_IS_DCE3(rdev)) {
468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469 args.v1.ucSpreadSpectrumType = ss->type;
470 args.v1.ucSpreadSpectrumStep = ss->step;
471 args.v1.ucSpreadSpectrumDelay = ss->delay;
472 args.v1.ucSpreadSpectrumRange = ss->range;
473 args.v1.ucPpll = pll_id;
474 args.v1.ucEnable = enable;
475 } else if (ASIC_IS_AVIVO(rdev)) {
476 if (enable == ATOM_DISABLE) {
477 atombios_disable_ss(crtc);
478 return;
479 }
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 486 } else {
ba032a58
AD		 487 if (enable == ATOM_DISABLE) {
488 atombios_disable_ss(crtc);
489 return;
490 }
491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.lvds_ss.ucSpreadSpectrumType = ss->type;
493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495 args.lvds_ss.ucEnable = enable;
ebbe1cb9 496 }
26b9fc3a 497 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 498}
499
4eaeca33
AD		 500union adjust_pixel_clock {
501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 503};
504
505static u32 atombios_adjust_pll(struct drm_crtc *crtc,
506 struct drm_display_mode *mode,
ba032a58
AD		 507 struct radeon_pll *pll,
508 bool ss_enabled,
509 struct radeon_atom_ss *ss)
771fe6b9 510{
771fe6b9
JG		 511 struct drm_device *dev = crtc->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct drm_encoder *encoder = NULL;
514 struct radeon_encoder *radeon_encoder = NULL;
df271bec 515 struct drm_connector *connector = NULL;
4eaeca33 516 u32 adjusted_clock = mode->clock;
bcc1c2a1 517 int encoder_mode = 0;
fbee67a6
AD		 518 u32 dp_clock = mode->clock;
519 int bpc = 8;
fc10332b 520
4eaeca33
AD		 521 /* reset the pll flags */
522 pll->flags = 0;
771fe6b9
JG		 523
524 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 525 if ((rdev->family == CHIP_RS600) ||
526 (rdev->family == CHIP_RS690) ||
527 (rdev->family == CHIP_RS740))
2ff776cf 528 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 529 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 530
531 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
532 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
533 else
534 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
9bb09fa1 535
5785e53f 536 if (rdev->family < CHIP_RV770)
9bb09fa1 537 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
5480f727 538 } else {
fc10332b 539 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 540
5480f727
DA		 541 if (mode->clock > 200000) /* range limits??? */
542 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
543 else
544 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
5480f727
DA		 545 }
546
771fe6b9
JG		 547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
548 if (encoder->crtc == crtc) {
4eaeca33 549 radeon_encoder = to_radeon_encoder(encoder);
df271bec
AD		 550 connector = radeon_get_connector_for_encoder(encoder);
551 if (connector)
552 bpc = connector->display_info.bpc;
bcc1c2a1 553 encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6 554 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
fbee67a6
AD		 555 if (connector) {
556 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
557 struct radeon_connector_atom_dig *dig_connector =
558 radeon_connector->con_priv;
559
560 dp_clock = dig_connector->dp_clock;
561 }
562 }
5b40ddf8 563
ba032a58
AD		 564 /* use recommended ref_div for ss */
565 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
566 if (ss_enabled) {
567 if (ss->refdiv) {
568 pll->flags |= RADEON_PLL_USE_REF_DIV;
569 pll->reference_div = ss->refdiv;
5b40ddf8
AD		 570 if (ASIC_IS_AVIVO(rdev))
571 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
ba032a58
AD		 572 }
573 }
574 }
5b40ddf8 575
4eaeca33
AD		 576 if (ASIC_IS_AVIVO(rdev)) {
577 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
578 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
579 adjusted_clock = mode->clock * 2;
48dfaaeb 580 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 581 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
5b40ddf8
AD		 582 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
583 pll->flags |= RADEON_PLL_IS_LCD;
4eaeca33
AD		 584 } else {
585 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 586 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 587 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 588 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 589 }
3ce0a23d 590 break;
771fe6b9
JG		 591 }
592 }
593
2606c886
AD		 594 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
595 * accordingly based on the encoder/transmitter to work around
596 * special hw requirements.
597 */
598 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 599 union adjust_pixel_clock args;
4eaeca33
AD		 600 u8 frev, crev;
601 int index;
2606c886 602
2606c886 603 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 604 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
605 &crev))
606 return adjusted_clock;
4eaeca33
AD		 607
608 memset(&args, 0, sizeof(args));
609
610 switch (frev) {
611 case 1:
612 switch (crev) {
613 case 1:
614 case 2:
615 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
616 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 617 args.v1.ucEncodeMode = encoder_mode;
b526ce22 618 if (ss_enabled)
fbee67a6
AD		 619 args.v1.ucConfig |=
620 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 621
622 atom_execute_table(rdev->mode_info.atom_context,
623 index, (uint32_t *)&args);
624 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
625 break;
bcc1c2a1
AD		 626 case 3:
627 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
628 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
629 args.v3.sInput.ucEncodeMode = encoder_mode;
630 args.v3.sInput.ucDispPllConfig = 0;
b526ce22
AD		 631 if (ss_enabled)
632 args.v3.sInput.ucDispPllConfig |=
633 DISPPLL_CONFIG_SS_ENABLE;
bcc1c2a1
AD		 634 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
635 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
fbee67a6 636 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1
AD		 637 args.v3.sInput.ucDispPllConfig |=
638 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 639 /* 16200 or 27000 */
640 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
641 } else {
642 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
643 /* deep color support */
644 args.v3.sInput.usPixelClock =
645 cpu_to_le16((mode->clock * bpc / 8) / 10);
646 }
bcc1c2a1
AD		 647 if (dig->coherent_mode)
648 args.v3.sInput.ucDispPllConfig |=
649 DISPPLL_CONFIG_COHERENT_MODE;
650 if (mode->clock > 165000)
651 args.v3.sInput.ucDispPllConfig |=
652 DISPPLL_CONFIG_DUAL_LINK;
653 }
654 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
fbee67a6 655 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
bcc1c2a1 656 args.v3.sInput.ucDispPllConfig |=
9f998ad7 657 DISPPLL_CONFIG_COHERENT_MODE;
fbee67a6
AD		 658 /* 16200 or 27000 */
659 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
b526ce22 660 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
9f998ad7
AD		 661 if (mode->clock > 165000)
662 args.v3.sInput.ucDispPllConfig |=
663 DISPPLL_CONFIG_DUAL_LINK;
664 }
bcc1c2a1
AD		 665 }
666 atom_execute_table(rdev->mode_info.atom_context,
667 index, (uint32_t *)&args);
668 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
669 if (args.v3.sOutput.ucRefDiv) {
9f4283f4 670 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 671 pll->flags |= RADEON_PLL_USE_REF_DIV;
672 pll->reference_div = args.v3.sOutput.ucRefDiv;
673 }
674 if (args.v3.sOutput.ucPostDiv) {
9f4283f4 675 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 676 pll->flags |= RADEON_PLL_USE_POST_DIV;
677 pll->post_div = args.v3.sOutput.ucPostDiv;
678 }
679 break;
4eaeca33
AD		 680 default:
681 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
682 return adjusted_clock;
683 }
684 break;
685 default:
686 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
687 return adjusted_clock;
688 }
d56ef9c8 689 }
4eaeca33
AD		 690 return adjusted_clock;
691}
692
693union set_pixel_clock {
694 SET_PIXEL_CLOCK_PS_ALLOCATION base;
695 PIXEL_CLOCK_PARAMETERS v1;
696 PIXEL_CLOCK_PARAMETERS_V2 v2;
697 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 698 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 699 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 700};
701
f82b3ddc
AD		 702/* on DCE5, make sure the voltage is high enough to support the
703 * required disp clk.
704 */
705static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
706 u32 dispclk)
bcc1c2a1
AD		 707{
708 struct drm_device *dev = crtc->dev;
709 struct radeon_device *rdev = dev->dev_private;
710 u8 frev, crev;
711 int index;
712 union set_pixel_clock args;
713
714 memset(&args, 0, sizeof(args));
715
716 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 717 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
718 &crev))
719 return;
bcc1c2a1
AD		 720
721 switch (frev) {
722 case 1:
723 switch (crev) {
724 case 5:
725 /* if the default dcpll clock is specified,
726 * SetPixelClock provides the dividers
727 */
728 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 729 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 730 args.v5.ucPpll = ATOM_DCPLL;
731 break;
f82b3ddc
AD		 732 case 6:
733 /* if the default dcpll clock is specified,
734 * SetPixelClock provides the dividers
735 */
265aa6c8 736 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
f82b3ddc
AD		 737 args.v6.ucPpll = ATOM_DCPLL;
738 break;
bcc1c2a1
AD		 739 default:
740 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
741 return;
742 }
743 break;
744 default:
745 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
746 return;
747 }
748 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
749}
750
37f9003b
AD		 751static void atombios_crtc_program_pll(struct drm_crtc *crtc,
752 int crtc_id,
753 int pll_id,
754 u32 encoder_mode,
755 u32 encoder_id,
756 u32 clock,
757 u32 ref_div,
758 u32 fb_div,
759 u32 frac_fb_div,
df271bec
AD		 760 u32 post_div,
761 int bpc)
4eaeca33 762{
4eaeca33
AD		 763 struct drm_device *dev = crtc->dev;
764 struct radeon_device *rdev = dev->dev_private;
4eaeca33 765 u8 frev, crev;
37f9003b 766 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 767 union set_pixel_clock args;
4eaeca33
AD		 768
769 memset(&args, 0, sizeof(args));
770
a084e6ee
AD		 771 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
772 &crev))
773 return;
771fe6b9
JG		 774
775 switch (frev) {
776 case 1:
777 switch (crev) {
778 case 1:
37f9003b
AD		 779 if (clock == ATOM_DISABLE)
780 return;
781 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 782 args.v1.usRefDiv = cpu_to_le16(ref_div);
783 args.v1.usFbDiv = cpu_to_le16(fb_div);
784 args.v1.ucFracFbDiv = frac_fb_div;
785 args.v1.ucPostDiv = post_div;
37f9003b
AD		 786 args.v1.ucPpll = pll_id;
787 args.v1.ucCRTC = crtc_id;
4eaeca33 788 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 789 break;
790 case 2:
37f9003b 791 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 792 args.v2.usRefDiv = cpu_to_le16(ref_div);
793 args.v2.usFbDiv = cpu_to_le16(fb_div);
794 args.v2.ucFracFbDiv = frac_fb_div;
795 args.v2.ucPostDiv = post_div;
37f9003b
AD		 796 args.v2.ucPpll = pll_id;
797 args.v2.ucCRTC = crtc_id;
4eaeca33 798 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 799 break;
800 case 3:
37f9003b 801 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 802 args.v3.usRefDiv = cpu_to_le16(ref_div);
803 args.v3.usFbDiv = cpu_to_le16(fb_div);
804 args.v3.ucFracFbDiv = frac_fb_div;
805 args.v3.ucPostDiv = post_div;
37f9003b
AD		 806 args.v3.ucPpll = pll_id;
807 args.v3.ucMiscInfo = (pll_id << 2);
808 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 809 args.v3.ucEncoderMode = encoder_mode;
810 break;
811 case 5:
37f9003b
AD		 812 args.v5.ucCRTC = crtc_id;
813 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 814 args.v5.ucRefDiv = ref_div;
815 args.v5.usFbDiv = cpu_to_le16(fb_div);
816 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
817 args.v5.ucPostDiv = post_div;
818 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
df271bec
AD		 819 switch (bpc) {
820 case 8:
821 default:
822 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
823 break;
824 case 10:
825 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
826 break;
827 }
37f9003b 828 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 829 args.v5.ucEncoderMode = encoder_mode;
37f9003b 830 args.v5.ucPpll = pll_id;
771fe6b9 831 break;
f82b3ddc
AD		 832 case 6:
833 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
834 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
835 args.v6.ucRefDiv = ref_div;
836 args.v6.usFbDiv = cpu_to_le16(fb_div);
837 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
838 args.v6.ucPostDiv = post_div;
839 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
df271bec
AD		 840 switch (bpc) {
841 case 8:
842 default:
843 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
844 break;
845 case 10:
846 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
847 break;
848 case 12:
849 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
850 break;
851 case 16:
852 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
853 break;
854 }
f82b3ddc
AD		 855 args.v6.ucTransmitterID = encoder_id;
856 args.v6.ucEncoderMode = encoder_mode;
857 args.v6.ucPpll = pll_id;
858 break;
771fe6b9
JG		 859 default:
860 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
861 return;
862 }
863 break;
864 default:
865 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
866 return;
867 }
868
771fe6b9
JG		 869 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
870}
871
37f9003b
AD		 872static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
873{
874 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
875 struct drm_device *dev = crtc->dev;
876 struct radeon_device *rdev = dev->dev_private;
877 struct drm_encoder *encoder = NULL;
878 struct radeon_encoder *radeon_encoder = NULL;
879 u32 pll_clock = mode->clock;
880 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
881 struct radeon_pll *pll;
882 u32 adjusted_clock;
883 int encoder_mode = 0;
ba032a58
AD		 884 struct radeon_atom_ss ss;
885 bool ss_enabled = false;
df271bec 886 int bpc = 8;
37f9003b
AD		 887
888 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
889 if (encoder->crtc == crtc) {
890 radeon_encoder = to_radeon_encoder(encoder);
891 encoder_mode = atombios_get_encoder_mode(encoder);
892 break;
893 }
894 }
895
896 if (!radeon_encoder)
897 return;
898
899 switch (radeon_crtc->pll_id) {
900 case ATOM_PPLL1:
901 pll = &rdev->clock.p1pll;
902 break;
903 case ATOM_PPLL2:
904 pll = &rdev->clock.p2pll;
905 break;
906 case ATOM_DCPLL:
907 case ATOM_PPLL_INVALID:
908 default:
909 pll = &rdev->clock.dcpll;
910 break;
911 }
912
ba032a58
AD		 913 if (radeon_encoder->active_device &
914 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
915 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
916 struct drm_connector *connector =
917 radeon_get_connector_for_encoder(encoder);
918 struct radeon_connector *radeon_connector =
919 to_radeon_connector(connector);
920 struct radeon_connector_atom_dig *dig_connector =
921 radeon_connector->con_priv;
922 int dp_clock;
df271bec 923 bpc = connector->display_info.bpc;
ba032a58
AD		 924
925 switch (encoder_mode) {
926 case ATOM_ENCODER_MODE_DP:
927 /* DP/eDP */
928 dp_clock = dig_connector->dp_clock / 10;
929 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
930 if (ASIC_IS_DCE4(rdev))
931 ss_enabled =
932 radeon_atombios_get_asic_ss_info(rdev, &ss,
933 dig->lcd_ss_id,
934 dp_clock);
935 else
936 ss_enabled =
937 radeon_atombios_get_ppll_ss_info(rdev, &ss,
938 dig->lcd_ss_id);
939 } else {
940 if (ASIC_IS_DCE4(rdev))
941 ss_enabled =
942 radeon_atombios_get_asic_ss_info(rdev, &ss,
943 ASIC_INTERNAL_SS_ON_DP,
944 dp_clock);
945 else {
946 if (dp_clock == 16200) {
947 ss_enabled =
948 radeon_atombios_get_ppll_ss_info(rdev, &ss,
949 ATOM_DP_SS_ID2);
950 if (!ss_enabled)
951 ss_enabled =
952 radeon_atombios_get_ppll_ss_info(rdev, &ss,
953 ATOM_DP_SS_ID1);
954 } else
955 ss_enabled =
956 radeon_atombios_get_ppll_ss_info(rdev, &ss,
957 ATOM_DP_SS_ID1);
958 }
959 }
960 break;
961 case ATOM_ENCODER_MODE_LVDS:
962 if (ASIC_IS_DCE4(rdev))
963 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
964 dig->lcd_ss_id,
965 mode->clock / 10);
966 else
967 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
968 dig->lcd_ss_id);
969 break;
970 case ATOM_ENCODER_MODE_DVI:
971 if (ASIC_IS_DCE4(rdev))
972 ss_enabled =
973 radeon_atombios_get_asic_ss_info(rdev, &ss,
974 ASIC_INTERNAL_SS_ON_TMDS,
975 mode->clock / 10);
976 break;
977 case ATOM_ENCODER_MODE_HDMI:
978 if (ASIC_IS_DCE4(rdev))
979 ss_enabled =
980 radeon_atombios_get_asic_ss_info(rdev, &ss,
981 ASIC_INTERNAL_SS_ON_HDMI,
982 mode->clock / 10);
983 break;
984 default:
985 break;
986 }
987 }
988
37f9003b 989 /* adjust pixel clock as needed */
ba032a58 990 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b 991
64146f8b
AD		 992 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
993 /* TV seems to prefer the legacy algo on some boards */
994 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
995 &ref_div, &post_div);
996 else if (ASIC_IS_AVIVO(rdev))
619efb10
AD		 997 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
998 &ref_div, &post_div);
999 else
1000 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1001 &ref_div, &post_div);
37f9003b 1002
ba032a58
AD		 1003 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1004
37f9003b
AD		 1005 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1006 encoder_mode, radeon_encoder->encoder_id, mode->clock,
df271bec 1007 ref_div, fb_div, frac_fb_div, post_div, bpc);
37f9003b 1008
ba032a58
AD		 1009 if (ss_enabled) {
1010 /* calculate ss amount and step size */
1011 if (ASIC_IS_DCE4(rdev)) {
1012 u32 step_size;
1013 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1014 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1015 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1016 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1017 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1018 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1019 (125 * 25 * pll->reference_freq / 100);
1020 else
1021 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1022 (125 * 25 * pll->reference_freq / 100);
1023 ss.step = step_size;
1024 }
1025
1026 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1027 }
37f9003b
AD		 1028}
1029
c9417bdd
AD		 1030static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1031 struct drm_framebuffer *fb,
1032 int x, int y, int atomic)
bcc1c2a1
AD		 1033{
1034 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1035 struct drm_device *dev = crtc->dev;
1036 struct radeon_device *rdev = dev->dev_private;
1037 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1038 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1039 struct drm_gem_object *obj;
1040 struct radeon_bo *rbo;
1041 uint64_t fb_location;
1042 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1043 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
fb9674bd 1044 u32 tmp;
bcc1c2a1
AD		 1045 int r;
1046
1047 /* no fb bound */
4dd19b0d 1048 if (!atomic && !crtc->fb) {
d9fdaafb 1049 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1050 return 0;
1051 }
1052
4dd19b0d
CB		 1053 if (atomic) {
1054 radeon_fb = to_radeon_framebuffer(fb);
1055 target_fb = fb;
1056 }
1057 else {
1058 radeon_fb = to_radeon_framebuffer(crtc->fb);
1059 target_fb = crtc->fb;
1060 }
bcc1c2a1 1061
4dd19b0d
CB		 1062 /* If atomic, assume fb object is pinned & idle & fenced and
1063 * just update base pointers
1064 */
bcc1c2a1 1065 obj = radeon_fb->obj;
7e4d15d9 1066 rbo = gem_to_radeon_bo(obj);
bcc1c2a1
AD		 1067 r = radeon_bo_reserve(rbo, false);
1068 if (unlikely(r != 0))
1069 return r;
4dd19b0d
CB		 1070
1071 if (atomic)
1072 fb_location = radeon_bo_gpu_offset(rbo);
1073 else {
1074 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1075 if (unlikely(r != 0)) {
1076 radeon_bo_unreserve(rbo);
1077 return -EINVAL;
1078 }
bcc1c2a1 1079 }
4dd19b0d 1080
bcc1c2a1
AD		 1081 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1082 radeon_bo_unreserve(rbo);
1083
4dd19b0d 1084 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1085 case 8:
1086 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1087 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1088 break;
1089 case 15:
1090 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1091 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1092 break;
1093 case 16:
1094 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1095 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1096#ifdef __BIG_ENDIAN
1097 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1098#endif
bcc1c2a1
AD		 1099 break;
1100 case 24:
1101 case 32:
1102 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1103 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1104#ifdef __BIG_ENDIAN
1105 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1106#endif
bcc1c2a1
AD		 1107 break;
1108 default:
1109 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1110 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1111 return -EINVAL;
1112 }
1113
97d66328
AD		 1114 if (tiling_flags & RADEON_TILING_MACRO)
1115 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1116 else if (tiling_flags & RADEON_TILING_MICRO)
1117 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1118
bcc1c2a1
AD		 1119 switch (radeon_crtc->crtc_id) {
1120 case 0:
1121 WREG32(AVIVO_D1VGA_CONTROL, 0);
1122 break;
1123 case 1:
1124 WREG32(AVIVO_D2VGA_CONTROL, 0);
1125 break;
1126 case 2:
1127 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1128 break;
1129 case 3:
1130 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1131 break;
1132 case 4:
1133 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1134 break;
1135 case 5:
1136 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1137 break;
1138 default:
1139 break;
1140 }
1141
1142 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1143 upper_32_bits(fb_location));
1144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1145 upper_32_bits(fb_location));
1146 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1147 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1148 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1149 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1150 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1151 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1
AD		 1152
1153 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1154 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1155 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1156 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1157 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1158 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1159
4dd19b0d 1160 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1161 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1162 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1163
1164 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1165 crtc->mode.vdisplay);
1166 x &= ~3;
1167 y &= ~1;
1168 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1169 (x << 16) | y);
1170 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1171 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1172
fb9674bd
AD		 1173 /* pageflip setup */
1174 /* make sure flip is at vb rather than hb */
1175 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1176 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1177 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1178
1179 /* set pageflip to happen anywhere in vblank interval */
1180 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1181
4dd19b0d
CB		 1182 if (!atomic && fb && fb != crtc->fb) {
1183 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1184 rbo = gem_to_radeon_bo(radeon_fb->obj);
bcc1c2a1
AD		 1185 r = radeon_bo_reserve(rbo, false);
1186 if (unlikely(r != 0))
1187 return r;
1188 radeon_bo_unpin(rbo);
1189 radeon_bo_unreserve(rbo);
1190 }
1191
1192 /* Bytes per pixel may have changed */
1193 radeon_bandwidth_update(rdev);
1194
1195 return 0;
1196}
1197
4dd19b0d
CB		 1198static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1199 struct drm_framebuffer *fb,
1200 int x, int y, int atomic)
771fe6b9
JG		 1201{
1202 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1203 struct drm_device *dev = crtc->dev;
1204 struct radeon_device *rdev = dev->dev_private;
1205 struct radeon_framebuffer *radeon_fb;
1206 struct drm_gem_object *obj;
4c788679 1207 struct radeon_bo *rbo;
4dd19b0d 1208 struct drm_framebuffer *target_fb;
771fe6b9 1209 uint64_t fb_location;
e024e110 1210 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1211 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
fb9674bd 1212 u32 tmp;
4c788679 1213 int r;
771fe6b9 1214
2de3b484 1215 /* no fb bound */
4dd19b0d 1216 if (!atomic && !crtc->fb) {
d9fdaafb 1217 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1218 return 0;
1219 }
771fe6b9 1220
4dd19b0d
CB		 1221 if (atomic) {
1222 radeon_fb = to_radeon_framebuffer(fb);
1223 target_fb = fb;
1224 }
1225 else {
1226 radeon_fb = to_radeon_framebuffer(crtc->fb);
1227 target_fb = crtc->fb;
1228 }
771fe6b9
JG		 1229
1230 obj = radeon_fb->obj;
7e4d15d9 1231 rbo = gem_to_radeon_bo(obj);
4c788679
JG		 1232 r = radeon_bo_reserve(rbo, false);
1233 if (unlikely(r != 0))
1234 return r;
4dd19b0d
CB		 1235
1236 /* If atomic, assume fb object is pinned & idle & fenced and
1237 * just update base pointers
1238 */
1239 if (atomic)
1240 fb_location = radeon_bo_gpu_offset(rbo);
1241 else {
1242 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1243 if (unlikely(r != 0)) {
1244 radeon_bo_unreserve(rbo);
1245 return -EINVAL;
1246 }
771fe6b9 1247 }
4c788679
JG		 1248 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1249 radeon_bo_unreserve(rbo);
771fe6b9 1250
4dd19b0d 1251 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1252 case 8:
1253 fb_format =
1254 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1255 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1256 break;
771fe6b9
JG		 1257 case 15:
1258 fb_format =
1259 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1260 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1261 break;
1262 case 16:
1263 fb_format =
1264 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1265 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1266#ifdef __BIG_ENDIAN
1267 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1268#endif
771fe6b9
JG		 1269 break;
1270 case 24:
1271 case 32:
1272 fb_format =
1273 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1274 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1275#ifdef __BIG_ENDIAN
1276 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1277#endif
771fe6b9
JG		 1278 break;
1279 default:
1280 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1281 target_fb->bits_per_pixel);
771fe6b9
JG		 1282 return -EINVAL;
1283 }
1284
40c4ac1c
AD		 1285 if (rdev->family >= CHIP_R600) {
1286 if (tiling_flags & RADEON_TILING_MACRO)
1287 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1288 else if (tiling_flags & RADEON_TILING_MICRO)
1289 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1290 } else {
1291 if (tiling_flags & RADEON_TILING_MACRO)
1292 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1293
40c4ac1c
AD		 1294 if (tiling_flags & RADEON_TILING_MICRO)
1295 fb_format |= AVIVO_D1GRPH_TILED;
1296 }
e024e110 1297
771fe6b9
JG		 1298 if (radeon_crtc->crtc_id == 0)
1299 WREG32(AVIVO_D1VGA_CONTROL, 0);
1300 else
1301 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1302
1303 if (rdev->family >= CHIP_RV770) {
1304 if (radeon_crtc->crtc_id) {
95347871
AD		 1305 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1306 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1307 } else {
95347871
AD		 1308 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1309 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1310 }
1311 }
771fe6b9
JG		 1312 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1313 (u32) fb_location);
1314 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1315 radeon_crtc->crtc_offset, (u32) fb_location);
1316 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1317 if (rdev->family >= CHIP_R600)
1318 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9
JG		 1319
1320 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1321 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1322 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1323 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1324 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1325 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1326
4dd19b0d 1327 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1328 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1329 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1330
1331 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1332 crtc->mode.vdisplay);
1333 x &= ~3;
1334 y &= ~1;
1335 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1336 (x << 16) | y);
1337 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1338 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1339
fb9674bd
AD		 1340 /* pageflip setup */
1341 /* make sure flip is at vb rather than hb */
1342 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1343 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1344 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1345
1346 /* set pageflip to happen anywhere in vblank interval */
1347 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1348
4dd19b0d
CB		 1349 if (!atomic && fb && fb != crtc->fb) {
1350 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1351 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 1352 r = radeon_bo_reserve(rbo, false);
1353 if (unlikely(r != 0))
1354 return r;
1355 radeon_bo_unpin(rbo);
1356 radeon_bo_unreserve(rbo);
771fe6b9 1357 }
f30f37de
MD		 1358
1359 /* Bytes per pixel may have changed */
1360 radeon_bandwidth_update(rdev);
1361
771fe6b9
JG		 1362 return 0;
1363}
1364
54f088a9
AD		 1365int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1366 struct drm_framebuffer *old_fb)
1367{
1368 struct drm_device *dev = crtc->dev;
1369 struct radeon_device *rdev = dev->dev_private;
1370
bcc1c2a1 1371 if (ASIC_IS_DCE4(rdev))
c9417bdd 1372 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1373 else if (ASIC_IS_AVIVO(rdev))
1374 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1375 else
1376 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1377}
1378
1379int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1380 struct drm_framebuffer *fb,
21c74a8e 1381 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1382{
1383 struct drm_device *dev = crtc->dev;
1384 struct radeon_device *rdev = dev->dev_private;
1385
1386 if (ASIC_IS_DCE4(rdev))
c9417bdd 1387 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1388 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1389 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1390 else
4dd19b0d 1391 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1392}
1393
615e0cb6
AD		 1394/* properly set additional regs when using atombios */
1395static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1396{
1397 struct drm_device *dev = crtc->dev;
1398 struct radeon_device *rdev = dev->dev_private;
1399 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1400 u32 disp_merge_cntl;
1401
1402 switch (radeon_crtc->crtc_id) {
1403 case 0:
1404 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1405 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1406 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1407 break;
1408 case 1:
1409 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1410 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1411 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1412 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1413 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1414 break;
1415 }
1416}
1417
bcc1c2a1
AD		 1418static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1419{
1420 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1421 struct drm_device *dev = crtc->dev;
1422 struct radeon_device *rdev = dev->dev_private;
1423 struct drm_encoder *test_encoder;
1424 struct drm_crtc *test_crtc;
1425 uint32_t pll_in_use = 0;
1426
1427 if (ASIC_IS_DCE4(rdev)) {
1428 /* if crtc is driving DP and we have an ext clock, use that */
1429 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1430 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1431 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1432 if (rdev->clock.dp_extclk)
1433 return ATOM_PPLL_INVALID;
1434 }
1435 }
1436 }
1437
1438 /* otherwise, pick one of the plls */
1439 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1440 struct radeon_crtc *radeon_test_crtc;
1441
1442 if (crtc == test_crtc)
1443 continue;
1444
1445 radeon_test_crtc = to_radeon_crtc(test_crtc);
1446 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1447 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1448 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1449 }
1450 if (!(pll_in_use & 1))
1451 return ATOM_PPLL1;
1452 return ATOM_PPLL2;
1453 } else
1454 return radeon_crtc->crtc_id;
1455
1456}
1457
771fe6b9
JG		 1458int atombios_crtc_mode_set(struct drm_crtc *crtc,
1459 struct drm_display_mode *mode,
1460 struct drm_display_mode *adjusted_mode,
1461 int x, int y, struct drm_framebuffer *old_fb)
1462{
1463 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1464 struct drm_device *dev = crtc->dev;
1465 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1466 struct drm_encoder *encoder;
1467 bool is_tvcv = false;
771fe6b9 1468
54bfe496
AD		 1469 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1470 /* find tv std */
1471 if (encoder->crtc == crtc) {
1472 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1473 if (radeon_encoder->active_device &
1474 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1475 is_tvcv = true;
1476 }
1477 }
771fe6b9 1478
bcc1c2a1 1479 /* always set DCPLL */
ba032a58
AD		 1480 if (ASIC_IS_DCE4(rdev)) {
1481 struct radeon_atom_ss ss;
1482 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1483 ASIC_INTERNAL_SS_ON_DCPLL,
1484 rdev->clock.default_dispclk);
1485 if (ss_enabled)
1486 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
f82b3ddc
AD		 1487 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1488 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
ba032a58
AD		 1489 if (ss_enabled)
1490 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1491 }
771fe6b9 1492 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1493
54bfe496 1494 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1495 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1496 else if (ASIC_IS_AVIVO(rdev)) {
1497 if (is_tvcv)
1498 atombios_crtc_set_timing(crtc, adjusted_mode);
1499 else
1500 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1501 } else {
bcc1c2a1 1502 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1503 if (radeon_crtc->crtc_id == 0)
1504 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1505 radeon_legacy_atom_fixup(crtc);
771fe6b9 1506 }
bcc1c2a1 1507 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1508 atombios_overscan_setup(crtc, mode, adjusted_mode);
1509 atombios_scaler_setup(crtc);
771fe6b9
JG		 1510 return 0;
1511}
1512
1513static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1514 struct drm_display_mode *mode,
1515 struct drm_display_mode *adjusted_mode)
1516{
03214bd5
AD		 1517 struct drm_device *dev = crtc->dev;
1518 struct radeon_device *rdev = dev->dev_private;
1519
1520 /* adjust pm to upcoming mode change */
1521 radeon_pm_compute_clocks(rdev);
1522
c93bb85b
JG		 1523 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1524 return false;
771fe6b9
JG		 1525 return true;
1526}
1527
1528static void atombios_crtc_prepare(struct drm_crtc *crtc)
1529{
267364ac
AD		 1530 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1531
1532 /* pick pll */
1533 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1534
37b4390e 1535 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1536 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1537}
1538
1539static void atombios_crtc_commit(struct drm_crtc *crtc)
1540{
1541 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1542 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1543}
1544
37f9003b
AD		 1545static void atombios_crtc_disable(struct drm_crtc *crtc)
1546{
1547 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1548 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1549
1550 switch (radeon_crtc->pll_id) {
1551 case ATOM_PPLL1:
1552 case ATOM_PPLL2:
1553 /* disable the ppll */
1554 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
df271bec 1555 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0);
37f9003b
AD		 1556 break;
1557 default:
1558 break;
1559 }
1560 radeon_crtc->pll_id = -1;
1561}
1562
771fe6b9
JG		 1563static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1564 .dpms = atombios_crtc_dpms,
1565 .mode_fixup = atombios_crtc_mode_fixup,
1566 .mode_set = atombios_crtc_mode_set,
1567 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1568 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1569 .prepare = atombios_crtc_prepare,
1570 .commit = atombios_crtc_commit,
068143d3 1571 .load_lut = radeon_crtc_load_lut,
37f9003b 1572 .disable = atombios_crtc_disable,
771fe6b9
JG		 1573};
1574
1575void radeon_atombios_init_crtc(struct drm_device *dev,
1576 struct radeon_crtc *radeon_crtc)
1577{
bcc1c2a1
AD		 1578 struct radeon_device *rdev = dev->dev_private;
1579
1580 if (ASIC_IS_DCE4(rdev)) {
1581 switch (radeon_crtc->crtc_id) {
1582 case 0:
1583 default:
12d7798f 1584 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1585 break;
1586 case 1:
12d7798f 1587 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1588 break;
1589 case 2:
12d7798f 1590 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1591 break;
1592 case 3:
12d7798f 1593 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1594 break;
1595 case 4:
12d7798f 1596 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1597 break;
1598 case 5:
12d7798f 1599 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1600 break;
1601 }
1602 } else {
1603 if (radeon_crtc->crtc_id == 1)
1604 radeon_crtc->crtc_offset =
1605 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1606 else
1607 radeon_crtc->crtc_offset = 0;
1608 }
1609 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1610 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1611}
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