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b530602f AD |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/hdmi.h> | |
24 | #include <drm/drmP.h> | |
25 | #include "radeon.h" | |
26 | #include "sid.h" | |
27 | ||
28 | static u32 dce6_endpoint_rreg(struct radeon_device *rdev, | |
29 | u32 block_offset, u32 reg) | |
30 | { | |
0a5b7b0b | 31 | unsigned long flags; |
b530602f AD |
32 | u32 r; |
33 | ||
0a5b7b0b | 34 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
b530602f AD |
35 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
36 | r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); | |
0a5b7b0b AD |
37 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
38 | ||
b530602f AD |
39 | return r; |
40 | } | |
41 | ||
42 | static void dce6_endpoint_wreg(struct radeon_device *rdev, | |
43 | u32 block_offset, u32 reg, u32 v) | |
44 | { | |
0a5b7b0b AD |
45 | unsigned long flags; |
46 | ||
47 | spin_lock_irqsave(&rdev->end_idx_lock, flags); | |
b530602f AD |
48 | if (ASIC_IS_DCE8(rdev)) |
49 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); | |
50 | else | |
51 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, | |
52 | AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); | |
53 | WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); | |
0a5b7b0b | 54 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
b530602f AD |
55 | } |
56 | ||
57 | #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg)) | |
58 | #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v)) | |
59 | ||
60 | ||
61 | static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) | |
62 | { | |
63 | int i; | |
64 | u32 offset, tmp; | |
65 | ||
66 | for (i = 0; i < rdev->audio.num_pins; i++) { | |
67 | offset = rdev->audio.pin[i].offset; | |
68 | tmp = RREG32_ENDPOINT(offset, | |
69 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); | |
70 | if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) | |
71 | rdev->audio.pin[i].connected = false; | |
72 | else | |
73 | rdev->audio.pin[i].connected = true; | |
74 | } | |
75 | } | |
76 | ||
77 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) | |
78 | { | |
79 | int i; | |
80 | ||
81 | dce6_afmt_get_connected_pins(rdev); | |
82 | ||
83 | for (i = 0; i < rdev->audio.num_pins; i++) { | |
84 | if (rdev->audio.pin[i].connected) | |
85 | return &rdev->audio.pin[i]; | |
86 | } | |
87 | DRM_ERROR("No connected audio pins found!\n"); | |
88 | return NULL; | |
89 | } | |
90 | ||
91 | void dce6_afmt_select_pin(struct drm_encoder *encoder) | |
92 | { | |
93 | struct radeon_device *rdev = encoder->dev->dev_private; | |
94 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
95 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
53dc0b0c | 96 | u32 offset; |
b530602f | 97 | |
53dc0b0c | 98 | if (!dig || !dig->afmt || !dig->afmt->pin) |
b530602f AD |
99 | return; |
100 | ||
53dc0b0c AD |
101 | offset = dig->afmt->offset; |
102 | ||
7cc0a3d8 AD |
103 | WREG32(AFMT_AUDIO_SRC_CONTROL + offset, |
104 | AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); | |
b530602f AD |
105 | } |
106 | ||
b1880258 AD |
107 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
108 | struct drm_display_mode *mode) | |
109 | { | |
110 | struct radeon_device *rdev = encoder->dev->dev_private; | |
111 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
112 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
113 | struct drm_connector *connector; | |
114 | struct radeon_connector *radeon_connector = NULL; | |
115 | u32 tmp = 0, offset; | |
116 | ||
53dc0b0c | 117 | if (!dig || !dig->afmt || !dig->afmt->pin) |
b1880258 AD |
118 | return; |
119 | ||
120 | offset = dig->afmt->pin->offset; | |
121 | ||
122 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
123 | if (connector->encoder == encoder) { | |
124 | radeon_connector = to_radeon_connector(connector); | |
125 | break; | |
126 | } | |
127 | } | |
128 | ||
129 | if (!radeon_connector) { | |
130 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
131 | return; | |
132 | } | |
133 | ||
134 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
135 | if (connector->latency_present[1]) | |
136 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | | |
137 | AUDIO_LIPSYNC(connector->audio_latency[1]); | |
138 | else | |
139 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | |
140 | } else { | |
141 | if (connector->latency_present[0]) | |
142 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | | |
143 | AUDIO_LIPSYNC(connector->audio_latency[0]); | |
144 | else | |
145 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | |
146 | } | |
147 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); | |
148 | } | |
149 | ||
6159b65a | 150 | void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder) |
b530602f AD |
151 | { |
152 | struct radeon_device *rdev = encoder->dev->dev_private; | |
153 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
154 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
6159b65a RM |
155 | struct drm_connector *connector; |
156 | struct radeon_connector *radeon_connector = NULL; | |
b530602f | 157 | u32 offset, tmp; |
6159b65a RM |
158 | u8 *sadb; |
159 | int sad_count; | |
160 | ||
53dc0b0c | 161 | if (!dig || !dig->afmt || !dig->afmt->pin) |
6159b65a RM |
162 | return; |
163 | ||
164 | offset = dig->afmt->pin->offset; | |
165 | ||
166 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
167 | if (connector->encoder == encoder) | |
168 | radeon_connector = to_radeon_connector(connector); | |
169 | } | |
170 | ||
171 | if (!radeon_connector) { | |
172 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
173 | return; | |
174 | } | |
175 | ||
176 | sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb); | |
b67ce39a | 177 | if (sad_count <= 0) { |
6159b65a RM |
178 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
179 | return; | |
180 | } | |
181 | ||
182 | /* program the speaker allocation */ | |
183 | tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); | |
184 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); | |
185 | /* set HDMI mode */ | |
186 | tmp |= HDMI_CONNECTION; | |
187 | if (sad_count) | |
188 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
189 | else | |
190 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
191 | WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); | |
192 | ||
193 | kfree(sadb); | |
194 | } | |
195 | ||
196 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder) | |
197 | { | |
198 | struct radeon_device *rdev = encoder->dev->dev_private; | |
199 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
200 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
201 | u32 offset; | |
b530602f AD |
202 | struct drm_connector *connector; |
203 | struct radeon_connector *radeon_connector = NULL; | |
204 | struct cea_sad *sads; | |
6159b65a | 205 | int i, sad_count; |
b530602f AD |
206 | |
207 | static const u16 eld_reg_to_type[][2] = { | |
208 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
209 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
210 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
211 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
212 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
213 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
214 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
215 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
216 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
217 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
218 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
219 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
220 | }; | |
221 | ||
53dc0b0c | 222 | if (!dig || !dig->afmt || !dig->afmt->pin) |
b530602f AD |
223 | return; |
224 | ||
225 | offset = dig->afmt->pin->offset; | |
226 | ||
227 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
228 | if (connector->encoder == encoder) | |
229 | radeon_connector = to_radeon_connector(connector); | |
230 | } | |
231 | ||
232 | if (!radeon_connector) { | |
233 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
234 | return; | |
235 | } | |
236 | ||
237 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); | |
b67ce39a | 238 | if (sad_count <= 0) { |
b530602f AD |
239 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
240 | return; | |
241 | } | |
242 | BUG_ON(!sads); | |
243 | ||
b530602f AD |
244 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
245 | u32 value = 0; | |
0f57bca9 AH |
246 | u8 stereo_freqs = 0; |
247 | int max_channels = -1; | |
b530602f AD |
248 | int j; |
249 | ||
250 | for (j = 0; j < sad_count; j++) { | |
251 | struct cea_sad *sad = &sads[j]; | |
252 | ||
253 | if (sad->format == eld_reg_to_type[i][1]) { | |
0f57bca9 AH |
254 | if (sad->channels > max_channels) { |
255 | value = MAX_CHANNELS(sad->channels) | | |
256 | DESCRIPTOR_BYTE_2(sad->byte2) | | |
257 | SUPPORTED_FREQUENCIES(sad->freq); | |
258 | max_channels = sad->channels; | |
259 | } | |
260 | ||
b530602f | 261 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
0f57bca9 AH |
262 | stereo_freqs |= sad->freq; |
263 | else | |
264 | break; | |
b530602f AD |
265 | } |
266 | } | |
0f57bca9 AH |
267 | |
268 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); | |
269 | ||
b530602f AD |
270 | WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value); |
271 | } | |
272 | ||
273 | kfree(sads); | |
b530602f AD |
274 | } |
275 | ||
276 | static int dce6_audio_chipset_supported(struct radeon_device *rdev) | |
277 | { | |
278 | return !ASIC_IS_NODCE(rdev); | |
279 | } | |
280 | ||
281 | static void dce6_audio_enable(struct radeon_device *rdev, | |
282 | struct r600_audio_pin *pin, | |
283 | bool enable) | |
284 | { | |
285 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, | |
d7eb0a09 | 286 | enable ? AUDIO_ENABLED : 0); |
b530602f AD |
287 | DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); |
288 | } | |
289 | ||
290 | static const u32 pin_offsets[7] = | |
291 | { | |
292 | (0x5e00 - 0x5e00), | |
293 | (0x5e18 - 0x5e00), | |
294 | (0x5e30 - 0x5e00), | |
295 | (0x5e48 - 0x5e00), | |
296 | (0x5e60 - 0x5e00), | |
297 | (0x5e78 - 0x5e00), | |
298 | (0x5e90 - 0x5e00), | |
299 | }; | |
300 | ||
301 | int dce6_audio_init(struct radeon_device *rdev) | |
302 | { | |
303 | int i; | |
304 | ||
305 | if (!radeon_audio || !dce6_audio_chipset_supported(rdev)) | |
306 | return 0; | |
307 | ||
308 | rdev->audio.enabled = true; | |
309 | ||
310 | if (ASIC_IS_DCE8(rdev)) | |
533518a4 AD |
311 | rdev->audio.num_pins = 6; |
312 | else if (ASIC_IS_DCE61(rdev)) | |
313 | rdev->audio.num_pins = 4; | |
b530602f AD |
314 | else |
315 | rdev->audio.num_pins = 6; | |
316 | ||
317 | for (i = 0; i < rdev->audio.num_pins; i++) { | |
318 | rdev->audio.pin[i].channels = -1; | |
319 | rdev->audio.pin[i].rate = -1; | |
320 | rdev->audio.pin[i].bits_per_sample = -1; | |
321 | rdev->audio.pin[i].status_bits = 0; | |
322 | rdev->audio.pin[i].category_code = 0; | |
323 | rdev->audio.pin[i].connected = false; | |
324 | rdev->audio.pin[i].offset = pin_offsets[i]; | |
325 | rdev->audio.pin[i].id = i; | |
326 | dce6_audio_enable(rdev, &rdev->audio.pin[i], true); | |
327 | } | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | void dce6_audio_fini(struct radeon_device *rdev) | |
333 | { | |
334 | int i; | |
335 | ||
336 | if (!rdev->audio.enabled) | |
337 | return; | |
338 | ||
339 | for (i = 0; i < rdev->audio.num_pins; i++) | |
340 | dce6_audio_enable(rdev, &rdev->audio.pin[i], false); | |
341 | ||
342 | rdev->audio.enabled = false; | |
343 | } |