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e55d3e6c RM |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | * Rafał Miłecki | |
26 | */ | |
e3b2e034 | 27 | #include <linux/hdmi.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
e55d3e6c RM |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" | |
070a2e63 | 32 | #include "radeon_audio.h" |
e55d3e6c RM |
33 | #include "evergreend.h" |
34 | #include "atom.h" | |
35 | ||
d3d8c141 | 36 | /* enable the audio stream */ |
8bf59820 | 37 | void dce4_audio_enable(struct radeon_device *rdev, |
d3d8c141 AD |
38 | struct r600_audio_pin *pin, |
39 | u8 enable_mask) | |
40 | { | |
41 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); | |
42 | ||
43 | if (!pin) | |
44 | return; | |
45 | ||
46 | if (enable_mask) { | |
47 | tmp |= AUDIO_ENABLED; | |
48 | if (enable_mask & 1) | |
49 | tmp |= PIN0_AUDIO_ENABLED; | |
50 | if (enable_mask & 2) | |
51 | tmp |= PIN1_AUDIO_ENABLED; | |
52 | if (enable_mask & 4) | |
53 | tmp |= PIN2_AUDIO_ENABLED; | |
54 | if (enable_mask & 8) | |
55 | tmp |= PIN3_AUDIO_ENABLED; | |
56 | } else { | |
57 | tmp &= ~(AUDIO_ENABLED | | |
58 | PIN0_AUDIO_ENABLED | | |
59 | PIN1_AUDIO_ENABLED | | |
60 | PIN2_AUDIO_ENABLED | | |
61 | PIN3_AUDIO_ENABLED); | |
62 | } | |
63 | ||
64 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); | |
65 | } | |
66 | ||
64424d6e SG |
67 | void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
68 | const struct radeon_hdmi_acr *acr) | |
e55d3e6c RM |
69 | { |
70 | struct drm_device *dev = encoder->dev; | |
71 | struct radeon_device *rdev = dev->dev_private; | |
64424d6e SG |
72 | int bpc = 8; |
73 | ||
74 | if (encoder->crtc) { | |
75 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
76 | bpc = radeon_crtc->bpc; | |
77 | } | |
e55d3e6c | 78 | |
64424d6e SG |
79 | if (bpc > 8) |
80 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, | |
81 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ | |
82 | else | |
83 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, | |
84 | HDMI_ACR_SOURCE | /* select SW CTS value */ | |
85 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ | |
86 | ||
87 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); | |
88 | WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); | |
e55d3e6c | 89 | |
64424d6e SG |
90 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); |
91 | WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); | |
e55d3e6c | 92 | |
64424d6e SG |
93 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); |
94 | WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); | |
e55d3e6c RM |
95 | } |
96 | ||
87654f87 SG |
97 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
98 | struct drm_connector *connector, struct drm_display_mode *mode) | |
712fd8a2 AD |
99 | { |
100 | struct radeon_device *rdev = encoder->dev->dev_private; | |
712fd8a2 AD |
101 | u32 tmp = 0; |
102 | ||
712fd8a2 AD |
103 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
104 | if (connector->latency_present[1]) | |
105 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | | |
106 | AUDIO_LIPSYNC(connector->audio_latency[1]); | |
107 | else | |
108 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | |
109 | } else { | |
110 | if (connector->latency_present[0]) | |
111 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | | |
112 | AUDIO_LIPSYNC(connector->audio_latency[0]); | |
113 | else | |
114 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); | |
115 | } | |
87654f87 | 116 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
712fd8a2 AD |
117 | } |
118 | ||
00a9d4bc SG |
119 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
120 | u8 *sadb, int sad_count) | |
ba7def4f AD |
121 | { |
122 | struct radeon_device *rdev = encoder->dev->dev_private; | |
ba7def4f | 123 | u32 tmp; |
ba7def4f AD |
124 | |
125 | /* program the speaker allocation */ | |
00a9d4bc | 126 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
ba7def4f AD |
127 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
128 | /* set HDMI mode */ | |
129 | tmp |= HDMI_CONNECTION; | |
130 | if (sad_count) | |
131 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
132 | else | |
133 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
00a9d4bc SG |
134 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
135 | } | |
ba7def4f | 136 | |
00a9d4bc SG |
137 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
138 | u8 *sadb, int sad_count) | |
139 | { | |
140 | struct radeon_device *rdev = encoder->dev->dev_private; | |
141 | u32 tmp; | |
142 | ||
143 | /* program the speaker allocation */ | |
144 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); | |
145 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); | |
146 | /* set DP mode */ | |
147 | tmp |= DP_CONNECTION; | |
148 | if (sad_count) | |
149 | tmp |= SPEAKER_ALLOCATION(sadb[0]); | |
150 | else | |
151 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ | |
152 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); | |
ba7def4f AD |
153 | } |
154 | ||
070a2e63 AD |
155 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
156 | struct cea_sad *sads, int sad_count) | |
46892caa | 157 | { |
070a2e63 | 158 | int i; |
46892caa | 159 | struct radeon_device *rdev = encoder->dev->dev_private; |
46892caa RM |
160 | static const u16 eld_reg_to_type[][2] = { |
161 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
162 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
163 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
164 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
165 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
166 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
167 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
168 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
169 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
170 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
171 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
172 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
173 | }; | |
174 | ||
46892caa RM |
175 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
176 | u32 value = 0; | |
0f57bca9 AH |
177 | u8 stereo_freqs = 0; |
178 | int max_channels = -1; | |
46892caa RM |
179 | int j; |
180 | ||
181 | for (j = 0; j < sad_count; j++) { | |
182 | struct cea_sad *sad = &sads[j]; | |
183 | ||
184 | if (sad->format == eld_reg_to_type[i][1]) { | |
0f57bca9 AH |
185 | if (sad->channels > max_channels) { |
186 | value = MAX_CHANNELS(sad->channels) | | |
187 | DESCRIPTOR_BYTE_2(sad->byte2) | | |
188 | SUPPORTED_FREQUENCIES(sad->freq); | |
189 | max_channels = sad->channels; | |
190 | } | |
191 | ||
46892caa | 192 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
0f57bca9 AH |
193 | stereo_freqs |= sad->freq; |
194 | else | |
195 | break; | |
46892caa RM |
196 | } |
197 | } | |
0f57bca9 AH |
198 | |
199 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); | |
200 | ||
070a2e63 | 201 | WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); |
46892caa | 202 | } |
46892caa RM |
203 | } |
204 | ||
e55d3e6c | 205 | /* |
96ea7afb | 206 | * build a AVI Info Frame |
e55d3e6c | 207 | */ |
baa7d8e4 | 208 | void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
96ea7afb | 209 | unsigned char *buffer, size_t size) |
e55d3e6c | 210 | { |
e3b2e034 | 211 | uint8_t *frame = buffer + 3; |
e55d3e6c RM |
212 | |
213 | WREG32(AFMT_AVI_INFO0 + offset, | |
214 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); | |
215 | WREG32(AFMT_AVI_INFO1 + offset, | |
216 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); | |
217 | WREG32(AFMT_AVI_INFO2 + offset, | |
218 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); | |
219 | WREG32(AFMT_AVI_INFO3 + offset, | |
96ea7afb | 220 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
baa7d8e4 | 221 | |
baa7d8e4 | 222 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
304f07e9 AD |
223 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
224 | ~HDMI_AVI_INFO_LINE_MASK); | |
e55d3e6c RM |
225 | } |
226 | ||
a85d682a SG |
227 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
228 | struct radeon_crtc *crtc, unsigned int clock) | |
b1f6f47e | 229 | { |
a85d682a | 230 | unsigned int max_ratio = clock / 24000; |
1518dd8e | 231 | u32 dto_phase; |
1518dd8e | 232 | u32 wallclock_ratio; |
a85d682a SG |
233 | u32 value; |
234 | ||
235 | if (max_ratio >= 8) { | |
236 | dto_phase = 192 * 1000; | |
237 | wallclock_ratio = 3; | |
238 | } else if (max_ratio >= 4) { | |
239 | dto_phase = 96 * 1000; | |
240 | wallclock_ratio = 2; | |
241 | } else if (max_ratio >= 2) { | |
242 | dto_phase = 48 * 1000; | |
243 | wallclock_ratio = 1; | |
b530602f | 244 | } else { |
a85d682a SG |
245 | dto_phase = 24 * 1000; |
246 | wallclock_ratio = 0; | |
1518dd8e | 247 | } |
1518dd8e | 248 | |
a85d682a SG |
249 | value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
250 | value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); | |
251 | value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO; | |
252 | WREG32(DCCG_AUDIO_DTO0_CNTL, value); | |
253 | ||
254 | /* Two dtos; generally use dto0 for HDMI */ | |
255 | value = 0; | |
256 | ||
257 | if (crtc) | |
258 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); | |
259 | ||
260 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); | |
261 | ||
b1f6f47e AD |
262 | /* Express [24MHz / target pixel clock] as an exact rational |
263 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
264 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
265 | */ | |
1518dd8e | 266 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
a85d682a | 267 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
b1f6f47e AD |
268 | } |
269 | ||
a85d682a | 270 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
aeefd07e | 271 | struct radeon_crtc *crtc, unsigned int clock) |
a85d682a SG |
272 | { |
273 | u32 value; | |
274 | ||
275 | value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; | |
276 | value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO; | |
277 | WREG32(DCCG_AUDIO_DTO1_CNTL, value); | |
278 | ||
279 | /* Two dtos; generally use dto1 for DP */ | |
280 | value = 0; | |
281 | value |= DCCG_AUDIO_DTO_SEL; | |
282 | ||
283 | if (crtc) | |
284 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); | |
285 | ||
286 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); | |
287 | ||
288 | /* Express [24MHz / target pixel clock] as an exact rational | |
289 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
290 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
291 | */ | |
fe6fc1f1 SG |
292 | if (ASIC_IS_DCE41(rdev)) { |
293 | unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) & | |
294 | DENTIST_DPREFCLK_WDIVIDER_MASK) >> | |
295 | DENTIST_DPREFCLK_WDIVIDER_SHIFT; | |
296 | div = radeon_audio_decode_dfs_div(div); | |
297 | ||
298 | if (div) | |
299 | clock = 100 * clock / div; | |
300 | } | |
301 | ||
a85d682a | 302 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
aeefd07e | 303 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
a85d682a | 304 | } |
b1f6f47e | 305 | |
930a9785 AD |
306 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
307 | { | |
308 | struct drm_device *dev = encoder->dev; | |
309 | struct radeon_device *rdev = dev->dev_private; | |
310 | ||
311 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, | |
312 | HDMI_NULL_SEND | /* send null packets when required */ | |
313 | HDMI_GC_SEND | /* send general control packets */ | |
314 | HDMI_GC_CONT); /* send general control packets every frame */ | |
315 | } | |
316 | ||
be273e58 | 317 | void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) |
e55d3e6c RM |
318 | { |
319 | struct drm_device *dev = encoder->dev; | |
320 | struct radeon_device *rdev = dev->dev_private; | |
79766915 | 321 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
7b555e06 | 322 | uint32_t val; |
e55d3e6c | 323 | |
7b555e06 AD |
324 | val = RREG32(HDMI_CONTROL + offset); |
325 | val &= ~HDMI_DEEP_COLOR_ENABLE; | |
326 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; | |
327 | ||
328 | switch (bpc) { | |
329 | case 0: | |
330 | case 6: | |
331 | case 8: | |
332 | case 16: | |
333 | default: | |
334 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", | |
72082093 | 335 | connector->name, bpc); |
7b555e06 AD |
336 | break; |
337 | case 10: | |
338 | val |= HDMI_DEEP_COLOR_ENABLE; | |
339 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); | |
340 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", | |
72082093 | 341 | connector->name); |
7b555e06 AD |
342 | break; |
343 | case 12: | |
344 | val |= HDMI_DEEP_COLOR_ENABLE; | |
345 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); | |
346 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", | |
72082093 | 347 | connector->name); |
7b555e06 AD |
348 | break; |
349 | } | |
350 | ||
351 | WREG32(HDMI_CONTROL + offset, val); | |
be273e58 SG |
352 | } |
353 | ||
1852c9a0 SG |
354 | void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
355 | { | |
356 | struct drm_device *dev = encoder->dev; | |
357 | struct radeon_device *rdev = dev->dev_private; | |
358 | ||
1852c9a0 SG |
359 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
360 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ | |
361 | ||
1852c9a0 SG |
362 | WREG32(AFMT_60958_0 + offset, |
363 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); | |
364 | ||
365 | WREG32(AFMT_60958_1 + offset, | |
366 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); | |
367 | ||
368 | WREG32(AFMT_60958_2 + offset, | |
369 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | | |
370 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | | |
371 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | | |
372 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | | |
373 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | | |
374 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); | |
375 | ||
376 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, | |
377 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); | |
378 | ||
362ff251 AD |
379 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
380 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ | |
381 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | |
382 | ||
1852c9a0 | 383 | /* allow 60958 channel status and send audio packets fields to be updated */ |
362ff251 AD |
384 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
385 | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); | |
1852c9a0 SG |
386 | } |
387 | ||
3be2e7d0 SG |
388 | |
389 | void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) | |
390 | { | |
391 | struct drm_device *dev = encoder->dev; | |
392 | struct radeon_device *rdev = dev->dev_private; | |
393 | ||
394 | if (mute) | |
395 | WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); | |
396 | else | |
397 | WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); | |
398 | } | |
399 | ||
a973bea1 AD |
400 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
401 | { | |
4adb34ef AD |
402 | struct drm_device *dev = encoder->dev; |
403 | struct radeon_device *rdev = dev->dev_private; | |
a973bea1 AD |
404 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
405 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
406 | ||
c2b4cacf AD |
407 | if (!dig || !dig->afmt) |
408 | return; | |
409 | ||
add7d759 | 410 | if (enable) { |
38aef154 AD |
411 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
412 | ||
fbfd3bc7 | 413 | if (connector && drm_detect_monitor_audio(radeon_connector_edid(connector))) { |
38aef154 AD |
414 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
415 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ | |
416 | HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */ | |
417 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ | |
418 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ | |
419 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, | |
420 | AFMT_AUDIO_SAMPLE_SEND); | |
421 | } else { | |
422 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, | |
423 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ | |
424 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ | |
425 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, | |
426 | ~AFMT_AUDIO_SAMPLE_SEND); | |
427 | } | |
add7d759 | 428 | } else { |
362ff251 AD |
429 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
430 | ~AFMT_AUDIO_SAMPLE_SEND); | |
add7d759 | 431 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); |
4adb34ef AD |
432 | } |
433 | ||
a973bea1 AD |
434 | dig->afmt->enabled = enable; |
435 | ||
436 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", | |
437 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); | |
438 | } | |
e55bca26 | 439 | |
add7d759 | 440 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) |
e55bca26 SG |
441 | { |
442 | struct drm_device *dev = encoder->dev; | |
443 | struct radeon_device *rdev = dev->dev_private; | |
444 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
445 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
38aef154 | 446 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
e55bca26 SG |
447 | |
448 | if (!dig || !dig->afmt) | |
449 | return; | |
450 | ||
fbfd3bc7 AD |
451 | if (enable && connector && |
452 | drm_detect_monitor_audio(radeon_connector_edid(connector))) { | |
e55bca26 SG |
453 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
454 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
455 | struct radeon_connector_atom_dig *dig_connector; | |
456 | uint32_t val; | |
457 | ||
362ff251 AD |
458 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
459 | AFMT_AUDIO_SAMPLE_SEND); | |
460 | ||
add7d759 AD |
461 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
462 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); | |
e55bca26 | 463 | |
12428327 | 464 | if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { |
e55bca26 | 465 | dig_connector = radeon_connector->con_priv; |
add7d759 | 466 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); |
e55bca26 SG |
467 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); |
468 | ||
469 | if (dig_connector->dp_clock == 162000) | |
470 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); | |
471 | else | |
472 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); | |
473 | ||
add7d759 | 474 | WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); |
e55bca26 SG |
475 | } |
476 | ||
add7d759 | 477 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, |
e55bca26 SG |
478 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ |
479 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ | |
480 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ | |
481 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ | |
e55bca26 | 482 | } else { |
add7d759 | 483 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
362ff251 AD |
484 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
485 | ~AFMT_AUDIO_SAMPLE_SEND); | |
e55bca26 SG |
486 | } |
487 | ||
488 | dig->afmt->enabled = enable; | |
489 | } |