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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "radeon_drm.h" | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
e6990375 | 35 | #include "radeon_asic.h" |
3ce0a23d | 36 | #include "r100d.h" |
d4550907 JG |
37 | #include "rs100d.h" |
38 | #include "rv200d.h" | |
39 | #include "rv250d.h" | |
3ce0a23d | 40 | |
70967ab9 BH |
41 | #include <linux/firmware.h> |
42 | #include <linux/platform_device.h> | |
43 | ||
551ebd83 DA |
44 | #include "r100_reg_safe.h" |
45 | #include "rn50_reg_safe.h" | |
46 | ||
70967ab9 BH |
47 | /* Firmware Names */ |
48 | #define FIRMWARE_R100 "radeon/R100_cp.bin" | |
49 | #define FIRMWARE_R200 "radeon/R200_cp.bin" | |
50 | #define FIRMWARE_R300 "radeon/R300_cp.bin" | |
51 | #define FIRMWARE_R420 "radeon/R420_cp.bin" | |
52 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" | |
53 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" | |
54 | #define FIRMWARE_R520 "radeon/R520_cp.bin" | |
55 | ||
56 | MODULE_FIRMWARE(FIRMWARE_R100); | |
57 | MODULE_FIRMWARE(FIRMWARE_R200); | |
58 | MODULE_FIRMWARE(FIRMWARE_R300); | |
59 | MODULE_FIRMWARE(FIRMWARE_R420); | |
60 | MODULE_FIRMWARE(FIRMWARE_RS690); | |
61 | MODULE_FIRMWARE(FIRMWARE_RS600); | |
62 | MODULE_FIRMWARE(FIRMWARE_R520); | |
771fe6b9 | 63 | |
551ebd83 DA |
64 | #include "r100_track.h" |
65 | ||
771fe6b9 JG |
66 | /* This files gather functions specifics to: |
67 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 | |
771fe6b9 | 68 | */ |
771fe6b9 | 69 | |
05a05c50 AD |
70 | /* hpd for digital panel detect/disconnect */ |
71 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
72 | { | |
73 | bool connected = false; | |
74 | ||
75 | switch (hpd) { | |
76 | case RADEON_HPD_1: | |
77 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) | |
78 | connected = true; | |
79 | break; | |
80 | case RADEON_HPD_2: | |
81 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) | |
82 | connected = true; | |
83 | break; | |
84 | default: | |
85 | break; | |
86 | } | |
87 | return connected; | |
88 | } | |
89 | ||
90 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
91 | enum radeon_hpd_id hpd) | |
92 | { | |
93 | u32 tmp; | |
94 | bool connected = r100_hpd_sense(rdev, hpd); | |
95 | ||
96 | switch (hpd) { | |
97 | case RADEON_HPD_1: | |
98 | tmp = RREG32(RADEON_FP_GEN_CNTL); | |
99 | if (connected) | |
100 | tmp &= ~RADEON_FP_DETECT_INT_POL; | |
101 | else | |
102 | tmp |= RADEON_FP_DETECT_INT_POL; | |
103 | WREG32(RADEON_FP_GEN_CNTL, tmp); | |
104 | break; | |
105 | case RADEON_HPD_2: | |
106 | tmp = RREG32(RADEON_FP2_GEN_CNTL); | |
107 | if (connected) | |
108 | tmp &= ~RADEON_FP2_DETECT_INT_POL; | |
109 | else | |
110 | tmp |= RADEON_FP2_DETECT_INT_POL; | |
111 | WREG32(RADEON_FP2_GEN_CNTL, tmp); | |
112 | break; | |
113 | default: | |
114 | break; | |
115 | } | |
116 | } | |
117 | ||
118 | void r100_hpd_init(struct radeon_device *rdev) | |
119 | { | |
120 | struct drm_device *dev = rdev->ddev; | |
121 | struct drm_connector *connector; | |
122 | ||
123 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
124 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
125 | switch (radeon_connector->hpd.hpd) { | |
126 | case RADEON_HPD_1: | |
127 | rdev->irq.hpd[0] = true; | |
128 | break; | |
129 | case RADEON_HPD_2: | |
130 | rdev->irq.hpd[1] = true; | |
131 | break; | |
132 | default: | |
133 | break; | |
134 | } | |
135 | } | |
003e69f9 JG |
136 | if (rdev->irq.installed) |
137 | r100_irq_set(rdev); | |
05a05c50 AD |
138 | } |
139 | ||
140 | void r100_hpd_fini(struct radeon_device *rdev) | |
141 | { | |
142 | struct drm_device *dev = rdev->ddev; | |
143 | struct drm_connector *connector; | |
144 | ||
145 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
146 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
147 | switch (radeon_connector->hpd.hpd) { | |
148 | case RADEON_HPD_1: | |
149 | rdev->irq.hpd[0] = false; | |
150 | break; | |
151 | case RADEON_HPD_2: | |
152 | rdev->irq.hpd[1] = false; | |
153 | break; | |
154 | default: | |
155 | break; | |
156 | } | |
157 | } | |
158 | } | |
159 | ||
771fe6b9 JG |
160 | /* |
161 | * PCI GART | |
162 | */ | |
163 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) | |
164 | { | |
165 | /* TODO: can we do somethings here ? */ | |
166 | /* It seems hw only cache one entry so we should discard this | |
167 | * entry otherwise if first GPU GART read hit this entry it | |
168 | * could end up in wrong address. */ | |
169 | } | |
170 | ||
4aac0473 | 171 | int r100_pci_gart_init(struct radeon_device *rdev) |
771fe6b9 | 172 | { |
771fe6b9 JG |
173 | int r; |
174 | ||
4aac0473 JG |
175 | if (rdev->gart.table.ram.ptr) { |
176 | WARN(1, "R100 PCI GART already initialized.\n"); | |
177 | return 0; | |
178 | } | |
771fe6b9 JG |
179 | /* Initialize common gart structure */ |
180 | r = radeon_gart_init(rdev); | |
4aac0473 | 181 | if (r) |
771fe6b9 | 182 | return r; |
4aac0473 JG |
183 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
184 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; | |
185 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; | |
186 | return radeon_gart_table_ram_alloc(rdev); | |
187 | } | |
188 | ||
17e15b0c DA |
189 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
190 | void r100_enable_bm(struct radeon_device *rdev) | |
191 | { | |
192 | uint32_t tmp; | |
193 | /* Enable bus mastering */ | |
194 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
195 | WREG32(RADEON_BUS_CNTL, tmp); | |
196 | } | |
197 | ||
4aac0473 JG |
198 | int r100_pci_gart_enable(struct radeon_device *rdev) |
199 | { | |
200 | uint32_t tmp; | |
201 | ||
82568565 | 202 | radeon_gart_restore(rdev); |
771fe6b9 JG |
203 | /* discard memory request outside of configured range */ |
204 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
205 | WREG32(RADEON_AIC_CNTL, tmp); | |
206 | /* set address range for PCI address translate */ | |
d594e46a JG |
207 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
208 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); | |
771fe6b9 JG |
209 | /* set PCI GART page-table base address */ |
210 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); | |
211 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; | |
212 | WREG32(RADEON_AIC_CNTL, tmp); | |
213 | r100_pci_gart_tlb_flush(rdev); | |
214 | rdev->gart.ready = true; | |
215 | return 0; | |
216 | } | |
217 | ||
218 | void r100_pci_gart_disable(struct radeon_device *rdev) | |
219 | { | |
220 | uint32_t tmp; | |
221 | ||
222 | /* discard memory request outside of configured range */ | |
223 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
224 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
225 | WREG32(RADEON_AIC_LO_ADDR, 0); | |
226 | WREG32(RADEON_AIC_HI_ADDR, 0); | |
227 | } | |
228 | ||
229 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
230 | { | |
231 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
232 | return -EINVAL; | |
233 | } | |
ed10f95d | 234 | rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); |
771fe6b9 JG |
235 | return 0; |
236 | } | |
237 | ||
4aac0473 | 238 | void r100_pci_gart_fini(struct radeon_device *rdev) |
771fe6b9 | 239 | { |
f9274562 | 240 | radeon_gart_fini(rdev); |
4aac0473 JG |
241 | r100_pci_gart_disable(rdev); |
242 | radeon_gart_table_ram_free(rdev); | |
771fe6b9 JG |
243 | } |
244 | ||
7ed220d7 MD |
245 | int r100_irq_set(struct radeon_device *rdev) |
246 | { | |
247 | uint32_t tmp = 0; | |
248 | ||
003e69f9 JG |
249 | if (!rdev->irq.installed) { |
250 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
251 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
252 | return -EINVAL; | |
253 | } | |
7ed220d7 MD |
254 | if (rdev->irq.sw_int) { |
255 | tmp |= RADEON_SW_INT_ENABLE; | |
256 | } | |
257 | if (rdev->irq.crtc_vblank_int[0]) { | |
258 | tmp |= RADEON_CRTC_VBLANK_MASK; | |
259 | } | |
260 | if (rdev->irq.crtc_vblank_int[1]) { | |
261 | tmp |= RADEON_CRTC2_VBLANK_MASK; | |
262 | } | |
05a05c50 AD |
263 | if (rdev->irq.hpd[0]) { |
264 | tmp |= RADEON_FP_DETECT_MASK; | |
265 | } | |
266 | if (rdev->irq.hpd[1]) { | |
267 | tmp |= RADEON_FP2_DETECT_MASK; | |
268 | } | |
7ed220d7 MD |
269 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
270 | return 0; | |
271 | } | |
272 | ||
9f022ddf JG |
273 | void r100_irq_disable(struct radeon_device *rdev) |
274 | { | |
275 | u32 tmp; | |
276 | ||
277 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
278 | /* Wait and acknowledge irq */ | |
279 | mdelay(1); | |
280 | tmp = RREG32(R_000044_GEN_INT_STATUS); | |
281 | WREG32(R_000044_GEN_INT_STATUS, tmp); | |
282 | } | |
283 | ||
7ed220d7 MD |
284 | static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
285 | { | |
286 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); | |
05a05c50 AD |
287 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
288 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | | |
289 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; | |
7ed220d7 MD |
290 | |
291 | if (irqs) { | |
292 | WREG32(RADEON_GEN_INT_STATUS, irqs); | |
293 | } | |
294 | return irqs & irq_mask; | |
295 | } | |
296 | ||
297 | int r100_irq_process(struct radeon_device *rdev) | |
298 | { | |
3e5cb98d | 299 | uint32_t status, msi_rearm; |
d4877cf2 | 300 | bool queue_hotplug = false; |
7ed220d7 MD |
301 | |
302 | status = r100_irq_ack(rdev); | |
303 | if (!status) { | |
304 | return IRQ_NONE; | |
305 | } | |
a513c184 JG |
306 | if (rdev->shutdown) { |
307 | return IRQ_NONE; | |
308 | } | |
7ed220d7 MD |
309 | while (status) { |
310 | /* SW interrupt */ | |
311 | if (status & RADEON_SW_INT_TEST) { | |
312 | radeon_fence_process(rdev); | |
313 | } | |
314 | /* Vertical blank interrupts */ | |
315 | if (status & RADEON_CRTC_VBLANK_STAT) { | |
316 | drm_handle_vblank(rdev->ddev, 0); | |
839461d3 | 317 | rdev->pm.vblank_sync = true; |
73a6d3fc | 318 | wake_up(&rdev->irq.vblank_queue); |
7ed220d7 MD |
319 | } |
320 | if (status & RADEON_CRTC2_VBLANK_STAT) { | |
321 | drm_handle_vblank(rdev->ddev, 1); | |
839461d3 | 322 | rdev->pm.vblank_sync = true; |
73a6d3fc | 323 | wake_up(&rdev->irq.vblank_queue); |
7ed220d7 | 324 | } |
05a05c50 | 325 | if (status & RADEON_FP_DETECT_STAT) { |
d4877cf2 AD |
326 | queue_hotplug = true; |
327 | DRM_DEBUG("HPD1\n"); | |
05a05c50 AD |
328 | } |
329 | if (status & RADEON_FP2_DETECT_STAT) { | |
d4877cf2 AD |
330 | queue_hotplug = true; |
331 | DRM_DEBUG("HPD2\n"); | |
05a05c50 | 332 | } |
7ed220d7 MD |
333 | status = r100_irq_ack(rdev); |
334 | } | |
d4877cf2 AD |
335 | if (queue_hotplug) |
336 | queue_work(rdev->wq, &rdev->hotplug_work); | |
3e5cb98d AD |
337 | if (rdev->msi_enabled) { |
338 | switch (rdev->family) { | |
339 | case CHIP_RS400: | |
340 | case CHIP_RS480: | |
341 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; | |
342 | WREG32(RADEON_AIC_CNTL, msi_rearm); | |
343 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); | |
344 | break; | |
345 | default: | |
346 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; | |
347 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); | |
348 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); | |
349 | break; | |
350 | } | |
351 | } | |
7ed220d7 MD |
352 | return IRQ_HANDLED; |
353 | } | |
354 | ||
355 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
356 | { | |
357 | if (crtc == 0) | |
358 | return RREG32(RADEON_CRTC_CRNT_FRAME); | |
359 | else | |
360 | return RREG32(RADEON_CRTC2_CRNT_FRAME); | |
361 | } | |
362 | ||
9e5b2af7 PN |
363 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
364 | * for enough space (today caller are ib schedule and buffer move) */ | |
771fe6b9 JG |
365 | void r100_fence_ring_emit(struct radeon_device *rdev, |
366 | struct radeon_fence *fence) | |
367 | { | |
9e5b2af7 PN |
368 | /* We have to make sure that caches are flushed before |
369 | * CPU might read something from VRAM. */ | |
370 | radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); | |
371 | radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); | |
372 | radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); | |
373 | radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); | |
771fe6b9 | 374 | /* Wait until IDLE & CLEAN */ |
4612dc97 AD |
375 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
376 | radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); | |
cafe6609 JG |
377 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
378 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | | |
379 | RADEON_HDP_READ_BUFFER_INVALIDATE); | |
380 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); | |
381 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); | |
771fe6b9 JG |
382 | /* Emit fence sequence & fire IRQ */ |
383 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); | |
384 | radeon_ring_write(rdev, fence->seq); | |
385 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); | |
386 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); | |
387 | } | |
388 | ||
771fe6b9 JG |
389 | int r100_wb_init(struct radeon_device *rdev) |
390 | { | |
391 | int r; | |
392 | ||
393 | if (rdev->wb.wb_obj == NULL) { | |
4c788679 JG |
394 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
395 | RADEON_GEM_DOMAIN_GTT, | |
396 | &rdev->wb.wb_obj); | |
771fe6b9 | 397 | if (r) { |
4c788679 | 398 | dev_err(rdev->dev, "(%d) create WB buffer failed\n", r); |
771fe6b9 JG |
399 | return r; |
400 | } | |
4c788679 JG |
401 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
402 | if (unlikely(r != 0)) | |
403 | return r; | |
404 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, | |
405 | &rdev->wb.gpu_addr); | |
771fe6b9 | 406 | if (r) { |
4c788679 JG |
407 | dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r); |
408 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
771fe6b9 JG |
409 | return r; |
410 | } | |
4c788679 JG |
411 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
412 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
771fe6b9 | 413 | if (r) { |
4c788679 | 414 | dev_err(rdev->dev, "(%d) map WB buffer failed\n", r); |
771fe6b9 JG |
415 | return r; |
416 | } | |
417 | } | |
9f022ddf JG |
418 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); |
419 | WREG32(R_00070C_CP_RB_RPTR_ADDR, | |
420 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); | |
421 | WREG32(R_000770_SCRATCH_UMSK, 0xff); | |
771fe6b9 JG |
422 | return 0; |
423 | } | |
424 | ||
9f022ddf JG |
425 | void r100_wb_disable(struct radeon_device *rdev) |
426 | { | |
427 | WREG32(R_000770_SCRATCH_UMSK, 0); | |
428 | } | |
429 | ||
771fe6b9 JG |
430 | void r100_wb_fini(struct radeon_device *rdev) |
431 | { | |
4c788679 JG |
432 | int r; |
433 | ||
9f022ddf | 434 | r100_wb_disable(rdev); |
771fe6b9 | 435 | if (rdev->wb.wb_obj) { |
4c788679 JG |
436 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
437 | if (unlikely(r != 0)) { | |
438 | dev_err(rdev->dev, "(%d) can't finish WB\n", r); | |
439 | return; | |
440 | } | |
441 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
442 | radeon_bo_unpin(rdev->wb.wb_obj); | |
443 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
444 | radeon_bo_unref(&rdev->wb.wb_obj); | |
771fe6b9 JG |
445 | rdev->wb.wb = NULL; |
446 | rdev->wb.wb_obj = NULL; | |
447 | } | |
448 | } | |
449 | ||
450 | int r100_copy_blit(struct radeon_device *rdev, | |
451 | uint64_t src_offset, | |
452 | uint64_t dst_offset, | |
453 | unsigned num_pages, | |
454 | struct radeon_fence *fence) | |
455 | { | |
456 | uint32_t cur_pages; | |
457 | uint32_t stride_bytes = PAGE_SIZE; | |
458 | uint32_t pitch; | |
459 | uint32_t stride_pixels; | |
460 | unsigned ndw; | |
461 | int num_loops; | |
462 | int r = 0; | |
463 | ||
464 | /* radeon limited to 16k stride */ | |
465 | stride_bytes &= 0x3fff; | |
466 | /* radeon pitch is /64 */ | |
467 | pitch = stride_bytes / 64; | |
468 | stride_pixels = stride_bytes / 4; | |
469 | num_loops = DIV_ROUND_UP(num_pages, 8191); | |
470 | ||
471 | /* Ask for enough room for blit + flush + fence */ | |
472 | ndw = 64 + (10 * num_loops); | |
473 | r = radeon_ring_lock(rdev, ndw); | |
474 | if (r) { | |
475 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); | |
476 | return -EINVAL; | |
477 | } | |
478 | while (num_pages > 0) { | |
479 | cur_pages = num_pages; | |
480 | if (cur_pages > 8191) { | |
481 | cur_pages = 8191; | |
482 | } | |
483 | num_pages -= cur_pages; | |
484 | ||
485 | /* pages are in Y direction - height | |
486 | page width in X direction - width */ | |
487 | radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); | |
488 | radeon_ring_write(rdev, | |
489 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | | |
490 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
491 | RADEON_GMC_SRC_CLIPPING | | |
492 | RADEON_GMC_DST_CLIPPING | | |
493 | RADEON_GMC_BRUSH_NONE | | |
494 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | | |
495 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
496 | RADEON_ROP3_S | | |
497 | RADEON_DP_SRC_SOURCE_MEMORY | | |
498 | RADEON_GMC_CLR_CMP_CNTL_DIS | | |
499 | RADEON_GMC_WR_MSK_DIS); | |
500 | radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); | |
501 | radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); | |
502 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); | |
503 | radeon_ring_write(rdev, 0); | |
504 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); | |
505 | radeon_ring_write(rdev, num_pages); | |
506 | radeon_ring_write(rdev, num_pages); | |
507 | radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); | |
508 | } | |
509 | radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); | |
510 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); | |
511 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
512 | radeon_ring_write(rdev, | |
513 | RADEON_WAIT_2D_IDLECLEAN | | |
514 | RADEON_WAIT_HOST_IDLECLEAN | | |
515 | RADEON_WAIT_DMA_GUI_IDLE); | |
516 | if (fence) { | |
517 | r = radeon_fence_emit(rdev, fence); | |
518 | } | |
519 | radeon_ring_unlock_commit(rdev); | |
520 | return r; | |
521 | } | |
522 | ||
45600232 JG |
523 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
524 | { | |
525 | unsigned i; | |
526 | u32 tmp; | |
527 | ||
528 | for (i = 0; i < rdev->usec_timeout; i++) { | |
529 | tmp = RREG32(R_000E40_RBBM_STATUS); | |
530 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { | |
531 | return 0; | |
532 | } | |
533 | udelay(1); | |
534 | } | |
535 | return -1; | |
536 | } | |
537 | ||
771fe6b9 JG |
538 | void r100_ring_start(struct radeon_device *rdev) |
539 | { | |
540 | int r; | |
541 | ||
542 | r = radeon_ring_lock(rdev, 2); | |
543 | if (r) { | |
544 | return; | |
545 | } | |
546 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); | |
547 | radeon_ring_write(rdev, | |
548 | RADEON_ISYNC_ANY2D_IDLE3D | | |
549 | RADEON_ISYNC_ANY3D_IDLE2D | | |
550 | RADEON_ISYNC_WAIT_IDLEGUI | | |
551 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
552 | radeon_ring_unlock_commit(rdev); | |
553 | } | |
554 | ||
70967ab9 BH |
555 | |
556 | /* Load the microcode for the CP */ | |
557 | static int r100_cp_init_microcode(struct radeon_device *rdev) | |
771fe6b9 | 558 | { |
70967ab9 BH |
559 | struct platform_device *pdev; |
560 | const char *fw_name = NULL; | |
561 | int err; | |
771fe6b9 | 562 | |
70967ab9 | 563 | DRM_DEBUG("\n"); |
771fe6b9 | 564 | |
70967ab9 BH |
565 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
566 | err = IS_ERR(pdev); | |
567 | if (err) { | |
568 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
569 | return -EINVAL; | |
570 | } | |
771fe6b9 JG |
571 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
572 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || | |
573 | (rdev->family == CHIP_RS200)) { | |
574 | DRM_INFO("Loading R100 Microcode\n"); | |
70967ab9 | 575 | fw_name = FIRMWARE_R100; |
771fe6b9 JG |
576 | } else if ((rdev->family == CHIP_R200) || |
577 | (rdev->family == CHIP_RV250) || | |
578 | (rdev->family == CHIP_RV280) || | |
579 | (rdev->family == CHIP_RS300)) { | |
580 | DRM_INFO("Loading R200 Microcode\n"); | |
70967ab9 | 581 | fw_name = FIRMWARE_R200; |
771fe6b9 JG |
582 | } else if ((rdev->family == CHIP_R300) || |
583 | (rdev->family == CHIP_R350) || | |
584 | (rdev->family == CHIP_RV350) || | |
585 | (rdev->family == CHIP_RV380) || | |
586 | (rdev->family == CHIP_RS400) || | |
587 | (rdev->family == CHIP_RS480)) { | |
588 | DRM_INFO("Loading R300 Microcode\n"); | |
70967ab9 | 589 | fw_name = FIRMWARE_R300; |
771fe6b9 JG |
590 | } else if ((rdev->family == CHIP_R420) || |
591 | (rdev->family == CHIP_R423) || | |
592 | (rdev->family == CHIP_RV410)) { | |
593 | DRM_INFO("Loading R400 Microcode\n"); | |
70967ab9 | 594 | fw_name = FIRMWARE_R420; |
771fe6b9 JG |
595 | } else if ((rdev->family == CHIP_RS690) || |
596 | (rdev->family == CHIP_RS740)) { | |
597 | DRM_INFO("Loading RS690/RS740 Microcode\n"); | |
70967ab9 | 598 | fw_name = FIRMWARE_RS690; |
771fe6b9 JG |
599 | } else if (rdev->family == CHIP_RS600) { |
600 | DRM_INFO("Loading RS600 Microcode\n"); | |
70967ab9 | 601 | fw_name = FIRMWARE_RS600; |
771fe6b9 JG |
602 | } else if ((rdev->family == CHIP_RV515) || |
603 | (rdev->family == CHIP_R520) || | |
604 | (rdev->family == CHIP_RV530) || | |
605 | (rdev->family == CHIP_R580) || | |
606 | (rdev->family == CHIP_RV560) || | |
607 | (rdev->family == CHIP_RV570)) { | |
608 | DRM_INFO("Loading R500 Microcode\n"); | |
70967ab9 BH |
609 | fw_name = FIRMWARE_R520; |
610 | } | |
611 | ||
3ce0a23d | 612 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
70967ab9 BH |
613 | platform_device_unregister(pdev); |
614 | if (err) { | |
615 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", | |
616 | fw_name); | |
3ce0a23d | 617 | } else if (rdev->me_fw->size % 8) { |
70967ab9 BH |
618 | printk(KERN_ERR |
619 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", | |
3ce0a23d | 620 | rdev->me_fw->size, fw_name); |
70967ab9 | 621 | err = -EINVAL; |
3ce0a23d JG |
622 | release_firmware(rdev->me_fw); |
623 | rdev->me_fw = NULL; | |
70967ab9 BH |
624 | } |
625 | return err; | |
626 | } | |
d4550907 | 627 | |
70967ab9 BH |
628 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
629 | { | |
630 | const __be32 *fw_data; | |
631 | int i, size; | |
632 | ||
633 | if (r100_gui_wait_for_idle(rdev)) { | |
634 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
635 | "programming pipes. Bad things might happen.\n"); | |
636 | } | |
637 | ||
3ce0a23d JG |
638 | if (rdev->me_fw) { |
639 | size = rdev->me_fw->size / 4; | |
640 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; | |
70967ab9 BH |
641 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
642 | for (i = 0; i < size; i += 2) { | |
643 | WREG32(RADEON_CP_ME_RAM_DATAH, | |
644 | be32_to_cpup(&fw_data[i])); | |
645 | WREG32(RADEON_CP_ME_RAM_DATAL, | |
646 | be32_to_cpup(&fw_data[i + 1])); | |
771fe6b9 JG |
647 | } |
648 | } | |
649 | } | |
650 | ||
651 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |
652 | { | |
653 | unsigned rb_bufsz; | |
654 | unsigned rb_blksz; | |
655 | unsigned max_fetch; | |
656 | unsigned pre_write_timer; | |
657 | unsigned pre_write_limit; | |
658 | unsigned indirect2_start; | |
659 | unsigned indirect1_start; | |
660 | uint32_t tmp; | |
661 | int r; | |
662 | ||
663 | if (r100_debugfs_cp_init(rdev)) { | |
664 | DRM_ERROR("Failed to register debugfs file for CP !\n"); | |
665 | } | |
3ce0a23d | 666 | if (!rdev->me_fw) { |
70967ab9 BH |
667 | r = r100_cp_init_microcode(rdev); |
668 | if (r) { | |
669 | DRM_ERROR("Failed to load firmware!\n"); | |
670 | return r; | |
671 | } | |
672 | } | |
673 | ||
771fe6b9 JG |
674 | /* Align ring size */ |
675 | rb_bufsz = drm_order(ring_size / 8); | |
676 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
677 | r100_cp_load_microcode(rdev); | |
678 | r = radeon_ring_init(rdev, ring_size); | |
679 | if (r) { | |
680 | return r; | |
681 | } | |
682 | /* Each time the cp read 1024 bytes (16 dword/quadword) update | |
683 | * the rptr copy in system ram */ | |
684 | rb_blksz = 9; | |
685 | /* cp will read 128bytes at a time (4 dwords) */ | |
686 | max_fetch = 1; | |
687 | rdev->cp.align_mask = 16 - 1; | |
688 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ | |
689 | pre_write_timer = 64; | |
690 | /* Force CP_RB_WPTR write if written more than one time before the | |
691 | * delay expire | |
692 | */ | |
693 | pre_write_limit = 0; | |
694 | /* Setup the cp cache like this (cache size is 96 dwords) : | |
695 | * RING 0 to 15 | |
696 | * INDIRECT1 16 to 79 | |
697 | * INDIRECT2 80 to 95 | |
698 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
699 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) | |
700 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
701 | * Idea being that most of the gpu cmd will be through indirect1 buffer | |
702 | * so it gets the bigger cache. | |
703 | */ | |
704 | indirect2_start = 80; | |
705 | indirect1_start = 16; | |
706 | /* cp setup */ | |
707 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); | |
d6f28938 | 708 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
771fe6b9 JG |
709 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
710 | REG_SET(RADEON_MAX_FETCH, max_fetch) | | |
711 | RADEON_RB_NO_UPDATE); | |
d6f28938 AD |
712 | #ifdef __BIG_ENDIAN |
713 | tmp |= RADEON_BUF_SWAP_32BIT; | |
714 | #endif | |
715 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
716 | ||
771fe6b9 JG |
717 | /* Set ring address */ |
718 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); | |
719 | WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); | |
720 | /* Force read & write ptr to 0 */ | |
771fe6b9 JG |
721 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
722 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
723 | WREG32(RADEON_CP_RB_WPTR, 0); | |
724 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
725 | udelay(10); | |
726 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); | |
727 | rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); | |
9e5786bd DA |
728 | /* protect against crazy HW on resume */ |
729 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
771fe6b9 JG |
730 | /* Set cp mode to bus mastering & enable cp*/ |
731 | WREG32(RADEON_CP_CSQ_MODE, | |
732 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | | |
733 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); | |
734 | WREG32(0x718, 0); | |
735 | WREG32(0x744, 0x00004D4D); | |
736 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); | |
737 | radeon_ring_start(rdev); | |
738 | r = radeon_ring_test(rdev); | |
739 | if (r) { | |
740 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); | |
741 | return r; | |
742 | } | |
743 | rdev->cp.ready = true; | |
744 | return 0; | |
745 | } | |
746 | ||
747 | void r100_cp_fini(struct radeon_device *rdev) | |
748 | { | |
45600232 JG |
749 | if (r100_cp_wait_for_idle(rdev)) { |
750 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); | |
751 | } | |
771fe6b9 | 752 | /* Disable ring */ |
a18d7ea1 | 753 | r100_cp_disable(rdev); |
771fe6b9 JG |
754 | radeon_ring_fini(rdev); |
755 | DRM_INFO("radeon: cp finalized\n"); | |
756 | } | |
757 | ||
758 | void r100_cp_disable(struct radeon_device *rdev) | |
759 | { | |
760 | /* Disable ring */ | |
761 | rdev->cp.ready = false; | |
762 | WREG32(RADEON_CP_CSQ_MODE, 0); | |
763 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
764 | if (r100_gui_wait_for_idle(rdev)) { | |
765 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
766 | "programming pipes. Bad things might happen.\n"); | |
767 | } | |
768 | } | |
769 | ||
3ce0a23d JG |
770 | void r100_cp_commit(struct radeon_device *rdev) |
771 | { | |
772 | WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); | |
773 | (void)RREG32(RADEON_CP_RB_WPTR); | |
774 | } | |
775 | ||
771fe6b9 JG |
776 | |
777 | /* | |
778 | * CS functions | |
779 | */ | |
780 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
781 | struct radeon_cs_packet *pkt, | |
068a117c | 782 | const unsigned *auth, unsigned n, |
771fe6b9 JG |
783 | radeon_packet0_check_t check) |
784 | { | |
785 | unsigned reg; | |
786 | unsigned i, j, m; | |
787 | unsigned idx; | |
788 | int r; | |
789 | ||
790 | idx = pkt->idx + 1; | |
791 | reg = pkt->reg; | |
068a117c JG |
792 | /* Check that register fall into register range |
793 | * determined by the number of entry (n) in the | |
794 | * safe register bitmap. | |
795 | */ | |
771fe6b9 JG |
796 | if (pkt->one_reg_wr) { |
797 | if ((reg >> 7) > n) { | |
798 | return -EINVAL; | |
799 | } | |
800 | } else { | |
801 | if (((reg + (pkt->count << 2)) >> 7) > n) { | |
802 | return -EINVAL; | |
803 | } | |
804 | } | |
805 | for (i = 0; i <= pkt->count; i++, idx++) { | |
806 | j = (reg >> 7); | |
807 | m = 1 << ((reg >> 2) & 31); | |
808 | if (auth[j] & m) { | |
809 | r = check(p, pkt, idx, reg); | |
810 | if (r) { | |
811 | return r; | |
812 | } | |
813 | } | |
814 | if (pkt->one_reg_wr) { | |
815 | if (!(auth[j] & m)) { | |
816 | break; | |
817 | } | |
818 | } else { | |
819 | reg += 4; | |
820 | } | |
821 | } | |
822 | return 0; | |
823 | } | |
824 | ||
771fe6b9 JG |
825 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
826 | struct radeon_cs_packet *pkt) | |
827 | { | |
771fe6b9 JG |
828 | volatile uint32_t *ib; |
829 | unsigned i; | |
830 | unsigned idx; | |
831 | ||
832 | ib = p->ib->ptr; | |
771fe6b9 JG |
833 | idx = pkt->idx; |
834 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { | |
835 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | |
836 | } | |
837 | } | |
838 | ||
839 | /** | |
840 | * r100_cs_packet_parse() - parse cp packet and point ib index to next packet | |
841 | * @parser: parser structure holding parsing context. | |
842 | * @pkt: where to store packet informations | |
843 | * | |
844 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
845 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
846 | **/ | |
847 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
848 | struct radeon_cs_packet *pkt, | |
849 | unsigned idx) | |
850 | { | |
851 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
fa99239c | 852 | uint32_t header; |
771fe6b9 JG |
853 | |
854 | if (idx >= ib_chunk->length_dw) { | |
855 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
856 | idx, ib_chunk->length_dw); | |
857 | return -EINVAL; | |
858 | } | |
513bcb46 | 859 | header = radeon_get_ib_value(p, idx); |
771fe6b9 JG |
860 | pkt->idx = idx; |
861 | pkt->type = CP_PACKET_GET_TYPE(header); | |
862 | pkt->count = CP_PACKET_GET_COUNT(header); | |
863 | switch (pkt->type) { | |
864 | case PACKET_TYPE0: | |
865 | pkt->reg = CP_PACKET0_GET_REG(header); | |
866 | pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); | |
867 | break; | |
868 | case PACKET_TYPE3: | |
869 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); | |
870 | break; | |
871 | case PACKET_TYPE2: | |
872 | pkt->count = -1; | |
873 | break; | |
874 | default: | |
875 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
876 | return -EINVAL; | |
877 | } | |
878 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
879 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
880 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
881 | return -EINVAL; | |
882 | } | |
883 | return 0; | |
884 | } | |
885 | ||
531369e6 DA |
886 | /** |
887 | * r100_cs_packet_next_vline() - parse userspace VLINE packet | |
888 | * @parser: parser structure holding parsing context. | |
889 | * | |
890 | * Userspace sends a special sequence for VLINE waits. | |
891 | * PACKET0 - VLINE_START_END + value | |
892 | * PACKET0 - WAIT_UNTIL +_value | |
893 | * RELOC (P3) - crtc_id in reloc. | |
894 | * | |
895 | * This function parses this and relocates the VLINE START END | |
896 | * and WAIT UNTIL packets to the correct crtc. | |
897 | * It also detects a switched off crtc and nulls out the | |
898 | * wait in that case. | |
899 | */ | |
900 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |
901 | { | |
531369e6 DA |
902 | struct drm_mode_object *obj; |
903 | struct drm_crtc *crtc; | |
904 | struct radeon_crtc *radeon_crtc; | |
905 | struct radeon_cs_packet p3reloc, waitreloc; | |
906 | int crtc_id; | |
907 | int r; | |
908 | uint32_t header, h_idx, reg; | |
513bcb46 | 909 | volatile uint32_t *ib; |
531369e6 | 910 | |
513bcb46 | 911 | ib = p->ib->ptr; |
531369e6 DA |
912 | |
913 | /* parse the wait until */ | |
914 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); | |
915 | if (r) | |
916 | return r; | |
917 | ||
918 | /* check its a wait until and only 1 count */ | |
919 | if (waitreloc.reg != RADEON_WAIT_UNTIL || | |
920 | waitreloc.count != 0) { | |
921 | DRM_ERROR("vline wait had illegal wait until segment\n"); | |
922 | r = -EINVAL; | |
923 | return r; | |
924 | } | |
925 | ||
513bcb46 | 926 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
531369e6 DA |
927 | DRM_ERROR("vline wait had illegal wait until\n"); |
928 | r = -EINVAL; | |
929 | return r; | |
930 | } | |
931 | ||
932 | /* jump over the NOP */ | |
90ebd065 | 933 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
531369e6 DA |
934 | if (r) |
935 | return r; | |
936 | ||
937 | h_idx = p->idx - 2; | |
90ebd065 AD |
938 | p->idx += waitreloc.count + 2; |
939 | p->idx += p3reloc.count + 2; | |
531369e6 | 940 | |
513bcb46 DA |
941 | header = radeon_get_ib_value(p, h_idx); |
942 | crtc_id = radeon_get_ib_value(p, h_idx + 5); | |
d4ac6a05 | 943 | reg = CP_PACKET0_GET_REG(header); |
531369e6 DA |
944 | mutex_lock(&p->rdev->ddev->mode_config.mutex); |
945 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); | |
946 | if (!obj) { | |
947 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | |
948 | r = -EINVAL; | |
949 | goto out; | |
950 | } | |
951 | crtc = obj_to_crtc(obj); | |
952 | radeon_crtc = to_radeon_crtc(crtc); | |
953 | crtc_id = radeon_crtc->crtc_id; | |
954 | ||
955 | if (!crtc->enabled) { | |
956 | /* if the CRTC isn't enabled - we need to nop out the wait until */ | |
513bcb46 DA |
957 | ib[h_idx + 2] = PACKET2(0); |
958 | ib[h_idx + 3] = PACKET2(0); | |
531369e6 DA |
959 | } else if (crtc_id == 1) { |
960 | switch (reg) { | |
961 | case AVIVO_D1MODE_VLINE_START_END: | |
90ebd065 | 962 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
963 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
964 | break; | |
965 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
90ebd065 | 966 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
967 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
968 | break; | |
969 | default: | |
970 | DRM_ERROR("unknown crtc reloc\n"); | |
971 | r = -EINVAL; | |
972 | goto out; | |
973 | } | |
513bcb46 DA |
974 | ib[h_idx] = header; |
975 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; | |
531369e6 DA |
976 | } |
977 | out: | |
978 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); | |
979 | return r; | |
980 | } | |
981 | ||
771fe6b9 JG |
982 | /** |
983 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 | |
984 | * @parser: parser structure holding parsing context. | |
985 | * @data: pointer to relocation data | |
986 | * @offset_start: starting offset | |
987 | * @offset_mask: offset mask (to align start offset on) | |
988 | * @reloc: reloc informations | |
989 | * | |
990 | * Check next packet is relocation packet3, do bo validation and compute | |
991 | * GPU offset using the provided start. | |
992 | **/ | |
993 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
994 | struct radeon_cs_reloc **cs_reloc) | |
995 | { | |
771fe6b9 JG |
996 | struct radeon_cs_chunk *relocs_chunk; |
997 | struct radeon_cs_packet p3reloc; | |
998 | unsigned idx; | |
999 | int r; | |
1000 | ||
1001 | if (p->chunk_relocs_idx == -1) { | |
1002 | DRM_ERROR("No relocation chunk !\n"); | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | *cs_reloc = NULL; | |
771fe6b9 JG |
1006 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
1007 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); | |
1008 | if (r) { | |
1009 | return r; | |
1010 | } | |
1011 | p->idx += p3reloc.count + 2; | |
1012 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { | |
1013 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
1014 | p3reloc.idx); | |
1015 | r100_cs_dump_packet(p, &p3reloc); | |
1016 | return -EINVAL; | |
1017 | } | |
513bcb46 | 1018 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
771fe6b9 JG |
1019 | if (idx >= relocs_chunk->length_dw) { |
1020 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
1021 | idx, relocs_chunk->length_dw); | |
1022 | r100_cs_dump_packet(p, &p3reloc); | |
1023 | return -EINVAL; | |
1024 | } | |
1025 | /* FIXME: we assume reloc size is 4 dwords */ | |
1026 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | |
1027 | return 0; | |
1028 | } | |
1029 | ||
551ebd83 DA |
1030 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
1031 | { | |
1032 | int vtx_size; | |
1033 | vtx_size = 2; | |
1034 | /* ordered according to bits in spec */ | |
1035 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) | |
1036 | vtx_size++; | |
1037 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) | |
1038 | vtx_size += 3; | |
1039 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) | |
1040 | vtx_size++; | |
1041 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) | |
1042 | vtx_size++; | |
1043 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) | |
1044 | vtx_size += 3; | |
1045 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) | |
1046 | vtx_size++; | |
1047 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) | |
1048 | vtx_size++; | |
1049 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) | |
1050 | vtx_size += 2; | |
1051 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) | |
1052 | vtx_size += 2; | |
1053 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) | |
1054 | vtx_size++; | |
1055 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) | |
1056 | vtx_size += 2; | |
1057 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) | |
1058 | vtx_size++; | |
1059 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) | |
1060 | vtx_size += 2; | |
1061 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) | |
1062 | vtx_size++; | |
1063 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) | |
1064 | vtx_size++; | |
1065 | /* blend weight */ | |
1066 | if (vtx_fmt & (0x7 << 15)) | |
1067 | vtx_size += (vtx_fmt >> 15) & 0x7; | |
1068 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) | |
1069 | vtx_size += 3; | |
1070 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) | |
1071 | vtx_size += 2; | |
1072 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) | |
1073 | vtx_size++; | |
1074 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) | |
1075 | vtx_size++; | |
1076 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) | |
1077 | vtx_size++; | |
1078 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) | |
1079 | vtx_size++; | |
1080 | return vtx_size; | |
1081 | } | |
1082 | ||
771fe6b9 | 1083 | static int r100_packet0_check(struct radeon_cs_parser *p, |
551ebd83 DA |
1084 | struct radeon_cs_packet *pkt, |
1085 | unsigned idx, unsigned reg) | |
771fe6b9 | 1086 | { |
771fe6b9 | 1087 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1088 | struct r100_cs_track *track; |
771fe6b9 JG |
1089 | volatile uint32_t *ib; |
1090 | uint32_t tmp; | |
771fe6b9 | 1091 | int r; |
551ebd83 | 1092 | int i, face; |
e024e110 | 1093 | u32 tile_flags = 0; |
513bcb46 | 1094 | u32 idx_value; |
771fe6b9 JG |
1095 | |
1096 | ib = p->ib->ptr; | |
551ebd83 DA |
1097 | track = (struct r100_cs_track *)p->track; |
1098 | ||
513bcb46 DA |
1099 | idx_value = radeon_get_ib_value(p, idx); |
1100 | ||
551ebd83 DA |
1101 | switch (reg) { |
1102 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
1103 | r = r100_cs_packet_parse_vline(p); | |
1104 | if (r) { | |
1105 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1106 | idx, reg); | |
1107 | r100_cs_dump_packet(p, pkt); | |
1108 | return r; | |
1109 | } | |
1110 | break; | |
771fe6b9 JG |
1111 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1112 | * range access */ | |
551ebd83 DA |
1113 | case RADEON_DST_PITCH_OFFSET: |
1114 | case RADEON_SRC_PITCH_OFFSET: | |
1115 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); | |
1116 | if (r) | |
1117 | return r; | |
1118 | break; | |
1119 | case RADEON_RB3D_DEPTHOFFSET: | |
1120 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1121 | if (r) { | |
1122 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1123 | idx, reg); | |
1124 | r100_cs_dump_packet(p, pkt); | |
1125 | return r; | |
1126 | } | |
1127 | track->zb.robj = reloc->robj; | |
513bcb46 DA |
1128 | track->zb.offset = idx_value; |
1129 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1130 | break; |
1131 | case RADEON_RB3D_COLOROFFSET: | |
1132 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1133 | if (r) { | |
1134 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1135 | idx, reg); | |
1136 | r100_cs_dump_packet(p, pkt); | |
1137 | return r; | |
1138 | } | |
1139 | track->cb[0].robj = reloc->robj; | |
513bcb46 DA |
1140 | track->cb[0].offset = idx_value; |
1141 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1142 | break; |
1143 | case RADEON_PP_TXOFFSET_0: | |
1144 | case RADEON_PP_TXOFFSET_1: | |
1145 | case RADEON_PP_TXOFFSET_2: | |
1146 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; | |
1147 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1148 | if (r) { | |
1149 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1150 | idx, reg); | |
1151 | r100_cs_dump_packet(p, pkt); | |
1152 | return r; | |
1153 | } | |
513bcb46 | 1154 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
551ebd83 DA |
1155 | track->textures[i].robj = reloc->robj; |
1156 | break; | |
1157 | case RADEON_PP_CUBIC_OFFSET_T0_0: | |
1158 | case RADEON_PP_CUBIC_OFFSET_T0_1: | |
1159 | case RADEON_PP_CUBIC_OFFSET_T0_2: | |
1160 | case RADEON_PP_CUBIC_OFFSET_T0_3: | |
1161 | case RADEON_PP_CUBIC_OFFSET_T0_4: | |
1162 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; | |
1163 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1164 | if (r) { | |
1165 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1166 | idx, reg); | |
1167 | r100_cs_dump_packet(p, pkt); | |
1168 | return r; | |
1169 | } | |
513bcb46 DA |
1170 | track->textures[0].cube_info[i].offset = idx_value; |
1171 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1172 | track->textures[0].cube_info[i].robj = reloc->robj; |
1173 | break; | |
1174 | case RADEON_PP_CUBIC_OFFSET_T1_0: | |
1175 | case RADEON_PP_CUBIC_OFFSET_T1_1: | |
1176 | case RADEON_PP_CUBIC_OFFSET_T1_2: | |
1177 | case RADEON_PP_CUBIC_OFFSET_T1_3: | |
1178 | case RADEON_PP_CUBIC_OFFSET_T1_4: | |
1179 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; | |
1180 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1181 | if (r) { | |
1182 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1183 | idx, reg); | |
1184 | r100_cs_dump_packet(p, pkt); | |
1185 | return r; | |
1186 | } | |
513bcb46 DA |
1187 | track->textures[1].cube_info[i].offset = idx_value; |
1188 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1189 | track->textures[1].cube_info[i].robj = reloc->robj; |
1190 | break; | |
1191 | case RADEON_PP_CUBIC_OFFSET_T2_0: | |
1192 | case RADEON_PP_CUBIC_OFFSET_T2_1: | |
1193 | case RADEON_PP_CUBIC_OFFSET_T2_2: | |
1194 | case RADEON_PP_CUBIC_OFFSET_T2_3: | |
1195 | case RADEON_PP_CUBIC_OFFSET_T2_4: | |
1196 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; | |
1197 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1198 | if (r) { | |
1199 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1200 | idx, reg); | |
1201 | r100_cs_dump_packet(p, pkt); | |
1202 | return r; | |
1203 | } | |
513bcb46 DA |
1204 | track->textures[2].cube_info[i].offset = idx_value; |
1205 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1206 | track->textures[2].cube_info[i].robj = reloc->robj; |
1207 | break; | |
1208 | case RADEON_RE_WIDTH_HEIGHT: | |
513bcb46 | 1209 | track->maxy = ((idx_value >> 16) & 0x7FF); |
551ebd83 DA |
1210 | break; |
1211 | case RADEON_RB3D_COLORPITCH: | |
1212 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1213 | if (r) { | |
1214 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1215 | idx, reg); | |
1216 | r100_cs_dump_packet(p, pkt); | |
1217 | return r; | |
1218 | } | |
e024e110 | 1219 | |
551ebd83 DA |
1220 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
1221 | tile_flags |= RADEON_COLOR_TILE_ENABLE; | |
1222 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
1223 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | |
e024e110 | 1224 | |
513bcb46 | 1225 | tmp = idx_value & ~(0x7 << 16); |
551ebd83 DA |
1226 | tmp |= tile_flags; |
1227 | ib[idx] = tmp; | |
e024e110 | 1228 | |
513bcb46 | 1229 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
551ebd83 DA |
1230 | break; |
1231 | case RADEON_RB3D_DEPTHPITCH: | |
513bcb46 | 1232 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
551ebd83 DA |
1233 | break; |
1234 | case RADEON_RB3D_CNTL: | |
513bcb46 | 1235 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
551ebd83 DA |
1236 | case 7: |
1237 | case 8: | |
1238 | case 9: | |
1239 | case 11: | |
1240 | case 12: | |
1241 | track->cb[0].cpp = 1; | |
e024e110 | 1242 | break; |
551ebd83 DA |
1243 | case 3: |
1244 | case 4: | |
1245 | case 15: | |
1246 | track->cb[0].cpp = 2; | |
1247 | break; | |
1248 | case 6: | |
1249 | track->cb[0].cpp = 4; | |
1250 | break; | |
1251 | default: | |
1252 | DRM_ERROR("Invalid color buffer format (%d) !\n", | |
513bcb46 | 1253 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
551ebd83 DA |
1254 | return -EINVAL; |
1255 | } | |
513bcb46 | 1256 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
551ebd83 DA |
1257 | break; |
1258 | case RADEON_RB3D_ZSTENCILCNTL: | |
513bcb46 | 1259 | switch (idx_value & 0xf) { |
551ebd83 DA |
1260 | case 0: |
1261 | track->zb.cpp = 2; | |
1262 | break; | |
1263 | case 2: | |
1264 | case 3: | |
1265 | case 4: | |
1266 | case 5: | |
1267 | case 9: | |
1268 | case 11: | |
1269 | track->zb.cpp = 4; | |
17782d99 | 1270 | break; |
771fe6b9 | 1271 | default: |
771fe6b9 JG |
1272 | break; |
1273 | } | |
551ebd83 DA |
1274 | break; |
1275 | case RADEON_RB3D_ZPASS_ADDR: | |
1276 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1277 | if (r) { | |
1278 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1279 | idx, reg); | |
1280 | r100_cs_dump_packet(p, pkt); | |
1281 | return r; | |
1282 | } | |
513bcb46 | 1283 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
551ebd83 DA |
1284 | break; |
1285 | case RADEON_PP_CNTL: | |
1286 | { | |
513bcb46 | 1287 | uint32_t temp = idx_value >> 4; |
551ebd83 DA |
1288 | for (i = 0; i < track->num_texture; i++) |
1289 | track->textures[i].enabled = !!(temp & (1 << i)); | |
1290 | } | |
1291 | break; | |
1292 | case RADEON_SE_VF_CNTL: | |
513bcb46 | 1293 | track->vap_vf_cntl = idx_value; |
551ebd83 DA |
1294 | break; |
1295 | case RADEON_SE_VTX_FMT: | |
513bcb46 | 1296 | track->vtx_size = r100_get_vtx_size(idx_value); |
551ebd83 DA |
1297 | break; |
1298 | case RADEON_PP_TEX_SIZE_0: | |
1299 | case RADEON_PP_TEX_SIZE_1: | |
1300 | case RADEON_PP_TEX_SIZE_2: | |
1301 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; | |
513bcb46 DA |
1302 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1303 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | |
551ebd83 DA |
1304 | break; |
1305 | case RADEON_PP_TEX_PITCH_0: | |
1306 | case RADEON_PP_TEX_PITCH_1: | |
1307 | case RADEON_PP_TEX_PITCH_2: | |
1308 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; | |
513bcb46 | 1309 | track->textures[i].pitch = idx_value + 32; |
551ebd83 DA |
1310 | break; |
1311 | case RADEON_PP_TXFILTER_0: | |
1312 | case RADEON_PP_TXFILTER_1: | |
1313 | case RADEON_PP_TXFILTER_2: | |
1314 | i = (reg - RADEON_PP_TXFILTER_0) / 24; | |
513bcb46 | 1315 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
551ebd83 | 1316 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
513bcb46 | 1317 | tmp = (idx_value >> 23) & 0x7; |
551ebd83 DA |
1318 | if (tmp == 2 || tmp == 6) |
1319 | track->textures[i].roundup_w = false; | |
513bcb46 | 1320 | tmp = (idx_value >> 27) & 0x7; |
551ebd83 DA |
1321 | if (tmp == 2 || tmp == 6) |
1322 | track->textures[i].roundup_h = false; | |
1323 | break; | |
1324 | case RADEON_PP_TXFORMAT_0: | |
1325 | case RADEON_PP_TXFORMAT_1: | |
1326 | case RADEON_PP_TXFORMAT_2: | |
1327 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; | |
513bcb46 | 1328 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
551ebd83 DA |
1329 | track->textures[i].use_pitch = 1; |
1330 | } else { | |
1331 | track->textures[i].use_pitch = 0; | |
513bcb46 DA |
1332 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1333 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); | |
551ebd83 | 1334 | } |
513bcb46 | 1335 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
551ebd83 | 1336 | track->textures[i].tex_coord_type = 2; |
513bcb46 | 1337 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
551ebd83 DA |
1338 | case RADEON_TXFORMAT_I8: |
1339 | case RADEON_TXFORMAT_RGB332: | |
1340 | case RADEON_TXFORMAT_Y8: | |
1341 | track->textures[i].cpp = 1; | |
1342 | break; | |
1343 | case RADEON_TXFORMAT_AI88: | |
1344 | case RADEON_TXFORMAT_ARGB1555: | |
1345 | case RADEON_TXFORMAT_RGB565: | |
1346 | case RADEON_TXFORMAT_ARGB4444: | |
1347 | case RADEON_TXFORMAT_VYUY422: | |
1348 | case RADEON_TXFORMAT_YVYU422: | |
551ebd83 DA |
1349 | case RADEON_TXFORMAT_SHADOW16: |
1350 | case RADEON_TXFORMAT_LDUDV655: | |
1351 | case RADEON_TXFORMAT_DUDV88: | |
1352 | track->textures[i].cpp = 2; | |
771fe6b9 | 1353 | break; |
551ebd83 DA |
1354 | case RADEON_TXFORMAT_ARGB8888: |
1355 | case RADEON_TXFORMAT_RGBA8888: | |
551ebd83 DA |
1356 | case RADEON_TXFORMAT_SHADOW32: |
1357 | case RADEON_TXFORMAT_LDUDUV8888: | |
1358 | track->textures[i].cpp = 4; | |
1359 | break; | |
d785d78b DA |
1360 | case RADEON_TXFORMAT_DXT1: |
1361 | track->textures[i].cpp = 1; | |
1362 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | |
1363 | break; | |
1364 | case RADEON_TXFORMAT_DXT23: | |
1365 | case RADEON_TXFORMAT_DXT45: | |
1366 | track->textures[i].cpp = 1; | |
1367 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | |
1368 | break; | |
551ebd83 | 1369 | } |
513bcb46 DA |
1370 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1371 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); | |
551ebd83 DA |
1372 | break; |
1373 | case RADEON_PP_CUBIC_FACES_0: | |
1374 | case RADEON_PP_CUBIC_FACES_1: | |
1375 | case RADEON_PP_CUBIC_FACES_2: | |
513bcb46 | 1376 | tmp = idx_value; |
551ebd83 DA |
1377 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1378 | for (face = 0; face < 4; face++) { | |
1379 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | |
1380 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); | |
771fe6b9 | 1381 | } |
551ebd83 DA |
1382 | break; |
1383 | default: | |
1384 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | |
1385 | reg, idx); | |
1386 | return -EINVAL; | |
771fe6b9 JG |
1387 | } |
1388 | return 0; | |
1389 | } | |
1390 | ||
068a117c JG |
1391 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1392 | struct radeon_cs_packet *pkt, | |
4c788679 | 1393 | struct radeon_bo *robj) |
068a117c | 1394 | { |
068a117c | 1395 | unsigned idx; |
513bcb46 | 1396 | u32 value; |
068a117c | 1397 | idx = pkt->idx + 1; |
513bcb46 | 1398 | value = radeon_get_ib_value(p, idx + 2); |
4c788679 | 1399 | if ((value + 1) > radeon_bo_size(robj)) { |
068a117c JG |
1400 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1401 | "(need %u have %lu) !\n", | |
513bcb46 | 1402 | value + 1, |
4c788679 | 1403 | radeon_bo_size(robj)); |
068a117c JG |
1404 | return -EINVAL; |
1405 | } | |
1406 | return 0; | |
1407 | } | |
1408 | ||
771fe6b9 JG |
1409 | static int r100_packet3_check(struct radeon_cs_parser *p, |
1410 | struct radeon_cs_packet *pkt) | |
1411 | { | |
771fe6b9 | 1412 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1413 | struct r100_cs_track *track; |
771fe6b9 | 1414 | unsigned idx; |
771fe6b9 JG |
1415 | volatile uint32_t *ib; |
1416 | int r; | |
1417 | ||
1418 | ib = p->ib->ptr; | |
771fe6b9 | 1419 | idx = pkt->idx + 1; |
551ebd83 | 1420 | track = (struct r100_cs_track *)p->track; |
771fe6b9 JG |
1421 | switch (pkt->opcode) { |
1422 | case PACKET3_3D_LOAD_VBPNTR: | |
513bcb46 DA |
1423 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1424 | if (r) | |
1425 | return r; | |
771fe6b9 JG |
1426 | break; |
1427 | case PACKET3_INDX_BUFFER: | |
1428 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1429 | if (r) { | |
1430 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
1431 | r100_cs_dump_packet(p, pkt); | |
1432 | return r; | |
1433 | } | |
513bcb46 | 1434 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
068a117c JG |
1435 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1436 | if (r) { | |
1437 | return r; | |
1438 | } | |
771fe6b9 JG |
1439 | break; |
1440 | case 0x23: | |
771fe6b9 JG |
1441 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
1442 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1443 | if (r) { | |
1444 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
1445 | r100_cs_dump_packet(p, pkt); | |
1446 | return r; | |
1447 | } | |
513bcb46 | 1448 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
551ebd83 | 1449 | track->num_arrays = 1; |
513bcb46 | 1450 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
551ebd83 DA |
1451 | |
1452 | track->arrays[0].robj = reloc->robj; | |
1453 | track->arrays[0].esize = track->vtx_size; | |
1454 | ||
513bcb46 | 1455 | track->max_indx = radeon_get_ib_value(p, idx+1); |
551ebd83 | 1456 | |
513bcb46 | 1457 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
551ebd83 DA |
1458 | track->immd_dwords = pkt->count - 1; |
1459 | r = r100_cs_track_check(p->rdev, track); | |
1460 | if (r) | |
1461 | return r; | |
771fe6b9 JG |
1462 | break; |
1463 | case PACKET3_3D_DRAW_IMMD: | |
513bcb46 | 1464 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1465 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1466 | return -EINVAL; | |
1467 | } | |
cf57fc7a | 1468 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
513bcb46 | 1469 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1470 | track->immd_dwords = pkt->count - 1; |
1471 | r = r100_cs_track_check(p->rdev, track); | |
1472 | if (r) | |
1473 | return r; | |
1474 | break; | |
771fe6b9 JG |
1475 | /* triggers drawing using in-packet vertex data */ |
1476 | case PACKET3_3D_DRAW_IMMD_2: | |
513bcb46 | 1477 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1478 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1479 | return -EINVAL; | |
1480 | } | |
513bcb46 | 1481 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1482 | track->immd_dwords = pkt->count; |
1483 | r = r100_cs_track_check(p->rdev, track); | |
1484 | if (r) | |
1485 | return r; | |
1486 | break; | |
771fe6b9 JG |
1487 | /* triggers drawing using in-packet vertex data */ |
1488 | case PACKET3_3D_DRAW_VBUF_2: | |
513bcb46 | 1489 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1490 | r = r100_cs_track_check(p->rdev, track); |
1491 | if (r) | |
1492 | return r; | |
1493 | break; | |
771fe6b9 JG |
1494 | /* triggers drawing of vertex buffers setup elsewhere */ |
1495 | case PACKET3_3D_DRAW_INDX_2: | |
513bcb46 | 1496 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1497 | r = r100_cs_track_check(p->rdev, track); |
1498 | if (r) | |
1499 | return r; | |
1500 | break; | |
771fe6b9 JG |
1501 | /* triggers drawing using indices to vertex buffer */ |
1502 | case PACKET3_3D_DRAW_VBUF: | |
513bcb46 | 1503 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1504 | r = r100_cs_track_check(p->rdev, track); |
1505 | if (r) | |
1506 | return r; | |
1507 | break; | |
771fe6b9 JG |
1508 | /* triggers drawing of vertex buffers setup elsewhere */ |
1509 | case PACKET3_3D_DRAW_INDX: | |
513bcb46 | 1510 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1511 | r = r100_cs_track_check(p->rdev, track); |
1512 | if (r) | |
1513 | return r; | |
1514 | break; | |
771fe6b9 JG |
1515 | /* triggers drawing using indices to vertex buffer */ |
1516 | case PACKET3_NOP: | |
1517 | break; | |
1518 | default: | |
1519 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
1520 | return -EINVAL; | |
1521 | } | |
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | int r100_cs_parse(struct radeon_cs_parser *p) | |
1526 | { | |
1527 | struct radeon_cs_packet pkt; | |
9f022ddf | 1528 | struct r100_cs_track *track; |
771fe6b9 JG |
1529 | int r; |
1530 | ||
9f022ddf JG |
1531 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1532 | r100_cs_track_clear(p->rdev, track); | |
1533 | p->track = track; | |
771fe6b9 JG |
1534 | do { |
1535 | r = r100_cs_packet_parse(p, &pkt, p->idx); | |
1536 | if (r) { | |
1537 | return r; | |
1538 | } | |
1539 | p->idx += pkt.count + 2; | |
1540 | switch (pkt.type) { | |
068a117c | 1541 | case PACKET_TYPE0: |
551ebd83 DA |
1542 | if (p->rdev->family >= CHIP_R200) |
1543 | r = r100_cs_parse_packet0(p, &pkt, | |
1544 | p->rdev->config.r100.reg_safe_bm, | |
1545 | p->rdev->config.r100.reg_safe_bm_size, | |
1546 | &r200_packet0_check); | |
1547 | else | |
1548 | r = r100_cs_parse_packet0(p, &pkt, | |
1549 | p->rdev->config.r100.reg_safe_bm, | |
1550 | p->rdev->config.r100.reg_safe_bm_size, | |
1551 | &r100_packet0_check); | |
068a117c JG |
1552 | break; |
1553 | case PACKET_TYPE2: | |
1554 | break; | |
1555 | case PACKET_TYPE3: | |
1556 | r = r100_packet3_check(p, &pkt); | |
1557 | break; | |
1558 | default: | |
1559 | DRM_ERROR("Unknown packet type %d !\n", | |
1560 | pkt.type); | |
1561 | return -EINVAL; | |
771fe6b9 JG |
1562 | } |
1563 | if (r) { | |
1564 | return r; | |
1565 | } | |
1566 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); | |
1567 | return 0; | |
1568 | } | |
1569 | ||
1570 | ||
1571 | /* | |
1572 | * Global GPU functions | |
1573 | */ | |
1574 | void r100_errata(struct radeon_device *rdev) | |
1575 | { | |
1576 | rdev->pll_errata = 0; | |
1577 | ||
1578 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { | |
1579 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; | |
1580 | } | |
1581 | ||
1582 | if (rdev->family == CHIP_RV100 || | |
1583 | rdev->family == CHIP_RS100 || | |
1584 | rdev->family == CHIP_RS200) { | |
1585 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; | |
1586 | } | |
1587 | } | |
1588 | ||
1589 | /* Wait for vertical sync on primary CRTC */ | |
1590 | void r100_gpu_wait_for_vsync(struct radeon_device *rdev) | |
1591 | { | |
1592 | uint32_t crtc_gen_cntl, tmp; | |
1593 | int i; | |
1594 | ||
1595 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); | |
1596 | if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || | |
1597 | !(crtc_gen_cntl & RADEON_CRTC_EN)) { | |
1598 | return; | |
1599 | } | |
1600 | /* Clear the CRTC_VBLANK_SAVE bit */ | |
1601 | WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); | |
1602 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1603 | tmp = RREG32(RADEON_CRTC_STATUS); | |
1604 | if (tmp & RADEON_CRTC_VBLANK_SAVE) { | |
1605 | return; | |
1606 | } | |
1607 | DRM_UDELAY(1); | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | /* Wait for vertical sync on secondary CRTC */ | |
1612 | void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) | |
1613 | { | |
1614 | uint32_t crtc2_gen_cntl, tmp; | |
1615 | int i; | |
1616 | ||
1617 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); | |
1618 | if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || | |
1619 | !(crtc2_gen_cntl & RADEON_CRTC2_EN)) | |
1620 | return; | |
1621 | ||
1622 | /* Clear the CRTC_VBLANK_SAVE bit */ | |
1623 | WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); | |
1624 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1625 | tmp = RREG32(RADEON_CRTC2_STATUS); | |
1626 | if (tmp & RADEON_CRTC2_VBLANK_SAVE) { | |
1627 | return; | |
1628 | } | |
1629 | DRM_UDELAY(1); | |
1630 | } | |
1631 | } | |
1632 | ||
1633 | int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) | |
1634 | { | |
1635 | unsigned i; | |
1636 | uint32_t tmp; | |
1637 | ||
1638 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1639 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; | |
1640 | if (tmp >= n) { | |
1641 | return 0; | |
1642 | } | |
1643 | DRM_UDELAY(1); | |
1644 | } | |
1645 | return -1; | |
1646 | } | |
1647 | ||
1648 | int r100_gui_wait_for_idle(struct radeon_device *rdev) | |
1649 | { | |
1650 | unsigned i; | |
1651 | uint32_t tmp; | |
1652 | ||
1653 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { | |
1654 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" | |
1655 | " Bad things might happen.\n"); | |
1656 | } | |
1657 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1658 | tmp = RREG32(RADEON_RBBM_STATUS); | |
4612dc97 | 1659 | if (!(tmp & RADEON_RBBM_ACTIVE)) { |
771fe6b9 JG |
1660 | return 0; |
1661 | } | |
1662 | DRM_UDELAY(1); | |
1663 | } | |
1664 | return -1; | |
1665 | } | |
1666 | ||
1667 | int r100_mc_wait_for_idle(struct radeon_device *rdev) | |
1668 | { | |
1669 | unsigned i; | |
1670 | uint32_t tmp; | |
1671 | ||
1672 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1673 | /* read MC_STATUS */ | |
4612dc97 AD |
1674 | tmp = RREG32(RADEON_MC_STATUS); |
1675 | if (tmp & RADEON_MC_IDLE) { | |
771fe6b9 JG |
1676 | return 0; |
1677 | } | |
1678 | DRM_UDELAY(1); | |
1679 | } | |
1680 | return -1; | |
1681 | } | |
1682 | ||
225758d8 | 1683 | void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
771fe6b9 | 1684 | { |
225758d8 JG |
1685 | lockup->last_cp_rptr = cp->rptr; |
1686 | lockup->last_jiffies = jiffies; | |
1687 | } | |
1688 | ||
1689 | /** | |
1690 | * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information | |
1691 | * @rdev: radeon device structure | |
1692 | * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations | |
1693 | * @cp: radeon_cp structure holding CP information | |
1694 | * | |
1695 | * We don't need to initialize the lockup tracking information as we will either | |
1696 | * have CP rptr to a different value of jiffies wrap around which will force | |
1697 | * initialization of the lockup tracking informations. | |
1698 | * | |
1699 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
1700 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
1701 | * if the elapsed time since last call is bigger than 2 second than we return | |
1702 | * false and update the tracking information. Due to this the caller must call | |
1703 | * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported | |
1704 | * the fencing code should be cautious about that. | |
1705 | * | |
1706 | * Caller should write to the ring to force CP to do something so we don't get | |
1707 | * false positive when CP is just gived nothing to do. | |
1708 | * | |
1709 | **/ | |
1710 | bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) | |
1711 | { | |
1712 | unsigned long cjiffies, elapsed; | |
1713 | ||
1714 | cjiffies = jiffies; | |
1715 | if (!time_after(cjiffies, lockup->last_jiffies)) { | |
1716 | /* likely a wrap around */ | |
1717 | lockup->last_cp_rptr = cp->rptr; | |
1718 | lockup->last_jiffies = jiffies; | |
1719 | return false; | |
1720 | } | |
1721 | if (cp->rptr != lockup->last_cp_rptr) { | |
1722 | /* CP is still working no lockup */ | |
1723 | lockup->last_cp_rptr = cp->rptr; | |
1724 | lockup->last_jiffies = jiffies; | |
1725 | return false; | |
1726 | } | |
1727 | elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); | |
1728 | if (elapsed >= 3000) { | |
1729 | /* very likely the improbable case where current | |
1730 | * rptr is equal to last recorded, a while ago, rptr | |
1731 | * this is more likely a false positive update tracking | |
1732 | * information which should force us to be recall at | |
1733 | * latter point | |
1734 | */ | |
1735 | lockup->last_cp_rptr = cp->rptr; | |
1736 | lockup->last_jiffies = jiffies; | |
1737 | return false; | |
1738 | } | |
1739 | if (elapsed >= 1000) { | |
1740 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); | |
1741 | return true; | |
1742 | } | |
1743 | /* give a chance to the GPU ... */ | |
1744 | return false; | |
771fe6b9 JG |
1745 | } |
1746 | ||
225758d8 | 1747 | bool r100_gpu_is_lockup(struct radeon_device *rdev) |
771fe6b9 | 1748 | { |
225758d8 JG |
1749 | u32 rbbm_status; |
1750 | int r; | |
771fe6b9 | 1751 | |
225758d8 JG |
1752 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
1753 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { | |
1754 | r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); | |
1755 | return false; | |
1756 | } | |
1757 | /* force CP activities */ | |
1758 | r = radeon_ring_lock(rdev, 2); | |
1759 | if (!r) { | |
1760 | /* PACKET2 NOP */ | |
1761 | radeon_ring_write(rdev, 0x80000000); | |
1762 | radeon_ring_write(rdev, 0x80000000); | |
1763 | radeon_ring_unlock_commit(rdev); | |
1764 | } | |
1765 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); | |
1766 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); | |
771fe6b9 JG |
1767 | } |
1768 | ||
90aca4d2 | 1769 | void r100_bm_disable(struct radeon_device *rdev) |
771fe6b9 | 1770 | { |
90aca4d2 | 1771 | u32 tmp; |
771fe6b9 | 1772 | |
90aca4d2 JG |
1773 | /* disable bus mastering */ |
1774 | tmp = RREG32(R_000030_BUS_CNTL); | |
1775 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); | |
1776 | mdelay(1); | |
1777 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); | |
1778 | mdelay(1); | |
1779 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); | |
1780 | tmp = RREG32(RADEON_BUS_CNTL); | |
1781 | mdelay(1); | |
1782 | pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); | |
1783 | pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); | |
771fe6b9 | 1784 | mdelay(1); |
771fe6b9 JG |
1785 | } |
1786 | ||
a2d07b74 | 1787 | int r100_asic_reset(struct radeon_device *rdev) |
771fe6b9 | 1788 | { |
90aca4d2 JG |
1789 | struct r100_mc_save save; |
1790 | u32 status, tmp; | |
771fe6b9 | 1791 | |
90aca4d2 JG |
1792 | r100_mc_stop(rdev, &save); |
1793 | status = RREG32(R_000E40_RBBM_STATUS); | |
1794 | if (!G_000E40_GUI_ACTIVE(status)) { | |
1795 | return 0; | |
771fe6b9 | 1796 | } |
90aca4d2 JG |
1797 | status = RREG32(R_000E40_RBBM_STATUS); |
1798 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
1799 | /* stop CP */ | |
1800 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
1801 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
1802 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
1803 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
1804 | WREG32(RADEON_CP_RB_WPTR, 0); | |
1805 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
1806 | /* save PCI state */ | |
1807 | pci_save_state(rdev->pdev); | |
1808 | /* disable bus mastering */ | |
1809 | r100_bm_disable(rdev); | |
1810 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | | |
1811 | S_0000F0_SOFT_RESET_RE(1) | | |
1812 | S_0000F0_SOFT_RESET_PP(1) | | |
1813 | S_0000F0_SOFT_RESET_RB(1)); | |
1814 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
1815 | mdelay(500); | |
1816 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
1817 | mdelay(1); | |
1818 | status = RREG32(R_000E40_RBBM_STATUS); | |
1819 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
771fe6b9 | 1820 | /* reset CP */ |
90aca4d2 JG |
1821 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
1822 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
1823 | mdelay(500); | |
1824 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
1825 | mdelay(1); | |
1826 | status = RREG32(R_000E40_RBBM_STATUS); | |
1827 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
1828 | /* restore PCI & busmastering */ | |
1829 | pci_restore_state(rdev->pdev); | |
1830 | r100_enable_bm(rdev); | |
771fe6b9 | 1831 | /* Check if GPU is idle */ |
90aca4d2 JG |
1832 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || |
1833 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { | |
1834 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
1835 | rdev->gpu_lockup = true; | |
771fe6b9 JG |
1836 | return -1; |
1837 | } | |
90aca4d2 JG |
1838 | r100_mc_resume(rdev, &save); |
1839 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
771fe6b9 JG |
1840 | return 0; |
1841 | } | |
1842 | ||
92cde00c AD |
1843 | void r100_set_common_regs(struct radeon_device *rdev) |
1844 | { | |
2739d49c AD |
1845 | struct drm_device *dev = rdev->ddev; |
1846 | bool force_dac2 = false; | |
d668046c | 1847 | u32 tmp; |
2739d49c | 1848 | |
92cde00c AD |
1849 | /* set these so they don't interfere with anything */ |
1850 | WREG32(RADEON_OV0_SCALE_CNTL, 0); | |
1851 | WREG32(RADEON_SUBPIC_CNTL, 0); | |
1852 | WREG32(RADEON_VIPH_CONTROL, 0); | |
1853 | WREG32(RADEON_I2C_CNTL_1, 0); | |
1854 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); | |
1855 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); | |
1856 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); | |
2739d49c AD |
1857 | |
1858 | /* always set up dac2 on rn50 and some rv100 as lots | |
1859 | * of servers seem to wire it up to a VGA port but | |
1860 | * don't report it in the bios connector | |
1861 | * table. | |
1862 | */ | |
1863 | switch (dev->pdev->device) { | |
1864 | /* RN50 */ | |
1865 | case 0x515e: | |
1866 | case 0x5969: | |
1867 | force_dac2 = true; | |
1868 | break; | |
1869 | /* RV100*/ | |
1870 | case 0x5159: | |
1871 | case 0x515a: | |
1872 | /* DELL triple head servers */ | |
1873 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && | |
1874 | ((dev->pdev->subsystem_device == 0x016c) || | |
1875 | (dev->pdev->subsystem_device == 0x016d) || | |
1876 | (dev->pdev->subsystem_device == 0x016e) || | |
1877 | (dev->pdev->subsystem_device == 0x016f) || | |
1878 | (dev->pdev->subsystem_device == 0x0170) || | |
1879 | (dev->pdev->subsystem_device == 0x017d) || | |
1880 | (dev->pdev->subsystem_device == 0x017e) || | |
1881 | (dev->pdev->subsystem_device == 0x0183) || | |
1882 | (dev->pdev->subsystem_device == 0x018a) || | |
1883 | (dev->pdev->subsystem_device == 0x019a))) | |
1884 | force_dac2 = true; | |
1885 | break; | |
1886 | } | |
1887 | ||
1888 | if (force_dac2) { | |
1889 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); | |
1890 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); | |
1891 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
1892 | ||
1893 | /* For CRT on DAC2, don't turn it on if BIOS didn't | |
1894 | enable it, even it's detected. | |
1895 | */ | |
1896 | ||
1897 | /* force it to crtc0 */ | |
1898 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; | |
1899 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; | |
1900 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; | |
1901 | ||
1902 | /* set up the TV DAC */ | |
1903 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | | |
1904 | RADEON_TV_DAC_STD_MASK | | |
1905 | RADEON_TV_DAC_RDACPD | | |
1906 | RADEON_TV_DAC_GDACPD | | |
1907 | RADEON_TV_DAC_BDACPD | | |
1908 | RADEON_TV_DAC_BGADJ_MASK | | |
1909 | RADEON_TV_DAC_DACADJ_MASK); | |
1910 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | | |
1911 | RADEON_TV_DAC_NHOLD | | |
1912 | RADEON_TV_DAC_STD_PS2 | | |
1913 | (0x58 << 16)); | |
1914 | ||
1915 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); | |
1916 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); | |
1917 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
1918 | } | |
d668046c DA |
1919 | |
1920 | /* switch PM block to ACPI mode */ | |
1921 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); | |
1922 | tmp &= ~RADEON_PM_MODE_SEL; | |
1923 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); | |
1924 | ||
92cde00c | 1925 | } |
771fe6b9 JG |
1926 | |
1927 | /* | |
1928 | * VRAM info | |
1929 | */ | |
1930 | static void r100_vram_get_type(struct radeon_device *rdev) | |
1931 | { | |
1932 | uint32_t tmp; | |
1933 | ||
1934 | rdev->mc.vram_is_ddr = false; | |
1935 | if (rdev->flags & RADEON_IS_IGP) | |
1936 | rdev->mc.vram_is_ddr = true; | |
1937 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) | |
1938 | rdev->mc.vram_is_ddr = true; | |
1939 | if ((rdev->family == CHIP_RV100) || | |
1940 | (rdev->family == CHIP_RS100) || | |
1941 | (rdev->family == CHIP_RS200)) { | |
1942 | tmp = RREG32(RADEON_MEM_CNTL); | |
1943 | if (tmp & RV100_HALF_MODE) { | |
1944 | rdev->mc.vram_width = 32; | |
1945 | } else { | |
1946 | rdev->mc.vram_width = 64; | |
1947 | } | |
1948 | if (rdev->flags & RADEON_SINGLE_CRTC) { | |
1949 | rdev->mc.vram_width /= 4; | |
1950 | rdev->mc.vram_is_ddr = true; | |
1951 | } | |
1952 | } else if (rdev->family <= CHIP_RV280) { | |
1953 | tmp = RREG32(RADEON_MEM_CNTL); | |
1954 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { | |
1955 | rdev->mc.vram_width = 128; | |
1956 | } else { | |
1957 | rdev->mc.vram_width = 64; | |
1958 | } | |
1959 | } else { | |
1960 | /* newer IGPs */ | |
1961 | rdev->mc.vram_width = 128; | |
1962 | } | |
1963 | } | |
1964 | ||
2a0f8918 | 1965 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
771fe6b9 | 1966 | { |
2a0f8918 DA |
1967 | u32 aper_size; |
1968 | u8 byte; | |
1969 | ||
1970 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | |
1971 | ||
1972 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, | |
1973 | * that is has the 2nd generation multifunction PCI interface | |
1974 | */ | |
1975 | if (rdev->family == CHIP_RV280 || | |
1976 | rdev->family >= CHIP_RV350) { | |
1977 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, | |
1978 | ~RADEON_HDP_APER_CNTL); | |
1979 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); | |
1980 | return aper_size * 2; | |
1981 | } | |
1982 | ||
1983 | /* Older cards have all sorts of funny issues to deal with. First | |
1984 | * check if it's a multifunction card by reading the PCI config | |
1985 | * header type... Limit those to one aperture size | |
1986 | */ | |
1987 | pci_read_config_byte(rdev->pdev, 0xe, &byte); | |
1988 | if (byte & 0x80) { | |
1989 | DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); | |
1990 | DRM_INFO("Limiting VRAM to one aperture\n"); | |
1991 | return aper_size; | |
1992 | } | |
1993 | ||
1994 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS | |
1995 | * have set it up. We don't write this as it's broken on some ASICs but | |
1996 | * we expect the BIOS to have done the right thing (might be too optimistic...) | |
1997 | */ | |
1998 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) | |
1999 | return aper_size * 2; | |
2000 | return aper_size; | |
2001 | } | |
2002 | ||
2003 | void r100_vram_init_sizes(struct radeon_device *rdev) | |
2004 | { | |
2005 | u64 config_aper_size; | |
2a0f8918 | 2006 | |
d594e46a | 2007 | /* work out accessible VRAM */ |
d594e46a JG |
2008 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
2009 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
51e5fcd3 JG |
2010 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); |
2011 | /* FIXME we don't use the second aperture yet when we could use it */ | |
2012 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) | |
2013 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | |
2a0f8918 | 2014 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
771fe6b9 JG |
2015 | if (rdev->flags & RADEON_IS_IGP) { |
2016 | uint32_t tom; | |
2017 | /* read NB_TOM to get the amount of ram stolen for the GPU */ | |
2018 | tom = RREG32(RADEON_NB_TOM); | |
7a50f01a | 2019 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
7a50f01a DA |
2020 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
2021 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
771fe6b9 | 2022 | } else { |
7a50f01a | 2023 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
771fe6b9 JG |
2024 | /* Some production boards of m6 will report 0 |
2025 | * if it's 8 MB | |
2026 | */ | |
7a50f01a DA |
2027 | if (rdev->mc.real_vram_size == 0) { |
2028 | rdev->mc.real_vram_size = 8192 * 1024; | |
2029 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
771fe6b9 | 2030 | } |
d594e46a JG |
2031 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
2032 | * Novell bug 204882 + along with lots of ubuntu ones | |
2033 | */ | |
7a50f01a DA |
2034 | if (config_aper_size > rdev->mc.real_vram_size) |
2035 | rdev->mc.mc_vram_size = config_aper_size; | |
2036 | else | |
2037 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
771fe6b9 | 2038 | } |
2a0f8918 DA |
2039 | } |
2040 | ||
28d52043 DA |
2041 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
2042 | { | |
2043 | uint32_t temp; | |
2044 | ||
2045 | temp = RREG32(RADEON_CONFIG_CNTL); | |
2046 | if (state == false) { | |
2047 | temp &= ~(1<<8); | |
2048 | temp |= (1<<9); | |
2049 | } else { | |
2050 | temp &= ~(1<<9); | |
2051 | } | |
2052 | WREG32(RADEON_CONFIG_CNTL, temp); | |
2053 | } | |
2054 | ||
d594e46a | 2055 | void r100_mc_init(struct radeon_device *rdev) |
2a0f8918 | 2056 | { |
d594e46a | 2057 | u64 base; |
2a0f8918 | 2058 | |
d594e46a | 2059 | r100_vram_get_type(rdev); |
2a0f8918 | 2060 | r100_vram_init_sizes(rdev); |
d594e46a JG |
2061 | base = rdev->mc.aper_base; |
2062 | if (rdev->flags & RADEON_IS_IGP) | |
2063 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | |
2064 | radeon_vram_location(rdev, &rdev->mc, base); | |
2065 | if (!(rdev->flags & RADEON_IS_AGP)) | |
2066 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 2067 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
2068 | } |
2069 | ||
2070 | ||
2071 | /* | |
2072 | * Indirect registers accessor | |
2073 | */ | |
2074 | void r100_pll_errata_after_index(struct radeon_device *rdev) | |
2075 | { | |
2076 | if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { | |
2077 | return; | |
2078 | } | |
2079 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); | |
2080 | (void)RREG32(RADEON_CRTC_GEN_CNTL); | |
2081 | } | |
2082 | ||
2083 | static void r100_pll_errata_after_data(struct radeon_device *rdev) | |
2084 | { | |
2085 | /* This workarounds is necessary on RV100, RS100 and RS200 chips | |
2086 | * or the chip could hang on a subsequent access | |
2087 | */ | |
2088 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { | |
2089 | udelay(5000); | |
2090 | } | |
2091 | ||
2092 | /* This function is required to workaround a hardware bug in some (all?) | |
2093 | * revisions of the R300. This workaround should be called after every | |
2094 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward | |
2095 | * may not be correct. | |
2096 | */ | |
2097 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { | |
2098 | uint32_t save, tmp; | |
2099 | ||
2100 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); | |
2101 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); | |
2102 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); | |
2103 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2104 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); | |
2105 | } | |
2106 | } | |
2107 | ||
2108 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) | |
2109 | { | |
2110 | uint32_t data; | |
2111 | ||
2112 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); | |
2113 | r100_pll_errata_after_index(rdev); | |
2114 | data = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2115 | r100_pll_errata_after_data(rdev); | |
2116 | return data; | |
2117 | } | |
2118 | ||
2119 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
2120 | { | |
2121 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); | |
2122 | r100_pll_errata_after_index(rdev); | |
2123 | WREG32(RADEON_CLOCK_CNTL_DATA, v); | |
2124 | r100_pll_errata_after_data(rdev); | |
2125 | } | |
2126 | ||
d4550907 | 2127 | void r100_set_safe_registers(struct radeon_device *rdev) |
068a117c | 2128 | { |
551ebd83 DA |
2129 | if (ASIC_IS_RN50(rdev)) { |
2130 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; | |
2131 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); | |
2132 | } else if (rdev->family < CHIP_R200) { | |
2133 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; | |
2134 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); | |
2135 | } else { | |
d4550907 | 2136 | r200_set_safe_registers(rdev); |
551ebd83 | 2137 | } |
068a117c JG |
2138 | } |
2139 | ||
771fe6b9 JG |
2140 | /* |
2141 | * Debugfs info | |
2142 | */ | |
2143 | #if defined(CONFIG_DEBUG_FS) | |
2144 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) | |
2145 | { | |
2146 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2147 | struct drm_device *dev = node->minor->dev; | |
2148 | struct radeon_device *rdev = dev->dev_private; | |
2149 | uint32_t reg, value; | |
2150 | unsigned i; | |
2151 | ||
2152 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); | |
2153 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); | |
2154 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2155 | for (i = 0; i < 64; i++) { | |
2156 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); | |
2157 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; | |
2158 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); | |
2159 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); | |
2160 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); | |
2161 | } | |
2162 | return 0; | |
2163 | } | |
2164 | ||
2165 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) | |
2166 | { | |
2167 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2168 | struct drm_device *dev = node->minor->dev; | |
2169 | struct radeon_device *rdev = dev->dev_private; | |
2170 | uint32_t rdp, wdp; | |
2171 | unsigned count, i, j; | |
2172 | ||
2173 | radeon_ring_free_size(rdev); | |
2174 | rdp = RREG32(RADEON_CP_RB_RPTR); | |
2175 | wdp = RREG32(RADEON_CP_RB_WPTR); | |
2176 | count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; | |
2177 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2178 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); | |
2179 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); | |
2180 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); | |
2181 | seq_printf(m, "%u dwords in ring\n", count); | |
2182 | for (j = 0; j <= count; j++) { | |
2183 | i = (rdp + j) & rdev->cp.ptr_mask; | |
2184 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); | |
2185 | } | |
2186 | return 0; | |
2187 | } | |
2188 | ||
2189 | ||
2190 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) | |
2191 | { | |
2192 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2193 | struct drm_device *dev = node->minor->dev; | |
2194 | struct radeon_device *rdev = dev->dev_private; | |
2195 | uint32_t csq_stat, csq2_stat, tmp; | |
2196 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; | |
2197 | unsigned i; | |
2198 | ||
2199 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2200 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); | |
2201 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); | |
2202 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); | |
2203 | r_rptr = (csq_stat >> 0) & 0x3ff; | |
2204 | r_wptr = (csq_stat >> 10) & 0x3ff; | |
2205 | ib1_rptr = (csq_stat >> 20) & 0x3ff; | |
2206 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; | |
2207 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; | |
2208 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; | |
2209 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); | |
2210 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); | |
2211 | seq_printf(m, "Ring rptr %u\n", r_rptr); | |
2212 | seq_printf(m, "Ring wptr %u\n", r_wptr); | |
2213 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); | |
2214 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); | |
2215 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); | |
2216 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); | |
2217 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms | |
2218 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ | |
2219 | seq_printf(m, "Ring fifo:\n"); | |
2220 | for (i = 0; i < 256; i++) { | |
2221 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2222 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2223 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); | |
2224 | } | |
2225 | seq_printf(m, "Indirect1 fifo:\n"); | |
2226 | for (i = 256; i <= 512; i++) { | |
2227 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2228 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2229 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); | |
2230 | } | |
2231 | seq_printf(m, "Indirect2 fifo:\n"); | |
2232 | for (i = 640; i < ib1_wptr; i++) { | |
2233 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2234 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2235 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); | |
2236 | } | |
2237 | return 0; | |
2238 | } | |
2239 | ||
2240 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) | |
2241 | { | |
2242 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2243 | struct drm_device *dev = node->minor->dev; | |
2244 | struct radeon_device *rdev = dev->dev_private; | |
2245 | uint32_t tmp; | |
2246 | ||
2247 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); | |
2248 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); | |
2249 | tmp = RREG32(RADEON_MC_FB_LOCATION); | |
2250 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); | |
2251 | tmp = RREG32(RADEON_BUS_CNTL); | |
2252 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); | |
2253 | tmp = RREG32(RADEON_MC_AGP_LOCATION); | |
2254 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); | |
2255 | tmp = RREG32(RADEON_AGP_BASE); | |
2256 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); | |
2257 | tmp = RREG32(RADEON_HOST_PATH_CNTL); | |
2258 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); | |
2259 | tmp = RREG32(0x01D0); | |
2260 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); | |
2261 | tmp = RREG32(RADEON_AIC_LO_ADDR); | |
2262 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); | |
2263 | tmp = RREG32(RADEON_AIC_HI_ADDR); | |
2264 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); | |
2265 | tmp = RREG32(0x01E4); | |
2266 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); | |
2267 | return 0; | |
2268 | } | |
2269 | ||
2270 | static struct drm_info_list r100_debugfs_rbbm_list[] = { | |
2271 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, | |
2272 | }; | |
2273 | ||
2274 | static struct drm_info_list r100_debugfs_cp_list[] = { | |
2275 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, | |
2276 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, | |
2277 | }; | |
2278 | ||
2279 | static struct drm_info_list r100_debugfs_mc_info_list[] = { | |
2280 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, | |
2281 | }; | |
2282 | #endif | |
2283 | ||
2284 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) | |
2285 | { | |
2286 | #if defined(CONFIG_DEBUG_FS) | |
2287 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); | |
2288 | #else | |
2289 | return 0; | |
2290 | #endif | |
2291 | } | |
2292 | ||
2293 | int r100_debugfs_cp_init(struct radeon_device *rdev) | |
2294 | { | |
2295 | #if defined(CONFIG_DEBUG_FS) | |
2296 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); | |
2297 | #else | |
2298 | return 0; | |
2299 | #endif | |
2300 | } | |
2301 | ||
2302 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) | |
2303 | { | |
2304 | #if defined(CONFIG_DEBUG_FS) | |
2305 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); | |
2306 | #else | |
2307 | return 0; | |
2308 | #endif | |
2309 | } | |
e024e110 DA |
2310 | |
2311 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, | |
2312 | uint32_t tiling_flags, uint32_t pitch, | |
2313 | uint32_t offset, uint32_t obj_size) | |
2314 | { | |
2315 | int surf_index = reg * 16; | |
2316 | int flags = 0; | |
2317 | ||
2318 | /* r100/r200 divide by 16 */ | |
2319 | if (rdev->family < CHIP_R300) | |
2320 | flags = pitch / 16; | |
2321 | else | |
2322 | flags = pitch / 8; | |
2323 | ||
2324 | if (rdev->family <= CHIP_RS200) { | |
2325 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
2326 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
2327 | flags |= RADEON_SURF_TILE_COLOR_BOTH; | |
2328 | if (tiling_flags & RADEON_TILING_MACRO) | |
2329 | flags |= RADEON_SURF_TILE_COLOR_MACRO; | |
2330 | } else if (rdev->family <= CHIP_RV280) { | |
2331 | if (tiling_flags & (RADEON_TILING_MACRO)) | |
2332 | flags |= R200_SURF_TILE_COLOR_MACRO; | |
2333 | if (tiling_flags & RADEON_TILING_MICRO) | |
2334 | flags |= R200_SURF_TILE_COLOR_MICRO; | |
2335 | } else { | |
2336 | if (tiling_flags & RADEON_TILING_MACRO) | |
2337 | flags |= R300_SURF_TILE_MACRO; | |
2338 | if (tiling_flags & RADEON_TILING_MICRO) | |
2339 | flags |= R300_SURF_TILE_MICRO; | |
2340 | } | |
2341 | ||
c88f9f0c MD |
2342 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
2343 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; | |
2344 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) | |
2345 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; | |
2346 | ||
e024e110 DA |
2347 | DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
2348 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); | |
2349 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); | |
2350 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); | |
2351 | return 0; | |
2352 | } | |
2353 | ||
2354 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) | |
2355 | { | |
2356 | int surf_index = reg * 16; | |
2357 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); | |
2358 | } | |
c93bb85b JG |
2359 | |
2360 | void r100_bandwidth_update(struct radeon_device *rdev) | |
2361 | { | |
2362 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; | |
2363 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; | |
2364 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; | |
2365 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; | |
2366 | fixed20_12 memtcas_ff[8] = { | |
2367 | fixed_init(1), | |
2368 | fixed_init(2), | |
2369 | fixed_init(3), | |
2370 | fixed_init(0), | |
2371 | fixed_init_half(1), | |
2372 | fixed_init_half(2), | |
2373 | fixed_init(0), | |
2374 | }; | |
2375 | fixed20_12 memtcas_rs480_ff[8] = { | |
2376 | fixed_init(0), | |
2377 | fixed_init(1), | |
2378 | fixed_init(2), | |
2379 | fixed_init(3), | |
2380 | fixed_init(0), | |
2381 | fixed_init_half(1), | |
2382 | fixed_init_half(2), | |
2383 | fixed_init_half(3), | |
2384 | }; | |
2385 | fixed20_12 memtcas2_ff[8] = { | |
2386 | fixed_init(0), | |
2387 | fixed_init(1), | |
2388 | fixed_init(2), | |
2389 | fixed_init(3), | |
2390 | fixed_init(4), | |
2391 | fixed_init(5), | |
2392 | fixed_init(6), | |
2393 | fixed_init(7), | |
2394 | }; | |
2395 | fixed20_12 memtrbs[8] = { | |
2396 | fixed_init(1), | |
2397 | fixed_init_half(1), | |
2398 | fixed_init(2), | |
2399 | fixed_init_half(2), | |
2400 | fixed_init(3), | |
2401 | fixed_init_half(3), | |
2402 | fixed_init(4), | |
2403 | fixed_init_half(4) | |
2404 | }; | |
2405 | fixed20_12 memtrbs_r4xx[8] = { | |
2406 | fixed_init(4), | |
2407 | fixed_init(5), | |
2408 | fixed_init(6), | |
2409 | fixed_init(7), | |
2410 | fixed_init(8), | |
2411 | fixed_init(9), | |
2412 | fixed_init(10), | |
2413 | fixed_init(11) | |
2414 | }; | |
2415 | fixed20_12 min_mem_eff; | |
2416 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; | |
2417 | fixed20_12 cur_latency_mclk, cur_latency_sclk; | |
2418 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, | |
2419 | disp_drain_rate2, read_return_rate; | |
2420 | fixed20_12 time_disp1_drop_priority; | |
2421 | int c; | |
2422 | int cur_size = 16; /* in octawords */ | |
2423 | int critical_point = 0, critical_point2; | |
2424 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ | |
2425 | int stop_req, max_stop_req; | |
2426 | struct drm_display_mode *mode1 = NULL; | |
2427 | struct drm_display_mode *mode2 = NULL; | |
2428 | uint32_t pixel_bytes1 = 0; | |
2429 | uint32_t pixel_bytes2 = 0; | |
2430 | ||
f46c0120 AD |
2431 | radeon_update_display_priority(rdev); |
2432 | ||
c93bb85b JG |
2433 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
2434 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; | |
2435 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; | |
2436 | } | |
dfee5614 DA |
2437 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
2438 | if (rdev->mode_info.crtcs[1]->base.enabled) { | |
2439 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; | |
2440 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; | |
2441 | } | |
c93bb85b JG |
2442 | } |
2443 | ||
2444 | min_mem_eff.full = rfixed_const_8(0); | |
2445 | /* get modes */ | |
2446 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { | |
2447 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); | |
2448 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
2449 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
2450 | /* check crtc enables */ | |
2451 | if (mode2) | |
2452 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
2453 | if (mode1) | |
2454 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
2455 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); | |
2456 | } | |
2457 | ||
2458 | /* | |
2459 | * determine is there is enough bw for current mode | |
2460 | */ | |
f47299c5 AD |
2461 | sclk_ff = rdev->pm.sclk; |
2462 | mclk_ff = rdev->pm.mclk; | |
c93bb85b JG |
2463 | |
2464 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); | |
2465 | temp_ff.full = rfixed_const(temp); | |
2466 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); | |
2467 | ||
2468 | pix_clk.full = 0; | |
2469 | pix_clk2.full = 0; | |
2470 | peak_disp_bw.full = 0; | |
2471 | if (mode1) { | |
2472 | temp_ff.full = rfixed_const(1000); | |
2473 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ | |
2474 | pix_clk.full = rfixed_div(pix_clk, temp_ff); | |
2475 | temp_ff.full = rfixed_const(pixel_bytes1); | |
2476 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); | |
2477 | } | |
2478 | if (mode2) { | |
2479 | temp_ff.full = rfixed_const(1000); | |
2480 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ | |
2481 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); | |
2482 | temp_ff.full = rfixed_const(pixel_bytes2); | |
2483 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); | |
2484 | } | |
2485 | ||
2486 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); | |
2487 | if (peak_disp_bw.full >= mem_bw.full) { | |
2488 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" | |
2489 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | |
2490 | } | |
2491 | ||
2492 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ | |
2493 | temp = RREG32(RADEON_MEM_TIMING_CNTL); | |
2494 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ | |
2495 | mem_trcd = ((temp >> 2) & 0x3) + 1; | |
2496 | mem_trp = ((temp & 0x3)) + 1; | |
2497 | mem_tras = ((temp & 0x70) >> 4) + 1; | |
2498 | } else if (rdev->family == CHIP_R300 || | |
2499 | rdev->family == CHIP_R350) { /* r300, r350 */ | |
2500 | mem_trcd = (temp & 0x7) + 1; | |
2501 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
2502 | mem_tras = ((temp >> 11) & 0xf) + 4; | |
2503 | } else if (rdev->family == CHIP_RV350 || | |
2504 | rdev->family <= CHIP_RV380) { | |
2505 | /* rv3x0 */ | |
2506 | mem_trcd = (temp & 0x7) + 3; | |
2507 | mem_trp = ((temp >> 8) & 0x7) + 3; | |
2508 | mem_tras = ((temp >> 11) & 0xf) + 6; | |
2509 | } else if (rdev->family == CHIP_R420 || | |
2510 | rdev->family == CHIP_R423 || | |
2511 | rdev->family == CHIP_RV410) { | |
2512 | /* r4xx */ | |
2513 | mem_trcd = (temp & 0xf) + 3; | |
2514 | if (mem_trcd > 15) | |
2515 | mem_trcd = 15; | |
2516 | mem_trp = ((temp >> 8) & 0xf) + 3; | |
2517 | if (mem_trp > 15) | |
2518 | mem_trp = 15; | |
2519 | mem_tras = ((temp >> 12) & 0x1f) + 6; | |
2520 | if (mem_tras > 31) | |
2521 | mem_tras = 31; | |
2522 | } else { /* RV200, R200 */ | |
2523 | mem_trcd = (temp & 0x7) + 1; | |
2524 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
2525 | mem_tras = ((temp >> 12) & 0xf) + 4; | |
2526 | } | |
2527 | /* convert to FF */ | |
2528 | trcd_ff.full = rfixed_const(mem_trcd); | |
2529 | trp_ff.full = rfixed_const(mem_trp); | |
2530 | tras_ff.full = rfixed_const(mem_tras); | |
2531 | ||
2532 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ | |
2533 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | |
2534 | data = (temp & (7 << 20)) >> 20; | |
2535 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { | |
2536 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ | |
2537 | tcas_ff = memtcas_rs480_ff[data]; | |
2538 | else | |
2539 | tcas_ff = memtcas_ff[data]; | |
2540 | } else | |
2541 | tcas_ff = memtcas2_ff[data]; | |
2542 | ||
2543 | if (rdev->family == CHIP_RS400 || | |
2544 | rdev->family == CHIP_RS480) { | |
2545 | /* extra cas latency stored in bits 23-25 0-4 clocks */ | |
2546 | data = (temp >> 23) & 0x7; | |
2547 | if (data < 5) | |
2548 | tcas_ff.full += rfixed_const(data); | |
2549 | } | |
2550 | ||
2551 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { | |
2552 | /* on the R300, Tcas is included in Trbs. | |
2553 | */ | |
2554 | temp = RREG32(RADEON_MEM_CNTL); | |
2555 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); | |
2556 | if (data == 1) { | |
2557 | if (R300_MEM_USE_CD_CH_ONLY & temp) { | |
2558 | temp = RREG32(R300_MC_IND_INDEX); | |
2559 | temp &= ~R300_MC_IND_ADDR_MASK; | |
2560 | temp |= R300_MC_READ_CNTL_CD_mcind; | |
2561 | WREG32(R300_MC_IND_INDEX, temp); | |
2562 | temp = RREG32(R300_MC_IND_DATA); | |
2563 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); | |
2564 | } else { | |
2565 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
2566 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
2567 | } | |
2568 | } else { | |
2569 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
2570 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
2571 | } | |
2572 | if (rdev->family == CHIP_RV410 || | |
2573 | rdev->family == CHIP_R420 || | |
2574 | rdev->family == CHIP_R423) | |
2575 | trbs_ff = memtrbs_r4xx[data]; | |
2576 | else | |
2577 | trbs_ff = memtrbs[data]; | |
2578 | tcas_ff.full += trbs_ff.full; | |
2579 | } | |
2580 | ||
2581 | sclk_eff_ff.full = sclk_ff.full; | |
2582 | ||
2583 | if (rdev->flags & RADEON_IS_AGP) { | |
2584 | fixed20_12 agpmode_ff; | |
2585 | agpmode_ff.full = rfixed_const(radeon_agpmode); | |
2586 | temp_ff.full = rfixed_const_666(16); | |
2587 | sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); | |
2588 | } | |
2589 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ | |
2590 | ||
2591 | if (ASIC_IS_R300(rdev)) { | |
2592 | sclk_delay_ff.full = rfixed_const(250); | |
2593 | } else { | |
2594 | if ((rdev->family == CHIP_RV100) || | |
2595 | rdev->flags & RADEON_IS_IGP) { | |
2596 | if (rdev->mc.vram_is_ddr) | |
2597 | sclk_delay_ff.full = rfixed_const(41); | |
2598 | else | |
2599 | sclk_delay_ff.full = rfixed_const(33); | |
2600 | } else { | |
2601 | if (rdev->mc.vram_width == 128) | |
2602 | sclk_delay_ff.full = rfixed_const(57); | |
2603 | else | |
2604 | sclk_delay_ff.full = rfixed_const(41); | |
2605 | } | |
2606 | } | |
2607 | ||
2608 | mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); | |
2609 | ||
2610 | if (rdev->mc.vram_is_ddr) { | |
2611 | if (rdev->mc.vram_width == 32) { | |
2612 | k1.full = rfixed_const(40); | |
2613 | c = 3; | |
2614 | } else { | |
2615 | k1.full = rfixed_const(20); | |
2616 | c = 1; | |
2617 | } | |
2618 | } else { | |
2619 | k1.full = rfixed_const(40); | |
2620 | c = 3; | |
2621 | } | |
2622 | ||
2623 | temp_ff.full = rfixed_const(2); | |
2624 | mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); | |
2625 | temp_ff.full = rfixed_const(c); | |
2626 | mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); | |
2627 | temp_ff.full = rfixed_const(4); | |
2628 | mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); | |
2629 | mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); | |
2630 | mc_latency_mclk.full += k1.full; | |
2631 | ||
2632 | mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); | |
2633 | mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); | |
2634 | ||
2635 | /* | |
2636 | HW cursor time assuming worst case of full size colour cursor. | |
2637 | */ | |
2638 | temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); | |
2639 | temp_ff.full += trcd_ff.full; | |
2640 | if (temp_ff.full < tras_ff.full) | |
2641 | temp_ff.full = tras_ff.full; | |
2642 | cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); | |
2643 | ||
2644 | temp_ff.full = rfixed_const(cur_size); | |
2645 | cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); | |
2646 | /* | |
2647 | Find the total latency for the display data. | |
2648 | */ | |
b5fc9010 | 2649 | disp_latency_overhead.full = rfixed_const(8); |
c93bb85b JG |
2650 | disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); |
2651 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; | |
2652 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; | |
2653 | ||
2654 | if (mc_latency_mclk.full > mc_latency_sclk.full) | |
2655 | disp_latency.full = mc_latency_mclk.full; | |
2656 | else | |
2657 | disp_latency.full = mc_latency_sclk.full; | |
2658 | ||
2659 | /* setup Max GRPH_STOP_REQ default value */ | |
2660 | if (ASIC_IS_RV100(rdev)) | |
2661 | max_stop_req = 0x5c; | |
2662 | else | |
2663 | max_stop_req = 0x7c; | |
2664 | ||
2665 | if (mode1) { | |
2666 | /* CRTC1 | |
2667 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. | |
2668 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] | |
2669 | */ | |
2670 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; | |
2671 | ||
2672 | if (stop_req > max_stop_req) | |
2673 | stop_req = max_stop_req; | |
2674 | ||
2675 | /* | |
2676 | Find the drain rate of the display buffer. | |
2677 | */ | |
2678 | temp_ff.full = rfixed_const((16/pixel_bytes1)); | |
2679 | disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); | |
2680 | ||
2681 | /* | |
2682 | Find the critical point of the display buffer. | |
2683 | */ | |
2684 | crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); | |
2685 | crit_point_ff.full += rfixed_const_half(0); | |
2686 | ||
2687 | critical_point = rfixed_trunc(crit_point_ff); | |
2688 | ||
2689 | if (rdev->disp_priority == 2) { | |
2690 | critical_point = 0; | |
2691 | } | |
2692 | ||
2693 | /* | |
2694 | The critical point should never be above max_stop_req-4. Setting | |
2695 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. | |
2696 | */ | |
2697 | if (max_stop_req - critical_point < 4) | |
2698 | critical_point = 0; | |
2699 | ||
2700 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { | |
2701 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ | |
2702 | critical_point = 0x10; | |
2703 | } | |
2704 | ||
2705 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); | |
2706 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
2707 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
2708 | temp &= ~(RADEON_GRPH_START_REQ_MASK); | |
2709 | if ((rdev->family == CHIP_R350) && | |
2710 | (stop_req > 0x15)) { | |
2711 | stop_req -= 0x10; | |
2712 | } | |
2713 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | |
2714 | temp |= RADEON_GRPH_BUFFER_SIZE; | |
2715 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
2716 | RADEON_GRPH_CRITICAL_AT_SOF | | |
2717 | RADEON_GRPH_STOP_CNTL); | |
2718 | /* | |
2719 | Write the result into the register. | |
2720 | */ | |
2721 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | |
2722 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
2723 | ||
2724 | #if 0 | |
2725 | if ((rdev->family == CHIP_RS400) || | |
2726 | (rdev->family == CHIP_RS480)) { | |
2727 | /* attempt to program RS400 disp regs correctly ??? */ | |
2728 | temp = RREG32(RS400_DISP1_REG_CNTL); | |
2729 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | | |
2730 | RS400_DISP1_STOP_REQ_LEVEL_MASK); | |
2731 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | | |
2732 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
2733 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
2734 | temp = RREG32(RS400_DMIF_MEM_CNTL1); | |
2735 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | | |
2736 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); | |
2737 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | | |
2738 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | | |
2739 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); | |
2740 | } | |
2741 | #endif | |
2742 | ||
2743 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", | |
2744 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ | |
2745 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); | |
2746 | } | |
2747 | ||
2748 | if (mode2) { | |
2749 | u32 grph2_cntl; | |
2750 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; | |
2751 | ||
2752 | if (stop_req > max_stop_req) | |
2753 | stop_req = max_stop_req; | |
2754 | ||
2755 | /* | |
2756 | Find the drain rate of the display buffer. | |
2757 | */ | |
2758 | temp_ff.full = rfixed_const((16/pixel_bytes2)); | |
2759 | disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); | |
2760 | ||
2761 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); | |
2762 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
2763 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
2764 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); | |
2765 | if ((rdev->family == CHIP_R350) && | |
2766 | (stop_req > 0x15)) { | |
2767 | stop_req -= 0x10; | |
2768 | } | |
2769 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | |
2770 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; | |
2771 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
2772 | RADEON_GRPH_CRITICAL_AT_SOF | | |
2773 | RADEON_GRPH_STOP_CNTL); | |
2774 | ||
2775 | if ((rdev->family == CHIP_RS100) || | |
2776 | (rdev->family == CHIP_RS200)) | |
2777 | critical_point2 = 0; | |
2778 | else { | |
2779 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; | |
2780 | temp_ff.full = rfixed_const(temp); | |
2781 | temp_ff.full = rfixed_mul(mclk_ff, temp_ff); | |
2782 | if (sclk_ff.full < temp_ff.full) | |
2783 | temp_ff.full = sclk_ff.full; | |
2784 | ||
2785 | read_return_rate.full = temp_ff.full; | |
2786 | ||
2787 | if (mode1) { | |
2788 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; | |
2789 | time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); | |
2790 | } else { | |
2791 | time_disp1_drop_priority.full = 0; | |
2792 | } | |
2793 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; | |
2794 | crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); | |
2795 | crit_point_ff.full += rfixed_const_half(0); | |
2796 | ||
2797 | critical_point2 = rfixed_trunc(crit_point_ff); | |
2798 | ||
2799 | if (rdev->disp_priority == 2) { | |
2800 | critical_point2 = 0; | |
2801 | } | |
2802 | ||
2803 | if (max_stop_req - critical_point2 < 4) | |
2804 | critical_point2 = 0; | |
2805 | ||
2806 | } | |
2807 | ||
2808 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { | |
2809 | /* some R300 cards have problem with this set to 0 */ | |
2810 | critical_point2 = 0x10; | |
2811 | } | |
2812 | ||
2813 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | |
2814 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
2815 | ||
2816 | if ((rdev->family == CHIP_RS400) || | |
2817 | (rdev->family == CHIP_RS480)) { | |
2818 | #if 0 | |
2819 | /* attempt to program RS400 disp2 regs correctly ??? */ | |
2820 | temp = RREG32(RS400_DISP2_REQ_CNTL1); | |
2821 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | | |
2822 | RS400_DISP2_STOP_REQ_LEVEL_MASK); | |
2823 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | | |
2824 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
2825 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
2826 | temp = RREG32(RS400_DISP2_REQ_CNTL2); | |
2827 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | | |
2828 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); | |
2829 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | | |
2830 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | | |
2831 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); | |
2832 | #endif | |
2833 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); | |
2834 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); | |
2835 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); | |
2836 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); | |
2837 | } | |
2838 | ||
2839 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", | |
2840 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); | |
2841 | } | |
2842 | } | |
551ebd83 DA |
2843 | |
2844 | static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) | |
2845 | { | |
2846 | DRM_ERROR("pitch %d\n", t->pitch); | |
ceb776bc | 2847 | DRM_ERROR("use_pitch %d\n", t->use_pitch); |
551ebd83 | 2848 | DRM_ERROR("width %d\n", t->width); |
ceb776bc | 2849 | DRM_ERROR("width_11 %d\n", t->width_11); |
551ebd83 | 2850 | DRM_ERROR("height %d\n", t->height); |
ceb776bc | 2851 | DRM_ERROR("height_11 %d\n", t->height_11); |
551ebd83 DA |
2852 | DRM_ERROR("num levels %d\n", t->num_levels); |
2853 | DRM_ERROR("depth %d\n", t->txdepth); | |
2854 | DRM_ERROR("bpp %d\n", t->cpp); | |
2855 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); | |
2856 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); | |
2857 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); | |
d785d78b | 2858 | DRM_ERROR("compress format %d\n", t->compress_format); |
551ebd83 DA |
2859 | } |
2860 | ||
2861 | static int r100_cs_track_cube(struct radeon_device *rdev, | |
2862 | struct r100_cs_track *track, unsigned idx) | |
2863 | { | |
2864 | unsigned face, w, h; | |
4c788679 | 2865 | struct radeon_bo *cube_robj; |
551ebd83 DA |
2866 | unsigned long size; |
2867 | ||
2868 | for (face = 0; face < 5; face++) { | |
2869 | cube_robj = track->textures[idx].cube_info[face].robj; | |
2870 | w = track->textures[idx].cube_info[face].width; | |
2871 | h = track->textures[idx].cube_info[face].height; | |
2872 | ||
2873 | size = w * h; | |
2874 | size *= track->textures[idx].cpp; | |
2875 | ||
2876 | size += track->textures[idx].cube_info[face].offset; | |
2877 | ||
4c788679 | 2878 | if (size > radeon_bo_size(cube_robj)) { |
551ebd83 | 2879 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", |
4c788679 | 2880 | size, radeon_bo_size(cube_robj)); |
551ebd83 DA |
2881 | r100_cs_track_texture_print(&track->textures[idx]); |
2882 | return -1; | |
2883 | } | |
2884 | } | |
2885 | return 0; | |
2886 | } | |
2887 | ||
d785d78b DA |
2888 | static int r100_track_compress_size(int compress_format, int w, int h) |
2889 | { | |
2890 | int block_width, block_height, block_bytes; | |
2891 | int wblocks, hblocks; | |
2892 | int min_wblocks; | |
2893 | int sz; | |
2894 | ||
2895 | block_width = 4; | |
2896 | block_height = 4; | |
2897 | ||
2898 | switch (compress_format) { | |
2899 | case R100_TRACK_COMP_DXT1: | |
2900 | block_bytes = 8; | |
2901 | min_wblocks = 4; | |
2902 | break; | |
2903 | default: | |
2904 | case R100_TRACK_COMP_DXT35: | |
2905 | block_bytes = 16; | |
2906 | min_wblocks = 2; | |
2907 | break; | |
2908 | } | |
2909 | ||
2910 | hblocks = (h + block_height - 1) / block_height; | |
2911 | wblocks = (w + block_width - 1) / block_width; | |
2912 | if (wblocks < min_wblocks) | |
2913 | wblocks = min_wblocks; | |
2914 | sz = wblocks * hblocks * block_bytes; | |
2915 | return sz; | |
2916 | } | |
2917 | ||
551ebd83 DA |
2918 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
2919 | struct r100_cs_track *track) | |
2920 | { | |
4c788679 | 2921 | struct radeon_bo *robj; |
551ebd83 | 2922 | unsigned long size; |
b73c5f8b | 2923 | unsigned u, i, w, h, d; |
551ebd83 DA |
2924 | int ret; |
2925 | ||
2926 | for (u = 0; u < track->num_texture; u++) { | |
2927 | if (!track->textures[u].enabled) | |
2928 | continue; | |
2929 | robj = track->textures[u].robj; | |
2930 | if (robj == NULL) { | |
2931 | DRM_ERROR("No texture bound to unit %u\n", u); | |
2932 | return -EINVAL; | |
2933 | } | |
2934 | size = 0; | |
2935 | for (i = 0; i <= track->textures[u].num_levels; i++) { | |
2936 | if (track->textures[u].use_pitch) { | |
2937 | if (rdev->family < CHIP_R300) | |
2938 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); | |
2939 | else | |
2940 | w = track->textures[u].pitch / (1 << i); | |
2941 | } else { | |
ceb776bc | 2942 | w = track->textures[u].width; |
551ebd83 DA |
2943 | if (rdev->family >= CHIP_RV515) |
2944 | w |= track->textures[u].width_11; | |
ceb776bc | 2945 | w = w / (1 << i); |
551ebd83 DA |
2946 | if (track->textures[u].roundup_w) |
2947 | w = roundup_pow_of_two(w); | |
2948 | } | |
ceb776bc | 2949 | h = track->textures[u].height; |
551ebd83 DA |
2950 | if (rdev->family >= CHIP_RV515) |
2951 | h |= track->textures[u].height_11; | |
ceb776bc | 2952 | h = h / (1 << i); |
551ebd83 DA |
2953 | if (track->textures[u].roundup_h) |
2954 | h = roundup_pow_of_two(h); | |
b73c5f8b MO |
2955 | if (track->textures[u].tex_coord_type == 1) { |
2956 | d = (1 << track->textures[u].txdepth) / (1 << i); | |
2957 | if (!d) | |
2958 | d = 1; | |
2959 | } else { | |
2960 | d = 1; | |
2961 | } | |
d785d78b DA |
2962 | if (track->textures[u].compress_format) { |
2963 | ||
b73c5f8b | 2964 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
d785d78b DA |
2965 | /* compressed textures are block based */ |
2966 | } else | |
b73c5f8b | 2967 | size += w * h * d; |
551ebd83 DA |
2968 | } |
2969 | size *= track->textures[u].cpp; | |
d785d78b | 2970 | |
551ebd83 DA |
2971 | switch (track->textures[u].tex_coord_type) { |
2972 | case 0: | |
551ebd83 | 2973 | case 1: |
551ebd83 DA |
2974 | break; |
2975 | case 2: | |
2976 | if (track->separate_cube) { | |
2977 | ret = r100_cs_track_cube(rdev, track, u); | |
2978 | if (ret) | |
2979 | return ret; | |
2980 | } else | |
2981 | size *= 6; | |
2982 | break; | |
2983 | default: | |
2984 | DRM_ERROR("Invalid texture coordinate type %u for unit " | |
2985 | "%u\n", track->textures[u].tex_coord_type, u); | |
2986 | return -EINVAL; | |
2987 | } | |
4c788679 | 2988 | if (size > radeon_bo_size(robj)) { |
551ebd83 | 2989 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
4c788679 | 2990 | "%lu\n", u, size, radeon_bo_size(robj)); |
551ebd83 DA |
2991 | r100_cs_track_texture_print(&track->textures[u]); |
2992 | return -EINVAL; | |
2993 | } | |
2994 | } | |
2995 | return 0; | |
2996 | } | |
2997 | ||
2998 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) | |
2999 | { | |
3000 | unsigned i; | |
3001 | unsigned long size; | |
3002 | unsigned prim_walk; | |
3003 | unsigned nverts; | |
3004 | ||
3005 | for (i = 0; i < track->num_cb; i++) { | |
3006 | if (track->cb[i].robj == NULL) { | |
46c64d4b MO |
3007 | if (!(track->fastfill || track->color_channel_mask || |
3008 | track->blend_read_enable)) { | |
3009 | continue; | |
3010 | } | |
551ebd83 DA |
3011 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
3012 | return -EINVAL; | |
3013 | } | |
3014 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; | |
3015 | size += track->cb[i].offset; | |
4c788679 | 3016 | if (size > radeon_bo_size(track->cb[i].robj)) { |
551ebd83 DA |
3017 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
3018 | "(need %lu have %lu) !\n", i, size, | |
4c788679 | 3019 | radeon_bo_size(track->cb[i].robj)); |
551ebd83 DA |
3020 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
3021 | i, track->cb[i].pitch, track->cb[i].cpp, | |
3022 | track->cb[i].offset, track->maxy); | |
3023 | return -EINVAL; | |
3024 | } | |
3025 | } | |
3026 | if (track->z_enabled) { | |
3027 | if (track->zb.robj == NULL) { | |
3028 | DRM_ERROR("[drm] No buffer for z buffer !\n"); | |
3029 | return -EINVAL; | |
3030 | } | |
3031 | size = track->zb.pitch * track->zb.cpp * track->maxy; | |
3032 | size += track->zb.offset; | |
4c788679 | 3033 | if (size > radeon_bo_size(track->zb.robj)) { |
551ebd83 DA |
3034 | DRM_ERROR("[drm] Buffer too small for z buffer " |
3035 | "(need %lu have %lu) !\n", size, | |
4c788679 | 3036 | radeon_bo_size(track->zb.robj)); |
551ebd83 DA |
3037 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", |
3038 | track->zb.pitch, track->zb.cpp, | |
3039 | track->zb.offset, track->maxy); | |
3040 | return -EINVAL; | |
3041 | } | |
3042 | } | |
3043 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; | |
cae94b0a MO |
3044 | if (track->vap_vf_cntl & (1 << 14)) { |
3045 | nverts = track->vap_alt_nverts; | |
3046 | } else { | |
3047 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; | |
3048 | } | |
551ebd83 DA |
3049 | switch (prim_walk) { |
3050 | case 1: | |
3051 | for (i = 0; i < track->num_arrays; i++) { | |
3052 | size = track->arrays[i].esize * track->max_indx * 4; | |
3053 | if (track->arrays[i].robj == NULL) { | |
3054 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
3055 | "bound\n", prim_walk, i); | |
3056 | return -EINVAL; | |
3057 | } | |
4c788679 JG |
3058 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
3059 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
3060 | "need %lu dwords have %lu dwords\n", | |
3061 | prim_walk, i, size >> 2, | |
3062 | radeon_bo_size(track->arrays[i].robj) | |
3063 | >> 2); | |
551ebd83 DA |
3064 | DRM_ERROR("Max indices %u\n", track->max_indx); |
3065 | return -EINVAL; | |
3066 | } | |
3067 | } | |
3068 | break; | |
3069 | case 2: | |
3070 | for (i = 0; i < track->num_arrays; i++) { | |
3071 | size = track->arrays[i].esize * (nverts - 1) * 4; | |
3072 | if (track->arrays[i].robj == NULL) { | |
3073 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
3074 | "bound\n", prim_walk, i); | |
3075 | return -EINVAL; | |
3076 | } | |
4c788679 JG |
3077 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
3078 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
3079 | "need %lu dwords have %lu dwords\n", | |
3080 | prim_walk, i, size >> 2, | |
3081 | radeon_bo_size(track->arrays[i].robj) | |
3082 | >> 2); | |
551ebd83 DA |
3083 | return -EINVAL; |
3084 | } | |
3085 | } | |
3086 | break; | |
3087 | case 3: | |
3088 | size = track->vtx_size * nverts; | |
3089 | if (size != track->immd_dwords) { | |
3090 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", | |
3091 | track->immd_dwords, size); | |
3092 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", | |
3093 | nverts, track->vtx_size); | |
3094 | return -EINVAL; | |
3095 | } | |
3096 | break; | |
3097 | default: | |
3098 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", | |
3099 | prim_walk); | |
3100 | return -EINVAL; | |
3101 | } | |
3102 | return r100_cs_track_texture_check(rdev, track); | |
3103 | } | |
3104 | ||
3105 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) | |
3106 | { | |
3107 | unsigned i, face; | |
3108 | ||
3109 | if (rdev->family < CHIP_R300) { | |
3110 | track->num_cb = 1; | |
3111 | if (rdev->family <= CHIP_RS200) | |
3112 | track->num_texture = 3; | |
3113 | else | |
3114 | track->num_texture = 6; | |
3115 | track->maxy = 2048; | |
3116 | track->separate_cube = 1; | |
3117 | } else { | |
3118 | track->num_cb = 4; | |
3119 | track->num_texture = 16; | |
3120 | track->maxy = 4096; | |
3121 | track->separate_cube = 0; | |
3122 | } | |
3123 | ||
3124 | for (i = 0; i < track->num_cb; i++) { | |
3125 | track->cb[i].robj = NULL; | |
3126 | track->cb[i].pitch = 8192; | |
3127 | track->cb[i].cpp = 16; | |
3128 | track->cb[i].offset = 0; | |
3129 | } | |
3130 | track->z_enabled = true; | |
3131 | track->zb.robj = NULL; | |
3132 | track->zb.pitch = 8192; | |
3133 | track->zb.cpp = 4; | |
3134 | track->zb.offset = 0; | |
3135 | track->vtx_size = 0x7F; | |
3136 | track->immd_dwords = 0xFFFFFFFFUL; | |
3137 | track->num_arrays = 11; | |
3138 | track->max_indx = 0x00FFFFFFUL; | |
3139 | for (i = 0; i < track->num_arrays; i++) { | |
3140 | track->arrays[i].robj = NULL; | |
3141 | track->arrays[i].esize = 0x7F; | |
3142 | } | |
3143 | for (i = 0; i < track->num_texture; i++) { | |
d785d78b | 3144 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
551ebd83 DA |
3145 | track->textures[i].pitch = 16536; |
3146 | track->textures[i].width = 16536; | |
3147 | track->textures[i].height = 16536; | |
3148 | track->textures[i].width_11 = 1 << 11; | |
3149 | track->textures[i].height_11 = 1 << 11; | |
3150 | track->textures[i].num_levels = 12; | |
3151 | if (rdev->family <= CHIP_RS200) { | |
3152 | track->textures[i].tex_coord_type = 0; | |
3153 | track->textures[i].txdepth = 0; | |
3154 | } else { | |
3155 | track->textures[i].txdepth = 16; | |
3156 | track->textures[i].tex_coord_type = 1; | |
3157 | } | |
3158 | track->textures[i].cpp = 64; | |
3159 | track->textures[i].robj = NULL; | |
3160 | /* CS IB emission code makes sure texture unit are disabled */ | |
3161 | track->textures[i].enabled = false; | |
3162 | track->textures[i].roundup_w = true; | |
3163 | track->textures[i].roundup_h = true; | |
3164 | if (track->separate_cube) | |
3165 | for (face = 0; face < 5; face++) { | |
3166 | track->textures[i].cube_info[face].robj = NULL; | |
3167 | track->textures[i].cube_info[face].width = 16536; | |
3168 | track->textures[i].cube_info[face].height = 16536; | |
3169 | track->textures[i].cube_info[face].offset = 0; | |
3170 | } | |
3171 | } | |
3172 | } | |
3ce0a23d JG |
3173 | |
3174 | int r100_ring_test(struct radeon_device *rdev) | |
3175 | { | |
3176 | uint32_t scratch; | |
3177 | uint32_t tmp = 0; | |
3178 | unsigned i; | |
3179 | int r; | |
3180 | ||
3181 | r = radeon_scratch_get(rdev, &scratch); | |
3182 | if (r) { | |
3183 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
3184 | return r; | |
3185 | } | |
3186 | WREG32(scratch, 0xCAFEDEAD); | |
3187 | r = radeon_ring_lock(rdev, 2); | |
3188 | if (r) { | |
3189 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
3190 | radeon_scratch_free(rdev, scratch); | |
3191 | return r; | |
3192 | } | |
3193 | radeon_ring_write(rdev, PACKET0(scratch, 0)); | |
3194 | radeon_ring_write(rdev, 0xDEADBEEF); | |
3195 | radeon_ring_unlock_commit(rdev); | |
3196 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3197 | tmp = RREG32(scratch); | |
3198 | if (tmp == 0xDEADBEEF) { | |
3199 | break; | |
3200 | } | |
3201 | DRM_UDELAY(1); | |
3202 | } | |
3203 | if (i < rdev->usec_timeout) { | |
3204 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
3205 | } else { | |
3206 | DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", | |
3207 | scratch, tmp); | |
3208 | r = -EINVAL; | |
3209 | } | |
3210 | radeon_scratch_free(rdev, scratch); | |
3211 | return r; | |
3212 | } | |
3213 | ||
3214 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
3215 | { | |
3216 | radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); | |
3217 | radeon_ring_write(rdev, ib->gpu_addr); | |
3218 | radeon_ring_write(rdev, ib->length_dw); | |
3219 | } | |
3220 | ||
3221 | int r100_ib_test(struct radeon_device *rdev) | |
3222 | { | |
3223 | struct radeon_ib *ib; | |
3224 | uint32_t scratch; | |
3225 | uint32_t tmp = 0; | |
3226 | unsigned i; | |
3227 | int r; | |
3228 | ||
3229 | r = radeon_scratch_get(rdev, &scratch); | |
3230 | if (r) { | |
3231 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
3232 | return r; | |
3233 | } | |
3234 | WREG32(scratch, 0xCAFEDEAD); | |
3235 | r = radeon_ib_get(rdev, &ib); | |
3236 | if (r) { | |
3237 | return r; | |
3238 | } | |
3239 | ib->ptr[0] = PACKET0(scratch, 0); | |
3240 | ib->ptr[1] = 0xDEADBEEF; | |
3241 | ib->ptr[2] = PACKET2(0); | |
3242 | ib->ptr[3] = PACKET2(0); | |
3243 | ib->ptr[4] = PACKET2(0); | |
3244 | ib->ptr[5] = PACKET2(0); | |
3245 | ib->ptr[6] = PACKET2(0); | |
3246 | ib->ptr[7] = PACKET2(0); | |
3247 | ib->length_dw = 8; | |
3248 | r = radeon_ib_schedule(rdev, ib); | |
3249 | if (r) { | |
3250 | radeon_scratch_free(rdev, scratch); | |
3251 | radeon_ib_free(rdev, &ib); | |
3252 | return r; | |
3253 | } | |
3254 | r = radeon_fence_wait(ib->fence, false); | |
3255 | if (r) { | |
3256 | return r; | |
3257 | } | |
3258 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3259 | tmp = RREG32(scratch); | |
3260 | if (tmp == 0xDEADBEEF) { | |
3261 | break; | |
3262 | } | |
3263 | DRM_UDELAY(1); | |
3264 | } | |
3265 | if (i < rdev->usec_timeout) { | |
3266 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
3267 | } else { | |
3268 | DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", | |
3269 | scratch, tmp); | |
3270 | r = -EINVAL; | |
3271 | } | |
3272 | radeon_scratch_free(rdev, scratch); | |
3273 | radeon_ib_free(rdev, &ib); | |
3274 | return r; | |
3275 | } | |
9f022ddf JG |
3276 | |
3277 | void r100_ib_fini(struct radeon_device *rdev) | |
3278 | { | |
3279 | radeon_ib_pool_fini(rdev); | |
3280 | } | |
3281 | ||
3282 | int r100_ib_init(struct radeon_device *rdev) | |
3283 | { | |
3284 | int r; | |
3285 | ||
3286 | r = radeon_ib_pool_init(rdev); | |
3287 | if (r) { | |
3288 | dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); | |
3289 | r100_ib_fini(rdev); | |
3290 | return r; | |
3291 | } | |
3292 | r = r100_ib_test(rdev); | |
3293 | if (r) { | |
3294 | dev_err(rdev->dev, "failled testing IB (%d).\n", r); | |
3295 | r100_ib_fini(rdev); | |
3296 | return r; | |
3297 | } | |
3298 | return 0; | |
3299 | } | |
3300 | ||
3301 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) | |
3302 | { | |
3303 | /* Shutdown CP we shouldn't need to do that but better be safe than | |
3304 | * sorry | |
3305 | */ | |
3306 | rdev->cp.ready = false; | |
3307 | WREG32(R_000740_CP_CSQ_CNTL, 0); | |
3308 | ||
3309 | /* Save few CRTC registers */ | |
ca6ffc64 | 3310 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
9f022ddf JG |
3311 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
3312 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); | |
3313 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); | |
3314 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3315 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); | |
3316 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); | |
3317 | } | |
3318 | ||
3319 | /* Disable VGA aperture access */ | |
ca6ffc64 | 3320 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
9f022ddf JG |
3321 | /* Disable cursor, overlay, crtc */ |
3322 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); | |
3323 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | | |
3324 | S_000054_CRTC_DISPLAY_DIS(1)); | |
3325 | WREG32(R_000050_CRTC_GEN_CNTL, | |
3326 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | | |
3327 | S_000050_CRTC_DISP_REQ_EN_B(1)); | |
3328 | WREG32(R_000420_OV0_SCALE_CNTL, | |
3329 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); | |
3330 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); | |
3331 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3332 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | | |
3333 | S_000360_CUR2_LOCK(1)); | |
3334 | WREG32(R_0003F8_CRTC2_GEN_CNTL, | |
3335 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | | |
3336 | S_0003F8_CRTC2_DISPLAY_DIS(1) | | |
3337 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); | |
3338 | WREG32(R_000360_CUR2_OFFSET, | |
3339 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); | |
3340 | } | |
3341 | } | |
3342 | ||
3343 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) | |
3344 | { | |
3345 | /* Update base address for crtc */ | |
d594e46a | 3346 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf | 3347 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
d594e46a | 3348 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf JG |
3349 | } |
3350 | /* Restore CRTC registers */ | |
ca6ffc64 | 3351 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
9f022ddf JG |
3352 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
3353 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); | |
3354 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3355 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); | |
3356 | } | |
3357 | } | |
ca6ffc64 JG |
3358 | |
3359 | void r100_vga_render_disable(struct radeon_device *rdev) | |
3360 | { | |
d4550907 | 3361 | u32 tmp; |
ca6ffc64 | 3362 | |
d4550907 | 3363 | tmp = RREG8(R_0003C2_GENMO_WT); |
ca6ffc64 JG |
3364 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
3365 | } | |
d4550907 JG |
3366 | |
3367 | static void r100_debugfs(struct radeon_device *rdev) | |
3368 | { | |
3369 | int r; | |
3370 | ||
3371 | r = r100_debugfs_mc_info_init(rdev); | |
3372 | if (r) | |
3373 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); | |
3374 | } | |
3375 | ||
3376 | static void r100_mc_program(struct radeon_device *rdev) | |
3377 | { | |
3378 | struct r100_mc_save save; | |
3379 | ||
3380 | /* Stops all mc clients */ | |
3381 | r100_mc_stop(rdev, &save); | |
3382 | if (rdev->flags & RADEON_IS_AGP) { | |
3383 | WREG32(R_00014C_MC_AGP_LOCATION, | |
3384 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
3385 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
3386 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
3387 | if (rdev->family > CHIP_RV200) | |
3388 | WREG32(R_00015C_AGP_BASE_2, | |
3389 | upper_32_bits(rdev->mc.agp_base) & 0xff); | |
3390 | } else { | |
3391 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); | |
3392 | WREG32(R_000170_AGP_BASE, 0); | |
3393 | if (rdev->family > CHIP_RV200) | |
3394 | WREG32(R_00015C_AGP_BASE_2, 0); | |
3395 | } | |
3396 | /* Wait for mc idle */ | |
3397 | if (r100_mc_wait_for_idle(rdev)) | |
3398 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); | |
3399 | /* Program MC, should be a 32bits limited address space */ | |
3400 | WREG32(R_000148_MC_FB_LOCATION, | |
3401 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | | |
3402 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
3403 | r100_mc_resume(rdev, &save); | |
3404 | } | |
3405 | ||
3406 | void r100_clock_startup(struct radeon_device *rdev) | |
3407 | { | |
3408 | u32 tmp; | |
3409 | ||
3410 | if (radeon_dynclks != -1 && radeon_dynclks) | |
3411 | radeon_legacy_set_clock_gating(rdev, 1); | |
3412 | /* We need to force on some of the block */ | |
3413 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | |
3414 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
3415 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) | |
3416 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); | |
3417 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | |
3418 | } | |
3419 | ||
3420 | static int r100_startup(struct radeon_device *rdev) | |
3421 | { | |
3422 | int r; | |
3423 | ||
92cde00c AD |
3424 | /* set common regs */ |
3425 | r100_set_common_regs(rdev); | |
3426 | /* program mc */ | |
d4550907 JG |
3427 | r100_mc_program(rdev); |
3428 | /* Resume clock */ | |
3429 | r100_clock_startup(rdev); | |
3430 | /* Initialize GPU configuration (# pipes, ...) */ | |
90aca4d2 | 3431 | // r100_gpu_init(rdev); |
d4550907 JG |
3432 | /* Initialize GART (initialize after TTM so we can allocate |
3433 | * memory through TTM but finalize after TTM) */ | |
17e15b0c | 3434 | r100_enable_bm(rdev); |
d4550907 JG |
3435 | if (rdev->flags & RADEON_IS_PCI) { |
3436 | r = r100_pci_gart_enable(rdev); | |
3437 | if (r) | |
3438 | return r; | |
3439 | } | |
3440 | /* Enable IRQ */ | |
d4550907 | 3441 | r100_irq_set(rdev); |
cafe6609 | 3442 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
d4550907 JG |
3443 | /* 1M ring buffer */ |
3444 | r = r100_cp_init(rdev, 1024 * 1024); | |
3445 | if (r) { | |
3446 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
3447 | return r; | |
3448 | } | |
3449 | r = r100_wb_init(rdev); | |
3450 | if (r) | |
3451 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
3452 | r = r100_ib_init(rdev); | |
3453 | if (r) { | |
3454 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
3455 | return r; | |
3456 | } | |
3457 | return 0; | |
3458 | } | |
3459 | ||
3460 | int r100_resume(struct radeon_device *rdev) | |
3461 | { | |
3462 | /* Make sur GART are not working */ | |
3463 | if (rdev->flags & RADEON_IS_PCI) | |
3464 | r100_pci_gart_disable(rdev); | |
3465 | /* Resume clock before doing reset */ | |
3466 | r100_clock_startup(rdev); | |
3467 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 3468 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
3469 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
3470 | RREG32(R_000E40_RBBM_STATUS), | |
3471 | RREG32(R_0007C0_CP_STAT)); | |
3472 | } | |
3473 | /* post */ | |
3474 | radeon_combios_asic_init(rdev->ddev); | |
3475 | /* Resume clock after posting */ | |
3476 | r100_clock_startup(rdev); | |
550e2d92 DA |
3477 | /* Initialize surface registers */ |
3478 | radeon_surface_init(rdev); | |
d4550907 JG |
3479 | return r100_startup(rdev); |
3480 | } | |
3481 | ||
3482 | int r100_suspend(struct radeon_device *rdev) | |
3483 | { | |
3484 | r100_cp_disable(rdev); | |
3485 | r100_wb_disable(rdev); | |
3486 | r100_irq_disable(rdev); | |
3487 | if (rdev->flags & RADEON_IS_PCI) | |
3488 | r100_pci_gart_disable(rdev); | |
3489 | return 0; | |
3490 | } | |
3491 | ||
3492 | void r100_fini(struct radeon_device *rdev) | |
3493 | { | |
29fb52ca | 3494 | radeon_pm_fini(rdev); |
d4550907 JG |
3495 | r100_cp_fini(rdev); |
3496 | r100_wb_fini(rdev); | |
3497 | r100_ib_fini(rdev); | |
3498 | radeon_gem_fini(rdev); | |
3499 | if (rdev->flags & RADEON_IS_PCI) | |
3500 | r100_pci_gart_fini(rdev); | |
d0269ed8 | 3501 | radeon_agp_fini(rdev); |
d4550907 JG |
3502 | radeon_irq_kms_fini(rdev); |
3503 | radeon_fence_driver_fini(rdev); | |
4c788679 | 3504 | radeon_bo_fini(rdev); |
d4550907 JG |
3505 | radeon_atombios_fini(rdev); |
3506 | kfree(rdev->bios); | |
3507 | rdev->bios = NULL; | |
3508 | } | |
3509 | ||
d4550907 JG |
3510 | int r100_init(struct radeon_device *rdev) |
3511 | { | |
3512 | int r; | |
3513 | ||
d4550907 JG |
3514 | /* Register debugfs file specific to this group of asics */ |
3515 | r100_debugfs(rdev); | |
3516 | /* Disable VGA */ | |
3517 | r100_vga_render_disable(rdev); | |
3518 | /* Initialize scratch registers */ | |
3519 | radeon_scratch_init(rdev); | |
3520 | /* Initialize surface registers */ | |
3521 | radeon_surface_init(rdev); | |
3522 | /* TODO: disable VGA need to use VGA request */ | |
3523 | /* BIOS*/ | |
3524 | if (!radeon_get_bios(rdev)) { | |
3525 | if (ASIC_IS_AVIVO(rdev)) | |
3526 | return -EINVAL; | |
3527 | } | |
3528 | if (rdev->is_atom_bios) { | |
3529 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); | |
3530 | return -EINVAL; | |
3531 | } else { | |
3532 | r = radeon_combios_init(rdev); | |
3533 | if (r) | |
3534 | return r; | |
3535 | } | |
3536 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 3537 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
3538 | dev_warn(rdev->dev, |
3539 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
3540 | RREG32(R_000E40_RBBM_STATUS), | |
3541 | RREG32(R_0007C0_CP_STAT)); | |
3542 | } | |
3543 | /* check if cards are posted or not */ | |
72542d77 DA |
3544 | if (radeon_boot_test_post_card(rdev) == false) |
3545 | return -EINVAL; | |
d4550907 JG |
3546 | /* Set asic errata */ |
3547 | r100_errata(rdev); | |
3548 | /* Initialize clocks */ | |
3549 | radeon_get_clock_info(rdev->ddev); | |
6234077d RM |
3550 | /* Initialize power management */ |
3551 | radeon_pm_init(rdev); | |
d594e46a JG |
3552 | /* initialize AGP */ |
3553 | if (rdev->flags & RADEON_IS_AGP) { | |
3554 | r = radeon_agp_init(rdev); | |
3555 | if (r) { | |
3556 | radeon_agp_disable(rdev); | |
3557 | } | |
3558 | } | |
3559 | /* initialize VRAM */ | |
3560 | r100_mc_init(rdev); | |
d4550907 JG |
3561 | /* Fence driver */ |
3562 | r = radeon_fence_driver_init(rdev); | |
3563 | if (r) | |
3564 | return r; | |
3565 | r = radeon_irq_kms_init(rdev); | |
3566 | if (r) | |
3567 | return r; | |
3568 | /* Memory manager */ | |
4c788679 | 3569 | r = radeon_bo_init(rdev); |
d4550907 JG |
3570 | if (r) |
3571 | return r; | |
3572 | if (rdev->flags & RADEON_IS_PCI) { | |
3573 | r = r100_pci_gart_init(rdev); | |
3574 | if (r) | |
3575 | return r; | |
3576 | } | |
3577 | r100_set_safe_registers(rdev); | |
3578 | rdev->accel_working = true; | |
3579 | r = r100_startup(rdev); | |
3580 | if (r) { | |
3581 | /* Somethings want wront with the accel init stop accel */ | |
3582 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
d4550907 JG |
3583 | r100_cp_fini(rdev); |
3584 | r100_wb_fini(rdev); | |
3585 | r100_ib_fini(rdev); | |
655efd3d | 3586 | radeon_irq_kms_fini(rdev); |
d4550907 JG |
3587 | if (rdev->flags & RADEON_IS_PCI) |
3588 | r100_pci_gart_fini(rdev); | |
d4550907 JG |
3589 | rdev->accel_working = false; |
3590 | } | |
3591 | return 0; | |
3592 | } |