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drm/radeon/kms: add rv530 R300_SU_REG_DEST + reloc for ZPASS_ADDR
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
32#include "radeon_microcode.h"
33#include "radeon_reg.h"
34#include "radeon.h"
35
36/* This files gather functions specifics to:
37 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
38 *
39 * Some of these functions might be used by newer ASICs.
40 */
41void r100_hdp_reset(struct radeon_device *rdev);
42void r100_gpu_init(struct radeon_device *rdev);
43int r100_gui_wait_for_idle(struct radeon_device *rdev);
44int r100_mc_wait_for_idle(struct radeon_device *rdev);
45void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
46void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
47int r100_debugfs_mc_info_init(struct radeon_device *rdev);
48
49
50/*
51 * PCI GART
52 */
53void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
54{
55 /* TODO: can we do somethings here ? */
56 /* It seems hw only cache one entry so we should discard this
57 * entry otherwise if first GPU GART read hit this entry it
58 * could end up in wrong address. */
59}
60
61int r100_pci_gart_enable(struct radeon_device *rdev)
62{
63 uint32_t tmp;
64 int r;
65
66 /* Initialize common gart structure */
67 r = radeon_gart_init(rdev);
68 if (r) {
69 return r;
70 }
71 if (rdev->gart.table.ram.ptr == NULL) {
72 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
73 r = radeon_gart_table_ram_alloc(rdev);
74 if (r) {
75 return r;
76 }
77 }
78 /* discard memory request outside of configured range */
79 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
80 WREG32(RADEON_AIC_CNTL, tmp);
81 /* set address range for PCI address translate */
82 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
83 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
84 WREG32(RADEON_AIC_HI_ADDR, tmp);
85 /* Enable bus mastering */
86 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
87 WREG32(RADEON_BUS_CNTL, tmp);
88 /* set PCI GART page-table base address */
89 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
90 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
91 WREG32(RADEON_AIC_CNTL, tmp);
92 r100_pci_gart_tlb_flush(rdev);
93 rdev->gart.ready = true;
94 return 0;
95}
96
97void r100_pci_gart_disable(struct radeon_device *rdev)
98{
99 uint32_t tmp;
100
101 /* discard memory request outside of configured range */
102 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
103 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
104 WREG32(RADEON_AIC_LO_ADDR, 0);
105 WREG32(RADEON_AIC_HI_ADDR, 0);
106}
107
108int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
109{
110 if (i < 0 || i > rdev->gart.num_gpu_pages) {
111 return -EINVAL;
112 }
ed10f95d 113 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 114 return 0;
115}
116
117int r100_gart_enable(struct radeon_device *rdev)
118{
119 if (rdev->flags & RADEON_IS_AGP) {
120 r100_pci_gart_disable(rdev);
121 return 0;
122 }
123 return r100_pci_gart_enable(rdev);
124}
125
126
127/*
128 * MC
129 */
130void r100_mc_disable_clients(struct radeon_device *rdev)
131{
132 uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
133
134 /* FIXME: is this function correct for rs100,rs200,rs300 ? */
135 if (r100_gui_wait_for_idle(rdev)) {
136 printk(KERN_WARNING "Failed to wait GUI idle while "
137 "programming pipes. Bad things might happen.\n");
138 }
139
140 /* stop display and memory access */
141 ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
142 WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
143 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
144 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
145 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
146
147 r100_gpu_wait_for_vsync(rdev);
148
149 WREG32(RADEON_CRTC_GEN_CNTL,
150 (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
151 RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
152
153 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
154 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
155
156 r100_gpu_wait_for_vsync2(rdev);
157 WREG32(RADEON_CRTC2_GEN_CNTL,
158 (crtc2_gen_cntl &
159 ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
160 RADEON_CRTC2_DISP_REQ_EN_B);
161 }
162
163 udelay(500);
164}
165
166void r100_mc_setup(struct radeon_device *rdev)
167{
168 uint32_t tmp;
169 int r;
170
171 r = r100_debugfs_mc_info_init(rdev);
172 if (r) {
173 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
174 }
175 /* Write VRAM size in case we are limiting it */
7a50f01a
DA		 176 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
177 /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
178 * if the aperture is 64MB but we have 32MB VRAM
179 * we report only 32MB VRAM but we have to set MC_FB_LOCATION
180 * to 64MB, otherwise the gpu accidentially dies */
181 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
771fe6b9
JG		 182 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
183 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
184 WREG32(RADEON_MC_FB_LOCATION, tmp);
185
186 /* Enable bus mastering */
187 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
188 WREG32(RADEON_BUS_CNTL, tmp);
189
190 if (rdev->flags & RADEON_IS_AGP) {
191 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
192 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
193 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
194 WREG32(RADEON_MC_AGP_LOCATION, tmp);
195 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
196 } else {
197 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
198 WREG32(RADEON_AGP_BASE, 0);
199 }
200
201 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
202 tmp |= (7 << 28);
203 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
204 (void)RREG32(RADEON_HOST_PATH_CNTL);
205 WREG32(RADEON_HOST_PATH_CNTL, tmp);
206 (void)RREG32(RADEON_HOST_PATH_CNTL);
207}
208
209int r100_mc_init(struct radeon_device *rdev)
210{
211 int r;
212
213 if (r100_debugfs_rbbm_init(rdev)) {
214 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
215 }
216
217 r100_gpu_init(rdev);
218 /* Disable gart which also disable out of gart access */
219 r100_pci_gart_disable(rdev);
220
221 /* Setup GPU memory space */
771fe6b9
JG		 222 rdev->mc.gtt_location = 0xFFFFFFFFUL;
223 if (rdev->flags & RADEON_IS_AGP) {
224 r = radeon_agp_init(rdev);
225 if (r) {
226 printk(KERN_WARNING "[drm] Disabling AGP\n");
227 rdev->flags &= ~RADEON_IS_AGP;
228 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
229 } else {
230 rdev->mc.gtt_location = rdev->mc.agp_base;
231 }
232 }
233 r = radeon_mc_setup(rdev);
234 if (r) {
235 return r;
236 }
237
238 r100_mc_disable_clients(rdev);
239 if (r100_mc_wait_for_idle(rdev)) {
240 printk(KERN_WARNING "Failed to wait MC idle while "
241 "programming pipes. Bad things might happen.\n");
242 }
243
244 r100_mc_setup(rdev);
245 return 0;
246}
247
248void r100_mc_fini(struct radeon_device *rdev)
249{
250 r100_pci_gart_disable(rdev);
251 radeon_gart_table_ram_free(rdev);
252 radeon_gart_fini(rdev);
253}
254
255
256/*
257 * Fence emission
258 */
259void r100_fence_ring_emit(struct radeon_device *rdev,
260 struct radeon_fence *fence)
261{
262 /* Who ever call radeon_fence_emit should call ring_lock and ask
263 * for enough space (today caller are ib schedule and buffer move) */
264 /* Wait until IDLE & CLEAN */
265 radeon_ring_write(rdev, PACKET0(0x1720, 0));
266 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
267 /* Emit fence sequence & fire IRQ */
268 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
269 radeon_ring_write(rdev, fence->seq);
270 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
271 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
272}
273
274
275/*
276 * Writeback
277 */
278int r100_wb_init(struct radeon_device *rdev)
279{
280 int r;
281
282 if (rdev->wb.wb_obj == NULL) {
283 r = radeon_object_create(rdev, NULL, 4096,
284 true,
285 RADEON_GEM_DOMAIN_GTT,
286 false, &rdev->wb.wb_obj);
287 if (r) {
288 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
289 return r;
290 }
291 r = radeon_object_pin(rdev->wb.wb_obj,
292 RADEON_GEM_DOMAIN_GTT,
293 &rdev->wb.gpu_addr);
294 if (r) {
295 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
296 return r;
297 }
298 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
299 if (r) {
300 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
301 return r;
302 }
303 }
304 WREG32(0x774, rdev->wb.gpu_addr);
305 WREG32(0x70C, rdev->wb.gpu_addr + 1024);
306 WREG32(0x770, 0xff);
307 return 0;
308}
309
310void r100_wb_fini(struct radeon_device *rdev)
311{
312 if (rdev->wb.wb_obj) {
313 radeon_object_kunmap(rdev->wb.wb_obj);
314 radeon_object_unpin(rdev->wb.wb_obj);
315 radeon_object_unref(&rdev->wb.wb_obj);
316 rdev->wb.wb = NULL;
317 rdev->wb.wb_obj = NULL;
318 }
319}
320
321int r100_copy_blit(struct radeon_device *rdev,
322 uint64_t src_offset,
323 uint64_t dst_offset,
324 unsigned num_pages,
325 struct radeon_fence *fence)
326{
327 uint32_t cur_pages;
328 uint32_t stride_bytes = PAGE_SIZE;
329 uint32_t pitch;
330 uint32_t stride_pixels;
331 unsigned ndw;
332 int num_loops;
333 int r = 0;
334
335 /* radeon limited to 16k stride */
336 stride_bytes &= 0x3fff;
337 /* radeon pitch is /64 */
338 pitch = stride_bytes / 64;
339 stride_pixels = stride_bytes / 4;
340 num_loops = DIV_ROUND_UP(num_pages, 8191);
341
342 /* Ask for enough room for blit + flush + fence */
343 ndw = 64 + (10 * num_loops);
344 r = radeon_ring_lock(rdev, ndw);
345 if (r) {
346 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
347 return -EINVAL;
348 }
349 while (num_pages > 0) {
350 cur_pages = num_pages;
351 if (cur_pages > 8191) {
352 cur_pages = 8191;
353 }
354 num_pages -= cur_pages;
355
356 /* pages are in Y direction - height
357 page width in X direction - width */
358 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
359 radeon_ring_write(rdev,
360 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
361 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
362 RADEON_GMC_SRC_CLIPPING |
363 RADEON_GMC_DST_CLIPPING |
364 RADEON_GMC_BRUSH_NONE |
365 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
366 RADEON_GMC_SRC_DATATYPE_COLOR |
367 RADEON_ROP3_S |
368 RADEON_DP_SRC_SOURCE_MEMORY |
369 RADEON_GMC_CLR_CMP_CNTL_DIS |
370 RADEON_GMC_WR_MSK_DIS);
371 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
372 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
373 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
374 radeon_ring_write(rdev, 0);
375 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
376 radeon_ring_write(rdev, num_pages);
377 radeon_ring_write(rdev, num_pages);
378 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
379 }
380 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
381 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
382 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
383 radeon_ring_write(rdev,
384 RADEON_WAIT_2D_IDLECLEAN |
385 RADEON_WAIT_HOST_IDLECLEAN |
386 RADEON_WAIT_DMA_GUI_IDLE);
387 if (fence) {
388 r = radeon_fence_emit(rdev, fence);
389 }
390 radeon_ring_unlock_commit(rdev);
391 return r;
392}
393
394
395/*
396 * CP
397 */
398void r100_ring_start(struct radeon_device *rdev)
399{
400 int r;
401
402 r = radeon_ring_lock(rdev, 2);
403 if (r) {
404 return;
405 }
406 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
407 radeon_ring_write(rdev,
408 RADEON_ISYNC_ANY2D_IDLE3D |
409 RADEON_ISYNC_ANY3D_IDLE2D |
410 RADEON_ISYNC_WAIT_IDLEGUI |
411 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
412 radeon_ring_unlock_commit(rdev);
413}
414
415static void r100_cp_load_microcode(struct radeon_device *rdev)
416{
417 int i;
418
419 if (r100_gui_wait_for_idle(rdev)) {
420 printk(KERN_WARNING "Failed to wait GUI idle while "
421 "programming pipes. Bad things might happen.\n");
422 }
423
424 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
425 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
426 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
427 (rdev->family == CHIP_RS200)) {
428 DRM_INFO("Loading R100 Microcode\n");
429 for (i = 0; i < 256; i++) {
430 WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
431 WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
432 }
433 } else if ((rdev->family == CHIP_R200) ||
434 (rdev->family == CHIP_RV250) ||
435 (rdev->family == CHIP_RV280) ||
436 (rdev->family == CHIP_RS300)) {
437 DRM_INFO("Loading R200 Microcode\n");
438 for (i = 0; i < 256; i++) {
439 WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
440 WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
441 }
442 } else if ((rdev->family == CHIP_R300) ||
443 (rdev->family == CHIP_R350) ||
444 (rdev->family == CHIP_RV350) ||
445 (rdev->family == CHIP_RV380) ||
446 (rdev->family == CHIP_RS400) ||
447 (rdev->family == CHIP_RS480)) {
448 DRM_INFO("Loading R300 Microcode\n");
449 for (i = 0; i < 256; i++) {
450 WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
451 WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
452 }
453 } else if ((rdev->family == CHIP_R420) ||
454 (rdev->family == CHIP_R423) ||
455 (rdev->family == CHIP_RV410)) {
456 DRM_INFO("Loading R400 Microcode\n");
457 for (i = 0; i < 256; i++) {
458 WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
459 WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
460 }
461 } else if ((rdev->family == CHIP_RS690) ||
462 (rdev->family == CHIP_RS740)) {
463 DRM_INFO("Loading RS690/RS740 Microcode\n");
464 for (i = 0; i < 256; i++) {
465 WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
466 WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
467 }
468 } else if (rdev->family == CHIP_RS600) {
469 DRM_INFO("Loading RS600 Microcode\n");
470 for (i = 0; i < 256; i++) {
471 WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
472 WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
473 }
474 } else if ((rdev->family == CHIP_RV515) ||
475 (rdev->family == CHIP_R520) ||
476 (rdev->family == CHIP_RV530) ||
477 (rdev->family == CHIP_R580) ||
478 (rdev->family == CHIP_RV560) ||
479 (rdev->family == CHIP_RV570)) {
480 DRM_INFO("Loading R500 Microcode\n");
481 for (i = 0; i < 256; i++) {
482 WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
483 WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
484 }
485 }
486}
487
488int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
489{
490 unsigned rb_bufsz;
491 unsigned rb_blksz;
492 unsigned max_fetch;
493 unsigned pre_write_timer;
494 unsigned pre_write_limit;
495 unsigned indirect2_start;
496 unsigned indirect1_start;
497 uint32_t tmp;
498 int r;
499
500 if (r100_debugfs_cp_init(rdev)) {
501 DRM_ERROR("Failed to register debugfs file for CP !\n");
502 }
503 /* Reset CP */
504 tmp = RREG32(RADEON_CP_CSQ_STAT);
505 if ((tmp & (1 << 31))) {
506 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
507 WREG32(RADEON_CP_CSQ_MODE, 0);
508 WREG32(RADEON_CP_CSQ_CNTL, 0);
509 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
510 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
511 mdelay(2);
512 WREG32(RADEON_RBBM_SOFT_RESET, 0);
513 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
514 mdelay(2);
515 tmp = RREG32(RADEON_CP_CSQ_STAT);
516 if ((tmp & (1 << 31))) {
517 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
518 }
519 } else {
520 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
521 }
522 /* Align ring size */
523 rb_bufsz = drm_order(ring_size / 8);
524 ring_size = (1 << (rb_bufsz + 1)) * 4;
525 r100_cp_load_microcode(rdev);
526 r = radeon_ring_init(rdev, ring_size);
527 if (r) {
528 return r;
529 }
530 /* Each time the cp read 1024 bytes (16 dword/quadword) update
531 * the rptr copy in system ram */
532 rb_blksz = 9;
533 /* cp will read 128bytes at a time (4 dwords) */
534 max_fetch = 1;
535 rdev->cp.align_mask = 16 - 1;
536 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
537 pre_write_timer = 64;
538 /* Force CP_RB_WPTR write if written more than one time before the
539 * delay expire
540 */
541 pre_write_limit = 0;
542 /* Setup the cp cache like this (cache size is 96 dwords) :
543 * RING 0 to 15
544 * INDIRECT1 16 to 79
545 * INDIRECT2 80 to 95
546 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
547 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
548 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
549 * Idea being that most of the gpu cmd will be through indirect1 buffer
550 * so it gets the bigger cache.
551 */
552 indirect2_start = 80;
553 indirect1_start = 16;
554 /* cp setup */
555 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
556 WREG32(RADEON_CP_RB_CNTL,
4e484e7d
MD		 557#ifdef __BIG_ENDIAN
558 RADEON_BUF_SWAP_32BIT |
559#endif
771fe6b9
JG		 560 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
561 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
562 REG_SET(RADEON_MAX_FETCH, max_fetch) |
563 RADEON_RB_NO_UPDATE);
564 /* Set ring address */
565 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
566 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
567 /* Force read & write ptr to 0 */
568 tmp = RREG32(RADEON_CP_RB_CNTL);
569 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
570 WREG32(RADEON_CP_RB_RPTR_WR, 0);
571 WREG32(RADEON_CP_RB_WPTR, 0);
572 WREG32(RADEON_CP_RB_CNTL, tmp);
573 udelay(10);
574 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
575 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
576 /* Set cp mode to bus mastering & enable cp*/
577 WREG32(RADEON_CP_CSQ_MODE,
578 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
579 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
580 WREG32(0x718, 0);
581 WREG32(0x744, 0x00004D4D);
582 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
583 radeon_ring_start(rdev);
584 r = radeon_ring_test(rdev);
585 if (r) {
586 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
587 return r;
588 }
589 rdev->cp.ready = true;
590 return 0;
591}
592
593void r100_cp_fini(struct radeon_device *rdev)
594{
595 /* Disable ring */
596 rdev->cp.ready = false;
597 WREG32(RADEON_CP_CSQ_CNTL, 0);
598 radeon_ring_fini(rdev);
599 DRM_INFO("radeon: cp finalized\n");
600}
601
602void r100_cp_disable(struct radeon_device *rdev)
603{
604 /* Disable ring */
605 rdev->cp.ready = false;
606 WREG32(RADEON_CP_CSQ_MODE, 0);
607 WREG32(RADEON_CP_CSQ_CNTL, 0);
608 if (r100_gui_wait_for_idle(rdev)) {
609 printk(KERN_WARNING "Failed to wait GUI idle while "
610 "programming pipes. Bad things might happen.\n");
611 }
612}
613
614int r100_cp_reset(struct radeon_device *rdev)
615{
616 uint32_t tmp;
617 bool reinit_cp;
618 int i;
619
620 reinit_cp = rdev->cp.ready;
621 rdev->cp.ready = false;
622 WREG32(RADEON_CP_CSQ_MODE, 0);
623 WREG32(RADEON_CP_CSQ_CNTL, 0);
624 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
625 (void)RREG32(RADEON_RBBM_SOFT_RESET);
626 udelay(200);
627 WREG32(RADEON_RBBM_SOFT_RESET, 0);
628 /* Wait to prevent race in RBBM_STATUS */
629 mdelay(1);
630 for (i = 0; i < rdev->usec_timeout; i++) {
631 tmp = RREG32(RADEON_RBBM_STATUS);
632 if (!(tmp & (1 << 16))) {
633 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
634 tmp);
635 if (reinit_cp) {
636 return r100_cp_init(rdev, rdev->cp.ring_size);
637 }
638 return 0;
639 }
640 DRM_UDELAY(1);
641 }
642 tmp = RREG32(RADEON_RBBM_STATUS);
643 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
644 return -1;
645}
646
647
648/*
649 * CS functions
650 */
651int r100_cs_parse_packet0(struct radeon_cs_parser *p,
652 struct radeon_cs_packet *pkt,
068a117c 653 const unsigned *auth, unsigned n,
771fe6b9
JG		 654 radeon_packet0_check_t check)
655{
656 unsigned reg;
657 unsigned i, j, m;
658 unsigned idx;
659 int r;
660
661 idx = pkt->idx + 1;
662 reg = pkt->reg;
068a117c
JG		 663 /* Check that register fall into register range
664 * determined by the number of entry (n) in the
665 * safe register bitmap.
666 */
771fe6b9
JG		 667 if (pkt->one_reg_wr) {
668 if ((reg >> 7) > n) {
669 return -EINVAL;
670 }
671 } else {
672 if (((reg + (pkt->count << 2)) >> 7) > n) {
673 return -EINVAL;
674 }
675 }
676 for (i = 0; i <= pkt->count; i++, idx++) {
677 j = (reg >> 7);
678 m = 1 << ((reg >> 2) & 31);
679 if (auth[j] & m) {
680 r = check(p, pkt, idx, reg);
681 if (r) {
682 return r;
683 }
684 }
685 if (pkt->one_reg_wr) {
686 if (!(auth[j] & m)) {
687 break;
688 }
689 } else {
690 reg += 4;
691 }
692 }
693 return 0;
694}
695
771fe6b9
JG		 696void r100_cs_dump_packet(struct radeon_cs_parser *p,
697 struct radeon_cs_packet *pkt)
698{
699 struct radeon_cs_chunk *ib_chunk;
700 volatile uint32_t *ib;
701 unsigned i;
702 unsigned idx;
703
704 ib = p->ib->ptr;
705 ib_chunk = &p->chunks[p->chunk_ib_idx];
706 idx = pkt->idx;
707 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
708 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
709 }
710}
711
712/**
713 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
714 * @parser: parser structure holding parsing context.
715 * @pkt: where to store packet informations
716 *
717 * Assume that chunk_ib_index is properly set. Will return -EINVAL
718 * if packet is bigger than remaining ib size. or if packets is unknown.
719 **/
720int r100_cs_packet_parse(struct radeon_cs_parser *p,
721 struct radeon_cs_packet *pkt,
722 unsigned idx)
723{
724 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 725 uint32_t header;
771fe6b9
JG		 726
727 if (idx >= ib_chunk->length_dw) {
728 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
729 idx, ib_chunk->length_dw);
730 return -EINVAL;
731 }
fa99239c 732 header = ib_chunk->kdata[idx];
771fe6b9
JG		 733 pkt->idx = idx;
734 pkt->type = CP_PACKET_GET_TYPE(header);
735 pkt->count = CP_PACKET_GET_COUNT(header);
736 switch (pkt->type) {
737 case PACKET_TYPE0:
738 pkt->reg = CP_PACKET0_GET_REG(header);
739 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
740 break;
741 case PACKET_TYPE3:
742 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
743 break;
744 case PACKET_TYPE2:
745 pkt->count = -1;
746 break;
747 default:
748 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
749 return -EINVAL;
750 }
751 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
752 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
753 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
754 return -EINVAL;
755 }
756 return 0;
757}
758
531369e6
DA		 759/**
760 * r100_cs_packet_next_vline() - parse userspace VLINE packet
761 * @parser: parser structure holding parsing context.
762 *
763 * Userspace sends a special sequence for VLINE waits.
764 * PACKET0 - VLINE_START_END + value
765 * PACKET0 - WAIT_UNTIL +_value
766 * RELOC (P3) - crtc_id in reloc.
767 *
768 * This function parses this and relocates the VLINE START END
769 * and WAIT UNTIL packets to the correct crtc.
770 * It also detects a switched off crtc and nulls out the
771 * wait in that case.
772 */
773int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
774{
775 struct radeon_cs_chunk *ib_chunk;
776 struct drm_mode_object *obj;
777 struct drm_crtc *crtc;
778 struct radeon_crtc *radeon_crtc;
779 struct radeon_cs_packet p3reloc, waitreloc;
780 int crtc_id;
781 int r;
782 uint32_t header, h_idx, reg;
783
784 ib_chunk = &p->chunks[p->chunk_ib_idx];
785
786 /* parse the wait until */
787 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
788 if (r)
789 return r;
790
791 /* check its a wait until and only 1 count */
792 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
793 waitreloc.count != 0) {
794 DRM_ERROR("vline wait had illegal wait until segment\n");
795 r = -EINVAL;
796 return r;
797 }
798
799 if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) {
800 DRM_ERROR("vline wait had illegal wait until\n");
801 r = -EINVAL;
802 return r;
803 }
804
805 /* jump over the NOP */
806 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
807 if (r)
808 return r;
809
810 h_idx = p->idx - 2;
811 p->idx += waitreloc.count;
812 p->idx += p3reloc.count;
813
814 header = ib_chunk->kdata[h_idx];
815 crtc_id = ib_chunk->kdata[h_idx + 5];
816 reg = ib_chunk->kdata[h_idx] >> 2;
817 mutex_lock(&p->rdev->ddev->mode_config.mutex);
818 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
819 if (!obj) {
820 DRM_ERROR("cannot find crtc %d\n", crtc_id);
821 r = -EINVAL;
822 goto out;
823 }
824 crtc = obj_to_crtc(obj);
825 radeon_crtc = to_radeon_crtc(crtc);
826 crtc_id = radeon_crtc->crtc_id;
827
828 if (!crtc->enabled) {
829 /* if the CRTC isn't enabled - we need to nop out the wait until */
830 ib_chunk->kdata[h_idx + 2] = PACKET2(0);
831 ib_chunk->kdata[h_idx + 3] = PACKET2(0);
832 } else if (crtc_id == 1) {
833 switch (reg) {
834 case AVIVO_D1MODE_VLINE_START_END:
835 header &= R300_CP_PACKET0_REG_MASK;
836 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
837 break;
838 case RADEON_CRTC_GUI_TRIG_VLINE:
839 header &= R300_CP_PACKET0_REG_MASK;
840 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
841 break;
842 default:
843 DRM_ERROR("unknown crtc reloc\n");
844 r = -EINVAL;
845 goto out;
846 }
847 ib_chunk->kdata[h_idx] = header;
848 ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
849 }
850out:
851 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
852 return r;
853}
854
771fe6b9
JG		 855/**
856 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
857 * @parser: parser structure holding parsing context.
858 * @data: pointer to relocation data
859 * @offset_start: starting offset
860 * @offset_mask: offset mask (to align start offset on)
861 * @reloc: reloc informations
862 *
863 * Check next packet is relocation packet3, do bo validation and compute
864 * GPU offset using the provided start.
865 **/
866int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
867 struct radeon_cs_reloc **cs_reloc)
868{
869 struct radeon_cs_chunk *ib_chunk;
870 struct radeon_cs_chunk *relocs_chunk;
871 struct radeon_cs_packet p3reloc;
872 unsigned idx;
873 int r;
874
875 if (p->chunk_relocs_idx == -1) {
876 DRM_ERROR("No relocation chunk !\n");
877 return -EINVAL;
878 }
879 *cs_reloc = NULL;
880 ib_chunk = &p->chunks[p->chunk_ib_idx];
881 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
882 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
883 if (r) {
884 return r;
885 }
886 p->idx += p3reloc.count + 2;
887 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
888 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
889 p3reloc.idx);
890 r100_cs_dump_packet(p, &p3reloc);
891 return -EINVAL;
892 }
893 idx = ib_chunk->kdata[p3reloc.idx + 1];
894 if (idx >= relocs_chunk->length_dw) {
895 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
896 idx, relocs_chunk->length_dw);
897 r100_cs_dump_packet(p, &p3reloc);
898 return -EINVAL;
899 }
900 /* FIXME: we assume reloc size is 4 dwords */
901 *cs_reloc = p->relocs_ptr[(idx / 4)];
902 return 0;
903}
904
905static int r100_packet0_check(struct radeon_cs_parser *p,
906 struct radeon_cs_packet *pkt)
907{
908 struct radeon_cs_chunk *ib_chunk;
909 struct radeon_cs_reloc *reloc;
910 volatile uint32_t *ib;
911 uint32_t tmp;
912 unsigned reg;
913 unsigned i;
914 unsigned idx;
915 bool onereg;
916 int r;
e024e110 917 u32 tile_flags = 0;
771fe6b9
JG		 918
919 ib = p->ib->ptr;
920 ib_chunk = &p->chunks[p->chunk_ib_idx];
921 idx = pkt->idx + 1;
922 reg = pkt->reg;
923 onereg = false;
924 if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
925 onereg = true;
926 }
927 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
928 switch (reg) {
531369e6
DA		 929 case RADEON_CRTC_GUI_TRIG_VLINE:
930 r = r100_cs_packet_parse_vline(p);
931 if (r) {
932 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
933 idx, reg);
934 r100_cs_dump_packet(p, pkt);
935 return r;
936 }
937 break;
771fe6b9
JG		 938 /* FIXME: only allow PACKET3 blit? easier to check for out of
939 * range access */
940 case RADEON_DST_PITCH_OFFSET:
941 case RADEON_SRC_PITCH_OFFSET:
942 r = r100_cs_packet_next_reloc(p, &reloc);
943 if (r) {
944 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
945 idx, reg);
946 r100_cs_dump_packet(p, pkt);
947 return r;
948 }
949 tmp = ib_chunk->kdata[idx] & 0x003fffff;
950 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
e024e110
DA		 951
952 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
953 tile_flags |= RADEON_DST_TILE_MACRO;
954 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
955 if (reg == RADEON_SRC_PITCH_OFFSET) {
956 DRM_ERROR("Cannot src blit from microtiled surface\n");
957 r100_cs_dump_packet(p, pkt);
958 return -EINVAL;
959 }
960 tile_flags |= RADEON_DST_TILE_MICRO;
961 }
962
963 tmp |= tile_flags;
964 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
771fe6b9
JG		 965 break;
966 case RADEON_RB3D_DEPTHOFFSET:
967 case RADEON_RB3D_COLOROFFSET:
968 case R300_RB3D_COLOROFFSET0:
969 case R300_ZB_DEPTHOFFSET:
970 case R200_PP_TXOFFSET_0:
971 case R200_PP_TXOFFSET_1:
972 case R200_PP_TXOFFSET_2:
973 case R200_PP_TXOFFSET_3:
974 case R200_PP_TXOFFSET_4:
975 case R200_PP_TXOFFSET_5:
976 case RADEON_PP_TXOFFSET_0:
977 case RADEON_PP_TXOFFSET_1:
978 case RADEON_PP_TXOFFSET_2:
979 case R300_TX_OFFSET_0:
980 case R300_TX_OFFSET_0+4:
981 case R300_TX_OFFSET_0+8:
982 case R300_TX_OFFSET_0+12:
983 case R300_TX_OFFSET_0+16:
984 case R300_TX_OFFSET_0+20:
985 case R300_TX_OFFSET_0+24:
986 case R300_TX_OFFSET_0+28:
987 case R300_TX_OFFSET_0+32:
988 case R300_TX_OFFSET_0+36:
989 case R300_TX_OFFSET_0+40:
990 case R300_TX_OFFSET_0+44:
991 case R300_TX_OFFSET_0+48:
992 case R300_TX_OFFSET_0+52:
993 case R300_TX_OFFSET_0+56:
994 case R300_TX_OFFSET_0+60:
b995e433
DA		 995 /* rn50 has no 3D engine so fail on any 3d setup */
996 if (ASIC_IS_RN50(p->rdev)) {
997 DRM_ERROR("attempt to use RN50 3D engine failed\n");
998 return -EINVAL;
999 }
771fe6b9
JG		 1000 r = r100_cs_packet_next_reloc(p, &reloc);
1001 if (r) {
1002 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1003 idx, reg);
1004 r100_cs_dump_packet(p, pkt);
1005 return r;
1006 }
1007 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1008 break;
e024e110
DA		 1009 case R300_RB3D_COLORPITCH0:
1010 case RADEON_RB3D_COLORPITCH:
1011 r = r100_cs_packet_next_reloc(p, &reloc);
1012 if (r) {
1013 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1014 idx, reg);
1015 r100_cs_dump_packet(p, pkt);
1016 return r;
1017 }
1018
1019 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1020 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1021 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1022 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1023
1024 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1025 tmp |= tile_flags;
1026 ib[idx] = tmp;
1027 break;
771fe6b9
JG		 1028 default:
1029 /* FIXME: we don't want to allow anyothers packet */
1030 break;
1031 }
1032 if (onereg) {
1033 /* FIXME: forbid onereg write to register on relocate */
1034 break;
1035 }
1036 }
1037 return 0;
1038}
1039
068a117c
JG		 1040int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1041 struct radeon_cs_packet *pkt,
1042 struct radeon_object *robj)
1043{
1044 struct radeon_cs_chunk *ib_chunk;
1045 unsigned idx;
1046
1047 ib_chunk = &p->chunks[p->chunk_ib_idx];
1048 idx = pkt->idx + 1;
1049 if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
1050 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1051 "(need %u have %lu) !\n",
1052 ib_chunk->kdata[idx+2] + 1,
1053 radeon_object_size(robj));
1054 return -EINVAL;
1055 }
1056 return 0;
1057}
1058
771fe6b9
JG		 1059static int r100_packet3_check(struct radeon_cs_parser *p,
1060 struct radeon_cs_packet *pkt)
1061{
1062 struct radeon_cs_chunk *ib_chunk;
1063 struct radeon_cs_reloc *reloc;
1064 unsigned idx;
1065 unsigned i, c;
1066 volatile uint32_t *ib;
1067 int r;
1068
1069 ib = p->ib->ptr;
1070 ib_chunk = &p->chunks[p->chunk_ib_idx];
1071 idx = pkt->idx + 1;
1072 switch (pkt->opcode) {
1073 case PACKET3_3D_LOAD_VBPNTR:
1074 c = ib_chunk->kdata[idx++];
1075 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1076 r = r100_cs_packet_next_reloc(p, &reloc);
1077 if (r) {
1078 DRM_ERROR("No reloc for packet3 %d\n",
1079 pkt->opcode);
1080 r100_cs_dump_packet(p, pkt);
1081 return r;
1082 }
1083 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1084 r = r100_cs_packet_next_reloc(p, &reloc);
1085 if (r) {
1086 DRM_ERROR("No reloc for packet3 %d\n",
1087 pkt->opcode);
1088 r100_cs_dump_packet(p, pkt);
1089 return r;
1090 }
1091 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1092 }
1093 if (c & 1) {
1094 r = r100_cs_packet_next_reloc(p, &reloc);
1095 if (r) {
1096 DRM_ERROR("No reloc for packet3 %d\n",
1097 pkt->opcode);
1098 r100_cs_dump_packet(p, pkt);
1099 return r;
1100 }
1101 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1102 }
1103 break;
1104 case PACKET3_INDX_BUFFER:
1105 r = r100_cs_packet_next_reloc(p, &reloc);
1106 if (r) {
1107 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1108 r100_cs_dump_packet(p, pkt);
1109 return r;
1110 }
1111 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1112 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1113 if (r) {
1114 return r;
1115 }
771fe6b9
JG		 1116 break;
1117 case 0x23:
1118 /* FIXME: cleanup */
1119 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1120 r = r100_cs_packet_next_reloc(p, &reloc);
1121 if (r) {
1122 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1123 r100_cs_dump_packet(p, pkt);
1124 return r;
1125 }
1126 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1127 break;
1128 case PACKET3_3D_DRAW_IMMD:
1129 /* triggers drawing using in-packet vertex data */
1130 case PACKET3_3D_DRAW_IMMD_2:
1131 /* triggers drawing using in-packet vertex data */
1132 case PACKET3_3D_DRAW_VBUF_2:
1133 /* triggers drawing of vertex buffers setup elsewhere */
1134 case PACKET3_3D_DRAW_INDX_2:
1135 /* triggers drawing using indices to vertex buffer */
1136 case PACKET3_3D_DRAW_VBUF:
1137 /* triggers drawing of vertex buffers setup elsewhere */
1138 case PACKET3_3D_DRAW_INDX:
1139 /* triggers drawing using indices to vertex buffer */
1140 case PACKET3_NOP:
1141 break;
1142 default:
1143 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1144 return -EINVAL;
1145 }
1146 return 0;
1147}
1148
1149int r100_cs_parse(struct radeon_cs_parser *p)
1150{
1151 struct radeon_cs_packet pkt;
1152 int r;
1153
1154 do {
1155 r = r100_cs_packet_parse(p, &pkt, p->idx);
1156 if (r) {
1157 return r;
1158 }
1159 p->idx += pkt.count + 2;
1160 switch (pkt.type) {
068a117c
JG		 1161 case PACKET_TYPE0:
1162 r = r100_packet0_check(p, &pkt);
1163 break;
1164 case PACKET_TYPE2:
1165 break;
1166 case PACKET_TYPE3:
1167 r = r100_packet3_check(p, &pkt);
1168 break;
1169 default:
1170 DRM_ERROR("Unknown packet type %d !\n",
1171 pkt.type);
1172 return -EINVAL;
771fe6b9
JG		 1173 }
1174 if (r) {
1175 return r;
1176 }
1177 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1178 return 0;
1179}
1180
1181
1182/*
1183 * Global GPU functions
1184 */
1185void r100_errata(struct radeon_device *rdev)
1186{
1187 rdev->pll_errata = 0;
1188
1189 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1190 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1191 }
1192
1193 if (rdev->family == CHIP_RV100 ||
1194 rdev->family == CHIP_RS100 ||
1195 rdev->family == CHIP_RS200) {
1196 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1197 }
1198}
1199
1200/* Wait for vertical sync on primary CRTC */
1201void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1202{
1203 uint32_t crtc_gen_cntl, tmp;
1204 int i;
1205
1206 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1207 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1208 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1209 return;
1210 }
1211 /* Clear the CRTC_VBLANK_SAVE bit */
1212 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1213 for (i = 0; i < rdev->usec_timeout; i++) {
1214 tmp = RREG32(RADEON_CRTC_STATUS);
1215 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1216 return;
1217 }
1218 DRM_UDELAY(1);
1219 }
1220}
1221
1222/* Wait for vertical sync on secondary CRTC */
1223void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1224{
1225 uint32_t crtc2_gen_cntl, tmp;
1226 int i;
1227
1228 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1229 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1230 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1231 return;
1232
1233 /* Clear the CRTC_VBLANK_SAVE bit */
1234 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1235 for (i = 0; i < rdev->usec_timeout; i++) {
1236 tmp = RREG32(RADEON_CRTC2_STATUS);
1237 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1238 return;
1239 }
1240 DRM_UDELAY(1);
1241 }
1242}
1243
1244int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1245{
1246 unsigned i;
1247 uint32_t tmp;
1248
1249 for (i = 0; i < rdev->usec_timeout; i++) {
1250 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1251 if (tmp >= n) {
1252 return 0;
1253 }
1254 DRM_UDELAY(1);
1255 }
1256 return -1;
1257}
1258
1259int r100_gui_wait_for_idle(struct radeon_device *rdev)
1260{
1261 unsigned i;
1262 uint32_t tmp;
1263
1264 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1265 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1266 " Bad things might happen.\n");
1267 }
1268 for (i = 0; i < rdev->usec_timeout; i++) {
1269 tmp = RREG32(RADEON_RBBM_STATUS);
1270 if (!(tmp & (1 << 31))) {
1271 return 0;
1272 }
1273 DRM_UDELAY(1);
1274 }
1275 return -1;
1276}
1277
1278int r100_mc_wait_for_idle(struct radeon_device *rdev)
1279{
1280 unsigned i;
1281 uint32_t tmp;
1282
1283 for (i = 0; i < rdev->usec_timeout; i++) {
1284 /* read MC_STATUS */
1285 tmp = RREG32(0x0150);
1286 if (tmp & (1 << 2)) {
1287 return 0;
1288 }
1289 DRM_UDELAY(1);
1290 }
1291 return -1;
1292}
1293
1294void r100_gpu_init(struct radeon_device *rdev)
1295{
1296 /* TODO: anythings to do here ? pipes ? */
1297 r100_hdp_reset(rdev);
1298}
1299
1300void r100_hdp_reset(struct radeon_device *rdev)
1301{
1302 uint32_t tmp;
1303
1304 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1305 tmp |= (7 << 28);
1306 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1307 (void)RREG32(RADEON_HOST_PATH_CNTL);
1308 udelay(200);
1309 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1310 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1311 (void)RREG32(RADEON_HOST_PATH_CNTL);
1312}
1313
1314int r100_rb2d_reset(struct radeon_device *rdev)
1315{
1316 uint32_t tmp;
1317 int i;
1318
1319 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1320 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1321 udelay(200);
1322 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1323 /* Wait to prevent race in RBBM_STATUS */
1324 mdelay(1);
1325 for (i = 0; i < rdev->usec_timeout; i++) {
1326 tmp = RREG32(RADEON_RBBM_STATUS);
1327 if (!(tmp & (1 << 26))) {
1328 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1329 tmp);
1330 return 0;
1331 }
1332 DRM_UDELAY(1);
1333 }
1334 tmp = RREG32(RADEON_RBBM_STATUS);
1335 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1336 return -1;
1337}
1338
1339int r100_gpu_reset(struct radeon_device *rdev)
1340{
1341 uint32_t status;
1342
1343 /* reset order likely matter */
1344 status = RREG32(RADEON_RBBM_STATUS);
1345 /* reset HDP */
1346 r100_hdp_reset(rdev);
1347 /* reset rb2d */
1348 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1349 r100_rb2d_reset(rdev);
1350 }
1351 /* TODO: reset 3D engine */
1352 /* reset CP */
1353 status = RREG32(RADEON_RBBM_STATUS);
1354 if (status & (1 << 16)) {
1355 r100_cp_reset(rdev);
1356 }
1357 /* Check if GPU is idle */
1358 status = RREG32(RADEON_RBBM_STATUS);
1359 if (status & (1 << 31)) {
1360 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1361 return -1;
1362 }
1363 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1364 return 0;
1365}
1366
1367
1368/*
1369 * VRAM info
1370 */
1371static void r100_vram_get_type(struct radeon_device *rdev)
1372{
1373 uint32_t tmp;
1374
1375 rdev->mc.vram_is_ddr = false;
1376 if (rdev->flags & RADEON_IS_IGP)
1377 rdev->mc.vram_is_ddr = true;
1378 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1379 rdev->mc.vram_is_ddr = true;
1380 if ((rdev->family == CHIP_RV100) ||
1381 (rdev->family == CHIP_RS100) ||
1382 (rdev->family == CHIP_RS200)) {
1383 tmp = RREG32(RADEON_MEM_CNTL);
1384 if (tmp & RV100_HALF_MODE) {
1385 rdev->mc.vram_width = 32;
1386 } else {
1387 rdev->mc.vram_width = 64;
1388 }
1389 if (rdev->flags & RADEON_SINGLE_CRTC) {
1390 rdev->mc.vram_width /= 4;
1391 rdev->mc.vram_is_ddr = true;
1392 }
1393 } else if (rdev->family <= CHIP_RV280) {
1394 tmp = RREG32(RADEON_MEM_CNTL);
1395 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1396 rdev->mc.vram_width = 128;
1397 } else {
1398 rdev->mc.vram_width = 64;
1399 }
1400 } else {
1401 /* newer IGPs */
1402 rdev->mc.vram_width = 128;
1403 }
1404}
1405
2a0f8918 1406static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1407{
2a0f8918
DA		 1408 u32 aper_size;
1409 u8 byte;
1410
1411 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1412
1413 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1414 * that is has the 2nd generation multifunction PCI interface
1415 */
1416 if (rdev->family == CHIP_RV280 ||
1417 rdev->family >= CHIP_RV350) {
1418 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1419 ~RADEON_HDP_APER_CNTL);
1420 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1421 return aper_size * 2;
1422 }
1423
1424 /* Older cards have all sorts of funny issues to deal with. First
1425 * check if it's a multifunction card by reading the PCI config
1426 * header type... Limit those to one aperture size
1427 */
1428 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1429 if (byte & 0x80) {
1430 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1431 DRM_INFO("Limiting VRAM to one aperture\n");
1432 return aper_size;
1433 }
1434
1435 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1436 * have set it up. We don't write this as it's broken on some ASICs but
1437 * we expect the BIOS to have done the right thing (might be too optimistic...)
1438 */
1439 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1440 return aper_size * 2;
1441 return aper_size;
1442}
1443
1444void r100_vram_init_sizes(struct radeon_device *rdev)
1445{
1446 u64 config_aper_size;
1447 u32 accessible;
1448
1449 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1450
1451 if (rdev->flags & RADEON_IS_IGP) {
1452 uint32_t tom;
1453 /* read NB_TOM to get the amount of ram stolen for the GPU */
1454 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1455 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1456 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1457 rdev->mc.vram_location = (tom & 0xffff) << 16;
7a50f01a
DA		 1458 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1459 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1460 } else {
7a50f01a 1461 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1462 /* Some production boards of m6 will report 0
1463 * if it's 8 MB
1464 */
7a50f01a
DA		 1465 if (rdev->mc.real_vram_size == 0) {
1466 rdev->mc.real_vram_size = 8192 * 1024;
1467 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1468 }
3e43d821
DA		 1469 /* let driver place VRAM */
1470 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1471 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1472 * Novell bug 204882 + along with lots of ubuntu ones */
7a50f01a
DA		 1473 if (config_aper_size > rdev->mc.real_vram_size)
1474 rdev->mc.mc_vram_size = config_aper_size;
1475 else
1476 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1477 }
1478
2a0f8918
DA		 1479 /* work out accessible VRAM */
1480 accessible = r100_get_accessible_vram(rdev);
1481
771fe6b9
JG		 1482 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1483 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1484
1485 if (accessible > rdev->mc.aper_size)
1486 accessible = rdev->mc.aper_size;
1487
7a50f01a
DA		 1488 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1489 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1490
1491 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1492 rdev->mc.real_vram_size = rdev->mc.aper_size;
2a0f8918
DA		 1493}
1494
1495void r100_vram_info(struct radeon_device *rdev)
1496{
1497 r100_vram_get_type(rdev);
1498
1499 r100_vram_init_sizes(rdev);
771fe6b9
JG		 1500}
1501
1502
1503/*
1504 * Indirect registers accessor
1505 */
1506void r100_pll_errata_after_index(struct radeon_device *rdev)
1507{
1508 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1509 return;
1510 }
1511 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1512 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1513}
1514
1515static void r100_pll_errata_after_data(struct radeon_device *rdev)
1516{
1517 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1518 * or the chip could hang on a subsequent access
1519 */
1520 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1521 udelay(5000);
1522 }
1523
1524 /* This function is required to workaround a hardware bug in some (all?)
1525 * revisions of the R300. This workaround should be called after every
1526 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1527 * may not be correct.
1528 */
1529 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1530 uint32_t save, tmp;
1531
1532 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1533 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1534 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1535 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1536 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1537 }
1538}
1539
1540uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1541{
1542 uint32_t data;
1543
1544 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1545 r100_pll_errata_after_index(rdev);
1546 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1547 r100_pll_errata_after_data(rdev);
1548 return data;
1549}
1550
1551void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1552{
1553 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1554 r100_pll_errata_after_index(rdev);
1555 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1556 r100_pll_errata_after_data(rdev);
1557}
1558
1559uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1560{
1561 if (reg < 0x10000)
1562 return readl(((void __iomem *)rdev->rmmio) + reg);
1563 else {
1564 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1565 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1566 }
1567}
1568
1569void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1570{
1571 if (reg < 0x10000)
1572 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1573 else {
1574 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1575 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1576 }
1577}
1578
068a117c
JG		 1579int r100_init(struct radeon_device *rdev)
1580{
1581 return 0;
1582}
1583
771fe6b9
JG		 1584/*
1585 * Debugfs info
1586 */
1587#if defined(CONFIG_DEBUG_FS)
1588static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1589{
1590 struct drm_info_node *node = (struct drm_info_node *) m->private;
1591 struct drm_device *dev = node->minor->dev;
1592 struct radeon_device *rdev = dev->dev_private;
1593 uint32_t reg, value;
1594 unsigned i;
1595
1596 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1597 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1598 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1599 for (i = 0; i < 64; i++) {
1600 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1601 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1602 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1603 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1604 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1605 }
1606 return 0;
1607}
1608
1609static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1610{
1611 struct drm_info_node *node = (struct drm_info_node *) m->private;
1612 struct drm_device *dev = node->minor->dev;
1613 struct radeon_device *rdev = dev->dev_private;
1614 uint32_t rdp, wdp;
1615 unsigned count, i, j;
1616
1617 radeon_ring_free_size(rdev);
1618 rdp = RREG32(RADEON_CP_RB_RPTR);
1619 wdp = RREG32(RADEON_CP_RB_WPTR);
1620 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1621 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1622 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1623 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1624 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1625 seq_printf(m, "%u dwords in ring\n", count);
1626 for (j = 0; j <= count; j++) {
1627 i = (rdp + j) & rdev->cp.ptr_mask;
1628 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1629 }
1630 return 0;
1631}
1632
1633
1634static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1635{
1636 struct drm_info_node *node = (struct drm_info_node *) m->private;
1637 struct drm_device *dev = node->minor->dev;
1638 struct radeon_device *rdev = dev->dev_private;
1639 uint32_t csq_stat, csq2_stat, tmp;
1640 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1641 unsigned i;
1642
1643 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1644 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1645 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1646 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1647 r_rptr = (csq_stat >> 0) & 0x3ff;
1648 r_wptr = (csq_stat >> 10) & 0x3ff;
1649 ib1_rptr = (csq_stat >> 20) & 0x3ff;
1650 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1651 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1652 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1653 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1654 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1655 seq_printf(m, "Ring rptr %u\n", r_rptr);
1656 seq_printf(m, "Ring wptr %u\n", r_wptr);
1657 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1658 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1659 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1660 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1661 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1662 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1663 seq_printf(m, "Ring fifo:\n");
1664 for (i = 0; i < 256; i++) {
1665 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1666 tmp = RREG32(RADEON_CP_CSQ_DATA);
1667 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1668 }
1669 seq_printf(m, "Indirect1 fifo:\n");
1670 for (i = 256; i <= 512; i++) {
1671 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1672 tmp = RREG32(RADEON_CP_CSQ_DATA);
1673 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1674 }
1675 seq_printf(m, "Indirect2 fifo:\n");
1676 for (i = 640; i < ib1_wptr; i++) {
1677 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1678 tmp = RREG32(RADEON_CP_CSQ_DATA);
1679 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1680 }
1681 return 0;
1682}
1683
1684static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1685{
1686 struct drm_info_node *node = (struct drm_info_node *) m->private;
1687 struct drm_device *dev = node->minor->dev;
1688 struct radeon_device *rdev = dev->dev_private;
1689 uint32_t tmp;
1690
1691 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1692 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1693 tmp = RREG32(RADEON_MC_FB_LOCATION);
1694 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1695 tmp = RREG32(RADEON_BUS_CNTL);
1696 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1697 tmp = RREG32(RADEON_MC_AGP_LOCATION);
1698 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1699 tmp = RREG32(RADEON_AGP_BASE);
1700 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1701 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1702 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1703 tmp = RREG32(0x01D0);
1704 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1705 tmp = RREG32(RADEON_AIC_LO_ADDR);
1706 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1707 tmp = RREG32(RADEON_AIC_HI_ADDR);
1708 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1709 tmp = RREG32(0x01E4);
1710 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1711 return 0;
1712}
1713
1714static struct drm_info_list r100_debugfs_rbbm_list[] = {
1715 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
1716};
1717
1718static struct drm_info_list r100_debugfs_cp_list[] = {
1719 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
1720 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
1721};
1722
1723static struct drm_info_list r100_debugfs_mc_info_list[] = {
1724 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
1725};
1726#endif
1727
1728int r100_debugfs_rbbm_init(struct radeon_device *rdev)
1729{
1730#if defined(CONFIG_DEBUG_FS)
1731 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
1732#else
1733 return 0;
1734#endif
1735}
1736
1737int r100_debugfs_cp_init(struct radeon_device *rdev)
1738{
1739#if defined(CONFIG_DEBUG_FS)
1740 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
1741#else
1742 return 0;
1743#endif
1744}
1745
1746int r100_debugfs_mc_info_init(struct radeon_device *rdev)
1747{
1748#if defined(CONFIG_DEBUG_FS)
1749 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
1750#else
1751 return 0;
1752#endif
1753}
e024e110
DA		 1754
1755int r100_set_surface_reg(struct radeon_device *rdev, int reg,
1756 uint32_t tiling_flags, uint32_t pitch,
1757 uint32_t offset, uint32_t obj_size)
1758{
1759 int surf_index = reg * 16;
1760 int flags = 0;
1761
1762 /* r100/r200 divide by 16 */
1763 if (rdev->family < CHIP_R300)
1764 flags = pitch / 16;
1765 else
1766 flags = pitch / 8;
1767
1768 if (rdev->family <= CHIP_RS200) {
1769 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
1770 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
1771 flags |= RADEON_SURF_TILE_COLOR_BOTH;
1772 if (tiling_flags & RADEON_TILING_MACRO)
1773 flags |= RADEON_SURF_TILE_COLOR_MACRO;
1774 } else if (rdev->family <= CHIP_RV280) {
1775 if (tiling_flags & (RADEON_TILING_MACRO))
1776 flags |= R200_SURF_TILE_COLOR_MACRO;
1777 if (tiling_flags & RADEON_TILING_MICRO)
1778 flags |= R200_SURF_TILE_COLOR_MICRO;
1779 } else {
1780 if (tiling_flags & RADEON_TILING_MACRO)
1781 flags |= R300_SURF_TILE_MACRO;
1782 if (tiling_flags & RADEON_TILING_MICRO)
1783 flags |= R300_SURF_TILE_MICRO;
1784 }
1785
1786 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1787 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
1788 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
1789 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
1790 return 0;
1791}
1792
1793void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
1794{
1795 int surf_index = reg * 16;
1796 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
1797}
c93bb85b
JG		 1798
1799void r100_bandwidth_update(struct radeon_device *rdev)
1800{
1801 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
1802 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
1803 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
1804 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
1805 fixed20_12 memtcas_ff[8] = {
1806 fixed_init(1),
1807 fixed_init(2),
1808 fixed_init(3),
1809 fixed_init(0),
1810 fixed_init_half(1),
1811 fixed_init_half(2),
1812 fixed_init(0),
1813 };
1814 fixed20_12 memtcas_rs480_ff[8] = {
1815 fixed_init(0),
1816 fixed_init(1),
1817 fixed_init(2),
1818 fixed_init(3),
1819 fixed_init(0),
1820 fixed_init_half(1),
1821 fixed_init_half(2),
1822 fixed_init_half(3),
1823 };
1824 fixed20_12 memtcas2_ff[8] = {
1825 fixed_init(0),
1826 fixed_init(1),
1827 fixed_init(2),
1828 fixed_init(3),
1829 fixed_init(4),
1830 fixed_init(5),
1831 fixed_init(6),
1832 fixed_init(7),
1833 };
1834 fixed20_12 memtrbs[8] = {
1835 fixed_init(1),
1836 fixed_init_half(1),
1837 fixed_init(2),
1838 fixed_init_half(2),
1839 fixed_init(3),
1840 fixed_init_half(3),
1841 fixed_init(4),
1842 fixed_init_half(4)
1843 };
1844 fixed20_12 memtrbs_r4xx[8] = {
1845 fixed_init(4),
1846 fixed_init(5),
1847 fixed_init(6),
1848 fixed_init(7),
1849 fixed_init(8),
1850 fixed_init(9),
1851 fixed_init(10),
1852 fixed_init(11)
1853 };
1854 fixed20_12 min_mem_eff;
1855 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
1856 fixed20_12 cur_latency_mclk, cur_latency_sclk;
1857 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
1858 disp_drain_rate2, read_return_rate;
1859 fixed20_12 time_disp1_drop_priority;
1860 int c;
1861 int cur_size = 16; /* in octawords */
1862 int critical_point = 0, critical_point2;
1863/* uint32_t read_return_rate, time_disp1_drop_priority; */
1864 int stop_req, max_stop_req;
1865 struct drm_display_mode *mode1 = NULL;
1866 struct drm_display_mode *mode2 = NULL;
1867 uint32_t pixel_bytes1 = 0;
1868 uint32_t pixel_bytes2 = 0;
1869
1870 if (rdev->mode_info.crtcs[0]->base.enabled) {
1871 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
1872 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
1873 }
1874 if (rdev->mode_info.crtcs[1]->base.enabled) {
1875 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
1876 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
1877 }
1878
1879 min_mem_eff.full = rfixed_const_8(0);
1880 /* get modes */
1881 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
1882 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
1883 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
1884 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
1885 /* check crtc enables */
1886 if (mode2)
1887 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
1888 if (mode1)
1889 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
1890 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
1891 }
1892
1893 /*
1894 * determine is there is enough bw for current mode
1895 */
1896 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
1897 temp_ff.full = rfixed_const(100);
1898 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
1899 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
1900 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
1901
1902 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
1903 temp_ff.full = rfixed_const(temp);
1904 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
1905
1906 pix_clk.full = 0;
1907 pix_clk2.full = 0;
1908 peak_disp_bw.full = 0;
1909 if (mode1) {
1910 temp_ff.full = rfixed_const(1000);
1911 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
1912 pix_clk.full = rfixed_div(pix_clk, temp_ff);
1913 temp_ff.full = rfixed_const(pixel_bytes1);
1914 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
1915 }
1916 if (mode2) {
1917 temp_ff.full = rfixed_const(1000);
1918 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
1919 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
1920 temp_ff.full = rfixed_const(pixel_bytes2);
1921 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
1922 }
1923
1924 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
1925 if (peak_disp_bw.full >= mem_bw.full) {
1926 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
1927 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
1928 }
1929
1930 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
1931 temp = RREG32(RADEON_MEM_TIMING_CNTL);
1932 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
1933 mem_trcd = ((temp >> 2) & 0x3) + 1;
1934 mem_trp = ((temp & 0x3)) + 1;
1935 mem_tras = ((temp & 0x70) >> 4) + 1;
1936 } else if (rdev->family == CHIP_R300 ||
1937 rdev->family == CHIP_R350) { /* r300, r350 */
1938 mem_trcd = (temp & 0x7) + 1;
1939 mem_trp = ((temp >> 8) & 0x7) + 1;
1940 mem_tras = ((temp >> 11) & 0xf) + 4;
1941 } else if (rdev->family == CHIP_RV350 ||
1942 rdev->family <= CHIP_RV380) {
1943 /* rv3x0 */
1944 mem_trcd = (temp & 0x7) + 3;
1945 mem_trp = ((temp >> 8) & 0x7) + 3;
1946 mem_tras = ((temp >> 11) & 0xf) + 6;
1947 } else if (rdev->family == CHIP_R420 ||
1948 rdev->family == CHIP_R423 ||
1949 rdev->family == CHIP_RV410) {
1950 /* r4xx */
1951 mem_trcd = (temp & 0xf) + 3;
1952 if (mem_trcd > 15)
1953 mem_trcd = 15;
1954 mem_trp = ((temp >> 8) & 0xf) + 3;
1955 if (mem_trp > 15)
1956 mem_trp = 15;
1957 mem_tras = ((temp >> 12) & 0x1f) + 6;
1958 if (mem_tras > 31)
1959 mem_tras = 31;
1960 } else { /* RV200, R200 */
1961 mem_trcd = (temp & 0x7) + 1;
1962 mem_trp = ((temp >> 8) & 0x7) + 1;
1963 mem_tras = ((temp >> 12) & 0xf) + 4;
1964 }
1965 /* convert to FF */
1966 trcd_ff.full = rfixed_const(mem_trcd);
1967 trp_ff.full = rfixed_const(mem_trp);
1968 tras_ff.full = rfixed_const(mem_tras);
1969
1970 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
1971 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
1972 data = (temp & (7 << 20)) >> 20;
1973 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
1974 if (rdev->family == CHIP_RS480) /* don't think rs400 */
1975 tcas_ff = memtcas_rs480_ff[data];
1976 else
1977 tcas_ff = memtcas_ff[data];
1978 } else
1979 tcas_ff = memtcas2_ff[data];
1980
1981 if (rdev->family == CHIP_RS400 ||
1982 rdev->family == CHIP_RS480) {
1983 /* extra cas latency stored in bits 23-25 0-4 clocks */
1984 data = (temp >> 23) & 0x7;
1985 if (data < 5)
1986 tcas_ff.full += rfixed_const(data);
1987 }
1988
1989 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
1990 /* on the R300, Tcas is included in Trbs.
1991 */
1992 temp = RREG32(RADEON_MEM_CNTL);
1993 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
1994 if (data == 1) {
1995 if (R300_MEM_USE_CD_CH_ONLY & temp) {
1996 temp = RREG32(R300_MC_IND_INDEX);
1997 temp &= ~R300_MC_IND_ADDR_MASK;
1998 temp |= R300_MC_READ_CNTL_CD_mcind;
1999 WREG32(R300_MC_IND_INDEX, temp);
2000 temp = RREG32(R300_MC_IND_DATA);
2001 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2002 } else {
2003 temp = RREG32(R300_MC_READ_CNTL_AB);
2004 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2005 }
2006 } else {
2007 temp = RREG32(R300_MC_READ_CNTL_AB);
2008 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2009 }
2010 if (rdev->family == CHIP_RV410 ||
2011 rdev->family == CHIP_R420 ||
2012 rdev->family == CHIP_R423)
2013 trbs_ff = memtrbs_r4xx[data];
2014 else
2015 trbs_ff = memtrbs[data];
2016 tcas_ff.full += trbs_ff.full;
2017 }
2018
2019 sclk_eff_ff.full = sclk_ff.full;
2020
2021 if (rdev->flags & RADEON_IS_AGP) {
2022 fixed20_12 agpmode_ff;
2023 agpmode_ff.full = rfixed_const(radeon_agpmode);
2024 temp_ff.full = rfixed_const_666(16);
2025 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2026 }
2027 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2028
2029 if (ASIC_IS_R300(rdev)) {
2030 sclk_delay_ff.full = rfixed_const(250);
2031 } else {
2032 if ((rdev->family == CHIP_RV100) ||
2033 rdev->flags & RADEON_IS_IGP) {
2034 if (rdev->mc.vram_is_ddr)
2035 sclk_delay_ff.full = rfixed_const(41);
2036 else
2037 sclk_delay_ff.full = rfixed_const(33);
2038 } else {
2039 if (rdev->mc.vram_width == 128)
2040 sclk_delay_ff.full = rfixed_const(57);
2041 else
2042 sclk_delay_ff.full = rfixed_const(41);
2043 }
2044 }
2045
2046 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2047
2048 if (rdev->mc.vram_is_ddr) {
2049 if (rdev->mc.vram_width == 32) {
2050 k1.full = rfixed_const(40);
2051 c = 3;
2052 } else {
2053 k1.full = rfixed_const(20);
2054 c = 1;
2055 }
2056 } else {
2057 k1.full = rfixed_const(40);
2058 c = 3;
2059 }
2060
2061 temp_ff.full = rfixed_const(2);
2062 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2063 temp_ff.full = rfixed_const(c);
2064 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2065 temp_ff.full = rfixed_const(4);
2066 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2067 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2068 mc_latency_mclk.full += k1.full;
2069
2070 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2071 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2072
2073 /*
2074 HW cursor time assuming worst case of full size colour cursor.
2075 */
2076 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2077 temp_ff.full += trcd_ff.full;
2078 if (temp_ff.full < tras_ff.full)
2079 temp_ff.full = tras_ff.full;
2080 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2081
2082 temp_ff.full = rfixed_const(cur_size);
2083 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2084 /*
2085 Find the total latency for the display data.
2086 */
2087 disp_latency_overhead.full = rfixed_const(80);
2088 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2089 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2090 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2091
2092 if (mc_latency_mclk.full > mc_latency_sclk.full)
2093 disp_latency.full = mc_latency_mclk.full;
2094 else
2095 disp_latency.full = mc_latency_sclk.full;
2096
2097 /* setup Max GRPH_STOP_REQ default value */
2098 if (ASIC_IS_RV100(rdev))
2099 max_stop_req = 0x5c;
2100 else
2101 max_stop_req = 0x7c;
2102
2103 if (mode1) {
2104 /* CRTC1
2105 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2106 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2107 */
2108 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2109
2110 if (stop_req > max_stop_req)
2111 stop_req = max_stop_req;
2112
2113 /*
2114 Find the drain rate of the display buffer.
2115 */
2116 temp_ff.full = rfixed_const((16/pixel_bytes1));
2117 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2118
2119 /*
2120 Find the critical point of the display buffer.
2121 */
2122 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2123 crit_point_ff.full += rfixed_const_half(0);
2124
2125 critical_point = rfixed_trunc(crit_point_ff);
2126
2127 if (rdev->disp_priority == 2) {
2128 critical_point = 0;
2129 }
2130
2131 /*
2132 The critical point should never be above max_stop_req-4. Setting
2133 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2134 */
2135 if (max_stop_req - critical_point < 4)
2136 critical_point = 0;
2137
2138 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2139 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2140 critical_point = 0x10;
2141 }
2142
2143 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2144 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2145 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2146 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2147 if ((rdev->family == CHIP_R350) &&
2148 (stop_req > 0x15)) {
2149 stop_req -= 0x10;
2150 }
2151 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2152 temp |= RADEON_GRPH_BUFFER_SIZE;
2153 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2154 RADEON_GRPH_CRITICAL_AT_SOF |
2155 RADEON_GRPH_STOP_CNTL);
2156 /*
2157 Write the result into the register.
2158 */
2159 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2160 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2161
2162#if 0
2163 if ((rdev->family == CHIP_RS400) ||
2164 (rdev->family == CHIP_RS480)) {
2165 /* attempt to program RS400 disp regs correctly ??? */
2166 temp = RREG32(RS400_DISP1_REG_CNTL);
2167 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2168 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2169 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2170 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2171 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2172 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2173 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2174 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2175 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2176 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2177 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2178 }
2179#endif
2180
2181 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2182 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2183 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2184 }
2185
2186 if (mode2) {
2187 u32 grph2_cntl;
2188 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2189
2190 if (stop_req > max_stop_req)
2191 stop_req = max_stop_req;
2192
2193 /*
2194 Find the drain rate of the display buffer.
2195 */
2196 temp_ff.full = rfixed_const((16/pixel_bytes2));
2197 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2198
2199 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2200 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2201 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2202 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2203 if ((rdev->family == CHIP_R350) &&
2204 (stop_req > 0x15)) {
2205 stop_req -= 0x10;
2206 }
2207 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2208 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2209 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2210 RADEON_GRPH_CRITICAL_AT_SOF |
2211 RADEON_GRPH_STOP_CNTL);
2212
2213 if ((rdev->family == CHIP_RS100) ||
2214 (rdev->family == CHIP_RS200))
2215 critical_point2 = 0;
2216 else {
2217 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2218 temp_ff.full = rfixed_const(temp);
2219 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2220 if (sclk_ff.full < temp_ff.full)
2221 temp_ff.full = sclk_ff.full;
2222
2223 read_return_rate.full = temp_ff.full;
2224
2225 if (mode1) {
2226 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2227 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2228 } else {
2229 time_disp1_drop_priority.full = 0;
2230 }
2231 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2232 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2233 crit_point_ff.full += rfixed_const_half(0);
2234
2235 critical_point2 = rfixed_trunc(crit_point_ff);
2236
2237 if (rdev->disp_priority == 2) {
2238 critical_point2 = 0;
2239 }
2240
2241 if (max_stop_req - critical_point2 < 4)
2242 critical_point2 = 0;
2243
2244 }
2245
2246 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2247 /* some R300 cards have problem with this set to 0 */
2248 critical_point2 = 0x10;
2249 }
2250
2251 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2252 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2253
2254 if ((rdev->family == CHIP_RS400) ||
2255 (rdev->family == CHIP_RS480)) {
2256#if 0
2257 /* attempt to program RS400 disp2 regs correctly ??? */
2258 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2259 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2260 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2261 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2262 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2263 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2264 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2265 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2266 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2267 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2268 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2269 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2270#endif
2271 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2272 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2273 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2274 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2275 }
2276
2277 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2278 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2279 }
2280}
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