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[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
44
551ebd83
DA		 45#include "r100_reg_safe.h"
46#include "rn50_reg_safe.h"
47
70967ab9
BH		 48/* Firmware Names */
49#define FIRMWARE_R100 "radeon/R100_cp.bin"
50#define FIRMWARE_R200 "radeon/R200_cp.bin"
51#define FIRMWARE_R300 "radeon/R300_cp.bin"
52#define FIRMWARE_R420 "radeon/R420_cp.bin"
53#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55#define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57MODULE_FIRMWARE(FIRMWARE_R100);
58MODULE_FIRMWARE(FIRMWARE_R200);
59MODULE_FIRMWARE(FIRMWARE_R300);
60MODULE_FIRMWARE(FIRMWARE_R420);
61MODULE_FIRMWARE(FIRMWARE_RS690);
62MODULE_FIRMWARE(FIRMWARE_RS600);
63MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 64
551ebd83
DA		 65#include "r100_track.h"
66
771fe6b9
JG		 67/* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 69 */
771fe6b9 70
cbdd4501
AK		 71int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
72 struct radeon_cs_packet *pkt,
73 unsigned idx,
74 unsigned reg)
75{
76 int r;
77 u32 tile_flags = 0;
78 u32 tmp;
79 struct radeon_cs_reloc *reloc;
80 u32 value;
81
82 r = r100_cs_packet_next_reloc(p, &reloc);
83 if (r) {
84 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
85 idx, reg);
86 r100_cs_dump_packet(p, pkt);
87 return r;
88 }
89 value = radeon_get_ib_value(p, idx);
90 tmp = value & 0x003fffff;
91 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
92
93 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
94 tile_flags |= RADEON_DST_TILE_MACRO;
95 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
96 if (reg == RADEON_SRC_PITCH_OFFSET) {
97 DRM_ERROR("Cannot src blit from microtiled surface\n");
98 r100_cs_dump_packet(p, pkt);
99 return -EINVAL;
100 }
101 tile_flags |= RADEON_DST_TILE_MICRO;
102 }
103
104 tmp |= tile_flags;
105 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
106 return 0;
107}
108
109int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
110 struct radeon_cs_packet *pkt,
111 int idx)
112{
113 unsigned c, i;
114 struct radeon_cs_reloc *reloc;
115 struct r100_cs_track *track;
116 int r = 0;
117 volatile uint32_t *ib;
118 u32 idx_value;
119
120 ib = p->ib->ptr;
121 track = (struct r100_cs_track *)p->track;
122 c = radeon_get_ib_value(p, idx++) & 0x1F;
123 if (c > 16) {
124 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
125 pkt->opcode);
126 r100_cs_dump_packet(p, pkt);
127 return -EINVAL;
128 }
129 track->num_arrays = c;
130 for (i = 0; i < (c - 1); i+=2, idx+=3) {
131 r = r100_cs_packet_next_reloc(p, &reloc);
132 if (r) {
133 DRM_ERROR("No reloc for packet3 %d\n",
134 pkt->opcode);
135 r100_cs_dump_packet(p, pkt);
136 return r;
137 }
138 idx_value = radeon_get_ib_value(p, idx);
139 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
140
141 track->arrays[i + 0].esize = idx_value >> 8;
142 track->arrays[i + 0].robj = reloc->robj;
143 track->arrays[i + 0].esize &= 0x7F;
144 r = r100_cs_packet_next_reloc(p, &reloc);
145 if (r) {
146 DRM_ERROR("No reloc for packet3 %d\n",
147 pkt->opcode);
148 r100_cs_dump_packet(p, pkt);
149 return r;
150 }
151 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
152 track->arrays[i + 1].robj = reloc->robj;
153 track->arrays[i + 1].esize = idx_value >> 24;
154 track->arrays[i + 1].esize &= 0x7F;
155 }
156 if (c & 1) {
157 r = r100_cs_packet_next_reloc(p, &reloc);
158 if (r) {
159 DRM_ERROR("No reloc for packet3 %d\n",
160 pkt->opcode);
161 r100_cs_dump_packet(p, pkt);
162 return r;
163 }
164 idx_value = radeon_get_ib_value(p, idx);
165 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
166 track->arrays[i + 0].robj = reloc->robj;
167 track->arrays[i + 0].esize = idx_value >> 8;
168 track->arrays[i + 0].esize &= 0x7F;
169 }
170 return r;
171}
172
6f34be50
AD		 173void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
174{
6f34be50
AD		 175 /* enable the pflip int */
176 radeon_irq_kms_pflip_irq_get(rdev, crtc);
177}
178
179void r100_post_page_flip(struct radeon_device *rdev, int crtc)
180{
181 /* disable the pflip int */
182 radeon_irq_kms_pflip_irq_put(rdev, crtc);
183}
184
185u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
186{
187 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
188 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
189
190 /* Lock the graphics update lock */
191 /* update the scanout addresses */
192 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
193
acb32506
AD		 194 /* Wait for update_pending to go high. */
195 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
196 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 197
198 /* Unlock the lock, so double-buffering can take place inside vblank */
199 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
200 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
201
202 /* Return current update_pending status: */
203 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
204}
205
ce8f5370 206void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 207{
208 int i;
ce8f5370
AD		 209 rdev->pm.dynpm_can_upclock = true;
210 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 211
ce8f5370
AD		 212 switch (rdev->pm.dynpm_planned_action) {
213 case DYNPM_ACTION_MINIMUM:
a48b9b4e 214 rdev->pm.requested_power_state_index = 0;
ce8f5370 215 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 216 break;
ce8f5370 217 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 218 if (rdev->pm.current_power_state_index == 0) {
219 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 220 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 221 } else {
222 if (rdev->pm.active_crtc_count > 1) {
223 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 224 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 225 continue;
226 else if (i >= rdev->pm.current_power_state_index) {
227 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
228 break;
229 } else {
230 rdev->pm.requested_power_state_index = i;
231 break;
232 }
233 }
234 } else
235 rdev->pm.requested_power_state_index =
236 rdev->pm.current_power_state_index - 1;
237 }
d7311171
AD		 238 /* don't use the power state if crtcs are active and no display flag is set */
239 if ((rdev->pm.active_crtc_count > 0) &&
240 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
241 RADEON_PM_MODE_NO_DISPLAY)) {
242 rdev->pm.requested_power_state_index++;
243 }
a48b9b4e 244 break;
ce8f5370 245 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 246 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
247 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 248 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 249 } else {
250 if (rdev->pm.active_crtc_count > 1) {
251 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 252 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 253 continue;
254 else if (i <= rdev->pm.current_power_state_index) {
255 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
256 break;
257 } else {
258 rdev->pm.requested_power_state_index = i;
259 break;
260 }
261 }
262 } else
263 rdev->pm.requested_power_state_index =
264 rdev->pm.current_power_state_index + 1;
265 }
266 break;
ce8f5370 267 case DYNPM_ACTION_DEFAULT:
58e21dff 268 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 269 rdev->pm.dynpm_can_upclock = false;
58e21dff 270 break;
ce8f5370 271 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 272 default:
273 DRM_ERROR("Requested mode for not defined action\n");
274 return;
275 }
276 /* only one clock mode per power state */
277 rdev->pm.requested_clock_mode_index = 0;
278
d9fdaafb 279 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 280 rdev->pm.power_state[rdev->pm.requested_power_state_index].
281 clock_info[rdev->pm.requested_clock_mode_index].sclk,
282 rdev->pm.power_state[rdev->pm.requested_power_state_index].
283 clock_info[rdev->pm.requested_clock_mode_index].mclk,
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 pcie_lanes);
a48b9b4e
AD		 286}
287
ce8f5370
AD		 288void r100_pm_init_profile(struct radeon_device *rdev)
289{
290 /* default */
291 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
292 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
293 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
294 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
295 /* low sh */
296 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 300 /* mid sh */
301 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 305 /* high sh */
306 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
308 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
310 /* low mh */
311 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
313 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 315 /* mid mh */
316 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 320 /* high mh */
321 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 325}
326
49e02b73
AD		 327void r100_pm_misc(struct radeon_device *rdev)
328{
49e02b73
AD		 329 int requested_index = rdev->pm.requested_power_state_index;
330 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
331 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
332 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
333
334 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
335 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
336 tmp = RREG32(voltage->gpio.reg);
337 if (voltage->active_high)
338 tmp |= voltage->gpio.mask;
339 else
340 tmp &= ~(voltage->gpio.mask);
341 WREG32(voltage->gpio.reg, tmp);
342 if (voltage->delay)
343 udelay(voltage->delay);
344 } else {
345 tmp = RREG32(voltage->gpio.reg);
346 if (voltage->active_high)
347 tmp &= ~voltage->gpio.mask;
348 else
349 tmp |= voltage->gpio.mask;
350 WREG32(voltage->gpio.reg, tmp);
351 if (voltage->delay)
352 udelay(voltage->delay);
353 }
354 }
355
356 sclk_cntl = RREG32_PLL(SCLK_CNTL);
357 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
358 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
359 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
360 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
361 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
362 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
363 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
364 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
365 else
366 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
367 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
368 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
369 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
370 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
371 } else
372 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
373
374 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
375 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
376 if (voltage->delay) {
377 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
378 switch (voltage->delay) {
379 case 33:
380 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
381 break;
382 case 66:
383 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
384 break;
385 case 99:
386 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
387 break;
388 case 132:
389 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
390 break;
391 }
392 } else
393 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
394 } else
395 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
396
397 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
398 sclk_cntl &= ~FORCE_HDP;
399 else
400 sclk_cntl |= FORCE_HDP;
401
402 WREG32_PLL(SCLK_CNTL, sclk_cntl);
403 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
404 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
405
406 /* set pcie lanes */
407 if ((rdev->flags & RADEON_IS_PCIE) &&
408 !(rdev->flags & RADEON_IS_IGP) &&
409 rdev->asic->set_pcie_lanes &&
410 (ps->pcie_lanes !=
411 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
412 radeon_set_pcie_lanes(rdev,
413 ps->pcie_lanes);
d9fdaafb 414 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 415 }
49e02b73
AD		 416}
417
418void r100_pm_prepare(struct radeon_device *rdev)
419{
420 struct drm_device *ddev = rdev->ddev;
421 struct drm_crtc *crtc;
422 struct radeon_crtc *radeon_crtc;
423 u32 tmp;
424
425 /* disable any active CRTCs */
426 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
427 radeon_crtc = to_radeon_crtc(crtc);
428 if (radeon_crtc->enabled) {
429 if (radeon_crtc->crtc_id) {
430 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
431 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
432 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
433 } else {
434 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
435 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
436 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
437 }
438 }
439 }
440}
441
442void r100_pm_finish(struct radeon_device *rdev)
443{
444 struct drm_device *ddev = rdev->ddev;
445 struct drm_crtc *crtc;
446 struct radeon_crtc *radeon_crtc;
447 u32 tmp;
448
449 /* enable any active CRTCs */
450 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
451 radeon_crtc = to_radeon_crtc(crtc);
452 if (radeon_crtc->enabled) {
453 if (radeon_crtc->crtc_id) {
454 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
455 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
456 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
457 } else {
458 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
459 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
460 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
461 }
462 }
463 }
464}
465
def9ba9c
AD		 466bool r100_gui_idle(struct radeon_device *rdev)
467{
468 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
469 return false;
470 else
471 return true;
472}
473
05a05c50
AD		 474/* hpd for digital panel detect/disconnect */
475bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
476{
477 bool connected = false;
478
479 switch (hpd) {
480 case RADEON_HPD_1:
481 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
482 connected = true;
483 break;
484 case RADEON_HPD_2:
485 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
486 connected = true;
487 break;
488 default:
489 break;
490 }
491 return connected;
492}
493
494void r100_hpd_set_polarity(struct radeon_device *rdev,
495 enum radeon_hpd_id hpd)
496{
497 u32 tmp;
498 bool connected = r100_hpd_sense(rdev, hpd);
499
500 switch (hpd) {
501 case RADEON_HPD_1:
502 tmp = RREG32(RADEON_FP_GEN_CNTL);
503 if (connected)
504 tmp &= ~RADEON_FP_DETECT_INT_POL;
505 else
506 tmp |= RADEON_FP_DETECT_INT_POL;
507 WREG32(RADEON_FP_GEN_CNTL, tmp);
508 break;
509 case RADEON_HPD_2:
510 tmp = RREG32(RADEON_FP2_GEN_CNTL);
511 if (connected)
512 tmp &= ~RADEON_FP2_DETECT_INT_POL;
513 else
514 tmp |= RADEON_FP2_DETECT_INT_POL;
515 WREG32(RADEON_FP2_GEN_CNTL, tmp);
516 break;
517 default:
518 break;
519 }
520}
521
522void r100_hpd_init(struct radeon_device *rdev)
523{
524 struct drm_device *dev = rdev->ddev;
525 struct drm_connector *connector;
526
527 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
528 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
529 switch (radeon_connector->hpd.hpd) {
530 case RADEON_HPD_1:
531 rdev->irq.hpd[0] = true;
532 break;
533 case RADEON_HPD_2:
534 rdev->irq.hpd[1] = true;
535 break;
536 default:
537 break;
538 }
539 }
003e69f9
JG		 540 if (rdev->irq.installed)
541 r100_irq_set(rdev);
05a05c50
AD		 542}
543
544void r100_hpd_fini(struct radeon_device *rdev)
545{
546 struct drm_device *dev = rdev->ddev;
547 struct drm_connector *connector;
548
549 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
550 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
551 switch (radeon_connector->hpd.hpd) {
552 case RADEON_HPD_1:
553 rdev->irq.hpd[0] = false;
554 break;
555 case RADEON_HPD_2:
556 rdev->irq.hpd[1] = false;
557 break;
558 default:
559 break;
560 }
561 }
562}
563
771fe6b9
JG		 564/*
565 * PCI GART
566 */
567void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
568{
569 /* TODO: can we do somethings here ? */
570 /* It seems hw only cache one entry so we should discard this
571 * entry otherwise if first GPU GART read hit this entry it
572 * could end up in wrong address. */
573}
574
4aac0473 575int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 576{
771fe6b9
JG		 577 int r;
578
4aac0473 579 if (rdev->gart.table.ram.ptr) {
fce7d61b 580 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 581 return 0;
582 }
771fe6b9
JG		 583 /* Initialize common gart structure */
584 r = radeon_gart_init(rdev);
4aac0473 585 if (r)
771fe6b9 586 return r;
4aac0473
JG		 587 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
588 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
589 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
590 return radeon_gart_table_ram_alloc(rdev);
591}
592
17e15b0c
DA		 593/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
594void r100_enable_bm(struct radeon_device *rdev)
595{
596 uint32_t tmp;
597 /* Enable bus mastering */
598 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
599 WREG32(RADEON_BUS_CNTL, tmp);
600}
601
4aac0473
JG		 602int r100_pci_gart_enable(struct radeon_device *rdev)
603{
604 uint32_t tmp;
605
82568565 606 radeon_gart_restore(rdev);
771fe6b9
JG		 607 /* discard memory request outside of configured range */
608 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
609 WREG32(RADEON_AIC_CNTL, tmp);
610 /* set address range for PCI address translate */
d594e46a
JG		 611 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
612 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 613 /* set PCI GART page-table base address */
614 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
615 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
616 WREG32(RADEON_AIC_CNTL, tmp);
617 r100_pci_gart_tlb_flush(rdev);
fcf4de5a
TV		 618 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
619 (unsigned)(rdev->mc.gtt_size >> 20),
620 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 621 rdev->gart.ready = true;
622 return 0;
623}
624
625void r100_pci_gart_disable(struct radeon_device *rdev)
626{
627 uint32_t tmp;
628
629 /* discard memory request outside of configured range */
630 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
631 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
632 WREG32(RADEON_AIC_LO_ADDR, 0);
633 WREG32(RADEON_AIC_HI_ADDR, 0);
634}
635
636int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
637{
638 if (i < 0 || i > rdev->gart.num_gpu_pages) {
639 return -EINVAL;
640 }
ed10f95d 641 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 642 return 0;
643}
644
4aac0473 645void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 646{
f9274562 647 radeon_gart_fini(rdev);
4aac0473
JG		 648 r100_pci_gart_disable(rdev);
649 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 650}
651
7ed220d7
MD		 652int r100_irq_set(struct radeon_device *rdev)
653{
654 uint32_t tmp = 0;
655
003e69f9 656 if (!rdev->irq.installed) {
fce7d61b 657 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 658 WREG32(R_000040_GEN_INT_CNTL, 0);
659 return -EINVAL;
660 }
7ed220d7
MD		 661 if (rdev->irq.sw_int) {
662 tmp |= RADEON_SW_INT_ENABLE;
663 }
2031f77c
AD		 664 if (rdev->irq.gui_idle) {
665 tmp |= RADEON_GUI_IDLE_MASK;
666 }
6f34be50
AD		 667 if (rdev->irq.crtc_vblank_int[0] ||
668 rdev->irq.pflip[0]) {
7ed220d7
MD		 669 tmp |= RADEON_CRTC_VBLANK_MASK;
670 }
6f34be50
AD		 671 if (rdev->irq.crtc_vblank_int[1] ||
672 rdev->irq.pflip[1]) {
7ed220d7
MD		 673 tmp |= RADEON_CRTC2_VBLANK_MASK;
674 }
05a05c50
AD		 675 if (rdev->irq.hpd[0]) {
676 tmp |= RADEON_FP_DETECT_MASK;
677 }
678 if (rdev->irq.hpd[1]) {
679 tmp |= RADEON_FP2_DETECT_MASK;
680 }
7ed220d7
MD		 681 WREG32(RADEON_GEN_INT_CNTL, tmp);
682 return 0;
683}
684
9f022ddf
JG		 685void r100_irq_disable(struct radeon_device *rdev)
686{
687 u32 tmp;
688
689 WREG32(R_000040_GEN_INT_CNTL, 0);
690 /* Wait and acknowledge irq */
691 mdelay(1);
692 tmp = RREG32(R_000044_GEN_INT_STATUS);
693 WREG32(R_000044_GEN_INT_STATUS, tmp);
694}
695
cbdd4501 696static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 697{
698 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 699 uint32_t irq_mask = RADEON_SW_INT_TEST |
700 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
701 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7 702
2031f77c
AD		 703 /* the interrupt works, but the status bit is permanently asserted */
704 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
705 if (!rdev->irq.gui_idle_acked)
706 irq_mask |= RADEON_GUI_IDLE_STAT;
707 }
708
7ed220d7
MD		 709 if (irqs) {
710 WREG32(RADEON_GEN_INT_STATUS, irqs);
711 }
712 return irqs & irq_mask;
713}
714
715int r100_irq_process(struct radeon_device *rdev)
716{
3e5cb98d 717 uint32_t status, msi_rearm;
d4877cf2 718 bool queue_hotplug = false;
7ed220d7 719
2031f77c
AD		 720 /* reset gui idle ack. the status bit is broken */
721 rdev->irq.gui_idle_acked = false;
722
7ed220d7
MD		 723 status = r100_irq_ack(rdev);
724 if (!status) {
725 return IRQ_NONE;
726 }
a513c184
JG		 727 if (rdev->shutdown) {
728 return IRQ_NONE;
729 }
7ed220d7
MD		 730 while (status) {
731 /* SW interrupt */
732 if (status & RADEON_SW_INT_TEST) {
733 radeon_fence_process(rdev);
734 }
2031f77c
AD		 735 /* gui idle interrupt */
736 if (status & RADEON_GUI_IDLE_STAT) {
737 rdev->irq.gui_idle_acked = true;
738 rdev->pm.gui_idle = true;
739 wake_up(&rdev->irq.idle_queue);
740 }
7ed220d7
MD		 741 /* Vertical blank interrupts */
742 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 743 if (rdev->irq.crtc_vblank_int[0]) {
744 drm_handle_vblank(rdev->ddev, 0);
745 rdev->pm.vblank_sync = true;
746 wake_up(&rdev->irq.vblank_queue);
747 }
3e4ea742
MK		 748 if (rdev->irq.pflip[0])
749 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 750 }
751 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 752 if (rdev->irq.crtc_vblank_int[1]) {
753 drm_handle_vblank(rdev->ddev, 1);
754 rdev->pm.vblank_sync = true;
755 wake_up(&rdev->irq.vblank_queue);
756 }
3e4ea742
MK		 757 if (rdev->irq.pflip[1])
758 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 759 }
05a05c50 760 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 761 queue_hotplug = true;
762 DRM_DEBUG("HPD1\n");
05a05c50
AD		 763 }
764 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 765 queue_hotplug = true;
766 DRM_DEBUG("HPD2\n");
05a05c50 767 }
7ed220d7
MD		 768 status = r100_irq_ack(rdev);
769 }
2031f77c
AD		 770 /* reset gui idle ack. the status bit is broken */
771 rdev->irq.gui_idle_acked = false;
d4877cf2 772 if (queue_hotplug)
32c87fca 773 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 774 if (rdev->msi_enabled) {
775 switch (rdev->family) {
776 case CHIP_RS400:
777 case CHIP_RS480:
778 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
779 WREG32(RADEON_AIC_CNTL, msi_rearm);
780 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
781 break;
782 default:
783 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
784 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
785 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
786 break;
787 }
788 }
7ed220d7
MD		 789 return IRQ_HANDLED;
790}
791
792u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
793{
794 if (crtc == 0)
795 return RREG32(RADEON_CRTC_CRNT_FRAME);
796 else
797 return RREG32(RADEON_CRTC2_CRNT_FRAME);
798}
799
9e5b2af7
PN		 800/* Who ever call radeon_fence_emit should call ring_lock and ask
801 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 802void r100_fence_ring_emit(struct radeon_device *rdev,
803 struct radeon_fence *fence)
804{
9e5b2af7
PN		 805 /* We have to make sure that caches are flushed before
806 * CPU might read something from VRAM. */
807 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
808 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
809 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
810 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 811 /* Wait until IDLE & CLEAN */
4612dc97
AD		 812 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
813 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 814 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
815 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
816 RADEON_HDP_READ_BUFFER_INVALIDATE);
817 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
818 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 819 /* Emit fence sequence & fire IRQ */
820 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
821 radeon_ring_write(rdev, fence->seq);
822 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
823 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
824}
825
771fe6b9
JG		 826int r100_copy_blit(struct radeon_device *rdev,
827 uint64_t src_offset,
828 uint64_t dst_offset,
829 unsigned num_pages,
830 struct radeon_fence *fence)
831{
832 uint32_t cur_pages;
833 uint32_t stride_bytes = PAGE_SIZE;
834 uint32_t pitch;
835 uint32_t stride_pixels;
836 unsigned ndw;
837 int num_loops;
838 int r = 0;
839
840 /* radeon limited to 16k stride */
841 stride_bytes &= 0x3fff;
842 /* radeon pitch is /64 */
843 pitch = stride_bytes / 64;
844 stride_pixels = stride_bytes / 4;
845 num_loops = DIV_ROUND_UP(num_pages, 8191);
846
847 /* Ask for enough room for blit + flush + fence */
848 ndw = 64 + (10 * num_loops);
849 r = radeon_ring_lock(rdev, ndw);
850 if (r) {
851 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
852 return -EINVAL;
853 }
854 while (num_pages > 0) {
855 cur_pages = num_pages;
856 if (cur_pages > 8191) {
857 cur_pages = 8191;
858 }
859 num_pages -= cur_pages;
860
861 /* pages are in Y direction - height
862 page width in X direction - width */
863 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
864 radeon_ring_write(rdev,
865 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
866 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
867 RADEON_GMC_SRC_CLIPPING |
868 RADEON_GMC_DST_CLIPPING |
869 RADEON_GMC_BRUSH_NONE |
870 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
871 RADEON_GMC_SRC_DATATYPE_COLOR |
872 RADEON_ROP3_S |
873 RADEON_DP_SRC_SOURCE_MEMORY |
874 RADEON_GMC_CLR_CMP_CNTL_DIS |
875 RADEON_GMC_WR_MSK_DIS);
876 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
877 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
878 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
879 radeon_ring_write(rdev, 0);
880 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
881 radeon_ring_write(rdev, num_pages);
882 radeon_ring_write(rdev, num_pages);
883 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
884 }
885 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
886 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
887 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
888 radeon_ring_write(rdev,
889 RADEON_WAIT_2D_IDLECLEAN |
890 RADEON_WAIT_HOST_IDLECLEAN |
891 RADEON_WAIT_DMA_GUI_IDLE);
892 if (fence) {
893 r = radeon_fence_emit(rdev, fence);
894 }
895 radeon_ring_unlock_commit(rdev);
896 return r;
897}
898
45600232
JG		 899static int r100_cp_wait_for_idle(struct radeon_device *rdev)
900{
901 unsigned i;
902 u32 tmp;
903
904 for (i = 0; i < rdev->usec_timeout; i++) {
905 tmp = RREG32(R_000E40_RBBM_STATUS);
906 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
907 return 0;
908 }
909 udelay(1);
910 }
911 return -1;
912}
913
771fe6b9
JG		 914void r100_ring_start(struct radeon_device *rdev)
915{
916 int r;
917
918 r = radeon_ring_lock(rdev, 2);
919 if (r) {
920 return;
921 }
922 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
923 radeon_ring_write(rdev,
924 RADEON_ISYNC_ANY2D_IDLE3D |
925 RADEON_ISYNC_ANY3D_IDLE2D |
926 RADEON_ISYNC_WAIT_IDLEGUI |
927 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
928 radeon_ring_unlock_commit(rdev);
929}
930
70967ab9
BH		 931
932/* Load the microcode for the CP */
933static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 934{
70967ab9
BH		 935 struct platform_device *pdev;
936 const char *fw_name = NULL;
937 int err;
771fe6b9 938
d9fdaafb 939 DRM_DEBUG_KMS("\n");
771fe6b9 940
70967ab9
BH		 941 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
942 err = IS_ERR(pdev);
943 if (err) {
944 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
945 return -EINVAL;
946 }
771fe6b9
JG		 947 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
948 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
949 (rdev->family == CHIP_RS200)) {
950 DRM_INFO("Loading R100 Microcode\n");
70967ab9 951 fw_name = FIRMWARE_R100;
771fe6b9
JG		 952 } else if ((rdev->family == CHIP_R200) ||
953 (rdev->family == CHIP_RV250) ||
954 (rdev->family == CHIP_RV280) ||
955 (rdev->family == CHIP_RS300)) {
956 DRM_INFO("Loading R200 Microcode\n");
70967ab9 957 fw_name = FIRMWARE_R200;
771fe6b9
JG		 958 } else if ((rdev->family == CHIP_R300) ||
959 (rdev->family == CHIP_R350) ||
960 (rdev->family == CHIP_RV350) ||
961 (rdev->family == CHIP_RV380) ||
962 (rdev->family == CHIP_RS400) ||
963 (rdev->family == CHIP_RS480)) {
964 DRM_INFO("Loading R300 Microcode\n");
70967ab9 965 fw_name = FIRMWARE_R300;
771fe6b9
JG		 966 } else if ((rdev->family == CHIP_R420) ||
967 (rdev->family == CHIP_R423) ||
968 (rdev->family == CHIP_RV410)) {
969 DRM_INFO("Loading R400 Microcode\n");
70967ab9 970 fw_name = FIRMWARE_R420;
771fe6b9
JG		 971 } else if ((rdev->family == CHIP_RS690) ||
972 (rdev->family == CHIP_RS740)) {
973 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 974 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 975 } else if (rdev->family == CHIP_RS600) {
976 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 977 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 978 } else if ((rdev->family == CHIP_RV515) ||
979 (rdev->family == CHIP_R520) ||
980 (rdev->family == CHIP_RV530) ||
981 (rdev->family == CHIP_R580) ||
982 (rdev->family == CHIP_RV560) ||
983 (rdev->family == CHIP_RV570)) {
984 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 985 fw_name = FIRMWARE_R520;
986 }
987
3ce0a23d 988 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 989 platform_device_unregister(pdev);
990 if (err) {
991 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
992 fw_name);
3ce0a23d 993 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 994 printk(KERN_ERR
995 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 996 rdev->me_fw->size, fw_name);
70967ab9 997 err = -EINVAL;
3ce0a23d
JG		 998 release_firmware(rdev->me_fw);
999 rdev->me_fw = NULL;
70967ab9
BH		 1000 }
1001 return err;
1002}
d4550907 1003
70967ab9
BH		 1004static void r100_cp_load_microcode(struct radeon_device *rdev)
1005{
1006 const __be32 *fw_data;
1007 int i, size;
1008
1009 if (r100_gui_wait_for_idle(rdev)) {
1010 printk(KERN_WARNING "Failed to wait GUI idle while "
1011 "programming pipes. Bad things might happen.\n");
1012 }
1013
3ce0a23d
JG		 1014 if (rdev->me_fw) {
1015 size = rdev->me_fw->size / 4;
1016 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1017 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1018 for (i = 0; i < size; i += 2) {
1019 WREG32(RADEON_CP_ME_RAM_DATAH,
1020 be32_to_cpup(&fw_data[i]));
1021 WREG32(RADEON_CP_ME_RAM_DATAL,
1022 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1023 }
1024 }
1025}
1026
1027int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1028{
1029 unsigned rb_bufsz;
1030 unsigned rb_blksz;
1031 unsigned max_fetch;
1032 unsigned pre_write_timer;
1033 unsigned pre_write_limit;
1034 unsigned indirect2_start;
1035 unsigned indirect1_start;
1036 uint32_t tmp;
1037 int r;
1038
1039 if (r100_debugfs_cp_init(rdev)) {
1040 DRM_ERROR("Failed to register debugfs file for CP !\n");
1041 }
3ce0a23d 1042 if (!rdev->me_fw) {
70967ab9
BH		 1043 r = r100_cp_init_microcode(rdev);
1044 if (r) {
1045 DRM_ERROR("Failed to load firmware!\n");
1046 return r;
1047 }
1048 }
1049
771fe6b9
JG		 1050 /* Align ring size */
1051 rb_bufsz = drm_order(ring_size / 8);
1052 ring_size = (1 << (rb_bufsz + 1)) * 4;
1053 r100_cp_load_microcode(rdev);
1054 r = radeon_ring_init(rdev, ring_size);
1055 if (r) {
1056 return r;
1057 }
1058 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1059 * the rptr copy in system ram */
1060 rb_blksz = 9;
1061 /* cp will read 128bytes at a time (4 dwords) */
1062 max_fetch = 1;
1063 rdev->cp.align_mask = 16 - 1;
1064 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1065 pre_write_timer = 64;
1066 /* Force CP_RB_WPTR write if written more than one time before the
1067 * delay expire
1068 */
1069 pre_write_limit = 0;
1070 /* Setup the cp cache like this (cache size is 96 dwords) :
1071 * RING 0 to 15
1072 * INDIRECT1 16 to 79
1073 * INDIRECT2 80 to 95
1074 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1075 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1076 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1077 * Idea being that most of the gpu cmd will be through indirect1 buffer
1078 * so it gets the bigger cache.
1079 */
1080 indirect2_start = 80;
1081 indirect1_start = 16;
1082 /* cp setup */
1083 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1084 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1085 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1086 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1087#ifdef __BIG_ENDIAN
1088 tmp |= RADEON_BUF_SWAP_32BIT;
1089#endif
724c80e1 1090 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1091
771fe6b9
JG		 1092 /* Set ring address */
1093 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1094 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1095 /* Force read & write ptr to 0 */
724c80e1 1096 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9
JG		 1097 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1098 WREG32(RADEON_CP_RB_WPTR, 0);
724c80e1
AD		 1099
1100 /* set the wb address whether it's enabled or not */
1101 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1102 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1103 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1104
1105 if (rdev->wb.enabled)
1106 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1107 else {
1108 tmp |= RADEON_RB_NO_UPDATE;
1109 WREG32(R_000770_SCRATCH_UMSK, 0);
1110 }
1111
771fe6b9
JG		 1112 WREG32(RADEON_CP_RB_CNTL, tmp);
1113 udelay(10);
1114 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1115 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
9e5786bd
DA		 1116 /* protect against crazy HW on resume */
1117 rdev->cp.wptr &= rdev->cp.ptr_mask;
771fe6b9
JG		 1118 /* Set cp mode to bus mastering & enable cp*/
1119 WREG32(RADEON_CP_CSQ_MODE,
1120 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1121 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1122 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1123 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9
JG		 1124 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1125 radeon_ring_start(rdev);
1126 r = radeon_ring_test(rdev);
1127 if (r) {
1128 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1129 return r;
1130 }
1131 rdev->cp.ready = true;
53595338 1132 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
771fe6b9
JG		 1133 return 0;
1134}
1135
1136void r100_cp_fini(struct radeon_device *rdev)
1137{
45600232
JG		 1138 if (r100_cp_wait_for_idle(rdev)) {
1139 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1140 }
771fe6b9 1141 /* Disable ring */
a18d7ea1 1142 r100_cp_disable(rdev);
771fe6b9
JG		 1143 radeon_ring_fini(rdev);
1144 DRM_INFO("radeon: cp finalized\n");
1145}
1146
1147void r100_cp_disable(struct radeon_device *rdev)
1148{
1149 /* Disable ring */
53595338 1150 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
771fe6b9
JG		 1151 rdev->cp.ready = false;
1152 WREG32(RADEON_CP_CSQ_MODE, 0);
1153 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1154 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1155 if (r100_gui_wait_for_idle(rdev)) {
1156 printk(KERN_WARNING "Failed to wait GUI idle while "
1157 "programming pipes. Bad things might happen.\n");
1158 }
1159}
1160
3ce0a23d
JG		 1161void r100_cp_commit(struct radeon_device *rdev)
1162{
1163 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1164 (void)RREG32(RADEON_CP_RB_WPTR);
1165}
1166
771fe6b9
JG		 1167
1168/*
1169 * CS functions
1170 */
1171int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1172 struct radeon_cs_packet *pkt,
068a117c 1173 const unsigned *auth, unsigned n,
771fe6b9
JG		 1174 radeon_packet0_check_t check)
1175{
1176 unsigned reg;
1177 unsigned i, j, m;
1178 unsigned idx;
1179 int r;
1180
1181 idx = pkt->idx + 1;
1182 reg = pkt->reg;
068a117c
JG		 1183 /* Check that register fall into register range
1184 * determined by the number of entry (n) in the
1185 * safe register bitmap.
1186 */
771fe6b9
JG		 1187 if (pkt->one_reg_wr) {
1188 if ((reg >> 7) > n) {
1189 return -EINVAL;
1190 }
1191 } else {
1192 if (((reg + (pkt->count << 2)) >> 7) > n) {
1193 return -EINVAL;
1194 }
1195 }
1196 for (i = 0; i <= pkt->count; i++, idx++) {
1197 j = (reg >> 7);
1198 m = 1 << ((reg >> 2) & 31);
1199 if (auth[j] & m) {
1200 r = check(p, pkt, idx, reg);
1201 if (r) {
1202 return r;
1203 }
1204 }
1205 if (pkt->one_reg_wr) {
1206 if (!(auth[j] & m)) {
1207 break;
1208 }
1209 } else {
1210 reg += 4;
1211 }
1212 }
1213 return 0;
1214}
1215
771fe6b9
JG		 1216void r100_cs_dump_packet(struct radeon_cs_parser *p,
1217 struct radeon_cs_packet *pkt)
1218{
771fe6b9
JG		 1219 volatile uint32_t *ib;
1220 unsigned i;
1221 unsigned idx;
1222
1223 ib = p->ib->ptr;
771fe6b9
JG		 1224 idx = pkt->idx;
1225 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1226 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1227 }
1228}
1229
1230/**
1231 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1232 * @parser: parser structure holding parsing context.
1233 * @pkt: where to store packet informations
1234 *
1235 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1236 * if packet is bigger than remaining ib size. or if packets is unknown.
1237 **/
1238int r100_cs_packet_parse(struct radeon_cs_parser *p,
1239 struct radeon_cs_packet *pkt,
1240 unsigned idx)
1241{
1242 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1243 uint32_t header;
771fe6b9
JG		 1244
1245 if (idx >= ib_chunk->length_dw) {
1246 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1247 idx, ib_chunk->length_dw);
1248 return -EINVAL;
1249 }
513bcb46 1250 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1251 pkt->idx = idx;
1252 pkt->type = CP_PACKET_GET_TYPE(header);
1253 pkt->count = CP_PACKET_GET_COUNT(header);
1254 switch (pkt->type) {
1255 case PACKET_TYPE0:
1256 pkt->reg = CP_PACKET0_GET_REG(header);
1257 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1258 break;
1259 case PACKET_TYPE3:
1260 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1261 break;
1262 case PACKET_TYPE2:
1263 pkt->count = -1;
1264 break;
1265 default:
1266 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1267 return -EINVAL;
1268 }
1269 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1270 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1271 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1272 return -EINVAL;
1273 }
1274 return 0;
1275}
1276
531369e6
DA		 1277/**
1278 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1279 * @parser: parser structure holding parsing context.
1280 *
1281 * Userspace sends a special sequence for VLINE waits.
1282 * PACKET0 - VLINE_START_END + value
1283 * PACKET0 - WAIT_UNTIL +_value
1284 * RELOC (P3) - crtc_id in reloc.
1285 *
1286 * This function parses this and relocates the VLINE START END
1287 * and WAIT UNTIL packets to the correct crtc.
1288 * It also detects a switched off crtc and nulls out the
1289 * wait in that case.
1290 */
1291int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1292{
531369e6
DA		 1293 struct drm_mode_object *obj;
1294 struct drm_crtc *crtc;
1295 struct radeon_crtc *radeon_crtc;
1296 struct radeon_cs_packet p3reloc, waitreloc;
1297 int crtc_id;
1298 int r;
1299 uint32_t header, h_idx, reg;
513bcb46 1300 volatile uint32_t *ib;
531369e6 1301
513bcb46 1302 ib = p->ib->ptr;
531369e6
DA		 1303
1304 /* parse the wait until */
1305 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1306 if (r)
1307 return r;
1308
1309 /* check its a wait until and only 1 count */
1310 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1311 waitreloc.count != 0) {
1312 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1313 return -EINVAL;
531369e6
DA		 1314 }
1315
513bcb46 1316 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1317 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1318 return -EINVAL;
531369e6
DA		 1319 }
1320
1321 /* jump over the NOP */
90ebd065 1322 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1323 if (r)
1324 return r;
1325
1326 h_idx = p->idx - 2;
90ebd065
AD		 1327 p->idx += waitreloc.count + 2;
1328 p->idx += p3reloc.count + 2;
531369e6 1329
513bcb46
DA		 1330 header = radeon_get_ib_value(p, h_idx);
1331 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1332 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1333 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1334 if (!obj) {
1335 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1336 return -EINVAL;
531369e6
DA		 1337 }
1338 crtc = obj_to_crtc(obj);
1339 radeon_crtc = to_radeon_crtc(crtc);
1340 crtc_id = radeon_crtc->crtc_id;
1341
1342 if (!crtc->enabled) {
1343 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1344 ib[h_idx + 2] = PACKET2(0);
1345 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1346 } else if (crtc_id == 1) {
1347 switch (reg) {
1348 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1349 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1350 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1351 break;
1352 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1353 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1354 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1355 break;
1356 default:
1357 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1358 return -EINVAL;
531369e6 1359 }
513bcb46
DA		 1360 ib[h_idx] = header;
1361 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1362 }
a3a88a66
PB		 1363
1364 return 0;
531369e6
DA		 1365}
1366
771fe6b9
JG		 1367/**
1368 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1369 * @parser: parser structure holding parsing context.
1370 * @data: pointer to relocation data
1371 * @offset_start: starting offset
1372 * @offset_mask: offset mask (to align start offset on)
1373 * @reloc: reloc informations
1374 *
1375 * Check next packet is relocation packet3, do bo validation and compute
1376 * GPU offset using the provided start.
1377 **/
1378int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1379 struct radeon_cs_reloc **cs_reloc)
1380{
771fe6b9
JG		 1381 struct radeon_cs_chunk *relocs_chunk;
1382 struct radeon_cs_packet p3reloc;
1383 unsigned idx;
1384 int r;
1385
1386 if (p->chunk_relocs_idx == -1) {
1387 DRM_ERROR("No relocation chunk !\n");
1388 return -EINVAL;
1389 }
1390 *cs_reloc = NULL;
771fe6b9
JG		 1391 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1392 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1393 if (r) {
1394 return r;
1395 }
1396 p->idx += p3reloc.count + 2;
1397 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1398 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1399 p3reloc.idx);
1400 r100_cs_dump_packet(p, &p3reloc);
1401 return -EINVAL;
1402 }
513bcb46 1403 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1404 if (idx >= relocs_chunk->length_dw) {
1405 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1406 idx, relocs_chunk->length_dw);
1407 r100_cs_dump_packet(p, &p3reloc);
1408 return -EINVAL;
1409 }
1410 /* FIXME: we assume reloc size is 4 dwords */
1411 *cs_reloc = p->relocs_ptr[(idx / 4)];
1412 return 0;
1413}
1414
551ebd83
DA		 1415static int r100_get_vtx_size(uint32_t vtx_fmt)
1416{
1417 int vtx_size;
1418 vtx_size = 2;
1419 /* ordered according to bits in spec */
1420 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1421 vtx_size++;
1422 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1423 vtx_size += 3;
1424 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1425 vtx_size++;
1426 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1427 vtx_size++;
1428 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1429 vtx_size += 3;
1430 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1431 vtx_size++;
1432 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1433 vtx_size++;
1434 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1435 vtx_size += 2;
1436 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1437 vtx_size += 2;
1438 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1439 vtx_size++;
1440 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1441 vtx_size += 2;
1442 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1443 vtx_size++;
1444 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1445 vtx_size += 2;
1446 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1447 vtx_size++;
1448 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1449 vtx_size++;
1450 /* blend weight */
1451 if (vtx_fmt & (0x7 << 15))
1452 vtx_size += (vtx_fmt >> 15) & 0x7;
1453 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1454 vtx_size += 3;
1455 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1456 vtx_size += 2;
1457 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1458 vtx_size++;
1459 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1460 vtx_size++;
1461 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1462 vtx_size++;
1463 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1464 vtx_size++;
1465 return vtx_size;
1466}
1467
771fe6b9 1468static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1469 struct radeon_cs_packet *pkt,
1470 unsigned idx, unsigned reg)
771fe6b9 1471{
771fe6b9 1472 struct radeon_cs_reloc *reloc;
551ebd83 1473 struct r100_cs_track *track;
771fe6b9
JG		 1474 volatile uint32_t *ib;
1475 uint32_t tmp;
771fe6b9 1476 int r;
551ebd83 1477 int i, face;
e024e110 1478 u32 tile_flags = 0;
513bcb46 1479 u32 idx_value;
771fe6b9
JG		 1480
1481 ib = p->ib->ptr;
551ebd83
DA		 1482 track = (struct r100_cs_track *)p->track;
1483
513bcb46
DA		 1484 idx_value = radeon_get_ib_value(p, idx);
1485
551ebd83
DA		 1486 switch (reg) {
1487 case RADEON_CRTC_GUI_TRIG_VLINE:
1488 r = r100_cs_packet_parse_vline(p);
1489 if (r) {
1490 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1491 idx, reg);
1492 r100_cs_dump_packet(p, pkt);
1493 return r;
1494 }
1495 break;
771fe6b9
JG		 1496 /* FIXME: only allow PACKET3 blit? easier to check for out of
1497 * range access */
551ebd83
DA		 1498 case RADEON_DST_PITCH_OFFSET:
1499 case RADEON_SRC_PITCH_OFFSET:
1500 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1501 if (r)
1502 return r;
1503 break;
1504 case RADEON_RB3D_DEPTHOFFSET:
1505 r = r100_cs_packet_next_reloc(p, &reloc);
1506 if (r) {
1507 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1508 idx, reg);
1509 r100_cs_dump_packet(p, pkt);
1510 return r;
1511 }
1512 track->zb.robj = reloc->robj;
513bcb46 1513 track->zb.offset = idx_value;
40b4a759 1514 track->zb_dirty = true;
513bcb46 1515 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1516 break;
1517 case RADEON_RB3D_COLOROFFSET:
1518 r = r100_cs_packet_next_reloc(p, &reloc);
1519 if (r) {
1520 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1521 idx, reg);
1522 r100_cs_dump_packet(p, pkt);
1523 return r;
1524 }
1525 track->cb[0].robj = reloc->robj;
513bcb46 1526 track->cb[0].offset = idx_value;
40b4a759 1527 track->cb_dirty = true;
513bcb46 1528 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1529 break;
1530 case RADEON_PP_TXOFFSET_0:
1531 case RADEON_PP_TXOFFSET_1:
1532 case RADEON_PP_TXOFFSET_2:
1533 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1534 r = r100_cs_packet_next_reloc(p, &reloc);
1535 if (r) {
1536 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1537 idx, reg);
1538 r100_cs_dump_packet(p, pkt);
1539 return r;
1540 }
513bcb46 1541 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1542 track->textures[i].robj = reloc->robj;
40b4a759 1543 track->tex_dirty = true;
551ebd83
DA		 1544 break;
1545 case RADEON_PP_CUBIC_OFFSET_T0_0:
1546 case RADEON_PP_CUBIC_OFFSET_T0_1:
1547 case RADEON_PP_CUBIC_OFFSET_T0_2:
1548 case RADEON_PP_CUBIC_OFFSET_T0_3:
1549 case RADEON_PP_CUBIC_OFFSET_T0_4:
1550 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1551 r = r100_cs_packet_next_reloc(p, &reloc);
1552 if (r) {
1553 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1554 idx, reg);
1555 r100_cs_dump_packet(p, pkt);
1556 return r;
1557 }
513bcb46
DA		 1558 track->textures[0].cube_info[i].offset = idx_value;
1559 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1560 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1561 track->tex_dirty = true;
551ebd83
DA		 1562 break;
1563 case RADEON_PP_CUBIC_OFFSET_T1_0:
1564 case RADEON_PP_CUBIC_OFFSET_T1_1:
1565 case RADEON_PP_CUBIC_OFFSET_T1_2:
1566 case RADEON_PP_CUBIC_OFFSET_T1_3:
1567 case RADEON_PP_CUBIC_OFFSET_T1_4:
1568 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1569 r = r100_cs_packet_next_reloc(p, &reloc);
1570 if (r) {
1571 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1572 idx, reg);
1573 r100_cs_dump_packet(p, pkt);
1574 return r;
1575 }
513bcb46
DA		 1576 track->textures[1].cube_info[i].offset = idx_value;
1577 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1578 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1579 track->tex_dirty = true;
551ebd83
DA		 1580 break;
1581 case RADEON_PP_CUBIC_OFFSET_T2_0:
1582 case RADEON_PP_CUBIC_OFFSET_T2_1:
1583 case RADEON_PP_CUBIC_OFFSET_T2_2:
1584 case RADEON_PP_CUBIC_OFFSET_T2_3:
1585 case RADEON_PP_CUBIC_OFFSET_T2_4:
1586 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1587 r = r100_cs_packet_next_reloc(p, &reloc);
1588 if (r) {
1589 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1590 idx, reg);
1591 r100_cs_dump_packet(p, pkt);
1592 return r;
1593 }
513bcb46
DA		 1594 track->textures[2].cube_info[i].offset = idx_value;
1595 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1596 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1597 track->tex_dirty = true;
551ebd83
DA		 1598 break;
1599 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1600 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1601 track->cb_dirty = true;
1602 track->zb_dirty = true;
551ebd83
DA		 1603 break;
1604 case RADEON_RB3D_COLORPITCH:
1605 r = r100_cs_packet_next_reloc(p, &reloc);
1606 if (r) {
1607 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1608 idx, reg);
1609 r100_cs_dump_packet(p, pkt);
1610 return r;
1611 }
e024e110 1612
551ebd83
DA		 1613 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1614 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1615 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1616 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1617
513bcb46 1618 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1619 tmp |= tile_flags;
1620 ib[idx] = tmp;
e024e110 1621
513bcb46 1622 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1623 track->cb_dirty = true;
551ebd83
DA		 1624 break;
1625 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1626 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1627 track->zb_dirty = true;
551ebd83
DA		 1628 break;
1629 case RADEON_RB3D_CNTL:
513bcb46 1630 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1631 case 7:
1632 case 8:
1633 case 9:
1634 case 11:
1635 case 12:
1636 track->cb[0].cpp = 1;
e024e110 1637 break;
551ebd83
DA		 1638 case 3:
1639 case 4:
1640 case 15:
1641 track->cb[0].cpp = 2;
1642 break;
1643 case 6:
1644 track->cb[0].cpp = 4;
1645 break;
1646 default:
1647 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1648 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1649 return -EINVAL;
1650 }
513bcb46 1651 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1652 track->cb_dirty = true;
1653 track->zb_dirty = true;
551ebd83
DA		 1654 break;
1655 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1656 switch (idx_value & 0xf) {
551ebd83
DA		 1657 case 0:
1658 track->zb.cpp = 2;
1659 break;
1660 case 2:
1661 case 3:
1662 case 4:
1663 case 5:
1664 case 9:
1665 case 11:
1666 track->zb.cpp = 4;
17782d99 1667 break;
771fe6b9 1668 default:
771fe6b9
JG		 1669 break;
1670 }
40b4a759 1671 track->zb_dirty = true;
551ebd83
DA		 1672 break;
1673 case RADEON_RB3D_ZPASS_ADDR:
1674 r = r100_cs_packet_next_reloc(p, &reloc);
1675 if (r) {
1676 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1677 idx, reg);
1678 r100_cs_dump_packet(p, pkt);
1679 return r;
1680 }
513bcb46 1681 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1682 break;
1683 case RADEON_PP_CNTL:
1684 {
513bcb46 1685 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1686 for (i = 0; i < track->num_texture; i++)
1687 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1688 track->tex_dirty = true;
551ebd83
DA		 1689 }
1690 break;
1691 case RADEON_SE_VF_CNTL:
513bcb46 1692 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1693 break;
1694 case RADEON_SE_VTX_FMT:
513bcb46 1695 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1696 break;
1697 case RADEON_PP_TEX_SIZE_0:
1698 case RADEON_PP_TEX_SIZE_1:
1699 case RADEON_PP_TEX_SIZE_2:
1700 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1701 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1702 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1703 track->tex_dirty = true;
551ebd83
DA		 1704 break;
1705 case RADEON_PP_TEX_PITCH_0:
1706 case RADEON_PP_TEX_PITCH_1:
1707 case RADEON_PP_TEX_PITCH_2:
1708 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1709 track->textures[i].pitch = idx_value + 32;
40b4a759 1710 track->tex_dirty = true;
551ebd83
DA		 1711 break;
1712 case RADEON_PP_TXFILTER_0:
1713 case RADEON_PP_TXFILTER_1:
1714 case RADEON_PP_TXFILTER_2:
1715 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1716 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1717 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1718 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1719 if (tmp == 2 || tmp == 6)
1720 track->textures[i].roundup_w = false;
513bcb46 1721 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1722 if (tmp == 2 || tmp == 6)
1723 track->textures[i].roundup_h = false;
40b4a759 1724 track->tex_dirty = true;
551ebd83
DA		 1725 break;
1726 case RADEON_PP_TXFORMAT_0:
1727 case RADEON_PP_TXFORMAT_1:
1728 case RADEON_PP_TXFORMAT_2:
1729 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1730 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1731 track->textures[i].use_pitch = 1;
1732 } else {
1733 track->textures[i].use_pitch = 0;
513bcb46
DA		 1734 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1735 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1736 }
513bcb46 1737 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1738 track->textures[i].tex_coord_type = 2;
513bcb46 1739 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1740 case RADEON_TXFORMAT_I8:
1741 case RADEON_TXFORMAT_RGB332:
1742 case RADEON_TXFORMAT_Y8:
1743 track->textures[i].cpp = 1;
f9da52d5 1744 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1745 break;
1746 case RADEON_TXFORMAT_AI88:
1747 case RADEON_TXFORMAT_ARGB1555:
1748 case RADEON_TXFORMAT_RGB565:
1749 case RADEON_TXFORMAT_ARGB4444:
1750 case RADEON_TXFORMAT_VYUY422:
1751 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1752 case RADEON_TXFORMAT_SHADOW16:
1753 case RADEON_TXFORMAT_LDUDV655:
1754 case RADEON_TXFORMAT_DUDV88:
1755 track->textures[i].cpp = 2;
f9da52d5 1756 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1757 break;
551ebd83
DA		 1758 case RADEON_TXFORMAT_ARGB8888:
1759 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1760 case RADEON_TXFORMAT_SHADOW32:
1761 case RADEON_TXFORMAT_LDUDUV8888:
1762 track->textures[i].cpp = 4;
f9da52d5 1763 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1764 break;
d785d78b
DA		 1765 case RADEON_TXFORMAT_DXT1:
1766 track->textures[i].cpp = 1;
1767 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1768 break;
1769 case RADEON_TXFORMAT_DXT23:
1770 case RADEON_TXFORMAT_DXT45:
1771 track->textures[i].cpp = 1;
1772 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1773 break;
551ebd83 1774 }
513bcb46
DA		 1775 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1776 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1777 track->tex_dirty = true;
551ebd83
DA		 1778 break;
1779 case RADEON_PP_CUBIC_FACES_0:
1780 case RADEON_PP_CUBIC_FACES_1:
1781 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1782 tmp = idx_value;
551ebd83
DA		 1783 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1784 for (face = 0; face < 4; face++) {
1785 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1786 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1787 }
40b4a759 1788 track->tex_dirty = true;
551ebd83
DA		 1789 break;
1790 default:
1791 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1792 reg, idx);
1793 return -EINVAL;
771fe6b9
JG		 1794 }
1795 return 0;
1796}
1797
068a117c
JG		 1798int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1799 struct radeon_cs_packet *pkt,
4c788679 1800 struct radeon_bo *robj)
068a117c 1801{
068a117c 1802 unsigned idx;
513bcb46 1803 u32 value;
068a117c 1804 idx = pkt->idx + 1;
513bcb46 1805 value = radeon_get_ib_value(p, idx + 2);
4c788679 1806 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1807 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1808 "(need %u have %lu) !\n",
513bcb46 1809 value + 1,
4c788679 1810 radeon_bo_size(robj));
068a117c
JG		 1811 return -EINVAL;
1812 }
1813 return 0;
1814}
1815
771fe6b9
JG		 1816static int r100_packet3_check(struct radeon_cs_parser *p,
1817 struct radeon_cs_packet *pkt)
1818{
771fe6b9 1819 struct radeon_cs_reloc *reloc;
551ebd83 1820 struct r100_cs_track *track;
771fe6b9 1821 unsigned idx;
771fe6b9
JG		 1822 volatile uint32_t *ib;
1823 int r;
1824
1825 ib = p->ib->ptr;
771fe6b9 1826 idx = pkt->idx + 1;
551ebd83 1827 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1828 switch (pkt->opcode) {
1829 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1830 r = r100_packet3_load_vbpntr(p, pkt, idx);
1831 if (r)
1832 return r;
771fe6b9
JG		 1833 break;
1834 case PACKET3_INDX_BUFFER:
1835 r = r100_cs_packet_next_reloc(p, &reloc);
1836 if (r) {
1837 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1838 r100_cs_dump_packet(p, pkt);
1839 return r;
1840 }
513bcb46 1841 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1842 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1843 if (r) {
1844 return r;
1845 }
771fe6b9
JG		 1846 break;
1847 case 0x23:
771fe6b9
JG		 1848 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1849 r = r100_cs_packet_next_reloc(p, &reloc);
1850 if (r) {
1851 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1852 r100_cs_dump_packet(p, pkt);
1853 return r;
1854 }
513bcb46 1855 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1856 track->num_arrays = 1;
513bcb46 1857 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1858
1859 track->arrays[0].robj = reloc->robj;
1860 track->arrays[0].esize = track->vtx_size;
1861
513bcb46 1862 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1863
513bcb46 1864 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1865 track->immd_dwords = pkt->count - 1;
1866 r = r100_cs_track_check(p->rdev, track);
1867 if (r)
1868 return r;
771fe6b9
JG		 1869 break;
1870 case PACKET3_3D_DRAW_IMMD:
513bcb46 1871 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1872 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1873 return -EINVAL;
1874 }
cf57fc7a 1875 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1876 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1877 track->immd_dwords = pkt->count - 1;
1878 r = r100_cs_track_check(p->rdev, track);
1879 if (r)
1880 return r;
1881 break;
771fe6b9
JG		 1882 /* triggers drawing using in-packet vertex data */
1883 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1884 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1885 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1886 return -EINVAL;
1887 }
513bcb46 1888 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1889 track->immd_dwords = pkt->count;
1890 r = r100_cs_track_check(p->rdev, track);
1891 if (r)
1892 return r;
1893 break;
771fe6b9
JG		 1894 /* triggers drawing using in-packet vertex data */
1895 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1896 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1897 r = r100_cs_track_check(p->rdev, track);
1898 if (r)
1899 return r;
1900 break;
771fe6b9
JG		 1901 /* triggers drawing of vertex buffers setup elsewhere */
1902 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1903 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1904 r = r100_cs_track_check(p->rdev, track);
1905 if (r)
1906 return r;
1907 break;
771fe6b9
JG		 1908 /* triggers drawing using indices to vertex buffer */
1909 case PACKET3_3D_DRAW_VBUF:
513bcb46 1910 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1911 r = r100_cs_track_check(p->rdev, track);
1912 if (r)
1913 return r;
1914 break;
771fe6b9
JG		 1915 /* triggers drawing of vertex buffers setup elsewhere */
1916 case PACKET3_3D_DRAW_INDX:
513bcb46 1917 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1918 r = r100_cs_track_check(p->rdev, track);
1919 if (r)
1920 return r;
1921 break;
771fe6b9 1922 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 1923 case PACKET3_3D_CLEAR_HIZ:
1924 case PACKET3_3D_CLEAR_ZMASK:
1925 if (p->rdev->hyperz_filp != p->filp)
1926 return -EINVAL;
1927 break;
771fe6b9
JG		 1928 case PACKET3_NOP:
1929 break;
1930 default:
1931 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1932 return -EINVAL;
1933 }
1934 return 0;
1935}
1936
1937int r100_cs_parse(struct radeon_cs_parser *p)
1938{
1939 struct radeon_cs_packet pkt;
9f022ddf 1940 struct r100_cs_track *track;
771fe6b9
JG		 1941 int r;
1942
9f022ddf
JG		 1943 track = kzalloc(sizeof(*track), GFP_KERNEL);
1944 r100_cs_track_clear(p->rdev, track);
1945 p->track = track;
771fe6b9
JG		 1946 do {
1947 r = r100_cs_packet_parse(p, &pkt, p->idx);
1948 if (r) {
1949 return r;
1950 }
1951 p->idx += pkt.count + 2;
1952 switch (pkt.type) {
068a117c 1953 case PACKET_TYPE0:
551ebd83
DA		 1954 if (p->rdev->family >= CHIP_R200)
1955 r = r100_cs_parse_packet0(p, &pkt,
1956 p->rdev->config.r100.reg_safe_bm,
1957 p->rdev->config.r100.reg_safe_bm_size,
1958 &r200_packet0_check);
1959 else
1960 r = r100_cs_parse_packet0(p, &pkt,
1961 p->rdev->config.r100.reg_safe_bm,
1962 p->rdev->config.r100.reg_safe_bm_size,
1963 &r100_packet0_check);
068a117c
JG		 1964 break;
1965 case PACKET_TYPE2:
1966 break;
1967 case PACKET_TYPE3:
1968 r = r100_packet3_check(p, &pkt);
1969 break;
1970 default:
1971 DRM_ERROR("Unknown packet type %d !\n",
1972 pkt.type);
1973 return -EINVAL;
771fe6b9
JG		 1974 }
1975 if (r) {
1976 return r;
1977 }
1978 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1979 return 0;
1980}
1981
1982
1983/*
1984 * Global GPU functions
1985 */
1986void r100_errata(struct radeon_device *rdev)
1987{
1988 rdev->pll_errata = 0;
1989
1990 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1991 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1992 }
1993
1994 if (rdev->family == CHIP_RV100 ||
1995 rdev->family == CHIP_RS100 ||
1996 rdev->family == CHIP_RS200) {
1997 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1998 }
1999}
2000
2001/* Wait for vertical sync on primary CRTC */
2002void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2003{
2004 uint32_t crtc_gen_cntl, tmp;
2005 int i;
2006
2007 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2008 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2009 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2010 return;
2011 }
2012 /* Clear the CRTC_VBLANK_SAVE bit */
2013 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2014 for (i = 0; i < rdev->usec_timeout; i++) {
2015 tmp = RREG32(RADEON_CRTC_STATUS);
2016 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2017 return;
2018 }
2019 DRM_UDELAY(1);
2020 }
2021}
2022
2023/* Wait for vertical sync on secondary CRTC */
2024void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2025{
2026 uint32_t crtc2_gen_cntl, tmp;
2027 int i;
2028
2029 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2030 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2031 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2032 return;
2033
2034 /* Clear the CRTC_VBLANK_SAVE bit */
2035 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2036 for (i = 0; i < rdev->usec_timeout; i++) {
2037 tmp = RREG32(RADEON_CRTC2_STATUS);
2038 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2039 return;
2040 }
2041 DRM_UDELAY(1);
2042 }
2043}
2044
2045int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2046{
2047 unsigned i;
2048 uint32_t tmp;
2049
2050 for (i = 0; i < rdev->usec_timeout; i++) {
2051 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2052 if (tmp >= n) {
2053 return 0;
2054 }
2055 DRM_UDELAY(1);
2056 }
2057 return -1;
2058}
2059
2060int r100_gui_wait_for_idle(struct radeon_device *rdev)
2061{
2062 unsigned i;
2063 uint32_t tmp;
2064
2065 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2066 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2067 " Bad things might happen.\n");
2068 }
2069 for (i = 0; i < rdev->usec_timeout; i++) {
2070 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 2071 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 2072 return 0;
2073 }
2074 DRM_UDELAY(1);
2075 }
2076 return -1;
2077}
2078
2079int r100_mc_wait_for_idle(struct radeon_device *rdev)
2080{
2081 unsigned i;
2082 uint32_t tmp;
2083
2084 for (i = 0; i < rdev->usec_timeout; i++) {
2085 /* read MC_STATUS */
4612dc97
AD		 2086 tmp = RREG32(RADEON_MC_STATUS);
2087 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 2088 return 0;
2089 }
2090 DRM_UDELAY(1);
2091 }
2092 return -1;
2093}
2094
225758d8 2095void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
771fe6b9 2096{
225758d8
JG		 2097 lockup->last_cp_rptr = cp->rptr;
2098 lockup->last_jiffies = jiffies;
2099}
2100
2101/**
2102 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2103 * @rdev: radeon device structure
2104 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2105 * @cp: radeon_cp structure holding CP information
2106 *
2107 * We don't need to initialize the lockup tracking information as we will either
2108 * have CP rptr to a different value of jiffies wrap around which will force
2109 * initialization of the lockup tracking informations.
2110 *
2111 * A possible false positivie is if we get call after while and last_cp_rptr ==
2112 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2113 * if the elapsed time since last call is bigger than 2 second than we return
2114 * false and update the tracking information. Due to this the caller must call
2115 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2116 * the fencing code should be cautious about that.
2117 *
2118 * Caller should write to the ring to force CP to do something so we don't get
2119 * false positive when CP is just gived nothing to do.
2120 *
2121 **/
2122bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2123{
2124 unsigned long cjiffies, elapsed;
2125
2126 cjiffies = jiffies;
2127 if (!time_after(cjiffies, lockup->last_jiffies)) {
2128 /* likely a wrap around */
2129 lockup->last_cp_rptr = cp->rptr;
2130 lockup->last_jiffies = jiffies;
2131 return false;
2132 }
2133 if (cp->rptr != lockup->last_cp_rptr) {
2134 /* CP is still working no lockup */
2135 lockup->last_cp_rptr = cp->rptr;
2136 lockup->last_jiffies = jiffies;
2137 return false;
2138 }
2139 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
ec00efb7 2140 if (elapsed >= 10000) {
225758d8
JG		 2141 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2142 return true;
2143 }
2144 /* give a chance to the GPU ... */
2145 return false;
771fe6b9
JG		 2146}
2147
225758d8 2148bool r100_gpu_is_lockup(struct radeon_device *rdev)
771fe6b9 2149{
225758d8
JG		 2150 u32 rbbm_status;
2151 int r;
771fe6b9 2152
225758d8
JG		 2153 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2154 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2155 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2156 return false;
2157 }
2158 /* force CP activities */
2159 r = radeon_ring_lock(rdev, 2);
2160 if (!r) {
2161 /* PACKET2 NOP */
2162 radeon_ring_write(rdev, 0x80000000);
2163 radeon_ring_write(rdev, 0x80000000);
2164 radeon_ring_unlock_commit(rdev);
2165 }
2166 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2167 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
771fe6b9
JG		 2168}
2169
90aca4d2 2170void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2171{
90aca4d2 2172 u32 tmp;
771fe6b9 2173
90aca4d2
JG		 2174 /* disable bus mastering */
2175 tmp = RREG32(R_000030_BUS_CNTL);
2176 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2177 mdelay(1);
2178 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2179 mdelay(1);
2180 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2181 tmp = RREG32(RADEON_BUS_CNTL);
2182 mdelay(1);
2183 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2184 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
771fe6b9 2185 mdelay(1);
771fe6b9
JG		 2186}
2187
a2d07b74 2188int r100_asic_reset(struct radeon_device *rdev)
771fe6b9 2189{
90aca4d2
JG		 2190 struct r100_mc_save save;
2191 u32 status, tmp;
25b2ec5b 2192 int ret = 0;
771fe6b9 2193
90aca4d2
JG		 2194 status = RREG32(R_000E40_RBBM_STATUS);
2195 if (!G_000E40_GUI_ACTIVE(status)) {
2196 return 0;
771fe6b9 2197 }
25b2ec5b 2198 r100_mc_stop(rdev, &save);
90aca4d2
JG		 2199 status = RREG32(R_000E40_RBBM_STATUS);
2200 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2201 /* stop CP */
2202 WREG32(RADEON_CP_CSQ_CNTL, 0);
2203 tmp = RREG32(RADEON_CP_RB_CNTL);
2204 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2205 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2206 WREG32(RADEON_CP_RB_WPTR, 0);
2207 WREG32(RADEON_CP_RB_CNTL, tmp);
2208 /* save PCI state */
2209 pci_save_state(rdev->pdev);
2210 /* disable bus mastering */
2211 r100_bm_disable(rdev);
2212 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2213 S_0000F0_SOFT_RESET_RE(1) |
2214 S_0000F0_SOFT_RESET_PP(1) |
2215 S_0000F0_SOFT_RESET_RB(1));
2216 RREG32(R_0000F0_RBBM_SOFT_RESET);
2217 mdelay(500);
2218 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2219 mdelay(1);
2220 status = RREG32(R_000E40_RBBM_STATUS);
2221 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
771fe6b9 2222 /* reset CP */
90aca4d2
JG		 2223 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2224 RREG32(R_0000F0_RBBM_SOFT_RESET);
2225 mdelay(500);
2226 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2227 mdelay(1);
2228 status = RREG32(R_000E40_RBBM_STATUS);
2229 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2230 /* restore PCI & busmastering */
2231 pci_restore_state(rdev->pdev);
2232 r100_enable_bm(rdev);
771fe6b9 2233 /* Check if GPU is idle */
90aca4d2
JG		 2234 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2235 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2236 dev_err(rdev->dev, "failed to reset GPU\n");
2237 rdev->gpu_lockup = true;
25b2ec5b
AD		 2238 ret = -1;
2239 } else
2240 dev_info(rdev->dev, "GPU reset succeed\n");
90aca4d2 2241 r100_mc_resume(rdev, &save);
25b2ec5b 2242 return ret;
771fe6b9
JG		 2243}
2244
92cde00c
AD		 2245void r100_set_common_regs(struct radeon_device *rdev)
2246{
2739d49c
AD		 2247 struct drm_device *dev = rdev->ddev;
2248 bool force_dac2 = false;
d668046c 2249 u32 tmp;
2739d49c 2250
92cde00c
AD		 2251 /* set these so they don't interfere with anything */
2252 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2253 WREG32(RADEON_SUBPIC_CNTL, 0);
2254 WREG32(RADEON_VIPH_CONTROL, 0);
2255 WREG32(RADEON_I2C_CNTL_1, 0);
2256 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2257 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2258 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 2259
2260 /* always set up dac2 on rn50 and some rv100 as lots
2261 * of servers seem to wire it up to a VGA port but
2262 * don't report it in the bios connector
2263 * table.
2264 */
2265 switch (dev->pdev->device) {
2266 /* RN50 */
2267 case 0x515e:
2268 case 0x5969:
2269 force_dac2 = true;
2270 break;
2271 /* RV100*/
2272 case 0x5159:
2273 case 0x515a:
2274 /* DELL triple head servers */
2275 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2276 ((dev->pdev->subsystem_device == 0x016c) ||
2277 (dev->pdev->subsystem_device == 0x016d) ||
2278 (dev->pdev->subsystem_device == 0x016e) ||
2279 (dev->pdev->subsystem_device == 0x016f) ||
2280 (dev->pdev->subsystem_device == 0x0170) ||
2281 (dev->pdev->subsystem_device == 0x017d) ||
2282 (dev->pdev->subsystem_device == 0x017e) ||
2283 (dev->pdev->subsystem_device == 0x0183) ||
2284 (dev->pdev->subsystem_device == 0x018a) ||
2285 (dev->pdev->subsystem_device == 0x019a)))
2286 force_dac2 = true;
2287 break;
2288 }
2289
2290 if (force_dac2) {
2291 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2292 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2293 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2294
2295 /* For CRT on DAC2, don't turn it on if BIOS didn't
2296 enable it, even it's detected.
2297 */
2298
2299 /* force it to crtc0 */
2300 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2301 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2302 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2303
2304 /* set up the TV DAC */
2305 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2306 RADEON_TV_DAC_STD_MASK |
2307 RADEON_TV_DAC_RDACPD |
2308 RADEON_TV_DAC_GDACPD |
2309 RADEON_TV_DAC_BDACPD |
2310 RADEON_TV_DAC_BGADJ_MASK |
2311 RADEON_TV_DAC_DACADJ_MASK);
2312 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2313 RADEON_TV_DAC_NHOLD |
2314 RADEON_TV_DAC_STD_PS2 |
2315 (0x58 << 16));
2316
2317 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2318 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2319 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2320 }
d668046c
DA		 2321
2322 /* switch PM block to ACPI mode */
2323 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2324 tmp &= ~RADEON_PM_MODE_SEL;
2325 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2326
92cde00c 2327}
771fe6b9
JG		 2328
2329/*
2330 * VRAM info
2331 */
2332static void r100_vram_get_type(struct radeon_device *rdev)
2333{
2334 uint32_t tmp;
2335
2336 rdev->mc.vram_is_ddr = false;
2337 if (rdev->flags & RADEON_IS_IGP)
2338 rdev->mc.vram_is_ddr = true;
2339 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2340 rdev->mc.vram_is_ddr = true;
2341 if ((rdev->family == CHIP_RV100) ||
2342 (rdev->family == CHIP_RS100) ||
2343 (rdev->family == CHIP_RS200)) {
2344 tmp = RREG32(RADEON_MEM_CNTL);
2345 if (tmp & RV100_HALF_MODE) {
2346 rdev->mc.vram_width = 32;
2347 } else {
2348 rdev->mc.vram_width = 64;
2349 }
2350 if (rdev->flags & RADEON_SINGLE_CRTC) {
2351 rdev->mc.vram_width /= 4;
2352 rdev->mc.vram_is_ddr = true;
2353 }
2354 } else if (rdev->family <= CHIP_RV280) {
2355 tmp = RREG32(RADEON_MEM_CNTL);
2356 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2357 rdev->mc.vram_width = 128;
2358 } else {
2359 rdev->mc.vram_width = 64;
2360 }
2361 } else {
2362 /* newer IGPs */
2363 rdev->mc.vram_width = 128;
2364 }
2365}
2366
2a0f8918 2367static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 2368{
2a0f8918
DA		 2369 u32 aper_size;
2370 u8 byte;
2371
2372 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2373
2374 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2375 * that is has the 2nd generation multifunction PCI interface
2376 */
2377 if (rdev->family == CHIP_RV280 ||
2378 rdev->family >= CHIP_RV350) {
2379 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2380 ~RADEON_HDP_APER_CNTL);
2381 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2382 return aper_size * 2;
2383 }
2384
2385 /* Older cards have all sorts of funny issues to deal with. First
2386 * check if it's a multifunction card by reading the PCI config
2387 * header type... Limit those to one aperture size
2388 */
2389 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2390 if (byte & 0x80) {
2391 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2392 DRM_INFO("Limiting VRAM to one aperture\n");
2393 return aper_size;
2394 }
2395
2396 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2397 * have set it up. We don't write this as it's broken on some ASICs but
2398 * we expect the BIOS to have done the right thing (might be too optimistic...)
2399 */
2400 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2401 return aper_size * 2;
2402 return aper_size;
2403}
2404
2405void r100_vram_init_sizes(struct radeon_device *rdev)
2406{
2407 u64 config_aper_size;
2a0f8918 2408
d594e46a 2409 /* work out accessible VRAM */
01d73a69
JC		 2410 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2411 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
51e5fcd3
JG		 2412 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2413 /* FIXME we don't use the second aperture yet when we could use it */
2414 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2415 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 2416 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 2417 if (rdev->flags & RADEON_IS_IGP) {
2418 uint32_t tom;
2419 /* read NB_TOM to get the amount of ram stolen for the GPU */
2420 tom = RREG32(RADEON_NB_TOM);
7a50f01a 2421 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 2422 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2423 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2424 } else {
7a50f01a 2425 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 2426 /* Some production boards of m6 will report 0
2427 * if it's 8 MB
2428 */
7a50f01a
DA		 2429 if (rdev->mc.real_vram_size == 0) {
2430 rdev->mc.real_vram_size = 8192 * 1024;
2431 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 2432 }
d594e46a
JG		 2433 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2434 * Novell bug 204882 + along with lots of ubuntu ones
2435 */
b7d8cce5
AD		 2436 if (rdev->mc.aper_size > config_aper_size)
2437 config_aper_size = rdev->mc.aper_size;
2438
7a50f01a
DA		 2439 if (config_aper_size > rdev->mc.real_vram_size)
2440 rdev->mc.mc_vram_size = config_aper_size;
2441 else
2442 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2443 }
2a0f8918
DA		 2444}
2445
28d52043
DA		 2446void r100_vga_set_state(struct radeon_device *rdev, bool state)
2447{
2448 uint32_t temp;
2449
2450 temp = RREG32(RADEON_CONFIG_CNTL);
2451 if (state == false) {
d75ee3be
AD		 2452 temp &= ~RADEON_CFG_VGA_RAM_EN;
2453 temp |= RADEON_CFG_VGA_IO_DIS;
28d52043 2454 } else {
d75ee3be 2455 temp &= ~RADEON_CFG_VGA_IO_DIS;
28d52043
DA		 2456 }
2457 WREG32(RADEON_CONFIG_CNTL, temp);
2458}
2459
d594e46a 2460void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2461{
d594e46a 2462 u64 base;
2a0f8918 2463
d594e46a 2464 r100_vram_get_type(rdev);
2a0f8918 2465 r100_vram_init_sizes(rdev);
d594e46a
JG		 2466 base = rdev->mc.aper_base;
2467 if (rdev->flags & RADEON_IS_IGP)
2468 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2469 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 2470 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 2471 if (!(rdev->flags & RADEON_IS_AGP))
2472 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2473 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2474}
2475
2476
2477/*
2478 * Indirect registers accessor
2479 */
2480void r100_pll_errata_after_index(struct radeon_device *rdev)
2481{
4ce9198e
AD		 2482 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2483 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2484 (void)RREG32(RADEON_CRTC_GEN_CNTL);
771fe6b9 2485 }
771fe6b9
JG		 2486}
2487
2488static void r100_pll_errata_after_data(struct radeon_device *rdev)
2489{
2490 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2491 * or the chip could hang on a subsequent access
2492 */
2493 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2494 udelay(5000);
2495 }
2496
2497 /* This function is required to workaround a hardware bug in some (all?)
2498 * revisions of the R300. This workaround should be called after every
2499 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2500 * may not be correct.
2501 */
2502 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2503 uint32_t save, tmp;
2504
2505 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2506 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2507 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2508 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2509 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2510 }
2511}
2512
2513uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2514{
2515 uint32_t data;
2516
2517 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2518 r100_pll_errata_after_index(rdev);
2519 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2520 r100_pll_errata_after_data(rdev);
2521 return data;
2522}
2523
2524void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2525{
2526 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2527 r100_pll_errata_after_index(rdev);
2528 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2529 r100_pll_errata_after_data(rdev);
2530}
2531
d4550907 2532void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2533{
551ebd83
DA		 2534 if (ASIC_IS_RN50(rdev)) {
2535 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2536 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2537 } else if (rdev->family < CHIP_R200) {
2538 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2539 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2540 } else {
d4550907 2541 r200_set_safe_registers(rdev);
551ebd83 2542 }
068a117c
JG		 2543}
2544
771fe6b9
JG		 2545/*
2546 * Debugfs info
2547 */
2548#if defined(CONFIG_DEBUG_FS)
2549static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2550{
2551 struct drm_info_node *node = (struct drm_info_node *) m->private;
2552 struct drm_device *dev = node->minor->dev;
2553 struct radeon_device *rdev = dev->dev_private;
2554 uint32_t reg, value;
2555 unsigned i;
2556
2557 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2558 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2559 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2560 for (i = 0; i < 64; i++) {
2561 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2562 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2563 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2564 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2565 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2566 }
2567 return 0;
2568}
2569
2570static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2571{
2572 struct drm_info_node *node = (struct drm_info_node *) m->private;
2573 struct drm_device *dev = node->minor->dev;
2574 struct radeon_device *rdev = dev->dev_private;
2575 uint32_t rdp, wdp;
2576 unsigned count, i, j;
2577
2578 radeon_ring_free_size(rdev);
2579 rdp = RREG32(RADEON_CP_RB_RPTR);
2580 wdp = RREG32(RADEON_CP_RB_WPTR);
2581 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2582 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2583 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2584 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2585 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2586 seq_printf(m, "%u dwords in ring\n", count);
2587 for (j = 0; j <= count; j++) {
2588 i = (rdp + j) & rdev->cp.ptr_mask;
2589 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2590 }
2591 return 0;
2592}
2593
2594
2595static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2596{
2597 struct drm_info_node *node = (struct drm_info_node *) m->private;
2598 struct drm_device *dev = node->minor->dev;
2599 struct radeon_device *rdev = dev->dev_private;
2600 uint32_t csq_stat, csq2_stat, tmp;
2601 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2602 unsigned i;
2603
2604 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2605 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2606 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2607 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2608 r_rptr = (csq_stat >> 0) & 0x3ff;
2609 r_wptr = (csq_stat >> 10) & 0x3ff;
2610 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2611 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2612 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2613 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2614 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2615 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2616 seq_printf(m, "Ring rptr %u\n", r_rptr);
2617 seq_printf(m, "Ring wptr %u\n", r_wptr);
2618 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2619 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2620 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2621 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2622 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2623 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2624 seq_printf(m, "Ring fifo:\n");
2625 for (i = 0; i < 256; i++) {
2626 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2627 tmp = RREG32(RADEON_CP_CSQ_DATA);
2628 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2629 }
2630 seq_printf(m, "Indirect1 fifo:\n");
2631 for (i = 256; i <= 512; i++) {
2632 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2633 tmp = RREG32(RADEON_CP_CSQ_DATA);
2634 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2635 }
2636 seq_printf(m, "Indirect2 fifo:\n");
2637 for (i = 640; i < ib1_wptr; i++) {
2638 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2639 tmp = RREG32(RADEON_CP_CSQ_DATA);
2640 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2641 }
2642 return 0;
2643}
2644
2645static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2646{
2647 struct drm_info_node *node = (struct drm_info_node *) m->private;
2648 struct drm_device *dev = node->minor->dev;
2649 struct radeon_device *rdev = dev->dev_private;
2650 uint32_t tmp;
2651
2652 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2653 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2654 tmp = RREG32(RADEON_MC_FB_LOCATION);
2655 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2656 tmp = RREG32(RADEON_BUS_CNTL);
2657 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2658 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2659 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2660 tmp = RREG32(RADEON_AGP_BASE);
2661 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2662 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2663 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2664 tmp = RREG32(0x01D0);
2665 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2666 tmp = RREG32(RADEON_AIC_LO_ADDR);
2667 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2668 tmp = RREG32(RADEON_AIC_HI_ADDR);
2669 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2670 tmp = RREG32(0x01E4);
2671 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2672 return 0;
2673}
2674
2675static struct drm_info_list r100_debugfs_rbbm_list[] = {
2676 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2677};
2678
2679static struct drm_info_list r100_debugfs_cp_list[] = {
2680 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2681 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2682};
2683
2684static struct drm_info_list r100_debugfs_mc_info_list[] = {
2685 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2686};
2687#endif
2688
2689int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2690{
2691#if defined(CONFIG_DEBUG_FS)
2692 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2693#else
2694 return 0;
2695#endif
2696}
2697
2698int r100_debugfs_cp_init(struct radeon_device *rdev)
2699{
2700#if defined(CONFIG_DEBUG_FS)
2701 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2702#else
2703 return 0;
2704#endif
2705}
2706
2707int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2708{
2709#if defined(CONFIG_DEBUG_FS)
2710 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2711#else
2712 return 0;
2713#endif
2714}
e024e110
DA		 2715
2716int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2717 uint32_t tiling_flags, uint32_t pitch,
2718 uint32_t offset, uint32_t obj_size)
2719{
2720 int surf_index = reg * 16;
2721 int flags = 0;
2722
e024e110
DA		 2723 if (rdev->family <= CHIP_RS200) {
2724 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2725 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2726 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2727 if (tiling_flags & RADEON_TILING_MACRO)
2728 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2729 } else if (rdev->family <= CHIP_RV280) {
2730 if (tiling_flags & (RADEON_TILING_MACRO))
2731 flags |= R200_SURF_TILE_COLOR_MACRO;
2732 if (tiling_flags & RADEON_TILING_MICRO)
2733 flags |= R200_SURF_TILE_COLOR_MICRO;
2734 } else {
2735 if (tiling_flags & RADEON_TILING_MACRO)
2736 flags |= R300_SURF_TILE_MACRO;
2737 if (tiling_flags & RADEON_TILING_MICRO)
2738 flags |= R300_SURF_TILE_MICRO;
2739 }
2740
c88f9f0c
MD		 2741 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2742 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2743 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2744 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2745
f5c5f040
DA		 2746 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2747 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2748 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2749 if (ASIC_IS_RN50(rdev))
2750 pitch /= 16;
2751 }
2752
2753 /* r100/r200 divide by 16 */
2754 if (rdev->family < CHIP_R300)
2755 flags |= pitch / 16;
2756 else
2757 flags |= pitch / 8;
2758
2759
d9fdaafb 2760 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
e024e110
DA		 2761 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2762 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2763 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2764 return 0;
2765}
2766
2767void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2768{
2769 int surf_index = reg * 16;
2770 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2771}
c93bb85b
JG		 2772
2773void r100_bandwidth_update(struct radeon_device *rdev)
2774{
2775 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2776 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2777 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2778 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2779 fixed20_12 memtcas_ff[8] = {
68adac5e
BS		 2780 dfixed_init(1),
2781 dfixed_init(2),
2782 dfixed_init(3),
2783 dfixed_init(0),
2784 dfixed_init_half(1),
2785 dfixed_init_half(2),
2786 dfixed_init(0),
c93bb85b
JG		 2787 };
2788 fixed20_12 memtcas_rs480_ff[8] = {
68adac5e
BS		 2789 dfixed_init(0),
2790 dfixed_init(1),
2791 dfixed_init(2),
2792 dfixed_init(3),
2793 dfixed_init(0),
2794 dfixed_init_half(1),
2795 dfixed_init_half(2),
2796 dfixed_init_half(3),
c93bb85b
JG		 2797 };
2798 fixed20_12 memtcas2_ff[8] = {
68adac5e
BS		 2799 dfixed_init(0),
2800 dfixed_init(1),
2801 dfixed_init(2),
2802 dfixed_init(3),
2803 dfixed_init(4),
2804 dfixed_init(5),
2805 dfixed_init(6),
2806 dfixed_init(7),
c93bb85b
JG		 2807 };
2808 fixed20_12 memtrbs[8] = {
68adac5e
BS		 2809 dfixed_init(1),
2810 dfixed_init_half(1),
2811 dfixed_init(2),
2812 dfixed_init_half(2),
2813 dfixed_init(3),
2814 dfixed_init_half(3),
2815 dfixed_init(4),
2816 dfixed_init_half(4)
c93bb85b
JG		 2817 };
2818 fixed20_12 memtrbs_r4xx[8] = {
68adac5e
BS		 2819 dfixed_init(4),
2820 dfixed_init(5),
2821 dfixed_init(6),
2822 dfixed_init(7),
2823 dfixed_init(8),
2824 dfixed_init(9),
2825 dfixed_init(10),
2826 dfixed_init(11)
c93bb85b
JG		 2827 };
2828 fixed20_12 min_mem_eff;
2829 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2830 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2831 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2832 disp_drain_rate2, read_return_rate;
2833 fixed20_12 time_disp1_drop_priority;
2834 int c;
2835 int cur_size = 16; /* in octawords */
2836 int critical_point = 0, critical_point2;
2837/* uint32_t read_return_rate, time_disp1_drop_priority; */
2838 int stop_req, max_stop_req;
2839 struct drm_display_mode *mode1 = NULL;
2840 struct drm_display_mode *mode2 = NULL;
2841 uint32_t pixel_bytes1 = 0;
2842 uint32_t pixel_bytes2 = 0;
2843
f46c0120
AD		 2844 radeon_update_display_priority(rdev);
2845
c93bb85b
JG		 2846 if (rdev->mode_info.crtcs[0]->base.enabled) {
2847 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2848 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2849 }
dfee5614
DA		 2850 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2851 if (rdev->mode_info.crtcs[1]->base.enabled) {
2852 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2853 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2854 }
c93bb85b
JG		 2855 }
2856
68adac5e 2857 min_mem_eff.full = dfixed_const_8(0);
c93bb85b
JG		 2858 /* get modes */
2859 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2860 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2861 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2862 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2863 /* check crtc enables */
2864 if (mode2)
2865 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2866 if (mode1)
2867 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2868 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2869 }
2870
2871 /*
2872 * determine is there is enough bw for current mode
2873 */
f47299c5
AD		 2874 sclk_ff = rdev->pm.sclk;
2875 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2876
2877 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
68adac5e
BS		 2878 temp_ff.full = dfixed_const(temp);
2879 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 2880
2881 pix_clk.full = 0;
2882 pix_clk2.full = 0;
2883 peak_disp_bw.full = 0;
2884 if (mode1) {
68adac5e
BS		 2885 temp_ff.full = dfixed_const(1000);
2886 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2887 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2888 temp_ff.full = dfixed_const(pixel_bytes1);
2889 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
c93bb85b
JG		 2890 }
2891 if (mode2) {
68adac5e
BS		 2892 temp_ff.full = dfixed_const(1000);
2893 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2894 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2895 temp_ff.full = dfixed_const(pixel_bytes2);
2896 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
c93bb85b
JG		 2897 }
2898
68adac5e 2899 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
c93bb85b
JG		 2900 if (peak_disp_bw.full >= mem_bw.full) {
2901 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2902 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2903 }
2904
2905 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2906 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2907 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2908 mem_trcd = ((temp >> 2) & 0x3) + 1;
2909 mem_trp = ((temp & 0x3)) + 1;
2910 mem_tras = ((temp & 0x70) >> 4) + 1;
2911 } else if (rdev->family == CHIP_R300 ||
2912 rdev->family == CHIP_R350) { /* r300, r350 */
2913 mem_trcd = (temp & 0x7) + 1;
2914 mem_trp = ((temp >> 8) & 0x7) + 1;
2915 mem_tras = ((temp >> 11) & 0xf) + 4;
2916 } else if (rdev->family == CHIP_RV350 ||
2917 rdev->family <= CHIP_RV380) {
2918 /* rv3x0 */
2919 mem_trcd = (temp & 0x7) + 3;
2920 mem_trp = ((temp >> 8) & 0x7) + 3;
2921 mem_tras = ((temp >> 11) & 0xf) + 6;
2922 } else if (rdev->family == CHIP_R420 ||
2923 rdev->family == CHIP_R423 ||
2924 rdev->family == CHIP_RV410) {
2925 /* r4xx */
2926 mem_trcd = (temp & 0xf) + 3;
2927 if (mem_trcd > 15)
2928 mem_trcd = 15;
2929 mem_trp = ((temp >> 8) & 0xf) + 3;
2930 if (mem_trp > 15)
2931 mem_trp = 15;
2932 mem_tras = ((temp >> 12) & 0x1f) + 6;
2933 if (mem_tras > 31)
2934 mem_tras = 31;
2935 } else { /* RV200, R200 */
2936 mem_trcd = (temp & 0x7) + 1;
2937 mem_trp = ((temp >> 8) & 0x7) + 1;
2938 mem_tras = ((temp >> 12) & 0xf) + 4;
2939 }
2940 /* convert to FF */
68adac5e
BS		 2941 trcd_ff.full = dfixed_const(mem_trcd);
2942 trp_ff.full = dfixed_const(mem_trp);
2943 tras_ff.full = dfixed_const(mem_tras);
c93bb85b
JG		 2944
2945 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2946 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2947 data = (temp & (7 << 20)) >> 20;
2948 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2949 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2950 tcas_ff = memtcas_rs480_ff[data];
2951 else
2952 tcas_ff = memtcas_ff[data];
2953 } else
2954 tcas_ff = memtcas2_ff[data];
2955
2956 if (rdev->family == CHIP_RS400 ||
2957 rdev->family == CHIP_RS480) {
2958 /* extra cas latency stored in bits 23-25 0-4 clocks */
2959 data = (temp >> 23) & 0x7;
2960 if (data < 5)
68adac5e 2961 tcas_ff.full += dfixed_const(data);
c93bb85b
JG		 2962 }
2963
2964 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2965 /* on the R300, Tcas is included in Trbs.
2966 */
2967 temp = RREG32(RADEON_MEM_CNTL);
2968 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2969 if (data == 1) {
2970 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2971 temp = RREG32(R300_MC_IND_INDEX);
2972 temp &= ~R300_MC_IND_ADDR_MASK;
2973 temp |= R300_MC_READ_CNTL_CD_mcind;
2974 WREG32(R300_MC_IND_INDEX, temp);
2975 temp = RREG32(R300_MC_IND_DATA);
2976 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2977 } else {
2978 temp = RREG32(R300_MC_READ_CNTL_AB);
2979 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2980 }
2981 } else {
2982 temp = RREG32(R300_MC_READ_CNTL_AB);
2983 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2984 }
2985 if (rdev->family == CHIP_RV410 ||
2986 rdev->family == CHIP_R420 ||
2987 rdev->family == CHIP_R423)
2988 trbs_ff = memtrbs_r4xx[data];
2989 else
2990 trbs_ff = memtrbs[data];
2991 tcas_ff.full += trbs_ff.full;
2992 }
2993
2994 sclk_eff_ff.full = sclk_ff.full;
2995
2996 if (rdev->flags & RADEON_IS_AGP) {
2997 fixed20_12 agpmode_ff;
68adac5e
BS		 2998 agpmode_ff.full = dfixed_const(radeon_agpmode);
2999 temp_ff.full = dfixed_const_666(16);
3000 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
c93bb85b
JG		 3001 }
3002 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3003
3004 if (ASIC_IS_R300(rdev)) {
68adac5e 3005 sclk_delay_ff.full = dfixed_const(250);
c93bb85b
JG		 3006 } else {
3007 if ((rdev->family == CHIP_RV100) ||
3008 rdev->flags & RADEON_IS_IGP) {
3009 if (rdev->mc.vram_is_ddr)
68adac5e 3010 sclk_delay_ff.full = dfixed_const(41);
c93bb85b 3011 else
68adac5e 3012 sclk_delay_ff.full = dfixed_const(33);
c93bb85b
JG		 3013 } else {
3014 if (rdev->mc.vram_width == 128)
68adac5e 3015 sclk_delay_ff.full = dfixed_const(57);
c93bb85b 3016 else
68adac5e 3017 sclk_delay_ff.full = dfixed_const(41);
c93bb85b
JG		 3018 }
3019 }
3020
68adac5e 3021 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
c93bb85b
JG		 3022
3023 if (rdev->mc.vram_is_ddr) {
3024 if (rdev->mc.vram_width == 32) {
68adac5e 3025 k1.full = dfixed_const(40);
c93bb85b
JG		 3026 c = 3;
3027 } else {
68adac5e 3028 k1.full = dfixed_const(20);
c93bb85b
JG		 3029 c = 1;
3030 }
3031 } else {
68adac5e 3032 k1.full = dfixed_const(40);
c93bb85b
JG		 3033 c = 3;
3034 }
3035
68adac5e
BS		 3036 temp_ff.full = dfixed_const(2);
3037 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3038 temp_ff.full = dfixed_const(c);
3039 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3040 temp_ff.full = dfixed_const(4);
3041 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3042 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
c93bb85b
JG		 3043 mc_latency_mclk.full += k1.full;
3044
68adac5e
BS		 3045 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3046 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3047
3048 /*
3049 HW cursor time assuming worst case of full size colour cursor.
3050 */
68adac5e 3051 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
c93bb85b
JG		 3052 temp_ff.full += trcd_ff.full;
3053 if (temp_ff.full < tras_ff.full)
3054 temp_ff.full = tras_ff.full;
68adac5e 3055 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
c93bb85b 3056
68adac5e
BS		 3057 temp_ff.full = dfixed_const(cur_size);
3058 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3059 /*
3060 Find the total latency for the display data.
3061 */
68adac5e
BS		 3062 disp_latency_overhead.full = dfixed_const(8);
3063 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
c93bb85b
JG		 3064 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3065 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3066
3067 if (mc_latency_mclk.full > mc_latency_sclk.full)
3068 disp_latency.full = mc_latency_mclk.full;
3069 else
3070 disp_latency.full = mc_latency_sclk.full;
3071
3072 /* setup Max GRPH_STOP_REQ default value */
3073 if (ASIC_IS_RV100(rdev))
3074 max_stop_req = 0x5c;
3075 else
3076 max_stop_req = 0x7c;
3077
3078 if (mode1) {
3079 /* CRTC1
3080 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3081 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3082 */
3083 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3084
3085 if (stop_req > max_stop_req)
3086 stop_req = max_stop_req;
3087
3088 /*
3089 Find the drain rate of the display buffer.
3090 */
68adac5e
BS		 3091 temp_ff.full = dfixed_const((16/pixel_bytes1));
3092 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
c93bb85b
JG		 3093
3094 /*
3095 Find the critical point of the display buffer.
3096 */
68adac5e
BS		 3097 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3098 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3099
68adac5e 3100 critical_point = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3101
3102 if (rdev->disp_priority == 2) {
3103 critical_point = 0;
3104 }
3105
3106 /*
3107 The critical point should never be above max_stop_req-4. Setting
3108 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3109 */
3110 if (max_stop_req - critical_point < 4)
3111 critical_point = 0;
3112
3113 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3114 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3115 critical_point = 0x10;
3116 }
3117
3118 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3119 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3120 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3121 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3122 if ((rdev->family == CHIP_R350) &&
3123 (stop_req > 0x15)) {
3124 stop_req -= 0x10;
3125 }
3126 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3127 temp |= RADEON_GRPH_BUFFER_SIZE;
3128 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3129 RADEON_GRPH_CRITICAL_AT_SOF |
3130 RADEON_GRPH_STOP_CNTL);
3131 /*
3132 Write the result into the register.
3133 */
3134 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3135 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3136
3137#if 0
3138 if ((rdev->family == CHIP_RS400) ||
3139 (rdev->family == CHIP_RS480)) {
3140 /* attempt to program RS400 disp regs correctly ??? */
3141 temp = RREG32(RS400_DISP1_REG_CNTL);
3142 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3143 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3144 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3145 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3146 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3147 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3148 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3149 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3150 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3151 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3152 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3153 }
3154#endif
3155
d9fdaafb 3156 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3157 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3158 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3159 }
3160
3161 if (mode2) {
3162 u32 grph2_cntl;
3163 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3164
3165 if (stop_req > max_stop_req)
3166 stop_req = max_stop_req;
3167
3168 /*
3169 Find the drain rate of the display buffer.
3170 */
68adac5e
BS		 3171 temp_ff.full = dfixed_const((16/pixel_bytes2));
3172 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
c93bb85b
JG		 3173
3174 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3175 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3176 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3177 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3178 if ((rdev->family == CHIP_R350) &&
3179 (stop_req > 0x15)) {
3180 stop_req -= 0x10;
3181 }
3182 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3183 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3184 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3185 RADEON_GRPH_CRITICAL_AT_SOF |
3186 RADEON_GRPH_STOP_CNTL);
3187
3188 if ((rdev->family == CHIP_RS100) ||
3189 (rdev->family == CHIP_RS200))
3190 critical_point2 = 0;
3191 else {
3192 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
68adac5e
BS		 3193 temp_ff.full = dfixed_const(temp);
3194 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 3195 if (sclk_ff.full < temp_ff.full)
3196 temp_ff.full = sclk_ff.full;
3197
3198 read_return_rate.full = temp_ff.full;
3199
3200 if (mode1) {
3201 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
68adac5e 3202 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
c93bb85b
JG		 3203 } else {
3204 time_disp1_drop_priority.full = 0;
3205 }
3206 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
68adac5e
BS		 3207 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3208 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3209
68adac5e 3210 critical_point2 = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3211
3212 if (rdev->disp_priority == 2) {
3213 critical_point2 = 0;
3214 }
3215
3216 if (max_stop_req - critical_point2 < 4)
3217 critical_point2 = 0;
3218
3219 }
3220
3221 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3222 /* some R300 cards have problem with this set to 0 */
3223 critical_point2 = 0x10;
3224 }
3225
3226 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3227 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3228
3229 if ((rdev->family == CHIP_RS400) ||
3230 (rdev->family == CHIP_RS480)) {
3231#if 0
3232 /* attempt to program RS400 disp2 regs correctly ??? */
3233 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3234 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3235 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3236 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3237 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3238 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3239 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3240 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3241 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3242 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3243 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3244 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3245#endif
3246 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3247 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3248 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3249 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3250 }
3251
d9fdaafb 3252 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3253 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3254 }
3255}
551ebd83 3256
cbdd4501 3257static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
551ebd83
DA		 3258{
3259 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 3260 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 3261 DRM_ERROR("width %d\n", t->width);
ceb776bc 3262 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 3263 DRM_ERROR("height %d\n", t->height);
ceb776bc 3264 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 3265 DRM_ERROR("num levels %d\n", t->num_levels);
3266 DRM_ERROR("depth %d\n", t->txdepth);
3267 DRM_ERROR("bpp %d\n", t->cpp);
3268 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3269 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3270 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 3271 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 3272}
3273
d785d78b
DA		 3274static int r100_track_compress_size(int compress_format, int w, int h)
3275{
3276 int block_width, block_height, block_bytes;
3277 int wblocks, hblocks;
3278 int min_wblocks;
3279 int sz;
3280
3281 block_width = 4;
3282 block_height = 4;
3283
3284 switch (compress_format) {
3285 case R100_TRACK_COMP_DXT1:
3286 block_bytes = 8;
3287 min_wblocks = 4;
3288 break;
3289 default:
3290 case R100_TRACK_COMP_DXT35:
3291 block_bytes = 16;
3292 min_wblocks = 2;
3293 break;
3294 }
3295
3296 hblocks = (h + block_height - 1) / block_height;
3297 wblocks = (w + block_width - 1) / block_width;
3298 if (wblocks < min_wblocks)
3299 wblocks = min_wblocks;
3300 sz = wblocks * hblocks * block_bytes;
3301 return sz;
3302}
3303
37cf6b03
RS		 3304static int r100_cs_track_cube(struct radeon_device *rdev,
3305 struct r100_cs_track *track, unsigned idx)
3306{
3307 unsigned face, w, h;
3308 struct radeon_bo *cube_robj;
3309 unsigned long size;
3310 unsigned compress_format = track->textures[idx].compress_format;
3311
3312 for (face = 0; face < 5; face++) {
3313 cube_robj = track->textures[idx].cube_info[face].robj;
3314 w = track->textures[idx].cube_info[face].width;
3315 h = track->textures[idx].cube_info[face].height;
3316
3317 if (compress_format) {
3318 size = r100_track_compress_size(compress_format, w, h);
3319 } else
3320 size = w * h;
3321 size *= track->textures[idx].cpp;
3322
3323 size += track->textures[idx].cube_info[face].offset;
3324
3325 if (size > radeon_bo_size(cube_robj)) {
3326 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3327 size, radeon_bo_size(cube_robj));
3328 r100_cs_track_texture_print(&track->textures[idx]);
3329 return -1;
3330 }
3331 }
3332 return 0;
3333}
3334
551ebd83
DA		 3335static int r100_cs_track_texture_check(struct radeon_device *rdev,
3336 struct r100_cs_track *track)
3337{
4c788679 3338 struct radeon_bo *robj;
551ebd83 3339 unsigned long size;
b73c5f8b 3340 unsigned u, i, w, h, d;
551ebd83
DA		 3341 int ret;
3342
3343 for (u = 0; u < track->num_texture; u++) {
3344 if (!track->textures[u].enabled)
3345 continue;
43b93fbf
AD		 3346 if (track->textures[u].lookup_disable)
3347 continue;
551ebd83
DA		 3348 robj = track->textures[u].robj;
3349 if (robj == NULL) {
3350 DRM_ERROR("No texture bound to unit %u\n", u);
3351 return -EINVAL;
3352 }
3353 size = 0;
3354 for (i = 0; i <= track->textures[u].num_levels; i++) {
3355 if (track->textures[u].use_pitch) {
3356 if (rdev->family < CHIP_R300)
3357 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3358 else
3359 w = track->textures[u].pitch / (1 << i);
3360 } else {
ceb776bc 3361 w = track->textures[u].width;
551ebd83
DA		 3362 if (rdev->family >= CHIP_RV515)
3363 w |= track->textures[u].width_11;
ceb776bc 3364 w = w / (1 << i);
551ebd83
DA		 3365 if (track->textures[u].roundup_w)
3366 w = roundup_pow_of_two(w);
3367 }
ceb776bc 3368 h = track->textures[u].height;
551ebd83
DA		 3369 if (rdev->family >= CHIP_RV515)
3370 h |= track->textures[u].height_11;
ceb776bc 3371 h = h / (1 << i);
551ebd83
DA		 3372 if (track->textures[u].roundup_h)
3373 h = roundup_pow_of_two(h);
b73c5f8b
MO		 3374 if (track->textures[u].tex_coord_type == 1) {
3375 d = (1 << track->textures[u].txdepth) / (1 << i);
3376 if (!d)
3377 d = 1;
3378 } else {
3379 d = 1;
3380 }
d785d78b
DA		 3381 if (track->textures[u].compress_format) {
3382
b73c5f8b 3383 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
d785d78b
DA		 3384 /* compressed textures are block based */
3385 } else
b73c5f8b 3386 size += w * h * d;
551ebd83
DA		 3387 }
3388 size *= track->textures[u].cpp;
d785d78b 3389
551ebd83
DA		 3390 switch (track->textures[u].tex_coord_type) {
3391 case 0:
551ebd83 3392 case 1:
551ebd83
DA		 3393 break;
3394 case 2:
3395 if (track->separate_cube) {
3396 ret = r100_cs_track_cube(rdev, track, u);
3397 if (ret)
3398 return ret;
3399 } else
3400 size *= 6;
3401 break;
3402 default:
3403 DRM_ERROR("Invalid texture coordinate type %u for unit "
3404 "%u\n", track->textures[u].tex_coord_type, u);
3405 return -EINVAL;
3406 }
4c788679 3407 if (size > radeon_bo_size(robj)) {
551ebd83 3408 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 3409 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 3410 r100_cs_track_texture_print(&track->textures[u]);
3411 return -EINVAL;
3412 }
3413 }
3414 return 0;
3415}
3416
3417int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3418{
3419 unsigned i;
3420 unsigned long size;
3421 unsigned prim_walk;
3422 unsigned nverts;
40b4a759 3423 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
551ebd83 3424
40b4a759 3425 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
a41ceb1c
MO		 3426 !track->blend_read_enable)
3427 num_cb = 0;
3428
3429 for (i = 0; i < num_cb; i++) {
551ebd83
DA		 3430 if (track->cb[i].robj == NULL) {
3431 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3432 return -EINVAL;
3433 }
3434 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3435 size += track->cb[i].offset;
4c788679 3436 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 3437 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3438 "(need %lu have %lu) !\n", i, size,
4c788679 3439 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 3440 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3441 i, track->cb[i].pitch, track->cb[i].cpp,
3442 track->cb[i].offset, track->maxy);
3443 return -EINVAL;
3444 }
3445 }
40b4a759
MO		 3446 track->cb_dirty = false;
3447
3448 if (track->zb_dirty && track->z_enabled) {
551ebd83
DA		 3449 if (track->zb.robj == NULL) {
3450 DRM_ERROR("[drm] No buffer for z buffer !\n");
3451 return -EINVAL;
3452 }
3453 size = track->zb.pitch * track->zb.cpp * track->maxy;
3454 size += track->zb.offset;
4c788679 3455 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 3456 DRM_ERROR("[drm] Buffer too small for z buffer "
3457 "(need %lu have %lu) !\n", size,
4c788679 3458 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3459 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3460 track->zb.pitch, track->zb.cpp,
3461 track->zb.offset, track->maxy);
3462 return -EINVAL;
3463 }
3464 }
40b4a759
MO		 3465 track->zb_dirty = false;
3466
fff1ce4d
MO		 3467 if (track->aa_dirty && track->aaresolve) {
3468 if (track->aa.robj == NULL) {
3469 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3470 return -EINVAL;
3471 }
3472 /* I believe the format comes from colorbuffer0. */
3473 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3474 size += track->aa.offset;
3475 if (size > radeon_bo_size(track->aa.robj)) {
3476 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3477 "(need %lu have %lu) !\n", i, size,
3478 radeon_bo_size(track->aa.robj));
3479 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3480 i, track->aa.pitch, track->cb[0].cpp,
3481 track->aa.offset, track->maxy);
3482 return -EINVAL;
3483 }
3484 }
3485 track->aa_dirty = false;
3486
551ebd83 3487 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
cae94b0a
MO		 3488 if (track->vap_vf_cntl & (1 << 14)) {
3489 nverts = track->vap_alt_nverts;
3490 } else {
3491 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3492 }
551ebd83
DA		 3493 switch (prim_walk) {
3494 case 1:
3495 for (i = 0; i < track->num_arrays; i++) {
3496 size = track->arrays[i].esize * track->max_indx * 4;
3497 if (track->arrays[i].robj == NULL) {
3498 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3499 "bound\n", prim_walk, i);
3500 return -EINVAL;
3501 }
4c788679
JG		 3502 if (size > radeon_bo_size(track->arrays[i].robj)) {
3503 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3504 "need %lu dwords have %lu dwords\n",
3505 prim_walk, i, size >> 2,
3506 radeon_bo_size(track->arrays[i].robj)
3507 >> 2);
551ebd83
DA		 3508 DRM_ERROR("Max indices %u\n", track->max_indx);
3509 return -EINVAL;
3510 }
3511 }
3512 break;
3513 case 2:
3514 for (i = 0; i < track->num_arrays; i++) {
3515 size = track->arrays[i].esize * (nverts - 1) * 4;
3516 if (track->arrays[i].robj == NULL) {
3517 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3518 "bound\n", prim_walk, i);
3519 return -EINVAL;
3520 }
4c788679
JG		 3521 if (size > radeon_bo_size(track->arrays[i].robj)) {
3522 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3523 "need %lu dwords have %lu dwords\n",
3524 prim_walk, i, size >> 2,
3525 radeon_bo_size(track->arrays[i].robj)
3526 >> 2);
551ebd83
DA		 3527 return -EINVAL;
3528 }
3529 }
3530 break;
3531 case 3:
3532 size = track->vtx_size * nverts;
3533 if (size != track->immd_dwords) {
3534 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3535 track->immd_dwords, size);
3536 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3537 nverts, track->vtx_size);
3538 return -EINVAL;
3539 }
3540 break;
3541 default:
3542 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3543 prim_walk);
3544 return -EINVAL;
3545 }
40b4a759
MO		 3546
3547 if (track->tex_dirty) {
3548 track->tex_dirty = false;
3549 return r100_cs_track_texture_check(rdev, track);
3550 }
3551 return 0;
551ebd83
DA		 3552}
3553
3554void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3555{
3556 unsigned i, face;
3557
40b4a759
MO		 3558 track->cb_dirty = true;
3559 track->zb_dirty = true;
3560 track->tex_dirty = true;
fff1ce4d 3561 track->aa_dirty = true;
40b4a759 3562
551ebd83
DA		 3563 if (rdev->family < CHIP_R300) {
3564 track->num_cb = 1;
3565 if (rdev->family <= CHIP_RS200)
3566 track->num_texture = 3;
3567 else
3568 track->num_texture = 6;
3569 track->maxy = 2048;
3570 track->separate_cube = 1;
3571 } else {
3572 track->num_cb = 4;
3573 track->num_texture = 16;
3574 track->maxy = 4096;
3575 track->separate_cube = 0;
45e4039c 3576 track->aaresolve = false;
fff1ce4d 3577 track->aa.robj = NULL;
551ebd83
DA		 3578 }
3579
3580 for (i = 0; i < track->num_cb; i++) {
3581 track->cb[i].robj = NULL;
3582 track->cb[i].pitch = 8192;
3583 track->cb[i].cpp = 16;
3584 track->cb[i].offset = 0;
3585 }
3586 track->z_enabled = true;
3587 track->zb.robj = NULL;
3588 track->zb.pitch = 8192;
3589 track->zb.cpp = 4;
3590 track->zb.offset = 0;
3591 track->vtx_size = 0x7F;
3592 track->immd_dwords = 0xFFFFFFFFUL;
3593 track->num_arrays = 11;
3594 track->max_indx = 0x00FFFFFFUL;
3595 for (i = 0; i < track->num_arrays; i++) {
3596 track->arrays[i].robj = NULL;
3597 track->arrays[i].esize = 0x7F;
3598 }
3599 for (i = 0; i < track->num_texture; i++) {
d785d78b 3600 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3601 track->textures[i].pitch = 16536;
3602 track->textures[i].width = 16536;
3603 track->textures[i].height = 16536;
3604 track->textures[i].width_11 = 1 << 11;
3605 track->textures[i].height_11 = 1 << 11;
3606 track->textures[i].num_levels = 12;
3607 if (rdev->family <= CHIP_RS200) {
3608 track->textures[i].tex_coord_type = 0;
3609 track->textures[i].txdepth = 0;
3610 } else {
3611 track->textures[i].txdepth = 16;
3612 track->textures[i].tex_coord_type = 1;
3613 }
3614 track->textures[i].cpp = 64;
3615 track->textures[i].robj = NULL;
3616 /* CS IB emission code makes sure texture unit are disabled */
3617 track->textures[i].enabled = false;
43b93fbf 3618 track->textures[i].lookup_disable = false;
551ebd83
DA		 3619 track->textures[i].roundup_w = true;
3620 track->textures[i].roundup_h = true;
3621 if (track->separate_cube)
3622 for (face = 0; face < 5; face++) {
3623 track->textures[i].cube_info[face].robj = NULL;
3624 track->textures[i].cube_info[face].width = 16536;
3625 track->textures[i].cube_info[face].height = 16536;
3626 track->textures[i].cube_info[face].offset = 0;
3627 }
3628 }
3629}
3ce0a23d
JG		 3630
3631int r100_ring_test(struct radeon_device *rdev)
3632{
3633 uint32_t scratch;
3634 uint32_t tmp = 0;
3635 unsigned i;
3636 int r;
3637
3638 r = radeon_scratch_get(rdev, &scratch);
3639 if (r) {
3640 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3641 return r;
3642 }
3643 WREG32(scratch, 0xCAFEDEAD);
3644 r = radeon_ring_lock(rdev, 2);
3645 if (r) {
3646 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3647 radeon_scratch_free(rdev, scratch);
3648 return r;
3649 }
3650 radeon_ring_write(rdev, PACKET0(scratch, 0));
3651 radeon_ring_write(rdev, 0xDEADBEEF);
3652 radeon_ring_unlock_commit(rdev);
3653 for (i = 0; i < rdev->usec_timeout; i++) {
3654 tmp = RREG32(scratch);
3655 if (tmp == 0xDEADBEEF) {
3656 break;
3657 }
3658 DRM_UDELAY(1);
3659 }
3660 if (i < rdev->usec_timeout) {
3661 DRM_INFO("ring test succeeded in %d usecs\n", i);
3662 } else {
369d7ec1 3663 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3664 scratch, tmp);
3665 r = -EINVAL;
3666 }
3667 radeon_scratch_free(rdev, scratch);
3668 return r;
3669}
3670
3671void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3672{
3673 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3674 radeon_ring_write(rdev, ib->gpu_addr);
3675 radeon_ring_write(rdev, ib->length_dw);
3676}
3677
3678int r100_ib_test(struct radeon_device *rdev)
3679{
3680 struct radeon_ib *ib;
3681 uint32_t scratch;
3682 uint32_t tmp = 0;
3683 unsigned i;
3684 int r;
3685
3686 r = radeon_scratch_get(rdev, &scratch);
3687 if (r) {
3688 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3689 return r;
3690 }
3691 WREG32(scratch, 0xCAFEDEAD);
3692 r = radeon_ib_get(rdev, &ib);
3693 if (r) {
3694 return r;
3695 }
3696 ib->ptr[0] = PACKET0(scratch, 0);
3697 ib->ptr[1] = 0xDEADBEEF;
3698 ib->ptr[2] = PACKET2(0);
3699 ib->ptr[3] = PACKET2(0);
3700 ib->ptr[4] = PACKET2(0);
3701 ib->ptr[5] = PACKET2(0);
3702 ib->ptr[6] = PACKET2(0);
3703 ib->ptr[7] = PACKET2(0);
3704 ib->length_dw = 8;
3705 r = radeon_ib_schedule(rdev, ib);
3706 if (r) {
3707 radeon_scratch_free(rdev, scratch);
3708 radeon_ib_free(rdev, &ib);
3709 return r;
3710 }
3711 r = radeon_fence_wait(ib->fence, false);
3712 if (r) {
3713 return r;
3714 }
3715 for (i = 0; i < rdev->usec_timeout; i++) {
3716 tmp = RREG32(scratch);
3717 if (tmp == 0xDEADBEEF) {
3718 break;
3719 }
3720 DRM_UDELAY(1);
3721 }
3722 if (i < rdev->usec_timeout) {
3723 DRM_INFO("ib test succeeded in %u usecs\n", i);
3724 } else {
62f288cf 3725 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3726 scratch, tmp);
3727 r = -EINVAL;
3728 }
3729 radeon_scratch_free(rdev, scratch);
3730 radeon_ib_free(rdev, &ib);
3731 return r;
3732}
9f022ddf
JG		 3733
3734void r100_ib_fini(struct radeon_device *rdev)
3735{
3736 radeon_ib_pool_fini(rdev);
3737}
3738
3739int r100_ib_init(struct radeon_device *rdev)
3740{
3741 int r;
3742
3743 r = radeon_ib_pool_init(rdev);
3744 if (r) {
ec4f2ac4 3745 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
9f022ddf
JG		 3746 r100_ib_fini(rdev);
3747 return r;
3748 }
3749 r = r100_ib_test(rdev);
3750 if (r) {
ec4f2ac4 3751 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
9f022ddf
JG		 3752 r100_ib_fini(rdev);
3753 return r;
3754 }
3755 return 0;
3756}
3757
3758void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3759{
3760 /* Shutdown CP we shouldn't need to do that but better be safe than
3761 * sorry
3762 */
3763 rdev->cp.ready = false;
3764 WREG32(R_000740_CP_CSQ_CNTL, 0);
3765
3766 /* Save few CRTC registers */
ca6ffc64 3767 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3768 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3769 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3770 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3771 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3772 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3773 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3774 }
3775
3776 /* Disable VGA aperture access */
ca6ffc64 3777 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3778 /* Disable cursor, overlay, crtc */
3779 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3780 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3781 S_000054_CRTC_DISPLAY_DIS(1));
3782 WREG32(R_000050_CRTC_GEN_CNTL,
3783 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3784 S_000050_CRTC_DISP_REQ_EN_B(1));
3785 WREG32(R_000420_OV0_SCALE_CNTL,
3786 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3787 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3788 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3789 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3790 S_000360_CUR2_LOCK(1));
3791 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3792 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3793 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3794 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3795 WREG32(R_000360_CUR2_OFFSET,
3796 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3797 }
3798}
3799
3800void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3801{
3802 /* Update base address for crtc */
d594e46a 3803 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3804 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3805 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3806 }
3807 /* Restore CRTC registers */
ca6ffc64 3808 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3809 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3810 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3811 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3812 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3813 }
3814}
ca6ffc64
JG		 3815
3816void r100_vga_render_disable(struct radeon_device *rdev)
3817{
d4550907 3818 u32 tmp;
ca6ffc64 3819
d4550907 3820 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3821 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3822}
d4550907
JG		 3823
3824static void r100_debugfs(struct radeon_device *rdev)
3825{
3826 int r;
3827
3828 r = r100_debugfs_mc_info_init(rdev);
3829 if (r)
3830 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3831}
3832
3833static void r100_mc_program(struct radeon_device *rdev)
3834{
3835 struct r100_mc_save save;
3836
3837 /* Stops all mc clients */
3838 r100_mc_stop(rdev, &save);
3839 if (rdev->flags & RADEON_IS_AGP) {
3840 WREG32(R_00014C_MC_AGP_LOCATION,
3841 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3842 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3843 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3844 if (rdev->family > CHIP_RV200)
3845 WREG32(R_00015C_AGP_BASE_2,
3846 upper_32_bits(rdev->mc.agp_base) & 0xff);
3847 } else {
3848 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3849 WREG32(R_000170_AGP_BASE, 0);
3850 if (rdev->family > CHIP_RV200)
3851 WREG32(R_00015C_AGP_BASE_2, 0);
3852 }
3853 /* Wait for mc idle */
3854 if (r100_mc_wait_for_idle(rdev))
3855 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3856 /* Program MC, should be a 32bits limited address space */
3857 WREG32(R_000148_MC_FB_LOCATION,
3858 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3859 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3860 r100_mc_resume(rdev, &save);
3861}
3862
3863void r100_clock_startup(struct radeon_device *rdev)
3864{
3865 u32 tmp;
3866
3867 if (radeon_dynclks != -1 && radeon_dynclks)
3868 radeon_legacy_set_clock_gating(rdev, 1);
3869 /* We need to force on some of the block */
3870 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3871 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3872 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3873 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3874 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3875}
3876
3877static int r100_startup(struct radeon_device *rdev)
3878{
3879 int r;
3880
92cde00c
AD		 3881 /* set common regs */
3882 r100_set_common_regs(rdev);
3883 /* program mc */
d4550907
JG		 3884 r100_mc_program(rdev);
3885 /* Resume clock */
3886 r100_clock_startup(rdev);
d4550907
JG		 3887 /* Initialize GART (initialize after TTM so we can allocate
3888 * memory through TTM but finalize after TTM) */
17e15b0c 3889 r100_enable_bm(rdev);
d4550907
JG		 3890 if (rdev->flags & RADEON_IS_PCI) {
3891 r = r100_pci_gart_enable(rdev);
3892 if (r)
3893 return r;
3894 }
724c80e1
AD		 3895
3896 /* allocate wb buffer */
3897 r = radeon_wb_init(rdev);
3898 if (r)
3899 return r;
3900
d4550907 3901 /* Enable IRQ */
d4550907 3902 r100_irq_set(rdev);
cafe6609 3903 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3904 /* 1M ring buffer */
3905 r = r100_cp_init(rdev, 1024 * 1024);
3906 if (r) {
ec4f2ac4 3907 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3908 return r;
3909 }
d4550907
JG		 3910 r = r100_ib_init(rdev);
3911 if (r) {
ec4f2ac4 3912 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
d4550907
JG		 3913 return r;
3914 }
3915 return 0;
3916}
3917
3918int r100_resume(struct radeon_device *rdev)
3919{
3920 /* Make sur GART are not working */
3921 if (rdev->flags & RADEON_IS_PCI)
3922 r100_pci_gart_disable(rdev);
3923 /* Resume clock before doing reset */
3924 r100_clock_startup(rdev);
3925 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3926 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3927 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3928 RREG32(R_000E40_RBBM_STATUS),
3929 RREG32(R_0007C0_CP_STAT));
3930 }
3931 /* post */
3932 radeon_combios_asic_init(rdev->ddev);
3933 /* Resume clock after posting */
3934 r100_clock_startup(rdev);
550e2d92
DA		 3935 /* Initialize surface registers */
3936 radeon_surface_init(rdev);
d4550907
JG		 3937 return r100_startup(rdev);
3938}
3939
3940int r100_suspend(struct radeon_device *rdev)
3941{
3942 r100_cp_disable(rdev);
724c80e1 3943 radeon_wb_disable(rdev);
d4550907
JG		 3944 r100_irq_disable(rdev);
3945 if (rdev->flags & RADEON_IS_PCI)
3946 r100_pci_gart_disable(rdev);
3947 return 0;
3948}
3949
3950void r100_fini(struct radeon_device *rdev)
3951{
d4550907 3952 r100_cp_fini(rdev);
724c80e1 3953 radeon_wb_fini(rdev);
d4550907
JG		 3954 r100_ib_fini(rdev);
3955 radeon_gem_fini(rdev);
3956 if (rdev->flags & RADEON_IS_PCI)
3957 r100_pci_gart_fini(rdev);
d0269ed8 3958 radeon_agp_fini(rdev);
d4550907
JG		 3959 radeon_irq_kms_fini(rdev);
3960 radeon_fence_driver_fini(rdev);
4c788679 3961 radeon_bo_fini(rdev);
d4550907
JG		 3962 radeon_atombios_fini(rdev);
3963 kfree(rdev->bios);
3964 rdev->bios = NULL;
3965}
3966
4c712e6c
DA		 3967/*
3968 * Due to how kexec works, it can leave the hw fully initialised when it
3969 * boots the new kernel. However doing our init sequence with the CP and
3970 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3971 * do some quick sanity checks and restore sane values to avoid this
3972 * problem.
3973 */
3974void r100_restore_sanity(struct radeon_device *rdev)
3975{
3976 u32 tmp;
3977
3978 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3979 if (tmp) {
3980 WREG32(RADEON_CP_CSQ_CNTL, 0);
3981 }
3982 tmp = RREG32(RADEON_CP_RB_CNTL);
3983 if (tmp) {
3984 WREG32(RADEON_CP_RB_CNTL, 0);
3985 }
3986 tmp = RREG32(RADEON_SCRATCH_UMSK);
3987 if (tmp) {
3988 WREG32(RADEON_SCRATCH_UMSK, 0);
3989 }
3990}
3991
d4550907
JG		 3992int r100_init(struct radeon_device *rdev)
3993{
3994 int r;
3995
d4550907
JG		 3996 /* Register debugfs file specific to this group of asics */
3997 r100_debugfs(rdev);
3998 /* Disable VGA */
3999 r100_vga_render_disable(rdev);
4000 /* Initialize scratch registers */
4001 radeon_scratch_init(rdev);
4002 /* Initialize surface registers */
4003 radeon_surface_init(rdev);
4c712e6c
DA		 4004 /* sanity check some register to avoid hangs like after kexec */
4005 r100_restore_sanity(rdev);
d4550907
JG		 4006 /* TODO: disable VGA need to use VGA request */
4007 /* BIOS*/
4008 if (!radeon_get_bios(rdev)) {
4009 if (ASIC_IS_AVIVO(rdev))
4010 return -EINVAL;
4011 }
4012 if (rdev->is_atom_bios) {
4013 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4014 return -EINVAL;
4015 } else {
4016 r = radeon_combios_init(rdev);
4017 if (r)
4018 return r;
4019 }
4020 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4021 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4022 dev_warn(rdev->dev,
4023 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4024 RREG32(R_000E40_RBBM_STATUS),
4025 RREG32(R_0007C0_CP_STAT));
4026 }
4027 /* check if cards are posted or not */
72542d77
DA		 4028 if (radeon_boot_test_post_card(rdev) == false)
4029 return -EINVAL;
d4550907
JG		 4030 /* Set asic errata */
4031 r100_errata(rdev);
4032 /* Initialize clocks */
4033 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4034 /* initialize AGP */
4035 if (rdev->flags & RADEON_IS_AGP) {
4036 r = radeon_agp_init(rdev);
4037 if (r) {
4038 radeon_agp_disable(rdev);
4039 }
4040 }
4041 /* initialize VRAM */
4042 r100_mc_init(rdev);
d4550907
JG		 4043 /* Fence driver */
4044 r = radeon_fence_driver_init(rdev);
4045 if (r)
4046 return r;
4047 r = radeon_irq_kms_init(rdev);
4048 if (r)
4049 return r;
4050 /* Memory manager */
4c788679 4051 r = radeon_bo_init(rdev);
d4550907
JG		 4052 if (r)
4053 return r;
4054 if (rdev->flags & RADEON_IS_PCI) {
4055 r = r100_pci_gart_init(rdev);
4056 if (r)
4057 return r;
4058 }
4059 r100_set_safe_registers(rdev);
4060 rdev->accel_working = true;
4061 r = r100_startup(rdev);
4062 if (r) {
4063 /* Somethings want wront with the accel init stop accel */
4064 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4065 r100_cp_fini(rdev);
724c80e1 4066 radeon_wb_fini(rdev);
d4550907 4067 r100_ib_fini(rdev);
655efd3d 4068 radeon_irq_kms_fini(rdev);
d4550907
JG		 4069 if (rdev->flags & RADEON_IS_PCI)
4070 r100_pci_gart_fini(rdev);
d4550907
JG		 4071 rdev->accel_working = false;
4072 }
4073 return 0;
4074}
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