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drm/radeon: add a check to wait_reg_mem command
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7
DH		 30#include <drm/drmP.h>
31#include <drm/radeon_drm.h>
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "r100d.h"
d4550907
JG		 36#include "rs100d.h"
37#include "rv200d.h"
38#include "rv250d.h"
49e02b73 39#include "atom.h"
3ce0a23d 40
70967ab9
BH		 41#include <linux/firmware.h>
42#include <linux/platform_device.h>
e0cd3608 43#include <linux/module.h>
70967ab9 44
551ebd83
DA		 45#include "r100_reg_safe.h"
46#include "rn50_reg_safe.h"
47
70967ab9
BH		 48/* Firmware Names */
49#define FIRMWARE_R100 "radeon/R100_cp.bin"
50#define FIRMWARE_R200 "radeon/R200_cp.bin"
51#define FIRMWARE_R300 "radeon/R300_cp.bin"
52#define FIRMWARE_R420 "radeon/R420_cp.bin"
53#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55#define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57MODULE_FIRMWARE(FIRMWARE_R100);
58MODULE_FIRMWARE(FIRMWARE_R200);
59MODULE_FIRMWARE(FIRMWARE_R300);
60MODULE_FIRMWARE(FIRMWARE_R420);
61MODULE_FIRMWARE(FIRMWARE_RS690);
62MODULE_FIRMWARE(FIRMWARE_RS600);
63MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 64
551ebd83
DA		 65#include "r100_track.h"
66
48ef779f
AD		 67/* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 * and others in some cases.
70 */
71
72/**
73 * r100_wait_for_vblank - vblank wait asic callback.
74 *
75 * @rdev: radeon_device pointer
76 * @crtc: crtc to wait for vblank on
77 *
78 * Wait for vblank on the requested crtc (r1xx-r4xx).
79 */
3ae19b75
AD		 80void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
81{
3ae19b75
AD		 82 int i;
83
94f768fd
AD		 84 if (crtc >= rdev->num_crtc)
85 return;
86
87 if (crtc == 0) {
3ae19b75
AD		 88 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
89 for (i = 0; i < rdev->usec_timeout; i++) {
90 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
91 break;
92 udelay(1);
93 }
94 for (i = 0; i < rdev->usec_timeout; i++) {
95 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
96 break;
97 udelay(1);
98 }
99 }
100 } else {
101 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
102 for (i = 0; i < rdev->usec_timeout; i++) {
103 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
104 break;
105 udelay(1);
106 }
107 for (i = 0; i < rdev->usec_timeout; i++) {
108 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
109 break;
110 udelay(1);
111 }
112 }
113 }
114}
115
48ef779f
AD		 116/**
117 * r100_pre_page_flip - pre-pageflip callback.
118 *
119 * @rdev: radeon_device pointer
120 * @crtc: crtc to prepare for pageflip on
121 *
122 * Pre-pageflip callback (r1xx-r4xx).
123 * Enables the pageflip irq (vblank irq).
771fe6b9 124 */
6f34be50
AD		 125void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
126{
6f34be50
AD		 127 /* enable the pflip int */
128 radeon_irq_kms_pflip_irq_get(rdev, crtc);
129}
130
48ef779f
AD		 131/**
132 * r100_post_page_flip - pos-pageflip callback.
133 *
134 * @rdev: radeon_device pointer
135 * @crtc: crtc to cleanup pageflip on
136 *
137 * Post-pageflip callback (r1xx-r4xx).
138 * Disables the pageflip irq (vblank irq).
139 */
6f34be50
AD		 140void r100_post_page_flip(struct radeon_device *rdev, int crtc)
141{
142 /* disable the pflip int */
143 radeon_irq_kms_pflip_irq_put(rdev, crtc);
144}
145
48ef779f
AD		 146/**
147 * r100_page_flip - pageflip callback.
148 *
149 * @rdev: radeon_device pointer
150 * @crtc_id: crtc to cleanup pageflip on
151 * @crtc_base: new address of the crtc (GPU MC address)
152 *
153 * Does the actual pageflip (r1xx-r4xx).
154 * During vblank we take the crtc lock and wait for the update_pending
155 * bit to go high, when it does, we release the lock, and allow the
156 * double buffered update to take place.
157 * Returns the current update pending status.
158 */
6f34be50
AD		 159u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
160{
161 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
162 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 163 int i;
6f34be50
AD		 164
165 /* Lock the graphics update lock */
166 /* update the scanout addresses */
167 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
168
acb32506 169 /* Wait for update_pending to go high. */
f6496479
AD		 170 for (i = 0; i < rdev->usec_timeout; i++) {
171 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
172 break;
173 udelay(1);
174 }
acb32506 175 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 176
177 /* Unlock the lock, so double-buffering can take place inside vblank */
178 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
179 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
180
181 /* Return current update_pending status: */
182 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
183}
184
48ef779f
AD		 185/**
186 * r100_pm_get_dynpm_state - look up dynpm power state callback.
187 *
188 * @rdev: radeon_device pointer
189 *
190 * Look up the optimal power state based on the
191 * current state of the GPU (r1xx-r5xx).
192 * Used for dynpm only.
193 */
ce8f5370 194void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 195{
196 int i;
ce8f5370
AD		 197 rdev->pm.dynpm_can_upclock = true;
198 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 199
ce8f5370
AD		 200 switch (rdev->pm.dynpm_planned_action) {
201 case DYNPM_ACTION_MINIMUM:
a48b9b4e 202 rdev->pm.requested_power_state_index = 0;
ce8f5370 203 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 204 break;
ce8f5370 205 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 206 if (rdev->pm.current_power_state_index == 0) {
207 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 208 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 209 } else {
210 if (rdev->pm.active_crtc_count > 1) {
211 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 212 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 213 continue;
214 else if (i >= rdev->pm.current_power_state_index) {
215 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
216 break;
217 } else {
218 rdev->pm.requested_power_state_index = i;
219 break;
220 }
221 }
222 } else
223 rdev->pm.requested_power_state_index =
224 rdev->pm.current_power_state_index - 1;
225 }
d7311171
AD		 226 /* don't use the power state if crtcs are active and no display flag is set */
227 if ((rdev->pm.active_crtc_count > 0) &&
228 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
229 RADEON_PM_MODE_NO_DISPLAY)) {
230 rdev->pm.requested_power_state_index++;
231 }
a48b9b4e 232 break;
ce8f5370 233 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 234 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
235 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 236 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 237 } else {
238 if (rdev->pm.active_crtc_count > 1) {
239 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 240 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 241 continue;
242 else if (i <= rdev->pm.current_power_state_index) {
243 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
244 break;
245 } else {
246 rdev->pm.requested_power_state_index = i;
247 break;
248 }
249 }
250 } else
251 rdev->pm.requested_power_state_index =
252 rdev->pm.current_power_state_index + 1;
253 }
254 break;
ce8f5370 255 case DYNPM_ACTION_DEFAULT:
58e21dff 256 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 257 rdev->pm.dynpm_can_upclock = false;
58e21dff 258 break;
ce8f5370 259 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 260 default:
261 DRM_ERROR("Requested mode for not defined action\n");
262 return;
263 }
264 /* only one clock mode per power state */
265 rdev->pm.requested_clock_mode_index = 0;
266
d9fdaafb 267 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 268 rdev->pm.power_state[rdev->pm.requested_power_state_index].
269 clock_info[rdev->pm.requested_clock_mode_index].sclk,
270 rdev->pm.power_state[rdev->pm.requested_power_state_index].
271 clock_info[rdev->pm.requested_clock_mode_index].mclk,
272 rdev->pm.power_state[rdev->pm.requested_power_state_index].
273 pcie_lanes);
a48b9b4e
AD		 274}
275
48ef779f
AD		 276/**
277 * r100_pm_init_profile - Initialize power profiles callback.
278 *
279 * @rdev: radeon_device pointer
280 *
281 * Initialize the power states used in profile mode
282 * (r1xx-r3xx).
283 * Used for profile mode only.
284 */
ce8f5370
AD		 285void r100_pm_init_profile(struct radeon_device *rdev)
286{
287 /* default */
288 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
289 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
290 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
291 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
292 /* low sh */
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
294 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 297 /* mid sh */
298 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 302 /* high sh */
303 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
305 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
307 /* low mh */
308 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
310 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 312 /* mid mh */
313 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
315 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 317 /* high mh */
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
320 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 322}
323
48ef779f
AD		 324/**
325 * r100_pm_misc - set additional pm hw parameters callback.
326 *
327 * @rdev: radeon_device pointer
328 *
329 * Set non-clock parameters associated with a power state
330 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
331 */
49e02b73
AD		 332void r100_pm_misc(struct radeon_device *rdev)
333{
49e02b73
AD		 334 int requested_index = rdev->pm.requested_power_state_index;
335 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
336 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
337 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
338
339 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
340 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
341 tmp = RREG32(voltage->gpio.reg);
342 if (voltage->active_high)
343 tmp |= voltage->gpio.mask;
344 else
345 tmp &= ~(voltage->gpio.mask);
346 WREG32(voltage->gpio.reg, tmp);
347 if (voltage->delay)
348 udelay(voltage->delay);
349 } else {
350 tmp = RREG32(voltage->gpio.reg);
351 if (voltage->active_high)
352 tmp &= ~voltage->gpio.mask;
353 else
354 tmp |= voltage->gpio.mask;
355 WREG32(voltage->gpio.reg, tmp);
356 if (voltage->delay)
357 udelay(voltage->delay);
358 }
359 }
360
361 sclk_cntl = RREG32_PLL(SCLK_CNTL);
362 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
363 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
364 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
365 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
366 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
367 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
368 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
369 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
370 else
371 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
372 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
373 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
374 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
375 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
376 } else
377 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
378
379 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
380 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
381 if (voltage->delay) {
382 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
383 switch (voltage->delay) {
384 case 33:
385 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
386 break;
387 case 66:
388 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
389 break;
390 case 99:
391 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
392 break;
393 case 132:
394 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
395 break;
396 }
397 } else
398 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
399 } else
400 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
401
402 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
403 sclk_cntl &= ~FORCE_HDP;
404 else
405 sclk_cntl |= FORCE_HDP;
406
407 WREG32_PLL(SCLK_CNTL, sclk_cntl);
408 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
409 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
410
411 /* set pcie lanes */
412 if ((rdev->flags & RADEON_IS_PCIE) &&
413 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 414 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 415 (ps->pcie_lanes !=
416 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
417 radeon_set_pcie_lanes(rdev,
418 ps->pcie_lanes);
d9fdaafb 419 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 420 }
49e02b73
AD		 421}
422
48ef779f
AD		 423/**
424 * r100_pm_prepare - pre-power state change callback.
425 *
426 * @rdev: radeon_device pointer
427 *
428 * Prepare for a power state change (r1xx-r4xx).
429 */
49e02b73
AD		 430void r100_pm_prepare(struct radeon_device *rdev)
431{
432 struct drm_device *ddev = rdev->ddev;
433 struct drm_crtc *crtc;
434 struct radeon_crtc *radeon_crtc;
435 u32 tmp;
436
437 /* disable any active CRTCs */
438 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
439 radeon_crtc = to_radeon_crtc(crtc);
440 if (radeon_crtc->enabled) {
441 if (radeon_crtc->crtc_id) {
442 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
443 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
444 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
445 } else {
446 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
447 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
448 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
449 }
450 }
451 }
452}
453
48ef779f
AD		 454/**
455 * r100_pm_finish - post-power state change callback.
456 *
457 * @rdev: radeon_device pointer
458 *
459 * Clean up after a power state change (r1xx-r4xx).
460 */
49e02b73
AD		 461void r100_pm_finish(struct radeon_device *rdev)
462{
463 struct drm_device *ddev = rdev->ddev;
464 struct drm_crtc *crtc;
465 struct radeon_crtc *radeon_crtc;
466 u32 tmp;
467
468 /* enable any active CRTCs */
469 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
470 radeon_crtc = to_radeon_crtc(crtc);
471 if (radeon_crtc->enabled) {
472 if (radeon_crtc->crtc_id) {
473 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
474 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
475 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
476 } else {
477 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
478 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
479 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
480 }
481 }
482 }
483}
484
48ef779f
AD		 485/**
486 * r100_gui_idle - gui idle callback.
487 *
488 * @rdev: radeon_device pointer
489 *
490 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
491 * Returns true if idle, false if not.
492 */
def9ba9c
AD		 493bool r100_gui_idle(struct radeon_device *rdev)
494{
495 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
496 return false;
497 else
498 return true;
499}
500
05a05c50 501/* hpd for digital panel detect/disconnect */
48ef779f
AD		 502/**
503 * r100_hpd_sense - hpd sense callback.
504 *
505 * @rdev: radeon_device pointer
506 * @hpd: hpd (hotplug detect) pin
507 *
508 * Checks if a digital monitor is connected (r1xx-r4xx).
509 * Returns true if connected, false if not connected.
510 */
05a05c50
AD		 511bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
512{
513 bool connected = false;
514
515 switch (hpd) {
516 case RADEON_HPD_1:
517 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
518 connected = true;
519 break;
520 case RADEON_HPD_2:
521 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
522 connected = true;
523 break;
524 default:
525 break;
526 }
527 return connected;
528}
529
48ef779f
AD		 530/**
531 * r100_hpd_set_polarity - hpd set polarity callback.
532 *
533 * @rdev: radeon_device pointer
534 * @hpd: hpd (hotplug detect) pin
535 *
536 * Set the polarity of the hpd pin (r1xx-r4xx).
537 */
05a05c50
AD		 538void r100_hpd_set_polarity(struct radeon_device *rdev,
539 enum radeon_hpd_id hpd)
540{
541 u32 tmp;
542 bool connected = r100_hpd_sense(rdev, hpd);
543
544 switch (hpd) {
545 case RADEON_HPD_1:
546 tmp = RREG32(RADEON_FP_GEN_CNTL);
547 if (connected)
548 tmp &= ~RADEON_FP_DETECT_INT_POL;
549 else
550 tmp |= RADEON_FP_DETECT_INT_POL;
551 WREG32(RADEON_FP_GEN_CNTL, tmp);
552 break;
553 case RADEON_HPD_2:
554 tmp = RREG32(RADEON_FP2_GEN_CNTL);
555 if (connected)
556 tmp &= ~RADEON_FP2_DETECT_INT_POL;
557 else
558 tmp |= RADEON_FP2_DETECT_INT_POL;
559 WREG32(RADEON_FP2_GEN_CNTL, tmp);
560 break;
561 default:
562 break;
563 }
564}
565
48ef779f
AD		 566/**
567 * r100_hpd_init - hpd setup callback.
568 *
569 * @rdev: radeon_device pointer
570 *
571 * Setup the hpd pins used by the card (r1xx-r4xx).
572 * Set the polarity, and enable the hpd interrupts.
573 */
05a05c50
AD		 574void r100_hpd_init(struct radeon_device *rdev)
575{
576 struct drm_device *dev = rdev->ddev;
577 struct drm_connector *connector;
fb98257a 578 unsigned enable = 0;
05a05c50
AD		 579
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
581 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 582 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 583 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 584 }
fb98257a 585 radeon_irq_kms_enable_hpd(rdev, enable);
05a05c50
AD		 586}
587
48ef779f
AD		 588/**
589 * r100_hpd_fini - hpd tear down callback.
590 *
591 * @rdev: radeon_device pointer
592 *
593 * Tear down the hpd pins used by the card (r1xx-r4xx).
594 * Disable the hpd interrupts.
595 */
05a05c50
AD		 596void r100_hpd_fini(struct radeon_device *rdev)
597{
598 struct drm_device *dev = rdev->ddev;
599 struct drm_connector *connector;
fb98257a 600 unsigned disable = 0;
05a05c50
AD		 601
602 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
603 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 604 disable |= 1 << radeon_connector->hpd.hpd;
05a05c50 605 }
fb98257a 606 radeon_irq_kms_disable_hpd(rdev, disable);
05a05c50
AD		 607}
608
771fe6b9
JG		 609/*
610 * PCI GART
611 */
612void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
613{
614 /* TODO: can we do somethings here ? */
615 /* It seems hw only cache one entry so we should discard this
616 * entry otherwise if first GPU GART read hit this entry it
617 * could end up in wrong address. */
618}
619
4aac0473 620int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 621{
771fe6b9
JG		 622 int r;
623
c9a1be96 624 if (rdev->gart.ptr) {
fce7d61b 625 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 626 return 0;
627 }
771fe6b9
JG		 628 /* Initialize common gart structure */
629 r = radeon_gart_init(rdev);
4aac0473 630 if (r)
771fe6b9 631 return r;
4aac0473 632 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
c5b3b850
AD		 633 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
634 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
4aac0473
JG		 635 return radeon_gart_table_ram_alloc(rdev);
636}
637
638int r100_pci_gart_enable(struct radeon_device *rdev)
639{
640 uint32_t tmp;
641
82568565 642 radeon_gart_restore(rdev);
771fe6b9
JG		 643 /* discard memory request outside of configured range */
644 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
645 WREG32(RADEON_AIC_CNTL, tmp);
646 /* set address range for PCI address translate */
d594e46a
JG		 647 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
648 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 649 /* set PCI GART page-table base address */
650 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
651 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
652 WREG32(RADEON_AIC_CNTL, tmp);
653 r100_pci_gart_tlb_flush(rdev);
43caf451 654 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
fcf4de5a
TV		 655 (unsigned)(rdev->mc.gtt_size >> 20),
656 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 657 rdev->gart.ready = true;
658 return 0;
659}
660
661void r100_pci_gart_disable(struct radeon_device *rdev)
662{
663 uint32_t tmp;
664
665 /* discard memory request outside of configured range */
666 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
667 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
668 WREG32(RADEON_AIC_LO_ADDR, 0);
669 WREG32(RADEON_AIC_HI_ADDR, 0);
670}
671
672int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
673{
c9a1be96
JG		 674 u32 *gtt = rdev->gart.ptr;
675
771fe6b9
JG		 676 if (i < 0 || i > rdev->gart.num_gpu_pages) {
677 return -EINVAL;
678 }
c9a1be96 679 gtt[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 680 return 0;
681}
682
4aac0473 683void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 684{
f9274562 685 radeon_gart_fini(rdev);
4aac0473
JG		 686 r100_pci_gart_disable(rdev);
687 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 688}
689
7ed220d7
MD		 690int r100_irq_set(struct radeon_device *rdev)
691{
692 uint32_t tmp = 0;
693
003e69f9 694 if (!rdev->irq.installed) {
fce7d61b 695 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 696 WREG32(R_000040_GEN_INT_CNTL, 0);
697 return -EINVAL;
698 }
736fc37f 699 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7ed220d7
MD		 700 tmp |= RADEON_SW_INT_ENABLE;
701 }
6f34be50 702 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 703 atomic_read(&rdev->irq.pflip[0])) {
7ed220d7
MD		 704 tmp |= RADEON_CRTC_VBLANK_MASK;
705 }
6f34be50 706 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 707 atomic_read(&rdev->irq.pflip[1])) {
7ed220d7
MD		 708 tmp |= RADEON_CRTC2_VBLANK_MASK;
709 }
05a05c50
AD		 710 if (rdev->irq.hpd[0]) {
711 tmp |= RADEON_FP_DETECT_MASK;
712 }
713 if (rdev->irq.hpd[1]) {
714 tmp |= RADEON_FP2_DETECT_MASK;
715 }
7ed220d7
MD		 716 WREG32(RADEON_GEN_INT_CNTL, tmp);
717 return 0;
718}
719
9f022ddf
JG		 720void r100_irq_disable(struct radeon_device *rdev)
721{
722 u32 tmp;
723
724 WREG32(R_000040_GEN_INT_CNTL, 0);
725 /* Wait and acknowledge irq */
726 mdelay(1);
727 tmp = RREG32(R_000044_GEN_INT_STATUS);
728 WREG32(R_000044_GEN_INT_STATUS, tmp);
729}
730
cbdd4501 731static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 732{
733 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 734 uint32_t irq_mask = RADEON_SW_INT_TEST |
735 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
736 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 737
738 if (irqs) {
739 WREG32(RADEON_GEN_INT_STATUS, irqs);
740 }
741 return irqs & irq_mask;
742}
743
744int r100_irq_process(struct radeon_device *rdev)
745{
3e5cb98d 746 uint32_t status, msi_rearm;
d4877cf2 747 bool queue_hotplug = false;
7ed220d7
MD		 748
749 status = r100_irq_ack(rdev);
750 if (!status) {
751 return IRQ_NONE;
752 }
a513c184
JG		 753 if (rdev->shutdown) {
754 return IRQ_NONE;
755 }
7ed220d7
MD		 756 while (status) {
757 /* SW interrupt */
758 if (status & RADEON_SW_INT_TEST) {
7465280c 759 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7
MD		 760 }
761 /* Vertical blank interrupts */
762 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 763 if (rdev->irq.crtc_vblank_int[0]) {
764 drm_handle_vblank(rdev->ddev, 0);
765 rdev->pm.vblank_sync = true;
766 wake_up(&rdev->irq.vblank_queue);
767 }
736fc37f 768 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 769 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 770 }
771 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 772 if (rdev->irq.crtc_vblank_int[1]) {
773 drm_handle_vblank(rdev->ddev, 1);
774 rdev->pm.vblank_sync = true;
775 wake_up(&rdev->irq.vblank_queue);
776 }
736fc37f 777 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 778 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 779 }
05a05c50 780 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 781 queue_hotplug = true;
782 DRM_DEBUG("HPD1\n");
05a05c50
AD		 783 }
784 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 785 queue_hotplug = true;
786 DRM_DEBUG("HPD2\n");
05a05c50 787 }
7ed220d7
MD		 788 status = r100_irq_ack(rdev);
789 }
d4877cf2 790 if (queue_hotplug)
32c87fca 791 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 792 if (rdev->msi_enabled) {
793 switch (rdev->family) {
794 case CHIP_RS400:
795 case CHIP_RS480:
796 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
797 WREG32(RADEON_AIC_CNTL, msi_rearm);
798 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
799 break;
800 default:
b7f5b7de 801 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 802 break;
803 }
804 }
7ed220d7
MD		 805 return IRQ_HANDLED;
806}
807
808u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
809{
810 if (crtc == 0)
811 return RREG32(RADEON_CRTC_CRNT_FRAME);
812 else
813 return RREG32(RADEON_CRTC2_CRNT_FRAME);
814}
815
9e5b2af7
PN		 816/* Who ever call radeon_fence_emit should call ring_lock and ask
817 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 818void r100_fence_ring_emit(struct radeon_device *rdev,
819 struct radeon_fence *fence)
820{
e32eb50d 821 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 822
9e5b2af7
PN		 823 /* We have to make sure that caches are flushed before
824 * CPU might read something from VRAM. */
e32eb50d
CK		 825 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
826 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
827 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
828 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 829 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 830 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
831 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
832 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
833 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
cafe6609 834 RADEON_HDP_READ_BUFFER_INVALIDATE);
e32eb50d
CK		 835 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
836 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
771fe6b9 837 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 838 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
839 radeon_ring_write(ring, fence->seq);
840 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
841 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 842}
843
15d3332f 844void r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 845 struct radeon_ring *ring,
15d3332f 846 struct radeon_semaphore *semaphore,
7b1f2485 847 bool emit_wait)
15d3332f
CK		 848{
849 /* Unused on older asics, since we don't have semaphores or multiple rings */
850 BUG();
851}
852
771fe6b9
JG		 853int r100_copy_blit(struct radeon_device *rdev,
854 uint64_t src_offset,
855 uint64_t dst_offset,
003cefe0 856 unsigned num_gpu_pages,
876dc9f3 857 struct radeon_fence **fence)
771fe6b9 858{
e32eb50d 859 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9 860 uint32_t cur_pages;
003cefe0 861 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 862 uint32_t pitch;
863 uint32_t stride_pixels;
864 unsigned ndw;
865 int num_loops;
866 int r = 0;
867
868 /* radeon limited to 16k stride */
869 stride_bytes &= 0x3fff;
870 /* radeon pitch is /64 */
871 pitch = stride_bytes / 64;
872 stride_pixels = stride_bytes / 4;
003cefe0 873 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 874
875 /* Ask for enough room for blit + flush + fence */
876 ndw = 64 + (10 * num_loops);
e32eb50d 877 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 878 if (r) {
879 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
880 return -EINVAL;
881 }
003cefe0
AD		 882 while (num_gpu_pages > 0) {
883 cur_pages = num_gpu_pages;
771fe6b9
JG		 884 if (cur_pages > 8191) {
885 cur_pages = 8191;
886 }
003cefe0 887 num_gpu_pages -= cur_pages;
771fe6b9
JG		 888
889 /* pages are in Y direction - height
890 page width in X direction - width */
e32eb50d
CK		 891 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
892 radeon_ring_write(ring,
771fe6b9
JG		 893 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
894 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
895 RADEON_GMC_SRC_CLIPPING |
896 RADEON_GMC_DST_CLIPPING |
897 RADEON_GMC_BRUSH_NONE |
898 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
899 RADEON_GMC_SRC_DATATYPE_COLOR |
900 RADEON_ROP3_S |
901 RADEON_DP_SRC_SOURCE_MEMORY |
902 RADEON_GMC_CLR_CMP_CNTL_DIS |
903 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 904 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
905 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
906 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
907 radeon_ring_write(ring, 0);
908 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
909 radeon_ring_write(ring, num_gpu_pages);
910 radeon_ring_write(ring, num_gpu_pages);
911 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
912 }
913 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
914 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
915 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
916 radeon_ring_write(ring,
771fe6b9
JG		 917 RADEON_WAIT_2D_IDLECLEAN |
918 RADEON_WAIT_HOST_IDLECLEAN |
919 RADEON_WAIT_DMA_GUI_IDLE);
920 if (fence) {
876dc9f3 921 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
771fe6b9 922 }
e32eb50d 923 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 924 return r;
925}
926
45600232
JG		 927static int r100_cp_wait_for_idle(struct radeon_device *rdev)
928{
929 unsigned i;
930 u32 tmp;
931
932 for (i = 0; i < rdev->usec_timeout; i++) {
933 tmp = RREG32(R_000E40_RBBM_STATUS);
934 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
935 return 0;
936 }
937 udelay(1);
938 }
939 return -1;
940}
941
f712812e 942void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9
JG		 943{
944 int r;
945
e32eb50d 946 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 947 if (r) {
948 return;
949 }
e32eb50d
CK		 950 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
951 radeon_ring_write(ring,
771fe6b9
JG		 952 RADEON_ISYNC_ANY2D_IDLE3D |
953 RADEON_ISYNC_ANY3D_IDLE2D |
954 RADEON_ISYNC_WAIT_IDLEGUI |
955 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
e32eb50d 956 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 957}
958
70967ab9
BH		 959
960/* Load the microcode for the CP */
961static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 962{
70967ab9
BH		 963 struct platform_device *pdev;
964 const char *fw_name = NULL;
965 int err;
771fe6b9 966
d9fdaafb 967 DRM_DEBUG_KMS("\n");
771fe6b9 968
70967ab9
BH		 969 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
970 err = IS_ERR(pdev);
971 if (err) {
972 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
973 return -EINVAL;
974 }
771fe6b9
JG		 975 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
976 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
977 (rdev->family == CHIP_RS200)) {
978 DRM_INFO("Loading R100 Microcode\n");
70967ab9 979 fw_name = FIRMWARE_R100;
771fe6b9
JG		 980 } else if ((rdev->family == CHIP_R200) ||
981 (rdev->family == CHIP_RV250) ||
982 (rdev->family == CHIP_RV280) ||
983 (rdev->family == CHIP_RS300)) {
984 DRM_INFO("Loading R200 Microcode\n");
70967ab9 985 fw_name = FIRMWARE_R200;
771fe6b9
JG		 986 } else if ((rdev->family == CHIP_R300) ||
987 (rdev->family == CHIP_R350) ||
988 (rdev->family == CHIP_RV350) ||
989 (rdev->family == CHIP_RV380) ||
990 (rdev->family == CHIP_RS400) ||
991 (rdev->family == CHIP_RS480)) {
992 DRM_INFO("Loading R300 Microcode\n");
70967ab9 993 fw_name = FIRMWARE_R300;
771fe6b9
JG		 994 } else if ((rdev->family == CHIP_R420) ||
995 (rdev->family == CHIP_R423) ||
996 (rdev->family == CHIP_RV410)) {
997 DRM_INFO("Loading R400 Microcode\n");
70967ab9 998 fw_name = FIRMWARE_R420;
771fe6b9
JG		 999 } else if ((rdev->family == CHIP_RS690) ||
1000 (rdev->family == CHIP_RS740)) {
1001 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1002 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1003 } else if (rdev->family == CHIP_RS600) {
1004 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1005 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1006 } else if ((rdev->family == CHIP_RV515) ||
1007 (rdev->family == CHIP_R520) ||
1008 (rdev->family == CHIP_RV530) ||
1009 (rdev->family == CHIP_R580) ||
1010 (rdev->family == CHIP_RV560) ||
1011 (rdev->family == CHIP_RV570)) {
1012 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1013 fw_name = FIRMWARE_R520;
1014 }
1015
3ce0a23d 1016 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 1017 platform_device_unregister(pdev);
1018 if (err) {
1019 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1020 fw_name);
3ce0a23d 1021 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1022 printk(KERN_ERR
1023 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1024 rdev->me_fw->size, fw_name);
70967ab9 1025 err = -EINVAL;
3ce0a23d
JG		 1026 release_firmware(rdev->me_fw);
1027 rdev->me_fw = NULL;
70967ab9
BH		 1028 }
1029 return err;
1030}
d4550907 1031
70967ab9
BH		 1032static void r100_cp_load_microcode(struct radeon_device *rdev)
1033{
1034 const __be32 *fw_data;
1035 int i, size;
1036
1037 if (r100_gui_wait_for_idle(rdev)) {
1038 printk(KERN_WARNING "Failed to wait GUI idle while "
1039 "programming pipes. Bad things might happen.\n");
1040 }
1041
3ce0a23d
JG		 1042 if (rdev->me_fw) {
1043 size = rdev->me_fw->size / 4;
1044 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1045 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1046 for (i = 0; i < size; i += 2) {
1047 WREG32(RADEON_CP_ME_RAM_DATAH,
1048 be32_to_cpup(&fw_data[i]));
1049 WREG32(RADEON_CP_ME_RAM_DATAL,
1050 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1051 }
1052 }
1053}
1054
1055int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1056{
e32eb50d 1057 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1058 unsigned rb_bufsz;
1059 unsigned rb_blksz;
1060 unsigned max_fetch;
1061 unsigned pre_write_timer;
1062 unsigned pre_write_limit;
1063 unsigned indirect2_start;
1064 unsigned indirect1_start;
1065 uint32_t tmp;
1066 int r;
1067
1068 if (r100_debugfs_cp_init(rdev)) {
1069 DRM_ERROR("Failed to register debugfs file for CP !\n");
1070 }
3ce0a23d 1071 if (!rdev->me_fw) {
70967ab9
BH		 1072 r = r100_cp_init_microcode(rdev);
1073 if (r) {
1074 DRM_ERROR("Failed to load firmware!\n");
1075 return r;
1076 }
1077 }
1078
771fe6b9
JG		 1079 /* Align ring size */
1080 rb_bufsz = drm_order(ring_size / 8);
1081 ring_size = (1 << (rb_bufsz + 1)) * 4;
1082 r100_cp_load_microcode(rdev);
e32eb50d 1083 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1084 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1085 0, 0x7fffff, RADEON_CP_PACKET2);
771fe6b9
JG		 1086 if (r) {
1087 return r;
1088 }
1089 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1090 * the rptr copy in system ram */
1091 rb_blksz = 9;
1092 /* cp will read 128bytes at a time (4 dwords) */
1093 max_fetch = 1;
e32eb50d 1094 ring->align_mask = 16 - 1;
771fe6b9
JG		 1095 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1096 pre_write_timer = 64;
1097 /* Force CP_RB_WPTR write if written more than one time before the
1098 * delay expire
1099 */
1100 pre_write_limit = 0;
1101 /* Setup the cp cache like this (cache size is 96 dwords) :
1102 * RING 0 to 15
1103 * INDIRECT1 16 to 79
1104 * INDIRECT2 80 to 95
1105 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1106 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1107 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1108 * Idea being that most of the gpu cmd will be through indirect1 buffer
1109 * so it gets the bigger cache.
1110 */
1111 indirect2_start = 80;
1112 indirect1_start = 16;
1113 /* cp setup */
1114 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1115 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1116 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1117 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1118#ifdef __BIG_ENDIAN
1119 tmp |= RADEON_BUF_SWAP_32BIT;
1120#endif
724c80e1 1121 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1122
771fe6b9 1123 /* Set ring address */
e32eb50d
CK		 1124 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1125 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1126 /* Force read & write ptr to 0 */
724c80e1 1127 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1128 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1129 ring->wptr = 0;
1130 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1131
1132 /* set the wb address whether it's enabled or not */
1133 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1134 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1135 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1136
1137 if (rdev->wb.enabled)
1138 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1139 else {
1140 tmp |= RADEON_RB_NO_UPDATE;
1141 WREG32(R_000770_SCRATCH_UMSK, 0);
1142 }
1143
771fe6b9
JG		 1144 WREG32(RADEON_CP_RB_CNTL, tmp);
1145 udelay(10);
e32eb50d 1146 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
771fe6b9
JG		 1147 /* Set cp mode to bus mastering & enable cp*/
1148 WREG32(RADEON_CP_CSQ_MODE,
1149 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1150 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1151 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1152 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9 1153 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2099810f
DA		 1154
1155 /* at this point everything should be setup correctly to enable master */
1156 pci_set_master(rdev->pdev);
1157
f712812e
AD		 1158 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1159 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
771fe6b9
JG		 1160 if (r) {
1161 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1162 return r;
1163 }
e32eb50d 1164 ring->ready = true;
53595338 1165 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
c7eff978 1166
16c58081
SK		 1167 if (!ring->rptr_save_reg /* not resuming from suspend */
1168 && radeon_ring_supports_scratch_reg(rdev, ring)) {
c7eff978
AD		 1169 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1170 if (r) {
1171 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1172 ring->rptr_save_reg = 0;
1173 }
1174 }
771fe6b9
JG		 1175 return 0;
1176}
1177
1178void r100_cp_fini(struct radeon_device *rdev)
1179{
45600232
JG		 1180 if (r100_cp_wait_for_idle(rdev)) {
1181 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1182 }
771fe6b9 1183 /* Disable ring */
a18d7ea1 1184 r100_cp_disable(rdev);
c7eff978 1185 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
e32eb50d 1186 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1187 DRM_INFO("radeon: cp finalized\n");
1188}
1189
1190void r100_cp_disable(struct radeon_device *rdev)
1191{
1192 /* Disable ring */
53595338 1193 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1194 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1195 WREG32(RADEON_CP_CSQ_MODE, 0);
1196 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1197 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1198 if (r100_gui_wait_for_idle(rdev)) {
1199 printk(KERN_WARNING "Failed to wait GUI idle while "
1200 "programming pipes. Bad things might happen.\n");
1201 }
1202}
1203
771fe6b9
JG		 1204/*
1205 * CS functions
1206 */
0242f74d
AD		 1207int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1208 struct radeon_cs_packet *pkt,
1209 unsigned idx,
1210 unsigned reg)
1211{
1212 int r;
1213 u32 tile_flags = 0;
1214 u32 tmp;
1215 struct radeon_cs_reloc *reloc;
1216 u32 value;
1217
1218 r = r100_cs_packet_next_reloc(p, &reloc);
1219 if (r) {
1220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1221 idx, reg);
1222 r100_cs_dump_packet(p, pkt);
1223 return r;
1224 }
1225
1226 value = radeon_get_ib_value(p, idx);
1227 tmp = value & 0x003fffff;
1228 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1229
1230 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1231 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1232 tile_flags |= RADEON_DST_TILE_MACRO;
1233 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1234 if (reg == RADEON_SRC_PITCH_OFFSET) {
1235 DRM_ERROR("Cannot src blit from microtiled surface\n");
1236 r100_cs_dump_packet(p, pkt);
1237 return -EINVAL;
1238 }
1239 tile_flags |= RADEON_DST_TILE_MICRO;
1240 }
1241
1242 tmp |= tile_flags;
1243 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1244 } else
1245 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1246 return 0;
1247}
1248
1249int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1250 struct radeon_cs_packet *pkt,
1251 int idx)
1252{
1253 unsigned c, i;
1254 struct radeon_cs_reloc *reloc;
1255 struct r100_cs_track *track;
1256 int r = 0;
1257 volatile uint32_t *ib;
1258 u32 idx_value;
1259
1260 ib = p->ib.ptr;
1261 track = (struct r100_cs_track *)p->track;
1262 c = radeon_get_ib_value(p, idx++) & 0x1F;
1263 if (c > 16) {
1264 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1265 pkt->opcode);
1266 r100_cs_dump_packet(p, pkt);
1267 return -EINVAL;
1268 }
1269 track->num_arrays = c;
1270 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1271 r = r100_cs_packet_next_reloc(p, &reloc);
1272 if (r) {
1273 DRM_ERROR("No reloc for packet3 %d\n",
1274 pkt->opcode);
1275 r100_cs_dump_packet(p, pkt);
1276 return r;
1277 }
1278 idx_value = radeon_get_ib_value(p, idx);
1279 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1280
1281 track->arrays[i + 0].esize = idx_value >> 8;
1282 track->arrays[i + 0].robj = reloc->robj;
1283 track->arrays[i + 0].esize &= 0x7F;
1284 r = r100_cs_packet_next_reloc(p, &reloc);
1285 if (r) {
1286 DRM_ERROR("No reloc for packet3 %d\n",
1287 pkt->opcode);
1288 r100_cs_dump_packet(p, pkt);
1289 return r;
1290 }
1291 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1292 track->arrays[i + 1].robj = reloc->robj;
1293 track->arrays[i + 1].esize = idx_value >> 24;
1294 track->arrays[i + 1].esize &= 0x7F;
1295 }
1296 if (c & 1) {
1297 r = r100_cs_packet_next_reloc(p, &reloc);
1298 if (r) {
1299 DRM_ERROR("No reloc for packet3 %d\n",
1300 pkt->opcode);
1301 r100_cs_dump_packet(p, pkt);
1302 return r;
1303 }
1304 idx_value = radeon_get_ib_value(p, idx);
1305 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1306 track->arrays[i + 0].robj = reloc->robj;
1307 track->arrays[i + 0].esize = idx_value >> 8;
1308 track->arrays[i + 0].esize &= 0x7F;
1309 }
1310 return r;
1311}
1312
771fe6b9
JG		 1313int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1314 struct radeon_cs_packet *pkt,
068a117c 1315 const unsigned *auth, unsigned n,
771fe6b9
JG		 1316 radeon_packet0_check_t check)
1317{
1318 unsigned reg;
1319 unsigned i, j, m;
1320 unsigned idx;
1321 int r;
1322
1323 idx = pkt->idx + 1;
1324 reg = pkt->reg;
068a117c
JG		 1325 /* Check that register fall into register range
1326 * determined by the number of entry (n) in the
1327 * safe register bitmap.
1328 */
771fe6b9
JG		 1329 if (pkt->one_reg_wr) {
1330 if ((reg >> 7) > n) {
1331 return -EINVAL;
1332 }
1333 } else {
1334 if (((reg + (pkt->count << 2)) >> 7) > n) {
1335 return -EINVAL;
1336 }
1337 }
1338 for (i = 0; i <= pkt->count; i++, idx++) {
1339 j = (reg >> 7);
1340 m = 1 << ((reg >> 2) & 31);
1341 if (auth[j] & m) {
1342 r = check(p, pkt, idx, reg);
1343 if (r) {
1344 return r;
1345 }
1346 }
1347 if (pkt->one_reg_wr) {
1348 if (!(auth[j] & m)) {
1349 break;
1350 }
1351 } else {
1352 reg += 4;
1353 }
1354 }
1355 return 0;
1356}
1357
771fe6b9
JG		 1358void r100_cs_dump_packet(struct radeon_cs_parser *p,
1359 struct radeon_cs_packet *pkt)
1360{
771fe6b9
JG		 1361 volatile uint32_t *ib;
1362 unsigned i;
1363 unsigned idx;
1364
f2e39221 1365 ib = p->ib.ptr;
771fe6b9
JG		 1366 idx = pkt->idx;
1367 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1368 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1369 }
1370}
1371
531369e6
DA		 1372/**
1373 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1374 * @parser: parser structure holding parsing context.
1375 *
1376 * Userspace sends a special sequence for VLINE waits.
1377 * PACKET0 - VLINE_START_END + value
1378 * PACKET0 - WAIT_UNTIL +_value
1379 * RELOC (P3) - crtc_id in reloc.
1380 *
1381 * This function parses this and relocates the VLINE START END
1382 * and WAIT UNTIL packets to the correct crtc.
1383 * It also detects a switched off crtc and nulls out the
1384 * wait in that case.
1385 */
1386int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1387{
531369e6
DA		 1388 struct drm_mode_object *obj;
1389 struct drm_crtc *crtc;
1390 struct radeon_crtc *radeon_crtc;
1391 struct radeon_cs_packet p3reloc, waitreloc;
1392 int crtc_id;
1393 int r;
1394 uint32_t header, h_idx, reg;
513bcb46 1395 volatile uint32_t *ib;
531369e6 1396
f2e39221 1397 ib = p->ib.ptr;
531369e6
DA		 1398
1399 /* parse the wait until */
c38f34b5 1400 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
531369e6
DA		 1401 if (r)
1402 return r;
1403
1404 /* check its a wait until and only 1 count */
1405 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1406 waitreloc.count != 0) {
1407 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1408 return -EINVAL;
531369e6
DA		 1409 }
1410
513bcb46 1411 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1412 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1413 return -EINVAL;
531369e6
DA		 1414 }
1415
1416 /* jump over the NOP */
c38f34b5 1417 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1418 if (r)
1419 return r;
1420
1421 h_idx = p->idx - 2;
90ebd065
AD		 1422 p->idx += waitreloc.count + 2;
1423 p->idx += p3reloc.count + 2;
531369e6 1424
513bcb46
DA		 1425 header = radeon_get_ib_value(p, h_idx);
1426 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1427 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1428 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1429 if (!obj) {
1430 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1431 return -EINVAL;
531369e6
DA		 1432 }
1433 crtc = obj_to_crtc(obj);
1434 radeon_crtc = to_radeon_crtc(crtc);
1435 crtc_id = radeon_crtc->crtc_id;
1436
1437 if (!crtc->enabled) {
1438 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1439 ib[h_idx + 2] = PACKET2(0);
1440 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1441 } else if (crtc_id == 1) {
1442 switch (reg) {
1443 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1444 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1445 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1446 break;
1447 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1448 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1449 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1450 break;
1451 default:
1452 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1453 return -EINVAL;
531369e6 1454 }
513bcb46
DA		 1455 ib[h_idx] = header;
1456 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1457 }
a3a88a66
PB		 1458
1459 return 0;
531369e6
DA		 1460}
1461
771fe6b9
JG		 1462/**
1463 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1464 * @parser: parser structure holding parsing context.
1465 * @data: pointer to relocation data
1466 * @offset_start: starting offset
1467 * @offset_mask: offset mask (to align start offset on)
1468 * @reloc: reloc informations
1469 *
1470 * Check next packet is relocation packet3, do bo validation and compute
1471 * GPU offset using the provided start.
1472 **/
1473int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1474 struct radeon_cs_reloc **cs_reloc)
1475{
771fe6b9
JG		 1476 struct radeon_cs_chunk *relocs_chunk;
1477 struct radeon_cs_packet p3reloc;
1478 unsigned idx;
1479 int r;
1480
1481 if (p->chunk_relocs_idx == -1) {
1482 DRM_ERROR("No relocation chunk !\n");
1483 return -EINVAL;
1484 }
1485 *cs_reloc = NULL;
771fe6b9 1486 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
c38f34b5 1487 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
771fe6b9
JG		 1488 if (r) {
1489 return r;
1490 }
1491 p->idx += p3reloc.count + 2;
1492 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1493 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1494 p3reloc.idx);
1495 r100_cs_dump_packet(p, &p3reloc);
1496 return -EINVAL;
1497 }
513bcb46 1498 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1499 if (idx >= relocs_chunk->length_dw) {
1500 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1501 idx, relocs_chunk->length_dw);
1502 r100_cs_dump_packet(p, &p3reloc);
1503 return -EINVAL;
1504 }
1505 /* FIXME: we assume reloc size is 4 dwords */
1506 *cs_reloc = p->relocs_ptr[(idx / 4)];
1507 return 0;
1508}
1509
551ebd83
DA		 1510static int r100_get_vtx_size(uint32_t vtx_fmt)
1511{
1512 int vtx_size;
1513 vtx_size = 2;
1514 /* ordered according to bits in spec */
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1516 vtx_size++;
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1518 vtx_size += 3;
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1520 vtx_size++;
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1522 vtx_size++;
1523 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1524 vtx_size += 3;
1525 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1526 vtx_size++;
1527 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1528 vtx_size++;
1529 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1530 vtx_size += 2;
1531 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1532 vtx_size += 2;
1533 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1534 vtx_size++;
1535 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1536 vtx_size += 2;
1537 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1538 vtx_size++;
1539 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1540 vtx_size += 2;
1541 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1542 vtx_size++;
1543 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1544 vtx_size++;
1545 /* blend weight */
1546 if (vtx_fmt & (0x7 << 15))
1547 vtx_size += (vtx_fmt >> 15) & 0x7;
1548 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1549 vtx_size += 3;
1550 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1551 vtx_size += 2;
1552 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1553 vtx_size++;
1554 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1555 vtx_size++;
1556 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1557 vtx_size++;
1558 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1559 vtx_size++;
1560 return vtx_size;
1561}
1562
771fe6b9 1563static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1564 struct radeon_cs_packet *pkt,
1565 unsigned idx, unsigned reg)
771fe6b9 1566{
771fe6b9 1567 struct radeon_cs_reloc *reloc;
551ebd83 1568 struct r100_cs_track *track;
771fe6b9
JG		 1569 volatile uint32_t *ib;
1570 uint32_t tmp;
771fe6b9 1571 int r;
551ebd83 1572 int i, face;
e024e110 1573 u32 tile_flags = 0;
513bcb46 1574 u32 idx_value;
771fe6b9 1575
f2e39221 1576 ib = p->ib.ptr;
551ebd83
DA		 1577 track = (struct r100_cs_track *)p->track;
1578
513bcb46
DA		 1579 idx_value = radeon_get_ib_value(p, idx);
1580
551ebd83
DA		 1581 switch (reg) {
1582 case RADEON_CRTC_GUI_TRIG_VLINE:
1583 r = r100_cs_packet_parse_vline(p);
1584 if (r) {
1585 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1586 idx, reg);
1587 r100_cs_dump_packet(p, pkt);
1588 return r;
1589 }
1590 break;
771fe6b9
JG		 1591 /* FIXME: only allow PACKET3 blit? easier to check for out of
1592 * range access */
551ebd83
DA		 1593 case RADEON_DST_PITCH_OFFSET:
1594 case RADEON_SRC_PITCH_OFFSET:
1595 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1596 if (r)
1597 return r;
1598 break;
1599 case RADEON_RB3D_DEPTHOFFSET:
1600 r = r100_cs_packet_next_reloc(p, &reloc);
1601 if (r) {
1602 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1603 idx, reg);
1604 r100_cs_dump_packet(p, pkt);
1605 return r;
1606 }
1607 track->zb.robj = reloc->robj;
513bcb46 1608 track->zb.offset = idx_value;
40b4a759 1609 track->zb_dirty = true;
513bcb46 1610 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1611 break;
1612 case RADEON_RB3D_COLOROFFSET:
1613 r = r100_cs_packet_next_reloc(p, &reloc);
1614 if (r) {
1615 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1616 idx, reg);
1617 r100_cs_dump_packet(p, pkt);
1618 return r;
1619 }
1620 track->cb[0].robj = reloc->robj;
513bcb46 1621 track->cb[0].offset = idx_value;
40b4a759 1622 track->cb_dirty = true;
513bcb46 1623 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1624 break;
1625 case RADEON_PP_TXOFFSET_0:
1626 case RADEON_PP_TXOFFSET_1:
1627 case RADEON_PP_TXOFFSET_2:
1628 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1629 r = r100_cs_packet_next_reloc(p, &reloc);
1630 if (r) {
1631 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1632 idx, reg);
1633 r100_cs_dump_packet(p, pkt);
1634 return r;
1635 }
f2746f83
AD		 1636 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1637 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1638 tile_flags |= RADEON_TXO_MACRO_TILE;
1639 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1640 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1641
1642 tmp = idx_value & ~(0x7 << 2);
1643 tmp |= tile_flags;
1644 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1645 } else
1646 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1647 track->textures[i].robj = reloc->robj;
40b4a759 1648 track->tex_dirty = true;
551ebd83
DA		 1649 break;
1650 case RADEON_PP_CUBIC_OFFSET_T0_0:
1651 case RADEON_PP_CUBIC_OFFSET_T0_1:
1652 case RADEON_PP_CUBIC_OFFSET_T0_2:
1653 case RADEON_PP_CUBIC_OFFSET_T0_3:
1654 case RADEON_PP_CUBIC_OFFSET_T0_4:
1655 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1656 r = r100_cs_packet_next_reloc(p, &reloc);
1657 if (r) {
1658 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1659 idx, reg);
1660 r100_cs_dump_packet(p, pkt);
1661 return r;
1662 }
513bcb46
DA		 1663 track->textures[0].cube_info[i].offset = idx_value;
1664 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1665 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1666 track->tex_dirty = true;
551ebd83
DA		 1667 break;
1668 case RADEON_PP_CUBIC_OFFSET_T1_0:
1669 case RADEON_PP_CUBIC_OFFSET_T1_1:
1670 case RADEON_PP_CUBIC_OFFSET_T1_2:
1671 case RADEON_PP_CUBIC_OFFSET_T1_3:
1672 case RADEON_PP_CUBIC_OFFSET_T1_4:
1673 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1674 r = r100_cs_packet_next_reloc(p, &reloc);
1675 if (r) {
1676 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1677 idx, reg);
1678 r100_cs_dump_packet(p, pkt);
1679 return r;
1680 }
513bcb46
DA		 1681 track->textures[1].cube_info[i].offset = idx_value;
1682 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1683 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1684 track->tex_dirty = true;
551ebd83
DA		 1685 break;
1686 case RADEON_PP_CUBIC_OFFSET_T2_0:
1687 case RADEON_PP_CUBIC_OFFSET_T2_1:
1688 case RADEON_PP_CUBIC_OFFSET_T2_2:
1689 case RADEON_PP_CUBIC_OFFSET_T2_3:
1690 case RADEON_PP_CUBIC_OFFSET_T2_4:
1691 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1692 r = r100_cs_packet_next_reloc(p, &reloc);
1693 if (r) {
1694 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1695 idx, reg);
1696 r100_cs_dump_packet(p, pkt);
1697 return r;
1698 }
513bcb46
DA		 1699 track->textures[2].cube_info[i].offset = idx_value;
1700 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1701 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1702 track->tex_dirty = true;
551ebd83
DA		 1703 break;
1704 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1705 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1706 track->cb_dirty = true;
1707 track->zb_dirty = true;
551ebd83
DA		 1708 break;
1709 case RADEON_RB3D_COLORPITCH:
1710 r = r100_cs_packet_next_reloc(p, &reloc);
1711 if (r) {
1712 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1713 idx, reg);
1714 r100_cs_dump_packet(p, pkt);
1715 return r;
1716 }
c9068eb2
AD		 1717 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1718 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1719 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1720 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1721 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1722
1723 tmp = idx_value & ~(0x7 << 16);
1724 tmp |= tile_flags;
1725 ib[idx] = tmp;
1726 } else
1727 ib[idx] = idx_value;
e024e110 1728
513bcb46 1729 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1730 track->cb_dirty = true;
551ebd83
DA		 1731 break;
1732 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1733 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1734 track->zb_dirty = true;
551ebd83
DA		 1735 break;
1736 case RADEON_RB3D_CNTL:
513bcb46 1737 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1738 case 7:
1739 case 8:
1740 case 9:
1741 case 11:
1742 case 12:
1743 track->cb[0].cpp = 1;
e024e110 1744 break;
551ebd83
DA		 1745 case 3:
1746 case 4:
1747 case 15:
1748 track->cb[0].cpp = 2;
1749 break;
1750 case 6:
1751 track->cb[0].cpp = 4;
1752 break;
1753 default:
1754 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1755 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1756 return -EINVAL;
1757 }
513bcb46 1758 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1759 track->cb_dirty = true;
1760 track->zb_dirty = true;
551ebd83
DA		 1761 break;
1762 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1763 switch (idx_value & 0xf) {
551ebd83
DA		 1764 case 0:
1765 track->zb.cpp = 2;
1766 break;
1767 case 2:
1768 case 3:
1769 case 4:
1770 case 5:
1771 case 9:
1772 case 11:
1773 track->zb.cpp = 4;
17782d99 1774 break;
771fe6b9 1775 default:
771fe6b9
JG		 1776 break;
1777 }
40b4a759 1778 track->zb_dirty = true;
551ebd83
DA		 1779 break;
1780 case RADEON_RB3D_ZPASS_ADDR:
1781 r = r100_cs_packet_next_reloc(p, &reloc);
1782 if (r) {
1783 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1784 idx, reg);
1785 r100_cs_dump_packet(p, pkt);
1786 return r;
1787 }
513bcb46 1788 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1789 break;
1790 case RADEON_PP_CNTL:
1791 {
513bcb46 1792 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1793 for (i = 0; i < track->num_texture; i++)
1794 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1795 track->tex_dirty = true;
551ebd83
DA		 1796 }
1797 break;
1798 case RADEON_SE_VF_CNTL:
513bcb46 1799 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1800 break;
1801 case RADEON_SE_VTX_FMT:
513bcb46 1802 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1803 break;
1804 case RADEON_PP_TEX_SIZE_0:
1805 case RADEON_PP_TEX_SIZE_1:
1806 case RADEON_PP_TEX_SIZE_2:
1807 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1808 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1809 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1810 track->tex_dirty = true;
551ebd83
DA		 1811 break;
1812 case RADEON_PP_TEX_PITCH_0:
1813 case RADEON_PP_TEX_PITCH_1:
1814 case RADEON_PP_TEX_PITCH_2:
1815 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1816 track->textures[i].pitch = idx_value + 32;
40b4a759 1817 track->tex_dirty = true;
551ebd83
DA		 1818 break;
1819 case RADEON_PP_TXFILTER_0:
1820 case RADEON_PP_TXFILTER_1:
1821 case RADEON_PP_TXFILTER_2:
1822 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1823 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1824 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1825 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1826 if (tmp == 2 || tmp == 6)
1827 track->textures[i].roundup_w = false;
513bcb46 1828 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1829 if (tmp == 2 || tmp == 6)
1830 track->textures[i].roundup_h = false;
40b4a759 1831 track->tex_dirty = true;
551ebd83
DA		 1832 break;
1833 case RADEON_PP_TXFORMAT_0:
1834 case RADEON_PP_TXFORMAT_1:
1835 case RADEON_PP_TXFORMAT_2:
1836 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1837 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1838 track->textures[i].use_pitch = 1;
1839 } else {
1840 track->textures[i].use_pitch = 0;
513bcb46
DA		 1841 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1842 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1843 }
513bcb46 1844 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1845 track->textures[i].tex_coord_type = 2;
513bcb46 1846 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1847 case RADEON_TXFORMAT_I8:
1848 case RADEON_TXFORMAT_RGB332:
1849 case RADEON_TXFORMAT_Y8:
1850 track->textures[i].cpp = 1;
f9da52d5 1851 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1852 break;
1853 case RADEON_TXFORMAT_AI88:
1854 case RADEON_TXFORMAT_ARGB1555:
1855 case RADEON_TXFORMAT_RGB565:
1856 case RADEON_TXFORMAT_ARGB4444:
1857 case RADEON_TXFORMAT_VYUY422:
1858 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1859 case RADEON_TXFORMAT_SHADOW16:
1860 case RADEON_TXFORMAT_LDUDV655:
1861 case RADEON_TXFORMAT_DUDV88:
1862 track->textures[i].cpp = 2;
f9da52d5 1863 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1864 break;
551ebd83
DA		 1865 case RADEON_TXFORMAT_ARGB8888:
1866 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1867 case RADEON_TXFORMAT_SHADOW32:
1868 case RADEON_TXFORMAT_LDUDUV8888:
1869 track->textures[i].cpp = 4;
f9da52d5 1870 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1871 break;
d785d78b
DA		 1872 case RADEON_TXFORMAT_DXT1:
1873 track->textures[i].cpp = 1;
1874 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1875 break;
1876 case RADEON_TXFORMAT_DXT23:
1877 case RADEON_TXFORMAT_DXT45:
1878 track->textures[i].cpp = 1;
1879 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1880 break;
551ebd83 1881 }
513bcb46
DA		 1882 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1883 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1884 track->tex_dirty = true;
551ebd83
DA		 1885 break;
1886 case RADEON_PP_CUBIC_FACES_0:
1887 case RADEON_PP_CUBIC_FACES_1:
1888 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1889 tmp = idx_value;
551ebd83
DA		 1890 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1891 for (face = 0; face < 4; face++) {
1892 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1893 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1894 }
40b4a759 1895 track->tex_dirty = true;
551ebd83
DA		 1896 break;
1897 default:
1898 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1899 reg, idx);
1900 return -EINVAL;
771fe6b9
JG		 1901 }
1902 return 0;
1903}
1904
068a117c
JG		 1905int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1906 struct radeon_cs_packet *pkt,
4c788679 1907 struct radeon_bo *robj)
068a117c 1908{
068a117c 1909 unsigned idx;
513bcb46 1910 u32 value;
068a117c 1911 idx = pkt->idx + 1;
513bcb46 1912 value = radeon_get_ib_value(p, idx + 2);
4c788679 1913 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1914 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1915 "(need %u have %lu) !\n",
513bcb46 1916 value + 1,
4c788679 1917 radeon_bo_size(robj));
068a117c
JG		 1918 return -EINVAL;
1919 }
1920 return 0;
1921}
1922
771fe6b9
JG		 1923static int r100_packet3_check(struct radeon_cs_parser *p,
1924 struct radeon_cs_packet *pkt)
1925{
771fe6b9 1926 struct radeon_cs_reloc *reloc;
551ebd83 1927 struct r100_cs_track *track;
771fe6b9 1928 unsigned idx;
771fe6b9
JG		 1929 volatile uint32_t *ib;
1930 int r;
1931
f2e39221 1932 ib = p->ib.ptr;
771fe6b9 1933 idx = pkt->idx + 1;
551ebd83 1934 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1935 switch (pkt->opcode) {
1936 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1937 r = r100_packet3_load_vbpntr(p, pkt, idx);
1938 if (r)
1939 return r;
771fe6b9
JG		 1940 break;
1941 case PACKET3_INDX_BUFFER:
1942 r = r100_cs_packet_next_reloc(p, &reloc);
1943 if (r) {
1944 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1945 r100_cs_dump_packet(p, pkt);
1946 return r;
1947 }
513bcb46 1948 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1949 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1950 if (r) {
1951 return r;
1952 }
771fe6b9
JG		 1953 break;
1954 case 0x23:
771fe6b9
JG		 1955 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1956 r = r100_cs_packet_next_reloc(p, &reloc);
1957 if (r) {
1958 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1959 r100_cs_dump_packet(p, pkt);
1960 return r;
1961 }
513bcb46 1962 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1963 track->num_arrays = 1;
513bcb46 1964 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1965
1966 track->arrays[0].robj = reloc->robj;
1967 track->arrays[0].esize = track->vtx_size;
1968
513bcb46 1969 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1970
513bcb46 1971 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1972 track->immd_dwords = pkt->count - 1;
1973 r = r100_cs_track_check(p->rdev, track);
1974 if (r)
1975 return r;
771fe6b9
JG		 1976 break;
1977 case PACKET3_3D_DRAW_IMMD:
513bcb46 1978 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1979 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1980 return -EINVAL;
1981 }
cf57fc7a 1982 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1984 track->immd_dwords = pkt->count - 1;
1985 r = r100_cs_track_check(p->rdev, track);
1986 if (r)
1987 return r;
1988 break;
771fe6b9
JG		 1989 /* triggers drawing using in-packet vertex data */
1990 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1991 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1992 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1993 return -EINVAL;
1994 }
513bcb46 1995 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1996 track->immd_dwords = pkt->count;
1997 r = r100_cs_track_check(p->rdev, track);
1998 if (r)
1999 return r;
2000 break;
771fe6b9
JG		 2001 /* triggers drawing using in-packet vertex data */
2002 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 2003 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 2004 r = r100_cs_track_check(p->rdev, track);
2005 if (r)
2006 return r;
2007 break;
771fe6b9
JG		 2008 /* triggers drawing of vertex buffers setup elsewhere */
2009 case PACKET3_3D_DRAW_INDX_2:
513bcb46 2010 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 2011 r = r100_cs_track_check(p->rdev, track);
2012 if (r)
2013 return r;
2014 break;
771fe6b9
JG		 2015 /* triggers drawing using indices to vertex buffer */
2016 case PACKET3_3D_DRAW_VBUF:
513bcb46 2017 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2018 r = r100_cs_track_check(p->rdev, track);
2019 if (r)
2020 return r;
2021 break;
771fe6b9
JG		 2022 /* triggers drawing of vertex buffers setup elsewhere */
2023 case PACKET3_3D_DRAW_INDX:
513bcb46 2024 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2025 r = r100_cs_track_check(p->rdev, track);
2026 if (r)
2027 return r;
2028 break;
771fe6b9 2029 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 2030 case PACKET3_3D_CLEAR_HIZ:
2031 case PACKET3_3D_CLEAR_ZMASK:
2032 if (p->rdev->hyperz_filp != p->filp)
2033 return -EINVAL;
2034 break;
771fe6b9
JG		 2035 case PACKET3_NOP:
2036 break;
2037 default:
2038 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2039 return -EINVAL;
2040 }
2041 return 0;
2042}
2043
2044int r100_cs_parse(struct radeon_cs_parser *p)
2045{
2046 struct radeon_cs_packet pkt;
9f022ddf 2047 struct r100_cs_track *track;
771fe6b9
JG		 2048 int r;
2049
9f022ddf 2050 track = kzalloc(sizeof(*track), GFP_KERNEL);
ce067913
DC		 2051 if (!track)
2052 return -ENOMEM;
9f022ddf
JG		 2053 r100_cs_track_clear(p->rdev, track);
2054 p->track = track;
771fe6b9 2055 do {
c38f34b5 2056 r = radeon_cs_packet_parse(p, &pkt, p->idx);
771fe6b9
JG		 2057 if (r) {
2058 return r;
2059 }
2060 p->idx += pkt.count + 2;
2061 switch (pkt.type) {
66b3543e
IH		 2062 case PACKET_TYPE0:
2063 if (p->rdev->family >= CHIP_R200)
2064 r = r100_cs_parse_packet0(p, &pkt,
2065 p->rdev->config.r100.reg_safe_bm,
2066 p->rdev->config.r100.reg_safe_bm_size,
2067 &r200_packet0_check);
2068 else
2069 r = r100_cs_parse_packet0(p, &pkt,
2070 p->rdev->config.r100.reg_safe_bm,
2071 p->rdev->config.r100.reg_safe_bm_size,
2072 &r100_packet0_check);
2073 break;
2074 case PACKET_TYPE2:
2075 break;
2076 case PACKET_TYPE3:
2077 r = r100_packet3_check(p, &pkt);
2078 break;
2079 default:
2080 DRM_ERROR("Unknown packet type %d !\n",
2081 pkt.type);
2082 return -EINVAL;
771fe6b9 2083 }
66b3543e 2084 if (r)
771fe6b9 2085 return r;
771fe6b9
JG		 2086 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2087 return 0;
2088}
2089
0242f74d 2090static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
771fe6b9 2091{
0242f74d
AD		 2092 DRM_ERROR("pitch %d\n", t->pitch);
2093 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2094 DRM_ERROR("width %d\n", t->width);
2095 DRM_ERROR("width_11 %d\n", t->width_11);
2096 DRM_ERROR("height %d\n", t->height);
2097 DRM_ERROR("height_11 %d\n", t->height_11);
2098 DRM_ERROR("num levels %d\n", t->num_levels);
2099 DRM_ERROR("depth %d\n", t->txdepth);
2100 DRM_ERROR("bpp %d\n", t->cpp);
2101 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2102 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2103 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2104 DRM_ERROR("compress format %d\n", t->compress_format);
771fe6b9
JG		 2105}
2106
0242f74d 2107static int r100_track_compress_size(int compress_format, int w, int h)
771fe6b9 2108{
0242f74d
AD		 2109 int block_width, block_height, block_bytes;
2110 int wblocks, hblocks;
2111 int min_wblocks;
2112 int sz;
771fe6b9 2113
0242f74d
AD		 2114 block_width = 4;
2115 block_height = 4;
2116
2117 switch (compress_format) {
2118 case R100_TRACK_COMP_DXT1:
2119 block_bytes = 8;
2120 min_wblocks = 4;
2121 break;
2122 default:
2123 case R100_TRACK_COMP_DXT35:
2124 block_bytes = 16;
2125 min_wblocks = 2;
2126 break;
771fe6b9 2127 }
0242f74d
AD		 2128
2129 hblocks = (h + block_height - 1) / block_height;
2130 wblocks = (w + block_width - 1) / block_width;
2131 if (wblocks < min_wblocks)
2132 wblocks = min_wblocks;
2133 sz = wblocks * hblocks * block_bytes;
2134 return sz;
771fe6b9
JG		 2135}
2136
0242f74d
AD		 2137static int r100_cs_track_cube(struct radeon_device *rdev,
2138 struct r100_cs_track *track, unsigned idx)
771fe6b9 2139{
0242f74d
AD		 2140 unsigned face, w, h;
2141 struct radeon_bo *cube_robj;
2142 unsigned long size;
2143 unsigned compress_format = track->textures[idx].compress_format;
771fe6b9 2144
0242f74d
AD		 2145 for (face = 0; face < 5; face++) {
2146 cube_robj = track->textures[idx].cube_info[face].robj;
2147 w = track->textures[idx].cube_info[face].width;
2148 h = track->textures[idx].cube_info[face].height;
771fe6b9 2149
0242f74d
AD		 2150 if (compress_format) {
2151 size = r100_track_compress_size(compress_format, w, h);
2152 } else
2153 size = w * h;
2154 size *= track->textures[idx].cpp;
2155
2156 size += track->textures[idx].cube_info[face].offset;
2157
2158 if (size > radeon_bo_size(cube_robj)) {
2159 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2160 size, radeon_bo_size(cube_robj));
2161 r100_cs_track_texture_print(&track->textures[idx]);
2162 return -1;
771fe6b9 2163 }
771fe6b9 2164 }
0242f74d 2165 return 0;
771fe6b9
JG		 2166}
2167
0242f74d
AD		 2168static int r100_cs_track_texture_check(struct radeon_device *rdev,
2169 struct r100_cs_track *track)
771fe6b9 2170{
0242f74d
AD		 2171 struct radeon_bo *robj;
2172 unsigned long size;
2173 unsigned u, i, w, h, d;
2174 int ret;
771fe6b9 2175
0242f74d
AD		 2176 for (u = 0; u < track->num_texture; u++) {
2177 if (!track->textures[u].enabled)
2178 continue;
2179 if (track->textures[u].lookup_disable)
2180 continue;
2181 robj = track->textures[u].robj;
2182 if (robj == NULL) {
2183 DRM_ERROR("No texture bound to unit %u\n", u);
2184 return -EINVAL;
771fe6b9 2185 }
0242f74d
AD		 2186 size = 0;
2187 for (i = 0; i <= track->textures[u].num_levels; i++) {
2188 if (track->textures[u].use_pitch) {
2189 if (rdev->family < CHIP_R300)
2190 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2191 else
2192 w = track->textures[u].pitch / (1 << i);
2193 } else {
2194 w = track->textures[u].width;
2195 if (rdev->family >= CHIP_RV515)
2196 w |= track->textures[u].width_11;
2197 w = w / (1 << i);
2198 if (track->textures[u].roundup_w)
2199 w = roundup_pow_of_two(w);
2200 }
2201 h = track->textures[u].height;
2202 if (rdev->family >= CHIP_RV515)
2203 h |= track->textures[u].height_11;
2204 h = h / (1 << i);
2205 if (track->textures[u].roundup_h)
2206 h = roundup_pow_of_two(h);
2207 if (track->textures[u].tex_coord_type == 1) {
2208 d = (1 << track->textures[u].txdepth) / (1 << i);
2209 if (!d)
2210 d = 1;
2211 } else {
2212 d = 1;
2213 }
2214 if (track->textures[u].compress_format) {
771fe6b9 2215
0242f74d
AD		 2216 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2217 /* compressed textures are block based */
2218 } else
2219 size += w * h * d;
2220 }
2221 size *= track->textures[u].cpp;
771fe6b9 2222
0242f74d
AD		 2223 switch (track->textures[u].tex_coord_type) {
2224 case 0:
2225 case 1:
2226 break;
2227 case 2:
2228 if (track->separate_cube) {
2229 ret = r100_cs_track_cube(rdev, track, u);
2230 if (ret)
2231 return ret;
2232 } else
2233 size *= 6;
2234 break;
2235 default:
2236 DRM_ERROR("Invalid texture coordinate type %u for unit "
2237 "%u\n", track->textures[u].tex_coord_type, u);
2238 return -EINVAL;
2239 }
2240 if (size > radeon_bo_size(robj)) {
2241 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2242 "%lu\n", u, size, radeon_bo_size(robj));
2243 r100_cs_track_texture_print(&track->textures[u]);
2244 return -EINVAL;
771fe6b9 2245 }
771fe6b9 2246 }
0242f74d 2247 return 0;
771fe6b9
JG		 2248}
2249
0242f74d 2250int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
771fe6b9
JG		 2251{
2252 unsigned i;
0242f74d
AD		 2253 unsigned long size;
2254 unsigned prim_walk;
2255 unsigned nverts;
2256 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
771fe6b9 2257
0242f74d
AD		 2258 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2259 !track->blend_read_enable)
2260 num_cb = 0;
2261
2262 for (i = 0; i < num_cb; i++) {
2263 if (track->cb[i].robj == NULL) {
2264 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2265 return -EINVAL;
2266 }
2267 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2268 size += track->cb[i].offset;
2269 if (size > radeon_bo_size(track->cb[i].robj)) {
2270 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2271 "(need %lu have %lu) !\n", i, size,
2272 radeon_bo_size(track->cb[i].robj));
2273 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2274 i, track->cb[i].pitch, track->cb[i].cpp,
2275 track->cb[i].offset, track->maxy);
2276 return -EINVAL;
771fe6b9 2277 }
771fe6b9 2278 }
0242f74d 2279 track->cb_dirty = false;
771fe6b9 2280
0242f74d
AD		 2281 if (track->zb_dirty && track->z_enabled) {
2282 if (track->zb.robj == NULL) {
2283 DRM_ERROR("[drm] No buffer for z buffer !\n");
2284 return -EINVAL;
2285 }
2286 size = track->zb.pitch * track->zb.cpp * track->maxy;
2287 size += track->zb.offset;
2288 if (size > radeon_bo_size(track->zb.robj)) {
2289 DRM_ERROR("[drm] Buffer too small for z buffer "
2290 "(need %lu have %lu) !\n", size,
2291 radeon_bo_size(track->zb.robj));
2292 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2293 track->zb.pitch, track->zb.cpp,
2294 track->zb.offset, track->maxy);
2295 return -EINVAL;
2296 }
225758d8 2297 }
0242f74d 2298 track->zb_dirty = false;
771fe6b9 2299
0242f74d
AD		 2300 if (track->aa_dirty && track->aaresolve) {
2301 if (track->aa.robj == NULL) {
2302 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2303 return -EINVAL;
2304 }
2305 /* I believe the format comes from colorbuffer0. */
2306 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2307 size += track->aa.offset;
2308 if (size > radeon_bo_size(track->aa.robj)) {
2309 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2310 "(need %lu have %lu) !\n", i, size,
2311 radeon_bo_size(track->aa.robj));
2312 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2313 i, track->aa.pitch, track->cb[0].cpp,
2314 track->aa.offset, track->maxy);
2315 return -EINVAL;
2316 }
2317 }
2318 track->aa_dirty = false;
771fe6b9 2319
0242f74d
AD		 2320 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2321 if (track->vap_vf_cntl & (1 << 14)) {
2322 nverts = track->vap_alt_nverts;
2323 } else {
2324 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2739d49c 2325 }
0242f74d
AD		 2326 switch (prim_walk) {
2327 case 1:
2328 for (i = 0; i < track->num_arrays; i++) {
2329 size = track->arrays[i].esize * track->max_indx * 4;
2330 if (track->arrays[i].robj == NULL) {
2331 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2332 "bound\n", prim_walk, i);
2333 return -EINVAL;
2334 }
2335 if (size > radeon_bo_size(track->arrays[i].robj)) {
2336 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2337 "need %lu dwords have %lu dwords\n",
2338 prim_walk, i, size >> 2,
2339 radeon_bo_size(track->arrays[i].robj)
2340 >> 2);
2341 DRM_ERROR("Max indices %u\n", track->max_indx);
2342 return -EINVAL;
2343 }
771fe6b9 2344 }
0242f74d
AD		 2345 break;
2346 case 2:
2347 for (i = 0; i < track->num_arrays; i++) {
2348 size = track->arrays[i].esize * (nverts - 1) * 4;
2349 if (track->arrays[i].robj == NULL) {
2350 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2351 "bound\n", prim_walk, i);
2352 return -EINVAL;
2353 }
2354 if (size > radeon_bo_size(track->arrays[i].robj)) {
2355 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2356 "need %lu dwords have %lu dwords\n",
2357 prim_walk, i, size >> 2,
2358 radeon_bo_size(track->arrays[i].robj)
2359 >> 2);
2360 return -EINVAL;
2361 }
771fe6b9 2362 }
0242f74d
AD		 2363 break;
2364 case 3:
2365 size = track->vtx_size * nverts;
2366 if (size != track->immd_dwords) {
2367 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2368 track->immd_dwords, size);
2369 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2370 nverts, track->vtx_size);
2371 return -EINVAL;
771fe6b9 2372 }
0242f74d
AD		 2373 break;
2374 default:
2375 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2376 prim_walk);
2377 return -EINVAL;
2a0f8918
DA		 2378 }
2379
0242f74d
AD		 2380 if (track->tex_dirty) {
2381 track->tex_dirty = false;
2382 return r100_cs_track_texture_check(rdev, track);
2a0f8918 2383 }
0242f74d 2384 return 0;
2a0f8918
DA		 2385}
2386
0242f74d 2387void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2a0f8918 2388{
0242f74d 2389 unsigned i, face;
2a0f8918 2390
0242f74d
AD		 2391 track->cb_dirty = true;
2392 track->zb_dirty = true;
2393 track->tex_dirty = true;
2394 track->aa_dirty = true;
b7d8cce5 2395
0242f74d
AD		 2396 if (rdev->family < CHIP_R300) {
2397 track->num_cb = 1;
2398 if (rdev->family <= CHIP_RS200)
2399 track->num_texture = 3;
7a50f01a 2400 else
0242f74d
AD		 2401 track->num_texture = 6;
2402 track->maxy = 2048;
2403 track->separate_cube = 1;
28d52043 2404 } else {
0242f74d
AD		 2405 track->num_cb = 4;
2406 track->num_texture = 16;
2407 track->maxy = 4096;
2408 track->separate_cube = 0;
2409 track->aaresolve = false;
2410 track->aa.robj = NULL;
28d52043 2411 }
2a0f8918 2412
0242f74d
AD		 2413 for (i = 0; i < track->num_cb; i++) {
2414 track->cb[i].robj = NULL;
2415 track->cb[i].pitch = 8192;
2416 track->cb[i].cpp = 16;
2417 track->cb[i].offset = 0;
771fe6b9 2418 }
0242f74d
AD		 2419 track->z_enabled = true;
2420 track->zb.robj = NULL;
2421 track->zb.pitch = 8192;
2422 track->zb.cpp = 4;
2423 track->zb.offset = 0;
2424 track->vtx_size = 0x7F;
2425 track->immd_dwords = 0xFFFFFFFFUL;
2426 track->num_arrays = 11;
2427 track->max_indx = 0x00FFFFFFUL;
2428 for (i = 0; i < track->num_arrays; i++) {
2429 track->arrays[i].robj = NULL;
2430 track->arrays[i].esize = 0x7F;
771fe6b9 2431 }
0242f74d
AD		 2432 for (i = 0; i < track->num_texture; i++) {
2433 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2434 track->textures[i].pitch = 16536;
2435 track->textures[i].width = 16536;
2436 track->textures[i].height = 16536;
2437 track->textures[i].width_11 = 1 << 11;
2438 track->textures[i].height_11 = 1 << 11;
2439 track->textures[i].num_levels = 12;
2440 if (rdev->family <= CHIP_RS200) {
2441 track->textures[i].tex_coord_type = 0;
2442 track->textures[i].txdepth = 0;
2443 } else {
2444 track->textures[i].txdepth = 16;
2445 track->textures[i].tex_coord_type = 1;
2446 }
2447 track->textures[i].cpp = 64;
2448 track->textures[i].robj = NULL;
2449 /* CS IB emission code makes sure texture unit are disabled */
2450 track->textures[i].enabled = false;
2451 track->textures[i].lookup_disable = false;
2452 track->textures[i].roundup_w = true;
2453 track->textures[i].roundup_h = true;
2454 if (track->separate_cube)
2455 for (face = 0; face < 5; face++) {
2456 track->textures[i].cube_info[face].robj = NULL;
2457 track->textures[i].cube_info[face].width = 16536;
2458 track->textures[i].cube_info[face].height = 16536;
2459 track->textures[i].cube_info[face].offset = 0;
2460 }
771fe6b9
JG		 2461 }
2462}
2463
0242f74d
AD		 2464/*
2465 * Global GPU functions
2466 */
1109ca09 2467static void r100_errata(struct radeon_device *rdev)
771fe6b9 2468{
0242f74d 2469 rdev->pll_errata = 0;
771fe6b9 2470
0242f74d
AD		 2471 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2472 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2473 }
771fe6b9 2474
0242f74d
AD		 2475 if (rdev->family == CHIP_RV100 ||
2476 rdev->family == CHIP_RS100 ||
2477 rdev->family == CHIP_RS200) {
2478 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2479 }
771fe6b9
JG		 2480}
2481
1109ca09 2482static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
771fe6b9 2483{
0242f74d
AD		 2484 unsigned i;
2485 uint32_t tmp;
771fe6b9 2486
0242f74d
AD		 2487 for (i = 0; i < rdev->usec_timeout; i++) {
2488 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2489 if (tmp >= n) {
2490 return 0;
2491 }
2492 DRM_UDELAY(1);
771fe6b9 2493 }
0242f74d 2494 return -1;
771fe6b9
JG		 2495}
2496
0242f74d 2497int r100_gui_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2498{
771fe6b9 2499 unsigned i;
0242f74d 2500 uint32_t tmp;
771fe6b9 2501
0242f74d
AD		 2502 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2503 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2504 " Bad things might happen.\n");
771fe6b9 2505 }
0242f74d
AD		 2506 for (i = 0; i < rdev->usec_timeout; i++) {
2507 tmp = RREG32(RADEON_RBBM_STATUS);
2508 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2509 return 0;
2510 }
2511 DRM_UDELAY(1);
771fe6b9 2512 }
0242f74d 2513 return -1;
771fe6b9
JG		 2514}
2515
0242f74d 2516int r100_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2517{
0242f74d 2518 unsigned i;
771fe6b9
JG		 2519 uint32_t tmp;
2520
0242f74d
AD		 2521 for (i = 0; i < rdev->usec_timeout; i++) {
2522 /* read MC_STATUS */
2523 tmp = RREG32(RADEON_MC_STATUS);
2524 if (tmp & RADEON_MC_IDLE) {
2525 return 0;
2526 }
2527 DRM_UDELAY(1);
2528 }
2529 return -1;
771fe6b9
JG		 2530}
2531
0242f74d 2532bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2533{
0242f74d 2534 u32 rbbm_status;
771fe6b9 2535
0242f74d
AD		 2536 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2537 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2538 radeon_ring_lockup_update(ring);
2539 return false;
2540 }
2541 /* force CP activities */
2542 radeon_ring_force_activity(rdev, ring);
2543 return radeon_ring_test_lockup(rdev, ring);
771fe6b9
JG		 2544}
2545
74da01dc
AD		 2546/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2547void r100_enable_bm(struct radeon_device *rdev)
2548{
2549 uint32_t tmp;
2550 /* Enable bus mastering */
2551 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2552 WREG32(RADEON_BUS_CNTL, tmp);
2553}
2554
0242f74d 2555void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2556{
0242f74d
AD		 2557 u32 tmp;
2558
2559 /* disable bus mastering */
2560 tmp = RREG32(R_000030_BUS_CNTL);
2561 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2562 mdelay(1);
2563 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2564 mdelay(1);
2565 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2566 tmp = RREG32(RADEON_BUS_CNTL);
2567 mdelay(1);
2568 pci_clear_master(rdev->pdev);
2569 mdelay(1);
771fe6b9 2570}
e024e110 2571
0242f74d 2572int r100_asic_reset(struct radeon_device *rdev)
e024e110 2573{
0242f74d
AD		 2574 struct r100_mc_save save;
2575 u32 status, tmp;
2576 int ret = 0;
e024e110 2577
0242f74d
AD		 2578 status = RREG32(R_000E40_RBBM_STATUS);
2579 if (!G_000E40_GUI_ACTIVE(status)) {
2580 return 0;
e024e110 2581 }
0242f74d
AD		 2582 r100_mc_stop(rdev, &save);
2583 status = RREG32(R_000E40_RBBM_STATUS);
2584 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2585 /* stop CP */
2586 WREG32(RADEON_CP_CSQ_CNTL, 0);
2587 tmp = RREG32(RADEON_CP_RB_CNTL);
2588 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2589 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2590 WREG32(RADEON_CP_RB_WPTR, 0);
2591 WREG32(RADEON_CP_RB_CNTL, tmp);
2592 /* save PCI state */
2593 pci_save_state(rdev->pdev);
2594 /* disable bus mastering */
2595 r100_bm_disable(rdev);
2596 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2597 S_0000F0_SOFT_RESET_RE(1) |
2598 S_0000F0_SOFT_RESET_PP(1) |
2599 S_0000F0_SOFT_RESET_RB(1));
2600 RREG32(R_0000F0_RBBM_SOFT_RESET);
2601 mdelay(500);
2602 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2603 mdelay(1);
2604 status = RREG32(R_000E40_RBBM_STATUS);
2605 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2606 /* reset CP */
2607 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2608 RREG32(R_0000F0_RBBM_SOFT_RESET);
2609 mdelay(500);
2610 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2611 mdelay(1);
2612 status = RREG32(R_000E40_RBBM_STATUS);
2613 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2614 /* restore PCI & busmastering */
2615 pci_restore_state(rdev->pdev);
2616 r100_enable_bm(rdev);
2617 /* Check if GPU is idle */
2618 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2619 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2620 dev_err(rdev->dev, "failed to reset GPU\n");
2621 ret = -1;
2622 } else
2623 dev_info(rdev->dev, "GPU reset succeed\n");
2624 r100_mc_resume(rdev, &save);
2625 return ret;
2626}
e024e110 2627
0242f74d
AD		 2628void r100_set_common_regs(struct radeon_device *rdev)
2629{
2630 struct drm_device *dev = rdev->ddev;
2631 bool force_dac2 = false;
2632 u32 tmp;
f5c5f040 2633
0242f74d
AD		 2634 /* set these so they don't interfere with anything */
2635 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2636 WREG32(RADEON_SUBPIC_CNTL, 0);
2637 WREG32(RADEON_VIPH_CONTROL, 0);
2638 WREG32(RADEON_I2C_CNTL_1, 0);
2639 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2640 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2641 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
f5c5f040 2642
0242f74d
AD		 2643 /* always set up dac2 on rn50 and some rv100 as lots
2644 * of servers seem to wire it up to a VGA port but
2645 * don't report it in the bios connector
2646 * table.
2647 */
2648 switch (dev->pdev->device) {
2649 /* RN50 */
2650 case 0x515e:
2651 case 0x5969:
2652 force_dac2 = true;
2653 break;
2654 /* RV100*/
2655 case 0x5159:
2656 case 0x515a:
2657 /* DELL triple head servers */
2658 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2659 ((dev->pdev->subsystem_device == 0x016c) ||
2660 (dev->pdev->subsystem_device == 0x016d) ||
2661 (dev->pdev->subsystem_device == 0x016e) ||
2662 (dev->pdev->subsystem_device == 0x016f) ||
2663 (dev->pdev->subsystem_device == 0x0170) ||
2664 (dev->pdev->subsystem_device == 0x017d) ||
2665 (dev->pdev->subsystem_device == 0x017e) ||
2666 (dev->pdev->subsystem_device == 0x0183) ||
2667 (dev->pdev->subsystem_device == 0x018a) ||
2668 (dev->pdev->subsystem_device == 0x019a)))
2669 force_dac2 = true;
2670 break;
2671 }
f5c5f040 2672
0242f74d
AD		 2673 if (force_dac2) {
2674 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2675 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2676 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
e024e110 2677
0242f74d
AD		 2678 /* For CRT on DAC2, don't turn it on if BIOS didn't
2679 enable it, even it's detected.
2680 */
c93bb85b 2681
0242f74d
AD		 2682 /* force it to crtc0 */
2683 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2684 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2685 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
c93bb85b 2686
0242f74d
AD		 2687 /* set up the TV DAC */
2688 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2689 RADEON_TV_DAC_STD_MASK |
2690 RADEON_TV_DAC_RDACPD |
2691 RADEON_TV_DAC_GDACPD |
2692 RADEON_TV_DAC_BDACPD |
2693 RADEON_TV_DAC_BGADJ_MASK |
2694 RADEON_TV_DAC_DACADJ_MASK);
2695 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2696 RADEON_TV_DAC_NHOLD |
2697 RADEON_TV_DAC_STD_PS2 |
2698 (0x58 << 16));
f46c0120 2699
0242f74d
AD		 2700 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2701 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2702 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
c93bb85b 2703 }
0242f74d
AD		 2704
2705 /* switch PM block to ACPI mode */
2706 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2707 tmp &= ~RADEON_PM_MODE_SEL;
2708 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2709
2710}
2711
2712/*
2713 * VRAM info
2714 */
2715static void r100_vram_get_type(struct radeon_device *rdev)
2716{
2717 uint32_t tmp;
2718
2719 rdev->mc.vram_is_ddr = false;
2720 if (rdev->flags & RADEON_IS_IGP)
2721 rdev->mc.vram_is_ddr = true;
2722 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2723 rdev->mc.vram_is_ddr = true;
2724 if ((rdev->family == CHIP_RV100) ||
2725 (rdev->family == CHIP_RS100) ||
2726 (rdev->family == CHIP_RS200)) {
2727 tmp = RREG32(RADEON_MEM_CNTL);
2728 if (tmp & RV100_HALF_MODE) {
2729 rdev->mc.vram_width = 32;
2730 } else {
2731 rdev->mc.vram_width = 64;
2732 }
2733 if (rdev->flags & RADEON_SINGLE_CRTC) {
2734 rdev->mc.vram_width /= 4;
2735 rdev->mc.vram_is_ddr = true;
dfee5614 2736 }
0242f74d
AD		 2737 } else if (rdev->family <= CHIP_RV280) {
2738 tmp = RREG32(RADEON_MEM_CNTL);
2739 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2740 rdev->mc.vram_width = 128;
2741 } else {
2742 rdev->mc.vram_width = 64;
2743 }
2744 } else {
2745 /* newer IGPs */
2746 rdev->mc.vram_width = 128;
c93bb85b 2747 }
0242f74d 2748}
c93bb85b 2749
0242f74d
AD		 2750static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2751{
2752 u32 aper_size;
2753 u8 byte;
2754
2755 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2756
2757 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2758 * that is has the 2nd generation multifunction PCI interface
2759 */
2760 if (rdev->family == CHIP_RV280 ||
2761 rdev->family >= CHIP_RV350) {
2762 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2763 ~RADEON_HDP_APER_CNTL);
2764 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2765 return aper_size * 2;
c93bb85b
JG		 2766 }
2767
0242f74d
AD		 2768 /* Older cards have all sorts of funny issues to deal with. First
2769 * check if it's a multifunction card by reading the PCI config
2770 * header type... Limit those to one aperture size
c93bb85b 2771 */
0242f74d
AD		 2772 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2773 if (byte & 0x80) {
2774 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2775 DRM_INFO("Limiting VRAM to one aperture\n");
2776 return aper_size;
2777 }
c93bb85b 2778
0242f74d
AD		 2779 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2780 * have set it up. We don't write this as it's broken on some ASICs but
2781 * we expect the BIOS to have done the right thing (might be too optimistic...)
2782 */
2783 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2784 return aper_size * 2;
2785 return aper_size;
2786}
c93bb85b 2787
0242f74d
AD		 2788void r100_vram_init_sizes(struct radeon_device *rdev)
2789{
2790 u64 config_aper_size;
c93bb85b 2791
0242f74d
AD		 2792 /* work out accessible VRAM */
2793 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2794 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2795 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2796 /* FIXME we don't use the second aperture yet when we could use it */
2797 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2798 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2799 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2800 if (rdev->flags & RADEON_IS_IGP) {
2801 uint32_t tom;
2802 /* read NB_TOM to get the amount of ram stolen for the GPU */
2803 tom = RREG32(RADEON_NB_TOM);
2804 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2805 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2806 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2807 } else {
2808 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2809 /* Some production boards of m6 will report 0
2810 * if it's 8 MB
2811 */
2812 if (rdev->mc.real_vram_size == 0) {
2813 rdev->mc.real_vram_size = 8192 * 1024;
2814 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2815 }
2816 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2817 * Novell bug 204882 + along with lots of ubuntu ones
2818 */
2819 if (rdev->mc.aper_size > config_aper_size)
2820 config_aper_size = rdev->mc.aper_size;
2821
2822 if (config_aper_size > rdev->mc.real_vram_size)
2823 rdev->mc.mc_vram_size = config_aper_size;
2824 else
2825 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
c93bb85b 2826 }
0242f74d 2827}
c93bb85b 2828
0242f74d
AD		 2829void r100_vga_set_state(struct radeon_device *rdev, bool state)
2830{
2831 uint32_t temp;
2832
2833 temp = RREG32(RADEON_CONFIG_CNTL);
2834 if (state == false) {
2835 temp &= ~RADEON_CFG_VGA_RAM_EN;
2836 temp |= RADEON_CFG_VGA_IO_DIS;
2837 } else {
2838 temp &= ~RADEON_CFG_VGA_IO_DIS;
c93bb85b 2839 }
0242f74d
AD		 2840 WREG32(RADEON_CONFIG_CNTL, temp);
2841}
c93bb85b 2842
1109ca09 2843static void r100_mc_init(struct radeon_device *rdev)
0242f74d
AD		 2844{
2845 u64 base;
c93bb85b 2846
0242f74d
AD		 2847 r100_vram_get_type(rdev);
2848 r100_vram_init_sizes(rdev);
2849 base = rdev->mc.aper_base;
2850 if (rdev->flags & RADEON_IS_IGP)
2851 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2852 radeon_vram_location(rdev, &rdev->mc, base);
2853 rdev->mc.gtt_base_align = 0;
2854 if (!(rdev->flags & RADEON_IS_AGP))
2855 radeon_gtt_location(rdev, &rdev->mc);
2856 radeon_update_bandwidth_info(rdev);
2857}
2858
2859
2860/*
2861 * Indirect registers accessor
2862 */
2863void r100_pll_errata_after_index(struct radeon_device *rdev)
2864{
2865 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2866 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2867 (void)RREG32(RADEON_CRTC_GEN_CNTL);
c93bb85b 2868 }
0242f74d 2869}
c93bb85b 2870
0242f74d
AD		 2871static void r100_pll_errata_after_data(struct radeon_device *rdev)
2872{
2873 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2874 * or the chip could hang on a subsequent access
2875 */
2876 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2877 mdelay(5);
c93bb85b
JG		 2878 }
2879
0242f74d
AD		 2880 /* This function is required to workaround a hardware bug in some (all?)
2881 * revisions of the R300. This workaround should be called after every
2882 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2883 * may not be correct.
2884 */
2885 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2886 uint32_t save, tmp;
c93bb85b 2887
0242f74d
AD		 2888 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2889 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2890 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2891 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2892 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
c93bb85b 2893 }
0242f74d 2894}
c93bb85b 2895
0242f74d
AD		 2896uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2897{
2898 uint32_t data;
c93bb85b 2899
0242f74d
AD		 2900 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2901 r100_pll_errata_after_index(rdev);
2902 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2903 r100_pll_errata_after_data(rdev);
2904 return data;
2905}
c93bb85b 2906
0242f74d
AD		 2907void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2908{
2909 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2910 r100_pll_errata_after_index(rdev);
2911 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2912 r100_pll_errata_after_data(rdev);
2913}
2914
1109ca09 2915static void r100_set_safe_registers(struct radeon_device *rdev)
0242f74d
AD		 2916{
2917 if (ASIC_IS_RN50(rdev)) {
2918 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2919 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2920 } else if (rdev->family < CHIP_R200) {
2921 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2922 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
c93bb85b 2923 } else {
0242f74d 2924 r200_set_safe_registers(rdev);
c93bb85b 2925 }
0242f74d 2926}
c93bb85b 2927
0242f74d
AD		 2928/*
2929 * Debugfs info
2930 */
2931#if defined(CONFIG_DEBUG_FS)
2932static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2933{
2934 struct drm_info_node *node = (struct drm_info_node *) m->private;
2935 struct drm_device *dev = node->minor->dev;
2936 struct radeon_device *rdev = dev->dev_private;
2937 uint32_t reg, value;
2938 unsigned i;
c93bb85b 2939
0242f74d
AD		 2940 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2941 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2942 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2943 for (i = 0; i < 64; i++) {
2944 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2945 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2946 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2947 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2948 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2949 }
2950 return 0;
2951}
c93bb85b 2952
0242f74d
AD		 2953static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2954{
2955 struct drm_info_node *node = (struct drm_info_node *) m->private;
2956 struct drm_device *dev = node->minor->dev;
2957 struct radeon_device *rdev = dev->dev_private;
2958 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2959 uint32_t rdp, wdp;
2960 unsigned count, i, j;
c93bb85b 2961
0242f74d
AD		 2962 radeon_ring_free_size(rdev, ring);
2963 rdp = RREG32(RADEON_CP_RB_RPTR);
2964 wdp = RREG32(RADEON_CP_RB_WPTR);
2965 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2966 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2967 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2968 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2969 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2970 seq_printf(m, "%u dwords in ring\n", count);
2971 for (j = 0; j <= count; j++) {
2972 i = (rdp + j) & ring->ptr_mask;
2973 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2974 }
2975 return 0;
2976}
c93bb85b 2977
c93bb85b 2978
0242f74d
AD		 2979static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2980{
2981 struct drm_info_node *node = (struct drm_info_node *) m->private;
2982 struct drm_device *dev = node->minor->dev;
2983 struct radeon_device *rdev = dev->dev_private;
2984 uint32_t csq_stat, csq2_stat, tmp;
2985 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2986 unsigned i;
c93bb85b 2987
0242f74d
AD		 2988 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2989 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2990 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2991 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2992 r_rptr = (csq_stat >> 0) & 0x3ff;
2993 r_wptr = (csq_stat >> 10) & 0x3ff;
2994 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2995 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2996 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2997 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2998 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2999 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3000 seq_printf(m, "Ring rptr %u\n", r_rptr);
3001 seq_printf(m, "Ring wptr %u\n", r_wptr);
3002 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3003 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3004 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3005 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3006 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3007 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3008 seq_printf(m, "Ring fifo:\n");
3009 for (i = 0; i < 256; i++) {
3010 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3011 tmp = RREG32(RADEON_CP_CSQ_DATA);
3012 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3013 }
3014 seq_printf(m, "Indirect1 fifo:\n");
3015 for (i = 256; i <= 512; i++) {
3016 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3017 tmp = RREG32(RADEON_CP_CSQ_DATA);
3018 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3019 }
3020 seq_printf(m, "Indirect2 fifo:\n");
3021 for (i = 640; i < ib1_wptr; i++) {
3022 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3023 tmp = RREG32(RADEON_CP_CSQ_DATA);
3024 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3025 }
3026 return 0;
3027}
3028
3029static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3030{
3031 struct drm_info_node *node = (struct drm_info_node *) m->private;
3032 struct drm_device *dev = node->minor->dev;
3033 struct radeon_device *rdev = dev->dev_private;
3034 uint32_t tmp;
c93bb85b 3035
0242f74d
AD		 3036 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3037 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3038 tmp = RREG32(RADEON_MC_FB_LOCATION);
3039 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3040 tmp = RREG32(RADEON_BUS_CNTL);
3041 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3042 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3043 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3044 tmp = RREG32(RADEON_AGP_BASE);
3045 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3046 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3047 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3048 tmp = RREG32(0x01D0);
3049 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3050 tmp = RREG32(RADEON_AIC_LO_ADDR);
3051 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3052 tmp = RREG32(RADEON_AIC_HI_ADDR);
3053 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3054 tmp = RREG32(0x01E4);
3055 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3056 return 0;
3057}
c93bb85b 3058
0242f74d
AD		 3059static struct drm_info_list r100_debugfs_rbbm_list[] = {
3060 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3061};
c93bb85b 3062
0242f74d
AD		 3063static struct drm_info_list r100_debugfs_cp_list[] = {
3064 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3065 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3066};
c93bb85b 3067
0242f74d
AD		 3068static struct drm_info_list r100_debugfs_mc_info_list[] = {
3069 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3070};
3071#endif
c93bb85b 3072
0242f74d
AD		 3073int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3074{
3075#if defined(CONFIG_DEBUG_FS)
3076 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3077#else
3078 return 0;
3079#endif
3080}
c93bb85b 3081
0242f74d
AD		 3082int r100_debugfs_cp_init(struct radeon_device *rdev)
3083{
3084#if defined(CONFIG_DEBUG_FS)
3085 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3086#else
3087 return 0;
3088#endif
3089}
c93bb85b 3090
0242f74d
AD		 3091int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3092{
3093#if defined(CONFIG_DEBUG_FS)
3094 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3095#else
3096 return 0;
3097#endif
3098}
c93bb85b 3099
0242f74d
AD		 3100int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3101 uint32_t tiling_flags, uint32_t pitch,
3102 uint32_t offset, uint32_t obj_size)
3103{
3104 int surf_index = reg * 16;
3105 int flags = 0;
c93bb85b 3106
0242f74d
AD		 3107 if (rdev->family <= CHIP_RS200) {
3108 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3109 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3110 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3111 if (tiling_flags & RADEON_TILING_MACRO)
3112 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3113 } else if (rdev->family <= CHIP_RV280) {
3114 if (tiling_flags & (RADEON_TILING_MACRO))
3115 flags |= R200_SURF_TILE_COLOR_MACRO;
3116 if (tiling_flags & RADEON_TILING_MICRO)
3117 flags |= R200_SURF_TILE_COLOR_MICRO;
3118 } else {
3119 if (tiling_flags & RADEON_TILING_MACRO)
3120 flags |= R300_SURF_TILE_MACRO;
3121 if (tiling_flags & RADEON_TILING_MICRO)
3122 flags |= R300_SURF_TILE_MICRO;
3123 }
c93bb85b 3124
0242f74d
AD		 3125 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3126 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3127 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3128 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3129
3130 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3131 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3132 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3133 if (ASIC_IS_RN50(rdev))
3134 pitch /= 16;
c93bb85b
JG		 3135 }
3136
0242f74d
AD		 3137 /* r100/r200 divide by 16 */
3138 if (rdev->family < CHIP_R300)
3139 flags |= pitch / 16;
3140 else
3141 flags |= pitch / 8;
c93bb85b 3142
c93bb85b 3143
0242f74d
AD		 3144 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3145 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3146 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3147 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3148 return 0;
3149}
c93bb85b 3150
0242f74d
AD		 3151void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3152{
3153 int surf_index = reg * 16;
3154 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3155}
c93bb85b 3156
0242f74d
AD		 3157void r100_bandwidth_update(struct radeon_device *rdev)
3158{
3159 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3160 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3161 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3162 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3163 fixed20_12 memtcas_ff[8] = {
3164 dfixed_init(1),
3165 dfixed_init(2),
3166 dfixed_init(3),
3167 dfixed_init(0),
3168 dfixed_init_half(1),
3169 dfixed_init_half(2),
3170 dfixed_init(0),
3171 };
3172 fixed20_12 memtcas_rs480_ff[8] = {
3173 dfixed_init(0),
3174 dfixed_init(1),
3175 dfixed_init(2),
3176 dfixed_init(3),
3177 dfixed_init(0),
3178 dfixed_init_half(1),
3179 dfixed_init_half(2),
3180 dfixed_init_half(3),
3181 };
3182 fixed20_12 memtcas2_ff[8] = {
3183 dfixed_init(0),
3184 dfixed_init(1),
3185 dfixed_init(2),
3186 dfixed_init(3),
3187 dfixed_init(4),
3188 dfixed_init(5),
3189 dfixed_init(6),
3190 dfixed_init(7),
3191 };
3192 fixed20_12 memtrbs[8] = {
3193 dfixed_init(1),
3194 dfixed_init_half(1),
3195 dfixed_init(2),
3196 dfixed_init_half(2),
3197 dfixed_init(3),
3198 dfixed_init_half(3),
3199 dfixed_init(4),
3200 dfixed_init_half(4)
3201 };
3202 fixed20_12 memtrbs_r4xx[8] = {
3203 dfixed_init(4),
3204 dfixed_init(5),
3205 dfixed_init(6),
3206 dfixed_init(7),
3207 dfixed_init(8),
3208 dfixed_init(9),
3209 dfixed_init(10),
3210 dfixed_init(11)
3211 };
3212 fixed20_12 min_mem_eff;
3213 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3214 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3215 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3216 disp_drain_rate2, read_return_rate;
3217 fixed20_12 time_disp1_drop_priority;
3218 int c;
3219 int cur_size = 16; /* in octawords */
3220 int critical_point = 0, critical_point2;
3221/* uint32_t read_return_rate, time_disp1_drop_priority; */
3222 int stop_req, max_stop_req;
3223 struct drm_display_mode *mode1 = NULL;
3224 struct drm_display_mode *mode2 = NULL;
3225 uint32_t pixel_bytes1 = 0;
3226 uint32_t pixel_bytes2 = 0;
c93bb85b 3227
0242f74d 3228 radeon_update_display_priority(rdev);
c93bb85b 3229
0242f74d
AD		 3230 if (rdev->mode_info.crtcs[0]->base.enabled) {
3231 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3232 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3233 }
3234 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3235 if (rdev->mode_info.crtcs[1]->base.enabled) {
3236 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3237 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3238 }
3239 }
c93bb85b 3240
0242f74d
AD		 3241 min_mem_eff.full = dfixed_const_8(0);
3242 /* get modes */
3243 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3244 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3245 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3246 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3247 /* check crtc enables */
3248 if (mode2)
3249 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3250 if (mode1)
3251 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3252 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3253 }
c93bb85b 3254
0242f74d
AD		 3255 /*
3256 * determine is there is enough bw for current mode
3257 */
3258 sclk_ff = rdev->pm.sclk;
3259 mclk_ff = rdev->pm.mclk;
c93bb85b 3260
0242f74d
AD		 3261 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3262 temp_ff.full = dfixed_const(temp);
3263 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b 3264
0242f74d
AD		 3265 pix_clk.full = 0;
3266 pix_clk2.full = 0;
3267 peak_disp_bw.full = 0;
3268 if (mode1) {
3269 temp_ff.full = dfixed_const(1000);
3270 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3271 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3272 temp_ff.full = dfixed_const(pixel_bytes1);
3273 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3274 }
3275 if (mode2) {
3276 temp_ff.full = dfixed_const(1000);
3277 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3278 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3279 temp_ff.full = dfixed_const(pixel_bytes2);
3280 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3281 }
c93bb85b 3282
0242f74d
AD		 3283 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3284 if (peak_disp_bw.full >= mem_bw.full) {
3285 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3286 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3287 }
c93bb85b 3288
0242f74d
AD		 3289 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3290 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3291 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3292 mem_trcd = ((temp >> 2) & 0x3) + 1;
3293 mem_trp = ((temp & 0x3)) + 1;
3294 mem_tras = ((temp & 0x70) >> 4) + 1;
3295 } else if (rdev->family == CHIP_R300 ||
3296 rdev->family == CHIP_R350) { /* r300, r350 */
3297 mem_trcd = (temp & 0x7) + 1;
3298 mem_trp = ((temp >> 8) & 0x7) + 1;
3299 mem_tras = ((temp >> 11) & 0xf) + 4;
3300 } else if (rdev->family == CHIP_RV350 ||
3301 rdev->family <= CHIP_RV380) {
3302 /* rv3x0 */
3303 mem_trcd = (temp & 0x7) + 3;
3304 mem_trp = ((temp >> 8) & 0x7) + 3;
3305 mem_tras = ((temp >> 11) & 0xf) + 6;
3306 } else if (rdev->family == CHIP_R420 ||
3307 rdev->family == CHIP_R423 ||
3308 rdev->family == CHIP_RV410) {
3309 /* r4xx */
3310 mem_trcd = (temp & 0xf) + 3;
3311 if (mem_trcd > 15)
3312 mem_trcd = 15;
3313 mem_trp = ((temp >> 8) & 0xf) + 3;
3314 if (mem_trp > 15)
3315 mem_trp = 15;
3316 mem_tras = ((temp >> 12) & 0x1f) + 6;
3317 if (mem_tras > 31)
3318 mem_tras = 31;
3319 } else { /* RV200, R200 */
3320 mem_trcd = (temp & 0x7) + 1;
3321 mem_trp = ((temp >> 8) & 0x7) + 1;
3322 mem_tras = ((temp >> 12) & 0xf) + 4;
3323 }
3324 /* convert to FF */
3325 trcd_ff.full = dfixed_const(mem_trcd);
3326 trp_ff.full = dfixed_const(mem_trp);
3327 tras_ff.full = dfixed_const(mem_tras);
c93bb85b 3328
0242f74d
AD		 3329 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3330 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3331 data = (temp & (7 << 20)) >> 20;
3332 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3333 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3334 tcas_ff = memtcas_rs480_ff[data];
3335 else
3336 tcas_ff = memtcas_ff[data];
3337 } else
3338 tcas_ff = memtcas2_ff[data];
c93bb85b 3339
0242f74d
AD		 3340 if (rdev->family == CHIP_RS400 ||
3341 rdev->family == CHIP_RS480) {
3342 /* extra cas latency stored in bits 23-25 0-4 clocks */
3343 data = (temp >> 23) & 0x7;
3344 if (data < 5)
3345 tcas_ff.full += dfixed_const(data);
c93bb85b 3346 }
551ebd83 3347
0242f74d
AD		 3348 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3349 /* on the R300, Tcas is included in Trbs.
3350 */
3351 temp = RREG32(RADEON_MEM_CNTL);
3352 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3353 if (data == 1) {
3354 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3355 temp = RREG32(R300_MC_IND_INDEX);
3356 temp &= ~R300_MC_IND_ADDR_MASK;
3357 temp |= R300_MC_READ_CNTL_CD_mcind;
3358 WREG32(R300_MC_IND_INDEX, temp);
3359 temp = RREG32(R300_MC_IND_DATA);
3360 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3361 } else {
3362 temp = RREG32(R300_MC_READ_CNTL_AB);
3363 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3364 }
3365 } else {
3366 temp = RREG32(R300_MC_READ_CNTL_AB);
3367 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3368 }
3369 if (rdev->family == CHIP_RV410 ||
3370 rdev->family == CHIP_R420 ||
3371 rdev->family == CHIP_R423)
3372 trbs_ff = memtrbs_r4xx[data];
3373 else
3374 trbs_ff = memtrbs[data];
3375 tcas_ff.full += trbs_ff.full;
3376 }
551ebd83 3377
0242f74d 3378 sclk_eff_ff.full = sclk_ff.full;
d785d78b 3379
0242f74d
AD		 3380 if (rdev->flags & RADEON_IS_AGP) {
3381 fixed20_12 agpmode_ff;
3382 agpmode_ff.full = dfixed_const(radeon_agpmode);
3383 temp_ff.full = dfixed_const_666(16);
3384 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3385 }
3386 /* TODO PCIE lanes may affect this - agpmode == 16?? */
d785d78b 3387
0242f74d
AD		 3388 if (ASIC_IS_R300(rdev)) {
3389 sclk_delay_ff.full = dfixed_const(250);
3390 } else {
3391 if ((rdev->family == CHIP_RV100) ||
3392 rdev->flags & RADEON_IS_IGP) {
3393 if (rdev->mc.vram_is_ddr)
3394 sclk_delay_ff.full = dfixed_const(41);
3395 else
3396 sclk_delay_ff.full = dfixed_const(33);
3397 } else {
3398 if (rdev->mc.vram_width == 128)
3399 sclk_delay_ff.full = dfixed_const(57);
3400 else
3401 sclk_delay_ff.full = dfixed_const(41);
3402 }
d785d78b
DA		 3403 }
3404
0242f74d 3405 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
d785d78b 3406
0242f74d
AD		 3407 if (rdev->mc.vram_is_ddr) {
3408 if (rdev->mc.vram_width == 32) {
3409 k1.full = dfixed_const(40);
3410 c = 3;
3411 } else {
3412 k1.full = dfixed_const(20);
3413 c = 1;
3414 }
3415 } else {
3416 k1.full = dfixed_const(40);
3417 c = 3;
3418 }
37cf6b03 3419
0242f74d
AD		 3420 temp_ff.full = dfixed_const(2);
3421 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3422 temp_ff.full = dfixed_const(c);
3423 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3424 temp_ff.full = dfixed_const(4);
3425 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3426 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3427 mc_latency_mclk.full += k1.full;
37cf6b03 3428
0242f74d
AD		 3429 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3430 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
37cf6b03 3431
0242f74d
AD		 3432 /*
3433 HW cursor time assuming worst case of full size colour cursor.
3434 */
3435 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3436 temp_ff.full += trcd_ff.full;
3437 if (temp_ff.full < tras_ff.full)
3438 temp_ff.full = tras_ff.full;
3439 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
37cf6b03 3440
0242f74d
AD		 3441 temp_ff.full = dfixed_const(cur_size);
3442 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3443 /*
3444 Find the total latency for the display data.
3445 */
3446 disp_latency_overhead.full = dfixed_const(8);
3447 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3448 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3449 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
37cf6b03 3450
0242f74d
AD		 3451 if (mc_latency_mclk.full > mc_latency_sclk.full)
3452 disp_latency.full = mc_latency_mclk.full;
3453 else
3454 disp_latency.full = mc_latency_sclk.full;
551ebd83 3455
0242f74d
AD		 3456 /* setup Max GRPH_STOP_REQ default value */
3457 if (ASIC_IS_RV100(rdev))
3458 max_stop_req = 0x5c;
3459 else
3460 max_stop_req = 0x7c;
d785d78b 3461
0242f74d
AD		 3462 if (mode1) {
3463 /* CRTC1
3464 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3465 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3466 */
3467 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
d785d78b 3468
0242f74d
AD		 3469 if (stop_req > max_stop_req)
3470 stop_req = max_stop_req;
551ebd83 3471
0242f74d
AD		 3472 /*
3473 Find the drain rate of the display buffer.
3474 */
3475 temp_ff.full = dfixed_const((16/pixel_bytes1));
3476 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
551ebd83 3477
0242f74d
AD		 3478 /*
3479 Find the critical point of the display buffer.
3480 */
3481 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3482 crit_point_ff.full += dfixed_const_half(0);
a41ceb1c 3483
0242f74d
AD		 3484 critical_point = dfixed_trunc(crit_point_ff);
3485
3486 if (rdev->disp_priority == 2) {
3487 critical_point = 0;
551ebd83 3488 }
40b4a759 3489
0242f74d
AD		 3490 /*
3491 The critical point should never be above max_stop_req-4. Setting
3492 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3493 */
3494 if (max_stop_req - critical_point < 4)
3495 critical_point = 0;
3496
3497 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3498 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3499 critical_point = 0x10;
551ebd83 3500 }
0242f74d
AD		 3501
3502 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3503 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3504 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3505 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3506 if ((rdev->family == CHIP_R350) &&
3507 (stop_req > 0x15)) {
3508 stop_req -= 0x10;
551ebd83 3509 }
0242f74d
AD		 3510 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3511 temp |= RADEON_GRPH_BUFFER_SIZE;
3512 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3513 RADEON_GRPH_CRITICAL_AT_SOF |
3514 RADEON_GRPH_STOP_CNTL);
3515 /*
3516 Write the result into the register.
3517 */
3518 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3519 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
40b4a759 3520
0242f74d
AD		 3521#if 0
3522 if ((rdev->family == CHIP_RS400) ||
3523 (rdev->family == CHIP_RS480)) {
3524 /* attempt to program RS400 disp regs correctly ??? */
3525 temp = RREG32(RS400_DISP1_REG_CNTL);
3526 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3527 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3528 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3529 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3530 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3531 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3532 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3533 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3534 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3535 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3536 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
fff1ce4d 3537 }
0242f74d 3538#endif
fff1ce4d 3539
0242f74d
AD		 3540 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3541 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3542 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
cae94b0a 3543 }
0242f74d
AD		 3544
3545 if (mode2) {
3546 u32 grph2_cntl;
3547 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3548
3549 if (stop_req > max_stop_req)
3550 stop_req = max_stop_req;
3551
3552 /*
3553 Find the drain rate of the display buffer.
3554 */
3555 temp_ff.full = dfixed_const((16/pixel_bytes2));
3556 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3557
3558 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3559 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3560 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3561 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3562 if ((rdev->family == CHIP_R350) &&
3563 (stop_req > 0x15)) {
3564 stop_req -= 0x10;
551ebd83 3565 }
0242f74d
AD		 3566 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3567 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3568 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3569 RADEON_GRPH_CRITICAL_AT_SOF |
3570 RADEON_GRPH_STOP_CNTL);
3571
3572 if ((rdev->family == CHIP_RS100) ||
3573 (rdev->family == CHIP_RS200))
3574 critical_point2 = 0;
3575 else {
3576 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3577 temp_ff.full = dfixed_const(temp);
3578 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3579 if (sclk_ff.full < temp_ff.full)
3580 temp_ff.full = sclk_ff.full;
3581
3582 read_return_rate.full = temp_ff.full;
3583
3584 if (mode1) {
3585 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3586 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3587 } else {
3588 time_disp1_drop_priority.full = 0;
551ebd83 3589 }
0242f74d
AD		 3590 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3591 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3592 crit_point_ff.full += dfixed_const_half(0);
3593
3594 critical_point2 = dfixed_trunc(crit_point_ff);
3595
3596 if (rdev->disp_priority == 2) {
3597 critical_point2 = 0;
551ebd83 3598 }
40b4a759 3599
0242f74d
AD		 3600 if (max_stop_req - critical_point2 < 4)
3601 critical_point2 = 0;
551ebd83 3602
0242f74d 3603 }
551ebd83 3604
0242f74d
AD		 3605 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3606 /* some R300 cards have problem with this set to 0 */
3607 critical_point2 = 0x10;
3608 }
40b4a759 3609
0242f74d
AD		 3610 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3611 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
551ebd83 3612
0242f74d
AD		 3613 if ((rdev->family == CHIP_RS400) ||
3614 (rdev->family == CHIP_RS480)) {
3615#if 0
3616 /* attempt to program RS400 disp2 regs correctly ??? */
3617 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3618 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3619 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3620 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3621 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3622 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3623 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3624 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3625 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3626 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3627 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3628 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3629#endif
3630 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3631 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3632 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3633 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
551ebd83 3634 }
0242f74d
AD		 3635
3636 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3637 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
551ebd83
DA		 3638 }
3639}
3ce0a23d 3640
e32eb50d 3641int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3642{
3643 uint32_t scratch;
3644 uint32_t tmp = 0;
3645 unsigned i;
3646 int r;
3647
3648 r = radeon_scratch_get(rdev, &scratch);
3649 if (r) {
3650 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3651 return r;
3652 }
3653 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3654 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3655 if (r) {
3656 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3657 radeon_scratch_free(rdev, scratch);
3658 return r;
3659 }
e32eb50d
CK		 3660 radeon_ring_write(ring, PACKET0(scratch, 0));
3661 radeon_ring_write(ring, 0xDEADBEEF);
3662 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 3663 for (i = 0; i < rdev->usec_timeout; i++) {
3664 tmp = RREG32(scratch);
3665 if (tmp == 0xDEADBEEF) {
3666 break;
3667 }
3668 DRM_UDELAY(1);
3669 }
3670 if (i < rdev->usec_timeout) {
3671 DRM_INFO("ring test succeeded in %d usecs\n", i);
3672 } else {
369d7ec1 3673 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3674 scratch, tmp);
3675 r = -EINVAL;
3676 }
3677 radeon_scratch_free(rdev, scratch);
3678 return r;
3679}
3680
3681void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3682{
e32eb50d 3683 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3684
c7eff978
AD		 3685 if (ring->rptr_save_reg) {
3686 u32 next_rptr = ring->wptr + 2 + 3;
3687 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3688 radeon_ring_write(ring, next_rptr);
3689 }
3690
e32eb50d
CK		 3691 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3692 radeon_ring_write(ring, ib->gpu_addr);
3693 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3694}
3695
f712812e 3696int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3697{
f2e39221 3698 struct radeon_ib ib;
3ce0a23d
JG		 3699 uint32_t scratch;
3700 uint32_t tmp = 0;
3701 unsigned i;
3702 int r;
3703
3704 r = radeon_scratch_get(rdev, &scratch);
3705 if (r) {
3706 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3707 return r;
3708 }
3709 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3710 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3ce0a23d 3711 if (r) {
af026c5b
MD		 3712 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3713 goto free_scratch;
3ce0a23d 3714 }
f2e39221
JG		 3715 ib.ptr[0] = PACKET0(scratch, 0);
3716 ib.ptr[1] = 0xDEADBEEF;
3717 ib.ptr[2] = PACKET2(0);
3718 ib.ptr[3] = PACKET2(0);
3719 ib.ptr[4] = PACKET2(0);
3720 ib.ptr[5] = PACKET2(0);
3721 ib.ptr[6] = PACKET2(0);
3722 ib.ptr[7] = PACKET2(0);
3723 ib.length_dw = 8;
4ef72566 3724 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d 3725 if (r) {
af026c5b
MD		 3726 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3727 goto free_ib;
3ce0a23d 3728 }
f2e39221 3729 r = radeon_fence_wait(ib.fence, false);
3ce0a23d 3730 if (r) {
af026c5b
MD		 3731 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3732 goto free_ib;
3ce0a23d
JG		 3733 }
3734 for (i = 0; i < rdev->usec_timeout; i++) {
3735 tmp = RREG32(scratch);
3736 if (tmp == 0xDEADBEEF) {
3737 break;
3738 }
3739 DRM_UDELAY(1);
3740 }
3741 if (i < rdev->usec_timeout) {
3742 DRM_INFO("ib test succeeded in %u usecs\n", i);
3743 } else {
62f288cf 3744 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3745 scratch, tmp);
3746 r = -EINVAL;
3747 }
af026c5b 3748free_ib:
3ce0a23d 3749 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3750free_scratch:
3751 radeon_scratch_free(rdev, scratch);
3ce0a23d
JG		 3752 return r;
3753}
9f022ddf 3754
9f022ddf
JG		 3755void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3756{
3757 /* Shutdown CP we shouldn't need to do that but better be safe than
3758 * sorry
3759 */
e32eb50d 3760 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3761 WREG32(R_000740_CP_CSQ_CNTL, 0);
3762
3763 /* Save few CRTC registers */
ca6ffc64 3764 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3765 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3766 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3767 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3768 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3769 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3770 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3771 }
3772
3773 /* Disable VGA aperture access */
ca6ffc64 3774 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3775 /* Disable cursor, overlay, crtc */
3776 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3777 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3778 S_000054_CRTC_DISPLAY_DIS(1));
3779 WREG32(R_000050_CRTC_GEN_CNTL,
3780 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3781 S_000050_CRTC_DISP_REQ_EN_B(1));
3782 WREG32(R_000420_OV0_SCALE_CNTL,
3783 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3784 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3785 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3786 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3787 S_000360_CUR2_LOCK(1));
3788 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3789 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3790 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3791 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3792 WREG32(R_000360_CUR2_OFFSET,
3793 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3794 }
3795}
3796
3797void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3798{
3799 /* Update base address for crtc */
d594e46a 3800 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3801 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3802 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3803 }
3804 /* Restore CRTC registers */
ca6ffc64 3805 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3806 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3807 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3808 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3809 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3810 }
3811}
ca6ffc64
JG		 3812
3813void r100_vga_render_disable(struct radeon_device *rdev)
3814{
d4550907 3815 u32 tmp;
ca6ffc64 3816
d4550907 3817 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3818 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3819}
d4550907
JG		 3820
3821static void r100_debugfs(struct radeon_device *rdev)
3822{
3823 int r;
3824
3825 r = r100_debugfs_mc_info_init(rdev);
3826 if (r)
3827 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3828}
3829
3830static void r100_mc_program(struct radeon_device *rdev)
3831{
3832 struct r100_mc_save save;
3833
3834 /* Stops all mc clients */
3835 r100_mc_stop(rdev, &save);
3836 if (rdev->flags & RADEON_IS_AGP) {
3837 WREG32(R_00014C_MC_AGP_LOCATION,
3838 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3839 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3840 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3841 if (rdev->family > CHIP_RV200)
3842 WREG32(R_00015C_AGP_BASE_2,
3843 upper_32_bits(rdev->mc.agp_base) & 0xff);
3844 } else {
3845 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3846 WREG32(R_000170_AGP_BASE, 0);
3847 if (rdev->family > CHIP_RV200)
3848 WREG32(R_00015C_AGP_BASE_2, 0);
3849 }
3850 /* Wait for mc idle */
3851 if (r100_mc_wait_for_idle(rdev))
3852 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3853 /* Program MC, should be a 32bits limited address space */
3854 WREG32(R_000148_MC_FB_LOCATION,
3855 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3856 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3857 r100_mc_resume(rdev, &save);
3858}
3859
1109ca09 3860static void r100_clock_startup(struct radeon_device *rdev)
d4550907
JG		 3861{
3862 u32 tmp;
3863
3864 if (radeon_dynclks != -1 && radeon_dynclks)
3865 radeon_legacy_set_clock_gating(rdev, 1);
3866 /* We need to force on some of the block */
3867 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3868 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3869 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3870 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3871 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3872}
3873
3874static int r100_startup(struct radeon_device *rdev)
3875{
3876 int r;
3877
92cde00c
AD		 3878 /* set common regs */
3879 r100_set_common_regs(rdev);
3880 /* program mc */
d4550907
JG		 3881 r100_mc_program(rdev);
3882 /* Resume clock */
3883 r100_clock_startup(rdev);
d4550907
JG		 3884 /* Initialize GART (initialize after TTM so we can allocate
3885 * memory through TTM but finalize after TTM) */
17e15b0c 3886 r100_enable_bm(rdev);
d4550907
JG		 3887 if (rdev->flags & RADEON_IS_PCI) {
3888 r = r100_pci_gart_enable(rdev);
3889 if (r)
3890 return r;
3891 }
724c80e1
AD		 3892
3893 /* allocate wb buffer */
3894 r = radeon_wb_init(rdev);
3895 if (r)
3896 return r;
3897
30eb77f4
JG		 3898 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3899 if (r) {
3900 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3901 return r;
3902 }
3903
d4550907 3904 /* Enable IRQ */
d4550907 3905 r100_irq_set(rdev);
cafe6609 3906 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3907 /* 1M ring buffer */
3908 r = r100_cp_init(rdev, 1024 * 1024);
3909 if (r) {
ec4f2ac4 3910 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3911 return r;
3912 }
b15ba512 3913
2898c348
CK		 3914 r = radeon_ib_pool_init(rdev);
3915 if (r) {
3916 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3917 return r;
2898c348 3918 }
b15ba512 3919
d4550907
JG		 3920 return 0;
3921}
3922
3923int r100_resume(struct radeon_device *rdev)
3924{
6b7746e8
JG		 3925 int r;
3926
d4550907
JG		 3927 /* Make sur GART are not working */
3928 if (rdev->flags & RADEON_IS_PCI)
3929 r100_pci_gart_disable(rdev);
3930 /* Resume clock before doing reset */
3931 r100_clock_startup(rdev);
3932 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3933 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3934 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3935 RREG32(R_000E40_RBBM_STATUS),
3936 RREG32(R_0007C0_CP_STAT));
3937 }
3938 /* post */
3939 radeon_combios_asic_init(rdev->ddev);
3940 /* Resume clock after posting */
3941 r100_clock_startup(rdev);
550e2d92
DA		 3942 /* Initialize surface registers */
3943 radeon_surface_init(rdev);
b15ba512
JG		 3944
3945 rdev->accel_working = true;
6b7746e8
JG		 3946 r = r100_startup(rdev);
3947 if (r) {
3948 rdev->accel_working = false;
3949 }
3950 return r;
d4550907
JG		 3951}
3952
3953int r100_suspend(struct radeon_device *rdev)
3954{
3955 r100_cp_disable(rdev);
724c80e1 3956 radeon_wb_disable(rdev);
d4550907
JG		 3957 r100_irq_disable(rdev);
3958 if (rdev->flags & RADEON_IS_PCI)
3959 r100_pci_gart_disable(rdev);
3960 return 0;
3961}
3962
3963void r100_fini(struct radeon_device *rdev)
3964{
d4550907 3965 r100_cp_fini(rdev);
724c80e1 3966 radeon_wb_fini(rdev);
2898c348 3967 radeon_ib_pool_fini(rdev);
d4550907
JG		 3968 radeon_gem_fini(rdev);
3969 if (rdev->flags & RADEON_IS_PCI)
3970 r100_pci_gart_fini(rdev);
d0269ed8 3971 radeon_agp_fini(rdev);
d4550907
JG		 3972 radeon_irq_kms_fini(rdev);
3973 radeon_fence_driver_fini(rdev);
4c788679 3974 radeon_bo_fini(rdev);
d4550907
JG		 3975 radeon_atombios_fini(rdev);
3976 kfree(rdev->bios);
3977 rdev->bios = NULL;
3978}
3979
4c712e6c
DA		 3980/*
3981 * Due to how kexec works, it can leave the hw fully initialised when it
3982 * boots the new kernel. However doing our init sequence with the CP and
3983 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3984 * do some quick sanity checks and restore sane values to avoid this
3985 * problem.
3986 */
3987void r100_restore_sanity(struct radeon_device *rdev)
3988{
3989 u32 tmp;
3990
3991 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3992 if (tmp) {
3993 WREG32(RADEON_CP_CSQ_CNTL, 0);
3994 }
3995 tmp = RREG32(RADEON_CP_RB_CNTL);
3996 if (tmp) {
3997 WREG32(RADEON_CP_RB_CNTL, 0);
3998 }
3999 tmp = RREG32(RADEON_SCRATCH_UMSK);
4000 if (tmp) {
4001 WREG32(RADEON_SCRATCH_UMSK, 0);
4002 }
4003}
4004
d4550907
JG		 4005int r100_init(struct radeon_device *rdev)
4006{
4007 int r;
4008
d4550907
JG		 4009 /* Register debugfs file specific to this group of asics */
4010 r100_debugfs(rdev);
4011 /* Disable VGA */
4012 r100_vga_render_disable(rdev);
4013 /* Initialize scratch registers */
4014 radeon_scratch_init(rdev);
4015 /* Initialize surface registers */
4016 radeon_surface_init(rdev);
4c712e6c
DA		 4017 /* sanity check some register to avoid hangs like after kexec */
4018 r100_restore_sanity(rdev);
d4550907
JG		 4019 /* TODO: disable VGA need to use VGA request */
4020 /* BIOS*/
4021 if (!radeon_get_bios(rdev)) {
4022 if (ASIC_IS_AVIVO(rdev))
4023 return -EINVAL;
4024 }
4025 if (rdev->is_atom_bios) {
4026 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4027 return -EINVAL;
4028 } else {
4029 r = radeon_combios_init(rdev);
4030 if (r)
4031 return r;
4032 }
4033 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4034 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4035 dev_warn(rdev->dev,
4036 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4037 RREG32(R_000E40_RBBM_STATUS),
4038 RREG32(R_0007C0_CP_STAT));
4039 }
4040 /* check if cards are posted or not */
72542d77
DA		 4041 if (radeon_boot_test_post_card(rdev) == false)
4042 return -EINVAL;
d4550907
JG		 4043 /* Set asic errata */
4044 r100_errata(rdev);
4045 /* Initialize clocks */
4046 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4047 /* initialize AGP */
4048 if (rdev->flags & RADEON_IS_AGP) {
4049 r = radeon_agp_init(rdev);
4050 if (r) {
4051 radeon_agp_disable(rdev);
4052 }
4053 }
4054 /* initialize VRAM */
4055 r100_mc_init(rdev);
d4550907 4056 /* Fence driver */
30eb77f4 4057 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4058 if (r)
4059 return r;
4060 r = radeon_irq_kms_init(rdev);
4061 if (r)
4062 return r;
4063 /* Memory manager */
4c788679 4064 r = radeon_bo_init(rdev);
d4550907
JG		 4065 if (r)
4066 return r;
4067 if (rdev->flags & RADEON_IS_PCI) {
4068 r = r100_pci_gart_init(rdev);
4069 if (r)
4070 return r;
4071 }
4072 r100_set_safe_registers(rdev);
b15ba512 4073
d4550907
JG		 4074 rdev->accel_working = true;
4075 r = r100_startup(rdev);
4076 if (r) {
4077 /* Somethings want wront with the accel init stop accel */
4078 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4079 r100_cp_fini(rdev);
724c80e1 4080 radeon_wb_fini(rdev);
2898c348 4081 radeon_ib_pool_fini(rdev);
655efd3d 4082 radeon_irq_kms_fini(rdev);
d4550907
JG		 4083 if (rdev->flags & RADEON_IS_PCI)
4084 r100_pci_gart_fini(rdev);
d4550907
JG		 4085 rdev->accel_working = false;
4086 }
4087 return 0;
4088}
6fcbef7a 4089
2ef9bdfe
DV		 4090uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4091 bool always_indirect)
6fcbef7a 4092{
2ef9bdfe 4093 if (reg < rdev->rmmio_size && !always_indirect)
6fcbef7a
AK		 4094 return readl(((void __iomem *)rdev->rmmio) + reg);
4095 else {
2c385151
DV		 4096 unsigned long flags;
4097 uint32_t ret;
4098
4099 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
6fcbef7a 4100 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2c385151
DV		 4101 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4102 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4103
4104 return ret;
6fcbef7a
AK		 4105 }
4106}
4107
2ef9bdfe
DV		 4108void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4109 bool always_indirect)
6fcbef7a 4110{
2ef9bdfe 4111 if (reg < rdev->rmmio_size && !always_indirect)
6fcbef7a
AK		 4112 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4113 else {
2c385151
DV		 4114 unsigned long flags;
4115
4116 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
6fcbef7a
AK		 4117 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4118 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2c385151 4119 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
6fcbef7a
AK		 4120 }
4121}
4122
4123u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4124{
4125 if (reg < rdev->rio_mem_size)
4126 return ioread32(rdev->rio_mem + reg);
4127 else {
4128 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4129 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4130 }
4131}
4132
4133void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4134{
4135 if (reg < rdev->rio_mem_size)
4136 iowrite32(v, rdev->rio_mem + reg);
4137 else {
4138 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4139 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4140 }
4141}
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