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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7
DH		 30#include <drm/drmP.h>
31#include <drm/radeon_drm.h>
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "r100d.h"
d4550907
JG		 36#include "rs100d.h"
37#include "rv200d.h"
38#include "rv250d.h"
49e02b73 39#include "atom.h"
3ce0a23d 40
70967ab9 41#include <linux/firmware.h>
e0cd3608 42#include <linux/module.h>
70967ab9 43
551ebd83
DA		 44#include "r100_reg_safe.h"
45#include "rn50_reg_safe.h"
46
70967ab9
BH		 47/* Firmware Names */
48#define FIRMWARE_R100 "radeon/R100_cp.bin"
49#define FIRMWARE_R200 "radeon/R200_cp.bin"
50#define FIRMWARE_R300 "radeon/R300_cp.bin"
51#define FIRMWARE_R420 "radeon/R420_cp.bin"
52#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54#define FIRMWARE_R520 "radeon/R520_cp.bin"
55
56MODULE_FIRMWARE(FIRMWARE_R100);
57MODULE_FIRMWARE(FIRMWARE_R200);
58MODULE_FIRMWARE(FIRMWARE_R300);
59MODULE_FIRMWARE(FIRMWARE_R420);
60MODULE_FIRMWARE(FIRMWARE_RS690);
61MODULE_FIRMWARE(FIRMWARE_RS600);
62MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 63
551ebd83
DA		 64#include "r100_track.h"
65
48ef779f
AD		 66/* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
69 */
70
2b48b968
AD		 71static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
72{
73 if (crtc == 0) {
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
75 return true;
76 else
77 return false;
78 } else {
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
80 return true;
81 else
82 return false;
83 }
84}
85
86static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
87{
88 u32 vline1, vline2;
89
90 if (crtc == 0) {
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 } else {
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 }
97 if (vline1 != vline2)
98 return true;
99 else
100 return false;
101}
102
48ef779f
AD		 103/**
104 * r100_wait_for_vblank - vblank wait asic callback.
105 *
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
108 *
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
110 */
3ae19b75
AD		 111void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
112{
2b48b968 113 unsigned i = 0;
3ae19b75 114
94f768fd
AD		 115 if (crtc >= rdev->num_crtc)
116 return;
117
118 if (crtc == 0) {
2b48b968
AD		 119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
120 return;
3ae19b75 121 } else {
2b48b968
AD		 122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
123 return;
124 }
125
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
128 */
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
132 break;
133 }
134 }
135
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
139 break;
3ae19b75
AD		 140 }
141 }
142}
143
48ef779f
AD		 144/**
145 * r100_page_flip - pageflip callback.
146 *
147 * @rdev: radeon_device pointer
148 * @crtc_id: crtc to cleanup pageflip on
149 * @crtc_base: new address of the crtc (GPU MC address)
150 *
151 * Does the actual pageflip (r1xx-r4xx).
152 * During vblank we take the crtc lock and wait for the update_pending
153 * bit to go high, when it does, we release the lock, and allow the
154 * double buffered update to take place.
48ef779f 155 */
157fa14d 156void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
6f34be50
AD		 157{
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 160 int i;
6f34be50
AD		 161
162 /* Lock the graphics update lock */
163 /* update the scanout addresses */
164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
165
acb32506 166 /* Wait for update_pending to go high. */
f6496479
AD		 167 for (i = 0; i < rdev->usec_timeout; i++) {
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
169 break;
170 udelay(1);
171 }
acb32506 172 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 173
174 /* Unlock the lock, so double-buffering can take place inside vblank */
175 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
177
157fa14d
CK		 178}
179
180/**
181 * r100_page_flip_pending - check if page flip is still pending
182 *
183 * @rdev: radeon_device pointer
184 * @crtc_id: crtc to check
185 *
186 * Check if the last pagefilp is still pending (r1xx-r4xx).
187 * Returns the current update pending status.
188 */
189bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
190{
191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
192
6f34be50 193 /* Return current update_pending status: */
157fa14d
CK		 194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
195 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
6f34be50
AD		 196}
197
48ef779f
AD		 198/**
199 * r100_pm_get_dynpm_state - look up dynpm power state callback.
200 *
201 * @rdev: radeon_device pointer
202 *
203 * Look up the optimal power state based on the
204 * current state of the GPU (r1xx-r5xx).
205 * Used for dynpm only.
206 */
ce8f5370 207void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 208{
209 int i;
ce8f5370
AD		 210 rdev->pm.dynpm_can_upclock = true;
211 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 212
ce8f5370
AD		 213 switch (rdev->pm.dynpm_planned_action) {
214 case DYNPM_ACTION_MINIMUM:
a48b9b4e 215 rdev->pm.requested_power_state_index = 0;
ce8f5370 216 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 217 break;
ce8f5370 218 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 219 if (rdev->pm.current_power_state_index == 0) {
220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 221 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 222 } else {
223 if (rdev->pm.active_crtc_count > 1) {
224 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 226 continue;
227 else if (i >= rdev->pm.current_power_state_index) {
228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
229 break;
230 } else {
231 rdev->pm.requested_power_state_index = i;
232 break;
233 }
234 }
235 } else
236 rdev->pm.requested_power_state_index =
237 rdev->pm.current_power_state_index - 1;
238 }
d7311171
AD		 239 /* don't use the power state if crtcs are active and no display flag is set */
240 if ((rdev->pm.active_crtc_count > 0) &&
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
242 RADEON_PM_MODE_NO_DISPLAY)) {
243 rdev->pm.requested_power_state_index++;
244 }
a48b9b4e 245 break;
ce8f5370 246 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 249 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 250 } else {
251 if (rdev->pm.active_crtc_count > 1) {
252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 254 continue;
255 else if (i <= rdev->pm.current_power_state_index) {
256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
257 break;
258 } else {
259 rdev->pm.requested_power_state_index = i;
260 break;
261 }
262 }
263 } else
264 rdev->pm.requested_power_state_index =
265 rdev->pm.current_power_state_index + 1;
266 }
267 break;
ce8f5370 268 case DYNPM_ACTION_DEFAULT:
58e21dff 269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 270 rdev->pm.dynpm_can_upclock = false;
58e21dff 271 break;
ce8f5370 272 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 273 default:
274 DRM_ERROR("Requested mode for not defined action\n");
275 return;
276 }
277 /* only one clock mode per power state */
278 rdev->pm.requested_clock_mode_index = 0;
279
d9fdaafb 280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 281 rdev->pm.power_state[rdev->pm.requested_power_state_index].
282 clock_info[rdev->pm.requested_clock_mode_index].sclk,
283 rdev->pm.power_state[rdev->pm.requested_power_state_index].
284 clock_info[rdev->pm.requested_clock_mode_index].mclk,
285 rdev->pm.power_state[rdev->pm.requested_power_state_index].
286 pcie_lanes);
a48b9b4e
AD		 287}
288
48ef779f
AD		 289/**
290 * r100_pm_init_profile - Initialize power profiles callback.
291 *
292 * @rdev: radeon_device pointer
293 *
294 * Initialize the power states used in profile mode
295 * (r1xx-r3xx).
296 * Used for profile mode only.
297 */
ce8f5370
AD		 298void r100_pm_init_profile(struct radeon_device *rdev)
299{
300 /* default */
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
305 /* low sh */
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 310 /* mid sh */
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 315 /* high sh */
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
320 /* low mh */
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 325 /* mid mh */
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 330 /* high mh */
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 335}
336
48ef779f
AD		 337/**
338 * r100_pm_misc - set additional pm hw parameters callback.
339 *
340 * @rdev: radeon_device pointer
341 *
342 * Set non-clock parameters associated with a power state
343 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
344 */
49e02b73
AD		 345void r100_pm_misc(struct radeon_device *rdev)
346{
49e02b73
AD		 347 int requested_index = rdev->pm.requested_power_state_index;
348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
349 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
350 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
351
352 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
353 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
354 tmp = RREG32(voltage->gpio.reg);
355 if (voltage->active_high)
356 tmp |= voltage->gpio.mask;
357 else
358 tmp &= ~(voltage->gpio.mask);
359 WREG32(voltage->gpio.reg, tmp);
360 if (voltage->delay)
361 udelay(voltage->delay);
362 } else {
363 tmp = RREG32(voltage->gpio.reg);
364 if (voltage->active_high)
365 tmp &= ~voltage->gpio.mask;
366 else
367 tmp |= voltage->gpio.mask;
368 WREG32(voltage->gpio.reg, tmp);
369 if (voltage->delay)
370 udelay(voltage->delay);
371 }
372 }
373
374 sclk_cntl = RREG32_PLL(SCLK_CNTL);
375 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
376 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
377 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
378 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
379 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
380 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
381 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
382 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
383 else
384 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
385 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
386 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
387 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
388 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
389 } else
390 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
391
392 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
393 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
394 if (voltage->delay) {
395 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
396 switch (voltage->delay) {
397 case 33:
398 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
399 break;
400 case 66:
401 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
402 break;
403 case 99:
404 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
405 break;
406 case 132:
407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
408 break;
409 }
410 } else
411 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
412 } else
413 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
414
415 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
416 sclk_cntl &= ~FORCE_HDP;
417 else
418 sclk_cntl |= FORCE_HDP;
419
420 WREG32_PLL(SCLK_CNTL, sclk_cntl);
421 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
422 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
423
424 /* set pcie lanes */
425 if ((rdev->flags & RADEON_IS_PCIE) &&
426 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 427 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 428 (ps->pcie_lanes !=
429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
430 radeon_set_pcie_lanes(rdev,
431 ps->pcie_lanes);
d9fdaafb 432 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 433 }
49e02b73
AD		 434}
435
48ef779f
AD		 436/**
437 * r100_pm_prepare - pre-power state change callback.
438 *
439 * @rdev: radeon_device pointer
440 *
441 * Prepare for a power state change (r1xx-r4xx).
442 */
49e02b73
AD		 443void r100_pm_prepare(struct radeon_device *rdev)
444{
445 struct drm_device *ddev = rdev->ddev;
446 struct drm_crtc *crtc;
447 struct radeon_crtc *radeon_crtc;
448 u32 tmp;
449
450 /* disable any active CRTCs */
451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
452 radeon_crtc = to_radeon_crtc(crtc);
453 if (radeon_crtc->enabled) {
454 if (radeon_crtc->crtc_id) {
455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
456 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
458 } else {
459 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
460 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
461 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
462 }
463 }
464 }
465}
466
48ef779f
AD		 467/**
468 * r100_pm_finish - post-power state change callback.
469 *
470 * @rdev: radeon_device pointer
471 *
472 * Clean up after a power state change (r1xx-r4xx).
473 */
49e02b73
AD		 474void r100_pm_finish(struct radeon_device *rdev)
475{
476 struct drm_device *ddev = rdev->ddev;
477 struct drm_crtc *crtc;
478 struct radeon_crtc *radeon_crtc;
479 u32 tmp;
480
481 /* enable any active CRTCs */
482 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
483 radeon_crtc = to_radeon_crtc(crtc);
484 if (radeon_crtc->enabled) {
485 if (radeon_crtc->crtc_id) {
486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
487 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
488 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
489 } else {
490 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
491 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
492 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
493 }
494 }
495 }
496}
497
48ef779f
AD		 498/**
499 * r100_gui_idle - gui idle callback.
500 *
501 * @rdev: radeon_device pointer
502 *
503 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
504 * Returns true if idle, false if not.
505 */
def9ba9c
AD		 506bool r100_gui_idle(struct radeon_device *rdev)
507{
508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
509 return false;
510 else
511 return true;
512}
513
05a05c50 514/* hpd for digital panel detect/disconnect */
48ef779f
AD		 515/**
516 * r100_hpd_sense - hpd sense callback.
517 *
518 * @rdev: radeon_device pointer
519 * @hpd: hpd (hotplug detect) pin
520 *
521 * Checks if a digital monitor is connected (r1xx-r4xx).
522 * Returns true if connected, false if not connected.
523 */
05a05c50
AD		 524bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
525{
526 bool connected = false;
527
528 switch (hpd) {
529 case RADEON_HPD_1:
530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
531 connected = true;
532 break;
533 case RADEON_HPD_2:
534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
535 connected = true;
536 break;
537 default:
538 break;
539 }
540 return connected;
541}
542
48ef779f
AD		 543/**
544 * r100_hpd_set_polarity - hpd set polarity callback.
545 *
546 * @rdev: radeon_device pointer
547 * @hpd: hpd (hotplug detect) pin
548 *
549 * Set the polarity of the hpd pin (r1xx-r4xx).
550 */
05a05c50
AD		 551void r100_hpd_set_polarity(struct radeon_device *rdev,
552 enum radeon_hpd_id hpd)
553{
554 u32 tmp;
555 bool connected = r100_hpd_sense(rdev, hpd);
556
557 switch (hpd) {
558 case RADEON_HPD_1:
559 tmp = RREG32(RADEON_FP_GEN_CNTL);
560 if (connected)
561 tmp &= ~RADEON_FP_DETECT_INT_POL;
562 else
563 tmp |= RADEON_FP_DETECT_INT_POL;
564 WREG32(RADEON_FP_GEN_CNTL, tmp);
565 break;
566 case RADEON_HPD_2:
567 tmp = RREG32(RADEON_FP2_GEN_CNTL);
568 if (connected)
569 tmp &= ~RADEON_FP2_DETECT_INT_POL;
570 else
571 tmp |= RADEON_FP2_DETECT_INT_POL;
572 WREG32(RADEON_FP2_GEN_CNTL, tmp);
573 break;
574 default:
575 break;
576 }
577}
578
48ef779f
AD		 579/**
580 * r100_hpd_init - hpd setup callback.
581 *
582 * @rdev: radeon_device pointer
583 *
584 * Setup the hpd pins used by the card (r1xx-r4xx).
585 * Set the polarity, and enable the hpd interrupts.
586 */
05a05c50
AD		 587void r100_hpd_init(struct radeon_device *rdev)
588{
589 struct drm_device *dev = rdev->ddev;
590 struct drm_connector *connector;
fb98257a 591 unsigned enable = 0;
05a05c50
AD		 592
593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
594 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 595 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 596 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 597 }
fb98257a 598 radeon_irq_kms_enable_hpd(rdev, enable);
05a05c50
AD		 599}
600
48ef779f
AD		 601/**
602 * r100_hpd_fini - hpd tear down callback.
603 *
604 * @rdev: radeon_device pointer
605 *
606 * Tear down the hpd pins used by the card (r1xx-r4xx).
607 * Disable the hpd interrupts.
608 */
05a05c50
AD		 609void r100_hpd_fini(struct radeon_device *rdev)
610{
611 struct drm_device *dev = rdev->ddev;
612 struct drm_connector *connector;
fb98257a 613 unsigned disable = 0;
05a05c50
AD		 614
615 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
616 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 617 disable |= 1 << radeon_connector->hpd.hpd;
05a05c50 618 }
fb98257a 619 radeon_irq_kms_disable_hpd(rdev, disable);
05a05c50
AD		 620}
621
771fe6b9
JG		 622/*
623 * PCI GART
624 */
625void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
626{
627 /* TODO: can we do somethings here ? */
628 /* It seems hw only cache one entry so we should discard this
629 * entry otherwise if first GPU GART read hit this entry it
630 * could end up in wrong address. */
631}
632
4aac0473 633int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 634{
771fe6b9
JG		 635 int r;
636
c9a1be96 637 if (rdev->gart.ptr) {
fce7d61b 638 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 639 return 0;
640 }
771fe6b9
JG		 641 /* Initialize common gart structure */
642 r = radeon_gart_init(rdev);
4aac0473 643 if (r)
771fe6b9 644 return r;
4aac0473 645 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
c5b3b850 646 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
cb658906 647 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
c5b3b850 648 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
4aac0473
JG		 649 return radeon_gart_table_ram_alloc(rdev);
650}
651
652int r100_pci_gart_enable(struct radeon_device *rdev)
653{
654 uint32_t tmp;
655
771fe6b9
JG		 656 /* discard memory request outside of configured range */
657 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
658 WREG32(RADEON_AIC_CNTL, tmp);
659 /* set address range for PCI address translate */
d594e46a
JG		 660 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
661 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 662 /* set PCI GART page-table base address */
663 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
664 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
665 WREG32(RADEON_AIC_CNTL, tmp);
666 r100_pci_gart_tlb_flush(rdev);
43caf451 667 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
fcf4de5a
TV		 668 (unsigned)(rdev->mc.gtt_size >> 20),
669 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 670 rdev->gart.ready = true;
671 return 0;
672}
673
674void r100_pci_gart_disable(struct radeon_device *rdev)
675{
676 uint32_t tmp;
677
678 /* discard memory request outside of configured range */
679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
680 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
681 WREG32(RADEON_AIC_LO_ADDR, 0);
682 WREG32(RADEON_AIC_HI_ADDR, 0);
683}
684
cb658906
MD		 685uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
686{
687 return addr;
688}
689
7f90fc96 690void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
cb658906 691 uint64_t entry)
771fe6b9 692{
c9a1be96 693 u32 *gtt = rdev->gart.ptr;
cb658906 694 gtt[i] = cpu_to_le32(lower_32_bits(entry));
771fe6b9
JG		 695}
696
4aac0473 697void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 698{
f9274562 699 radeon_gart_fini(rdev);
4aac0473
JG		 700 r100_pci_gart_disable(rdev);
701 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 702}
703
7ed220d7
MD		 704int r100_irq_set(struct radeon_device *rdev)
705{
706 uint32_t tmp = 0;
707
003e69f9 708 if (!rdev->irq.installed) {
fce7d61b 709 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 710 WREG32(R_000040_GEN_INT_CNTL, 0);
711 return -EINVAL;
712 }
736fc37f 713 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7ed220d7
MD		 714 tmp |= RADEON_SW_INT_ENABLE;
715 }
6f34be50 716 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 717 atomic_read(&rdev->irq.pflip[0])) {
7ed220d7
MD		 718 tmp |= RADEON_CRTC_VBLANK_MASK;
719 }
6f34be50 720 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 721 atomic_read(&rdev->irq.pflip[1])) {
7ed220d7
MD		 722 tmp |= RADEON_CRTC2_VBLANK_MASK;
723 }
05a05c50
AD		 724 if (rdev->irq.hpd[0]) {
725 tmp |= RADEON_FP_DETECT_MASK;
726 }
727 if (rdev->irq.hpd[1]) {
728 tmp |= RADEON_FP2_DETECT_MASK;
729 }
7ed220d7
MD		 730 WREG32(RADEON_GEN_INT_CNTL, tmp);
731 return 0;
732}
733
9f022ddf
JG		 734void r100_irq_disable(struct radeon_device *rdev)
735{
736 u32 tmp;
737
738 WREG32(R_000040_GEN_INT_CNTL, 0);
739 /* Wait and acknowledge irq */
740 mdelay(1);
741 tmp = RREG32(R_000044_GEN_INT_STATUS);
742 WREG32(R_000044_GEN_INT_STATUS, tmp);
743}
744
cbdd4501 745static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 746{
747 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 748 uint32_t irq_mask = RADEON_SW_INT_TEST |
749 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
750 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 751
752 if (irqs) {
753 WREG32(RADEON_GEN_INT_STATUS, irqs);
754 }
755 return irqs & irq_mask;
756}
757
758int r100_irq_process(struct radeon_device *rdev)
759{
3e5cb98d 760 uint32_t status, msi_rearm;
d4877cf2 761 bool queue_hotplug = false;
7ed220d7
MD		 762
763 status = r100_irq_ack(rdev);
764 if (!status) {
765 return IRQ_NONE;
766 }
a513c184
JG		 767 if (rdev->shutdown) {
768 return IRQ_NONE;
769 }
7ed220d7
MD		 770 while (status) {
771 /* SW interrupt */
772 if (status & RADEON_SW_INT_TEST) {
7465280c 773 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7
MD		 774 }
775 /* Vertical blank interrupts */
776 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 777 if (rdev->irq.crtc_vblank_int[0]) {
778 drm_handle_vblank(rdev->ddev, 0);
779 rdev->pm.vblank_sync = true;
780 wake_up(&rdev->irq.vblank_queue);
781 }
736fc37f 782 if (atomic_read(&rdev->irq.pflip[0]))
1a0e7918 783 radeon_crtc_handle_vblank(rdev, 0);
7ed220d7
MD		 784 }
785 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 786 if (rdev->irq.crtc_vblank_int[1]) {
787 drm_handle_vblank(rdev->ddev, 1);
788 rdev->pm.vblank_sync = true;
789 wake_up(&rdev->irq.vblank_queue);
790 }
736fc37f 791 if (atomic_read(&rdev->irq.pflip[1]))
1a0e7918 792 radeon_crtc_handle_vblank(rdev, 1);
7ed220d7 793 }
05a05c50 794 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 795 queue_hotplug = true;
796 DRM_DEBUG("HPD1\n");
05a05c50
AD		 797 }
798 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 799 queue_hotplug = true;
800 DRM_DEBUG("HPD2\n");
05a05c50 801 }
7ed220d7
MD		 802 status = r100_irq_ack(rdev);
803 }
d4877cf2 804 if (queue_hotplug)
32c87fca 805 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 806 if (rdev->msi_enabled) {
807 switch (rdev->family) {
808 case CHIP_RS400:
809 case CHIP_RS480:
810 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
811 WREG32(RADEON_AIC_CNTL, msi_rearm);
812 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
813 break;
814 default:
b7f5b7de 815 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 816 break;
817 }
818 }
7ed220d7
MD		 819 return IRQ_HANDLED;
820}
821
822u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
823{
824 if (crtc == 0)
825 return RREG32(RADEON_CRTC_CRNT_FRAME);
826 else
827 return RREG32(RADEON_CRTC2_CRNT_FRAME);
828}
829
897eba82
MD		 830/**
831 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
832 * rdev: radeon device structure
833 * ring: ring buffer struct for emitting packets
834 */
835static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
836{
837 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
838 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
839 RADEON_HDP_READ_BUFFER_INVALIDATE);
840 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
841 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
842}
843
9e5b2af7
PN		 844/* Who ever call radeon_fence_emit should call ring_lock and ask
845 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 846void r100_fence_ring_emit(struct radeon_device *rdev,
847 struct radeon_fence *fence)
848{
e32eb50d 849 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 850
9e5b2af7
PN		 851 /* We have to make sure that caches are flushed before
852 * CPU might read something from VRAM. */
e32eb50d
CK		 853 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
854 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
855 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
856 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 857 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 858 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
859 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
72a9987e 860 r100_ring_hdp_flush(rdev, ring);
771fe6b9 861 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 862 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
863 radeon_ring_write(ring, fence->seq);
864 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
865 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 866}
867
1654b817 868bool r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 869 struct radeon_ring *ring,
15d3332f 870 struct radeon_semaphore *semaphore,
7b1f2485 871 bool emit_wait)
15d3332f
CK		 872{
873 /* Unused on older asics, since we don't have semaphores or multiple rings */
874 BUG();
1654b817 875 return false;
15d3332f
CK		 876}
877
57d20a43
CK		 878struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
879 uint64_t src_offset,
880 uint64_t dst_offset,
881 unsigned num_gpu_pages,
882 struct reservation_object *resv)
771fe6b9 883{
e32eb50d 884 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
57d20a43 885 struct radeon_fence *fence;
771fe6b9 886 uint32_t cur_pages;
003cefe0 887 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 888 uint32_t pitch;
889 uint32_t stride_pixels;
890 unsigned ndw;
891 int num_loops;
892 int r = 0;
893
894 /* radeon limited to 16k stride */
895 stride_bytes &= 0x3fff;
896 /* radeon pitch is /64 */
897 pitch = stride_bytes / 64;
898 stride_pixels = stride_bytes / 4;
003cefe0 899 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 900
901 /* Ask for enough room for blit + flush + fence */
902 ndw = 64 + (10 * num_loops);
e32eb50d 903 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 904 if (r) {
905 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
57d20a43 906 return ERR_PTR(-EINVAL);
771fe6b9 907 }
003cefe0
AD		 908 while (num_gpu_pages > 0) {
909 cur_pages = num_gpu_pages;
771fe6b9
JG		 910 if (cur_pages > 8191) {
911 cur_pages = 8191;
912 }
003cefe0 913 num_gpu_pages -= cur_pages;
771fe6b9
JG		 914
915 /* pages are in Y direction - height
916 page width in X direction - width */
e32eb50d
CK		 917 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
918 radeon_ring_write(ring,
771fe6b9
JG		 919 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
920 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
921 RADEON_GMC_SRC_CLIPPING |
922 RADEON_GMC_DST_CLIPPING |
923 RADEON_GMC_BRUSH_NONE |
924 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
925 RADEON_GMC_SRC_DATATYPE_COLOR |
926 RADEON_ROP3_S |
927 RADEON_DP_SRC_SOURCE_MEMORY |
928 RADEON_GMC_CLR_CMP_CNTL_DIS |
929 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 930 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
931 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
932 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
933 radeon_ring_write(ring, 0);
934 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
935 radeon_ring_write(ring, num_gpu_pages);
936 radeon_ring_write(ring, num_gpu_pages);
937 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
938 }
939 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
940 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
941 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
942 radeon_ring_write(ring,
771fe6b9
JG		 943 RADEON_WAIT_2D_IDLECLEAN |
944 RADEON_WAIT_HOST_IDLECLEAN |
945 RADEON_WAIT_DMA_GUI_IDLE);
57d20a43
CK		 946 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
947 if (r) {
948 radeon_ring_unlock_undo(rdev, ring);
949 return ERR_PTR(r);
771fe6b9 950 }
1538a9e0 951 radeon_ring_unlock_commit(rdev, ring, false);
57d20a43 952 return fence;
771fe6b9
JG		 953}
954
45600232
JG		 955static int r100_cp_wait_for_idle(struct radeon_device *rdev)
956{
957 unsigned i;
958 u32 tmp;
959
960 for (i = 0; i < rdev->usec_timeout; i++) {
961 tmp = RREG32(R_000E40_RBBM_STATUS);
962 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
963 return 0;
964 }
965 udelay(1);
966 }
967 return -1;
968}
969
f712812e 970void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9
JG		 971{
972 int r;
973
e32eb50d 974 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 975 if (r) {
976 return;
977 }
e32eb50d
CK		 978 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
979 radeon_ring_write(ring,
771fe6b9
JG		 980 RADEON_ISYNC_ANY2D_IDLE3D |
981 RADEON_ISYNC_ANY3D_IDLE2D |
982 RADEON_ISYNC_WAIT_IDLEGUI |
983 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1538a9e0 984 radeon_ring_unlock_commit(rdev, ring, false);
771fe6b9
JG		 985}
986
70967ab9
BH		 987
988/* Load the microcode for the CP */
989static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 990{
70967ab9
BH		 991 const char *fw_name = NULL;
992 int err;
771fe6b9 993
d9fdaafb 994 DRM_DEBUG_KMS("\n");
771fe6b9 995
771fe6b9
JG		 996 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
997 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
998 (rdev->family == CHIP_RS200)) {
999 DRM_INFO("Loading R100 Microcode\n");
70967ab9 1000 fw_name = FIRMWARE_R100;
771fe6b9
JG		 1001 } else if ((rdev->family == CHIP_R200) ||
1002 (rdev->family == CHIP_RV250) ||
1003 (rdev->family == CHIP_RV280) ||
1004 (rdev->family == CHIP_RS300)) {
1005 DRM_INFO("Loading R200 Microcode\n");
70967ab9 1006 fw_name = FIRMWARE_R200;
771fe6b9
JG		 1007 } else if ((rdev->family == CHIP_R300) ||
1008 (rdev->family == CHIP_R350) ||
1009 (rdev->family == CHIP_RV350) ||
1010 (rdev->family == CHIP_RV380) ||
1011 (rdev->family == CHIP_RS400) ||
1012 (rdev->family == CHIP_RS480)) {
1013 DRM_INFO("Loading R300 Microcode\n");
70967ab9 1014 fw_name = FIRMWARE_R300;
771fe6b9
JG		 1015 } else if ((rdev->family == CHIP_R420) ||
1016 (rdev->family == CHIP_R423) ||
1017 (rdev->family == CHIP_RV410)) {
1018 DRM_INFO("Loading R400 Microcode\n");
70967ab9 1019 fw_name = FIRMWARE_R420;
771fe6b9
JG		 1020 } else if ((rdev->family == CHIP_RS690) ||
1021 (rdev->family == CHIP_RS740)) {
1022 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1023 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1024 } else if (rdev->family == CHIP_RS600) {
1025 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1026 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1027 } else if ((rdev->family == CHIP_RV515) ||
1028 (rdev->family == CHIP_R520) ||
1029 (rdev->family == CHIP_RV530) ||
1030 (rdev->family == CHIP_R580) ||
1031 (rdev->family == CHIP_RV560) ||
1032 (rdev->family == CHIP_RV570)) {
1033 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1034 fw_name = FIRMWARE_R520;
1035 }
1036
0a168933 1037 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
70967ab9
BH		 1038 if (err) {
1039 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1040 fw_name);
3ce0a23d 1041 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1042 printk(KERN_ERR
1043 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1044 rdev->me_fw->size, fw_name);
70967ab9 1045 err = -EINVAL;
3ce0a23d
JG		 1046 release_firmware(rdev->me_fw);
1047 rdev->me_fw = NULL;
70967ab9
BH		 1048 }
1049 return err;
1050}
d4550907 1051
ea31bf69
AD		 1052u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1053 struct radeon_ring *ring)
1054{
1055 u32 rptr;
1056
1057 if (rdev->wb.enabled)
1058 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1059 else
1060 rptr = RREG32(RADEON_CP_RB_RPTR);
1061
1062 return rptr;
1063}
1064
1065u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1066 struct radeon_ring *ring)
1067{
1068 u32 wptr;
1069
1070 wptr = RREG32(RADEON_CP_RB_WPTR);
1071
1072 return wptr;
1073}
1074
1075void r100_gfx_set_wptr(struct radeon_device *rdev,
1076 struct radeon_ring *ring)
1077{
1078 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1079 (void)RREG32(RADEON_CP_RB_WPTR);
1080}
1081
70967ab9
BH		 1082static void r100_cp_load_microcode(struct radeon_device *rdev)
1083{
1084 const __be32 *fw_data;
1085 int i, size;
1086
1087 if (r100_gui_wait_for_idle(rdev)) {
1088 printk(KERN_WARNING "Failed to wait GUI idle while "
1089 "programming pipes. Bad things might happen.\n");
1090 }
1091
3ce0a23d
JG		 1092 if (rdev->me_fw) {
1093 size = rdev->me_fw->size / 4;
1094 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1095 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1096 for (i = 0; i < size; i += 2) {
1097 WREG32(RADEON_CP_ME_RAM_DATAH,
1098 be32_to_cpup(&fw_data[i]));
1099 WREG32(RADEON_CP_ME_RAM_DATAL,
1100 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1101 }
1102 }
1103}
1104
1105int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1106{
e32eb50d 1107 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1108 unsigned rb_bufsz;
1109 unsigned rb_blksz;
1110 unsigned max_fetch;
1111 unsigned pre_write_timer;
1112 unsigned pre_write_limit;
1113 unsigned indirect2_start;
1114 unsigned indirect1_start;
1115 uint32_t tmp;
1116 int r;
1117
1118 if (r100_debugfs_cp_init(rdev)) {
1119 DRM_ERROR("Failed to register debugfs file for CP !\n");
1120 }
3ce0a23d 1121 if (!rdev->me_fw) {
70967ab9
BH		 1122 r = r100_cp_init_microcode(rdev);
1123 if (r) {
1124 DRM_ERROR("Failed to load firmware!\n");
1125 return r;
1126 }
1127 }
1128
771fe6b9 1129 /* Align ring size */
b72a8925 1130 rb_bufsz = order_base_2(ring_size / 8);
771fe6b9
JG		 1131 ring_size = (1 << (rb_bufsz + 1)) * 4;
1132 r100_cp_load_microcode(rdev);
e32eb50d 1133 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
2e1e6dad 1134 RADEON_CP_PACKET2);
771fe6b9
JG		 1135 if (r) {
1136 return r;
1137 }
1138 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1139 * the rptr copy in system ram */
1140 rb_blksz = 9;
1141 /* cp will read 128bytes at a time (4 dwords) */
1142 max_fetch = 1;
e32eb50d 1143 ring->align_mask = 16 - 1;
771fe6b9
JG		 1144 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1145 pre_write_timer = 64;
1146 /* Force CP_RB_WPTR write if written more than one time before the
1147 * delay expire
1148 */
1149 pre_write_limit = 0;
1150 /* Setup the cp cache like this (cache size is 96 dwords) :
1151 * RING 0 to 15
1152 * INDIRECT1 16 to 79
1153 * INDIRECT2 80 to 95
1154 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1155 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1156 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1157 * Idea being that most of the gpu cmd will be through indirect1 buffer
1158 * so it gets the bigger cache.
1159 */
1160 indirect2_start = 80;
1161 indirect1_start = 16;
1162 /* cp setup */
1163 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1164 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1165 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1166 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1167#ifdef __BIG_ENDIAN
1168 tmp |= RADEON_BUF_SWAP_32BIT;
1169#endif
724c80e1 1170 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1171
771fe6b9 1172 /* Set ring address */
e32eb50d
CK		 1173 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1174 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1175 /* Force read & write ptr to 0 */
724c80e1 1176 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1177 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1178 ring->wptr = 0;
1179 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1180
1181 /* set the wb address whether it's enabled or not */
1182 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1183 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1184 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1185
1186 if (rdev->wb.enabled)
1187 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1188 else {
1189 tmp |= RADEON_RB_NO_UPDATE;
1190 WREG32(R_000770_SCRATCH_UMSK, 0);
1191 }
1192
771fe6b9
JG		 1193 WREG32(RADEON_CP_RB_CNTL, tmp);
1194 udelay(10);
771fe6b9
JG		 1195 /* Set cp mode to bus mastering & enable cp*/
1196 WREG32(RADEON_CP_CSQ_MODE,
1197 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1198 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1199 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1200 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9 1201 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2099810f
DA		 1202
1203 /* at this point everything should be setup correctly to enable master */
1204 pci_set_master(rdev->pdev);
1205
f712812e
AD		 1206 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1207 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
771fe6b9
JG		 1208 if (r) {
1209 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1210 return r;
1211 }
e32eb50d 1212 ring->ready = true;
53595338 1213 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
c7eff978 1214
16c58081
SK		 1215 if (!ring->rptr_save_reg /* not resuming from suspend */
1216 && radeon_ring_supports_scratch_reg(rdev, ring)) {
c7eff978
AD		 1217 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1218 if (r) {
1219 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1220 ring->rptr_save_reg = 0;
1221 }
1222 }
771fe6b9
JG		 1223 return 0;
1224}
1225
1226void r100_cp_fini(struct radeon_device *rdev)
1227{
45600232
JG		 1228 if (r100_cp_wait_for_idle(rdev)) {
1229 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1230 }
771fe6b9 1231 /* Disable ring */
a18d7ea1 1232 r100_cp_disable(rdev);
c7eff978 1233 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
e32eb50d 1234 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1235 DRM_INFO("radeon: cp finalized\n");
1236}
1237
1238void r100_cp_disable(struct radeon_device *rdev)
1239{
1240 /* Disable ring */
53595338 1241 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1242 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1243 WREG32(RADEON_CP_CSQ_MODE, 0);
1244 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1245 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1246 if (r100_gui_wait_for_idle(rdev)) {
1247 printk(KERN_WARNING "Failed to wait GUI idle while "
1248 "programming pipes. Bad things might happen.\n");
1249 }
1250}
1251
771fe6b9
JG		 1252/*
1253 * CS functions
1254 */
0242f74d
AD		 1255int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1256 struct radeon_cs_packet *pkt,
1257 unsigned idx,
1258 unsigned reg)
1259{
1260 int r;
1261 u32 tile_flags = 0;
1262 u32 tmp;
1d0c0942 1263 struct radeon_bo_list *reloc;
0242f74d
AD		 1264 u32 value;
1265
012e976d 1266 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1267 if (r) {
1268 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1269 idx, reg);
c3ad63af 1270 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1271 return r;
1272 }
1273
1274 value = radeon_get_ib_value(p, idx);
1275 tmp = value & 0x003fffff;
df0af440 1276 tmp += (((u32)reloc->gpu_offset) >> 10);
0242f74d
AD		 1277
1278 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
df0af440 1279 if (reloc->tiling_flags & RADEON_TILING_MACRO)
0242f74d 1280 tile_flags |= RADEON_DST_TILE_MACRO;
df0af440 1281 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
0242f74d
AD		 1282 if (reg == RADEON_SRC_PITCH_OFFSET) {
1283 DRM_ERROR("Cannot src blit from microtiled surface\n");
c3ad63af 1284 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1285 return -EINVAL;
1286 }
1287 tile_flags |= RADEON_DST_TILE_MICRO;
1288 }
1289
1290 tmp |= tile_flags;
1291 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1292 } else
1293 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1294 return 0;
1295}
1296
1297int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1298 struct radeon_cs_packet *pkt,
1299 int idx)
1300{
1301 unsigned c, i;
1d0c0942 1302 struct radeon_bo_list *reloc;
0242f74d
AD		 1303 struct r100_cs_track *track;
1304 int r = 0;
1305 volatile uint32_t *ib;
1306 u32 idx_value;
1307
1308 ib = p->ib.ptr;
1309 track = (struct r100_cs_track *)p->track;
1310 c = radeon_get_ib_value(p, idx++) & 0x1F;
1311 if (c > 16) {
1312 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1313 pkt->opcode);
c3ad63af 1314 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1315 return -EINVAL;
1316 }
1317 track->num_arrays = c;
1318 for (i = 0; i < (c - 1); i+=2, idx+=3) {
012e976d 1319 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1320 if (r) {
1321 DRM_ERROR("No reloc for packet3 %d\n",
1322 pkt->opcode);
c3ad63af 1323 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1324 return r;
1325 }
1326 idx_value = radeon_get_ib_value(p, idx);
df0af440 1327 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
0242f74d
AD		 1328
1329 track->arrays[i + 0].esize = idx_value >> 8;
1330 track->arrays[i + 0].robj = reloc->robj;
1331 track->arrays[i + 0].esize &= 0x7F;
012e976d 1332 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1333 if (r) {
1334 DRM_ERROR("No reloc for packet3 %d\n",
1335 pkt->opcode);
c3ad63af 1336 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1337 return r;
1338 }
df0af440 1339 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
0242f74d
AD		 1340 track->arrays[i + 1].robj = reloc->robj;
1341 track->arrays[i + 1].esize = idx_value >> 24;
1342 track->arrays[i + 1].esize &= 0x7F;
1343 }
1344 if (c & 1) {
012e976d 1345 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1346 if (r) {
1347 DRM_ERROR("No reloc for packet3 %d\n",
1348 pkt->opcode);
c3ad63af 1349 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1350 return r;
1351 }
1352 idx_value = radeon_get_ib_value(p, idx);
df0af440 1353 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
0242f74d
AD		 1354 track->arrays[i + 0].robj = reloc->robj;
1355 track->arrays[i + 0].esize = idx_value >> 8;
1356 track->arrays[i + 0].esize &= 0x7F;
1357 }
1358 return r;
1359}
1360
771fe6b9
JG		 1361int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1362 struct radeon_cs_packet *pkt,
068a117c 1363 const unsigned *auth, unsigned n,
771fe6b9
JG		 1364 radeon_packet0_check_t check)
1365{
1366 unsigned reg;
1367 unsigned i, j, m;
1368 unsigned idx;
1369 int r;
1370
1371 idx = pkt->idx + 1;
1372 reg = pkt->reg;
068a117c
JG		 1373 /* Check that register fall into register range
1374 * determined by the number of entry (n) in the
1375 * safe register bitmap.
1376 */
771fe6b9
JG		 1377 if (pkt->one_reg_wr) {
1378 if ((reg >> 7) > n) {
1379 return -EINVAL;
1380 }
1381 } else {
1382 if (((reg + (pkt->count << 2)) >> 7) > n) {
1383 return -EINVAL;
1384 }
1385 }
1386 for (i = 0; i <= pkt->count; i++, idx++) {
1387 j = (reg >> 7);
1388 m = 1 << ((reg >> 2) & 31);
1389 if (auth[j] & m) {
1390 r = check(p, pkt, idx, reg);
1391 if (r) {
1392 return r;
1393 }
1394 }
1395 if (pkt->one_reg_wr) {
1396 if (!(auth[j] & m)) {
1397 break;
1398 }
1399 } else {
1400 reg += 4;
1401 }
1402 }
1403 return 0;
1404}
1405
531369e6
DA		 1406/**
1407 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1408 * @parser: parser structure holding parsing context.
1409 *
1410 * Userspace sends a special sequence for VLINE waits.
1411 * PACKET0 - VLINE_START_END + value
1412 * PACKET0 - WAIT_UNTIL +_value
1413 * RELOC (P3) - crtc_id in reloc.
1414 *
1415 * This function parses this and relocates the VLINE START END
1416 * and WAIT UNTIL packets to the correct crtc.
1417 * It also detects a switched off crtc and nulls out the
1418 * wait in that case.
1419 */
1420int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1421{
531369e6
DA		 1422 struct drm_crtc *crtc;
1423 struct radeon_crtc *radeon_crtc;
1424 struct radeon_cs_packet p3reloc, waitreloc;
1425 int crtc_id;
1426 int r;
1427 uint32_t header, h_idx, reg;
513bcb46 1428 volatile uint32_t *ib;
531369e6 1429
f2e39221 1430 ib = p->ib.ptr;
531369e6
DA		 1431
1432 /* parse the wait until */
c38f34b5 1433 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
531369e6
DA		 1434 if (r)
1435 return r;
1436
1437 /* check its a wait until and only 1 count */
1438 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1439 waitreloc.count != 0) {
1440 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1441 return -EINVAL;
531369e6
DA		 1442 }
1443
513bcb46 1444 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1445 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1446 return -EINVAL;
531369e6
DA		 1447 }
1448
1449 /* jump over the NOP */
c38f34b5 1450 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1451 if (r)
1452 return r;
1453
1454 h_idx = p->idx - 2;
90ebd065
AD		 1455 p->idx += waitreloc.count + 2;
1456 p->idx += p3reloc.count + 2;
531369e6 1457
513bcb46
DA		 1458 header = radeon_get_ib_value(p, h_idx);
1459 crtc_id = radeon_get_ib_value(p, h_idx + 5);
4e872ae2 1460 reg = R100_CP_PACKET0_GET_REG(header);
b957f457
RC		 1461 crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
1462 if (!crtc) {
531369e6 1463 DRM_ERROR("cannot find crtc %d\n", crtc_id);
10e10d34 1464 return -ENOENT;
531369e6 1465 }
531369e6
DA		 1466 radeon_crtc = to_radeon_crtc(crtc);
1467 crtc_id = radeon_crtc->crtc_id;
1468
1469 if (!crtc->enabled) {
1470 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1471 ib[h_idx + 2] = PACKET2(0);
1472 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1473 } else if (crtc_id == 1) {
1474 switch (reg) {
1475 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1476 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1477 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1478 break;
1479 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1480 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1481 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1482 break;
1483 default:
1484 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1485 return -EINVAL;
531369e6 1486 }
513bcb46
DA		 1487 ib[h_idx] = header;
1488 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1489 }
a3a88a66
PB		 1490
1491 return 0;
531369e6
DA		 1492}
1493
551ebd83
DA		 1494static int r100_get_vtx_size(uint32_t vtx_fmt)
1495{
1496 int vtx_size;
1497 vtx_size = 2;
1498 /* ordered according to bits in spec */
1499 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1500 vtx_size++;
1501 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1502 vtx_size += 3;
1503 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1504 vtx_size++;
1505 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1506 vtx_size++;
1507 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1508 vtx_size += 3;
1509 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1510 vtx_size++;
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1512 vtx_size++;
1513 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1514 vtx_size += 2;
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1516 vtx_size += 2;
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1518 vtx_size++;
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1520 vtx_size += 2;
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1522 vtx_size++;
1523 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1524 vtx_size += 2;
1525 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1526 vtx_size++;
1527 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1528 vtx_size++;
1529 /* blend weight */
1530 if (vtx_fmt & (0x7 << 15))
1531 vtx_size += (vtx_fmt >> 15) & 0x7;
1532 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1533 vtx_size += 3;
1534 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1535 vtx_size += 2;
1536 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1537 vtx_size++;
1538 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1539 vtx_size++;
1540 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1541 vtx_size++;
1542 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1543 vtx_size++;
1544 return vtx_size;
1545}
1546
771fe6b9 1547static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1548 struct radeon_cs_packet *pkt,
1549 unsigned idx, unsigned reg)
771fe6b9 1550{
1d0c0942 1551 struct radeon_bo_list *reloc;
551ebd83 1552 struct r100_cs_track *track;
771fe6b9
JG		 1553 volatile uint32_t *ib;
1554 uint32_t tmp;
771fe6b9 1555 int r;
551ebd83 1556 int i, face;
e024e110 1557 u32 tile_flags = 0;
513bcb46 1558 u32 idx_value;
771fe6b9 1559
f2e39221 1560 ib = p->ib.ptr;
551ebd83
DA		 1561 track = (struct r100_cs_track *)p->track;
1562
513bcb46
DA		 1563 idx_value = radeon_get_ib_value(p, idx);
1564
551ebd83
DA		 1565 switch (reg) {
1566 case RADEON_CRTC_GUI_TRIG_VLINE:
1567 r = r100_cs_packet_parse_vline(p);
1568 if (r) {
1569 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1570 idx, reg);
c3ad63af 1571 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1572 return r;
1573 }
1574 break;
771fe6b9
JG		 1575 /* FIXME: only allow PACKET3 blit? easier to check for out of
1576 * range access */
551ebd83
DA		 1577 case RADEON_DST_PITCH_OFFSET:
1578 case RADEON_SRC_PITCH_OFFSET:
1579 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1580 if (r)
1581 return r;
1582 break;
1583 case RADEON_RB3D_DEPTHOFFSET:
012e976d 1584 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1585 if (r) {
1586 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1587 idx, reg);
c3ad63af 1588 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1589 return r;
1590 }
1591 track->zb.robj = reloc->robj;
513bcb46 1592 track->zb.offset = idx_value;
40b4a759 1593 track->zb_dirty = true;
df0af440 1594 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83
DA		 1595 break;
1596 case RADEON_RB3D_COLOROFFSET:
012e976d 1597 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1598 if (r) {
1599 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1600 idx, reg);
c3ad63af 1601 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1602 return r;
1603 }
1604 track->cb[0].robj = reloc->robj;
513bcb46 1605 track->cb[0].offset = idx_value;
40b4a759 1606 track->cb_dirty = true;
df0af440 1607 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83
DA		 1608 break;
1609 case RADEON_PP_TXOFFSET_0:
1610 case RADEON_PP_TXOFFSET_1:
1611 case RADEON_PP_TXOFFSET_2:
1612 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
012e976d 1613 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1614 if (r) {
1615 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1616 idx, reg);
c3ad63af 1617 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1618 return r;
1619 }
f2746f83 1620 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
df0af440 1621 if (reloc->tiling_flags & RADEON_TILING_MACRO)
f2746f83 1622 tile_flags |= RADEON_TXO_MACRO_TILE;
df0af440 1623 if (reloc->tiling_flags & RADEON_TILING_MICRO)
f2746f83
AD		 1624 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1625
1626 tmp = idx_value & ~(0x7 << 2);
1627 tmp |= tile_flags;
df0af440 1628 ib[idx] = tmp + ((u32)reloc->gpu_offset);
f2746f83 1629 } else
df0af440 1630 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1631 track->textures[i].robj = reloc->robj;
40b4a759 1632 track->tex_dirty = true;
551ebd83
DA		 1633 break;
1634 case RADEON_PP_CUBIC_OFFSET_T0_0:
1635 case RADEON_PP_CUBIC_OFFSET_T0_1:
1636 case RADEON_PP_CUBIC_OFFSET_T0_2:
1637 case RADEON_PP_CUBIC_OFFSET_T0_3:
1638 case RADEON_PP_CUBIC_OFFSET_T0_4:
1639 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
012e976d 1640 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1641 if (r) {
1642 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1643 idx, reg);
c3ad63af 1644 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1645 return r;
1646 }
513bcb46 1647 track->textures[0].cube_info[i].offset = idx_value;
df0af440 1648 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1649 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1650 track->tex_dirty = true;
551ebd83
DA		 1651 break;
1652 case RADEON_PP_CUBIC_OFFSET_T1_0:
1653 case RADEON_PP_CUBIC_OFFSET_T1_1:
1654 case RADEON_PP_CUBIC_OFFSET_T1_2:
1655 case RADEON_PP_CUBIC_OFFSET_T1_3:
1656 case RADEON_PP_CUBIC_OFFSET_T1_4:
1657 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
012e976d 1658 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1659 if (r) {
1660 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1661 idx, reg);
c3ad63af 1662 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1663 return r;
1664 }
513bcb46 1665 track->textures[1].cube_info[i].offset = idx_value;
df0af440 1666 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1667 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1668 track->tex_dirty = true;
551ebd83
DA		 1669 break;
1670 case RADEON_PP_CUBIC_OFFSET_T2_0:
1671 case RADEON_PP_CUBIC_OFFSET_T2_1:
1672 case RADEON_PP_CUBIC_OFFSET_T2_2:
1673 case RADEON_PP_CUBIC_OFFSET_T2_3:
1674 case RADEON_PP_CUBIC_OFFSET_T2_4:
1675 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
012e976d 1676 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1677 if (r) {
1678 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1679 idx, reg);
c3ad63af 1680 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1681 return r;
1682 }
513bcb46 1683 track->textures[2].cube_info[i].offset = idx_value;
df0af440 1684 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83 1685 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1686 track->tex_dirty = true;
551ebd83
DA		 1687 break;
1688 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1689 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1690 track->cb_dirty = true;
1691 track->zb_dirty = true;
551ebd83
DA		 1692 break;
1693 case RADEON_RB3D_COLORPITCH:
012e976d 1694 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1695 if (r) {
1696 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1697 idx, reg);
c3ad63af 1698 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1699 return r;
1700 }
c9068eb2 1701 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
df0af440 1702 if (reloc->tiling_flags & RADEON_TILING_MACRO)
c9068eb2 1703 tile_flags |= RADEON_COLOR_TILE_ENABLE;
df0af440 1704 if (reloc->tiling_flags & RADEON_TILING_MICRO)
c9068eb2
AD		 1705 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1706
1707 tmp = idx_value & ~(0x7 << 16);
1708 tmp |= tile_flags;
1709 ib[idx] = tmp;
1710 } else
1711 ib[idx] = idx_value;
e024e110 1712
513bcb46 1713 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1714 track->cb_dirty = true;
551ebd83
DA		 1715 break;
1716 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1717 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1718 track->zb_dirty = true;
551ebd83
DA		 1719 break;
1720 case RADEON_RB3D_CNTL:
513bcb46 1721 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1722 case 7:
1723 case 8:
1724 case 9:
1725 case 11:
1726 case 12:
1727 track->cb[0].cpp = 1;
e024e110 1728 break;
551ebd83
DA		 1729 case 3:
1730 case 4:
1731 case 15:
1732 track->cb[0].cpp = 2;
1733 break;
1734 case 6:
1735 track->cb[0].cpp = 4;
1736 break;
1737 default:
1738 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1739 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1740 return -EINVAL;
1741 }
513bcb46 1742 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1743 track->cb_dirty = true;
1744 track->zb_dirty = true;
551ebd83
DA		 1745 break;
1746 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1747 switch (idx_value & 0xf) {
551ebd83
DA		 1748 case 0:
1749 track->zb.cpp = 2;
1750 break;
1751 case 2:
1752 case 3:
1753 case 4:
1754 case 5:
1755 case 9:
1756 case 11:
1757 track->zb.cpp = 4;
17782d99 1758 break;
771fe6b9 1759 default:
771fe6b9
JG		 1760 break;
1761 }
40b4a759 1762 track->zb_dirty = true;
551ebd83
DA		 1763 break;
1764 case RADEON_RB3D_ZPASS_ADDR:
012e976d 1765 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1766 if (r) {
1767 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1768 idx, reg);
c3ad63af 1769 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1770 return r;
1771 }
df0af440 1772 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
551ebd83
DA		 1773 break;
1774 case RADEON_PP_CNTL:
1775 {
513bcb46 1776 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1777 for (i = 0; i < track->num_texture; i++)
1778 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1779 track->tex_dirty = true;
551ebd83
DA		 1780 }
1781 break;
1782 case RADEON_SE_VF_CNTL:
513bcb46 1783 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1784 break;
1785 case RADEON_SE_VTX_FMT:
513bcb46 1786 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1787 break;
1788 case RADEON_PP_TEX_SIZE_0:
1789 case RADEON_PP_TEX_SIZE_1:
1790 case RADEON_PP_TEX_SIZE_2:
1791 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1792 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1793 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1794 track->tex_dirty = true;
551ebd83
DA		 1795 break;
1796 case RADEON_PP_TEX_PITCH_0:
1797 case RADEON_PP_TEX_PITCH_1:
1798 case RADEON_PP_TEX_PITCH_2:
1799 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1800 track->textures[i].pitch = idx_value + 32;
40b4a759 1801 track->tex_dirty = true;
551ebd83
DA		 1802 break;
1803 case RADEON_PP_TXFILTER_0:
1804 case RADEON_PP_TXFILTER_1:
1805 case RADEON_PP_TXFILTER_2:
1806 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1807 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1808 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1809 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1810 if (tmp == 2 || tmp == 6)
1811 track->textures[i].roundup_w = false;
513bcb46 1812 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1813 if (tmp == 2 || tmp == 6)
1814 track->textures[i].roundup_h = false;
40b4a759 1815 track->tex_dirty = true;
551ebd83
DA		 1816 break;
1817 case RADEON_PP_TXFORMAT_0:
1818 case RADEON_PP_TXFORMAT_1:
1819 case RADEON_PP_TXFORMAT_2:
1820 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1821 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1822 track->textures[i].use_pitch = 1;
1823 } else {
1824 track->textures[i].use_pitch = 0;
513bcb46
DA		 1825 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1826 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1827 }
513bcb46 1828 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1829 track->textures[i].tex_coord_type = 2;
513bcb46 1830 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1831 case RADEON_TXFORMAT_I8:
1832 case RADEON_TXFORMAT_RGB332:
1833 case RADEON_TXFORMAT_Y8:
1834 track->textures[i].cpp = 1;
f9da52d5 1835 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1836 break;
1837 case RADEON_TXFORMAT_AI88:
1838 case RADEON_TXFORMAT_ARGB1555:
1839 case RADEON_TXFORMAT_RGB565:
1840 case RADEON_TXFORMAT_ARGB4444:
1841 case RADEON_TXFORMAT_VYUY422:
1842 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1843 case RADEON_TXFORMAT_SHADOW16:
1844 case RADEON_TXFORMAT_LDUDV655:
1845 case RADEON_TXFORMAT_DUDV88:
1846 track->textures[i].cpp = 2;
f9da52d5 1847 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1848 break;
551ebd83
DA		 1849 case RADEON_TXFORMAT_ARGB8888:
1850 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1851 case RADEON_TXFORMAT_SHADOW32:
1852 case RADEON_TXFORMAT_LDUDUV8888:
1853 track->textures[i].cpp = 4;
f9da52d5 1854 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1855 break;
d785d78b
DA		 1856 case RADEON_TXFORMAT_DXT1:
1857 track->textures[i].cpp = 1;
1858 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1859 break;
1860 case RADEON_TXFORMAT_DXT23:
1861 case RADEON_TXFORMAT_DXT45:
1862 track->textures[i].cpp = 1;
1863 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1864 break;
551ebd83 1865 }
513bcb46
DA		 1866 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1867 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1868 track->tex_dirty = true;
551ebd83
DA		 1869 break;
1870 case RADEON_PP_CUBIC_FACES_0:
1871 case RADEON_PP_CUBIC_FACES_1:
1872 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1873 tmp = idx_value;
551ebd83
DA		 1874 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1875 for (face = 0; face < 4; face++) {
1876 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1877 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1878 }
40b4a759 1879 track->tex_dirty = true;
551ebd83
DA		 1880 break;
1881 default:
1882 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1883 reg, idx);
1884 return -EINVAL;
771fe6b9
JG		 1885 }
1886 return 0;
1887}
1888
068a117c
JG		 1889int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1890 struct radeon_cs_packet *pkt,
4c788679 1891 struct radeon_bo *robj)
068a117c 1892{
068a117c 1893 unsigned idx;
513bcb46 1894 u32 value;
068a117c 1895 idx = pkt->idx + 1;
513bcb46 1896 value = radeon_get_ib_value(p, idx + 2);
4c788679 1897 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1898 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1899 "(need %u have %lu) !\n",
513bcb46 1900 value + 1,
4c788679 1901 radeon_bo_size(robj));
068a117c
JG		 1902 return -EINVAL;
1903 }
1904 return 0;
1905}
1906
771fe6b9
JG		 1907static int r100_packet3_check(struct radeon_cs_parser *p,
1908 struct radeon_cs_packet *pkt)
1909{
1d0c0942 1910 struct radeon_bo_list *reloc;
551ebd83 1911 struct r100_cs_track *track;
771fe6b9 1912 unsigned idx;
771fe6b9
JG		 1913 volatile uint32_t *ib;
1914 int r;
1915
f2e39221 1916 ib = p->ib.ptr;
771fe6b9 1917 idx = pkt->idx + 1;
551ebd83 1918 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1919 switch (pkt->opcode) {
1920 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1921 r = r100_packet3_load_vbpntr(p, pkt, idx);
1922 if (r)
1923 return r;
771fe6b9
JG		 1924 break;
1925 case PACKET3_INDX_BUFFER:
012e976d 1926 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1927 if (r) {
1928 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1929 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1930 return r;
1931 }
df0af440 1932 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
068a117c
JG		 1933 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1934 if (r) {
1935 return r;
1936 }
771fe6b9
JG		 1937 break;
1938 case 0x23:
771fe6b9 1939 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
012e976d 1940 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1941 if (r) {
1942 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1943 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1944 return r;
1945 }
df0af440 1946 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
551ebd83 1947 track->num_arrays = 1;
513bcb46 1948 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1949
1950 track->arrays[0].robj = reloc->robj;
1951 track->arrays[0].esize = track->vtx_size;
1952
513bcb46 1953 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1954
513bcb46 1955 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1956 track->immd_dwords = pkt->count - 1;
1957 r = r100_cs_track_check(p->rdev, track);
1958 if (r)
1959 return r;
771fe6b9
JG		 1960 break;
1961 case PACKET3_3D_DRAW_IMMD:
513bcb46 1962 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1963 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1964 return -EINVAL;
1965 }
cf57fc7a 1966 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1967 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1968 track->immd_dwords = pkt->count - 1;
1969 r = r100_cs_track_check(p->rdev, track);
1970 if (r)
1971 return r;
1972 break;
771fe6b9
JG		 1973 /* triggers drawing using in-packet vertex data */
1974 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1975 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1976 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1977 return -EINVAL;
1978 }
513bcb46 1979 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1980 track->immd_dwords = pkt->count;
1981 r = r100_cs_track_check(p->rdev, track);
1982 if (r)
1983 return r;
1984 break;
771fe6b9
JG		 1985 /* triggers drawing using in-packet vertex data */
1986 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1987 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1988 r = r100_cs_track_check(p->rdev, track);
1989 if (r)
1990 return r;
1991 break;
771fe6b9
JG		 1992 /* triggers drawing of vertex buffers setup elsewhere */
1993 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1994 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1995 r = r100_cs_track_check(p->rdev, track);
1996 if (r)
1997 return r;
1998 break;
771fe6b9
JG		 1999 /* triggers drawing using indices to vertex buffer */
2000 case PACKET3_3D_DRAW_VBUF:
513bcb46 2001 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2002 r = r100_cs_track_check(p->rdev, track);
2003 if (r)
2004 return r;
2005 break;
771fe6b9
JG		 2006 /* triggers drawing of vertex buffers setup elsewhere */
2007 case PACKET3_3D_DRAW_INDX:
513bcb46 2008 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2009 r = r100_cs_track_check(p->rdev, track);
2010 if (r)
2011 return r;
2012 break;
771fe6b9 2013 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 2014 case PACKET3_3D_CLEAR_HIZ:
2015 case PACKET3_3D_CLEAR_ZMASK:
2016 if (p->rdev->hyperz_filp != p->filp)
2017 return -EINVAL;
2018 break;
771fe6b9
JG		 2019 case PACKET3_NOP:
2020 break;
2021 default:
2022 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2023 return -EINVAL;
2024 }
2025 return 0;
2026}
2027
2028int r100_cs_parse(struct radeon_cs_parser *p)
2029{
2030 struct radeon_cs_packet pkt;
9f022ddf 2031 struct r100_cs_track *track;
771fe6b9
JG		 2032 int r;
2033
9f022ddf 2034 track = kzalloc(sizeof(*track), GFP_KERNEL);
ce067913
DC		 2035 if (!track)
2036 return -ENOMEM;
9f022ddf
JG		 2037 r100_cs_track_clear(p->rdev, track);
2038 p->track = track;
771fe6b9 2039 do {
c38f34b5 2040 r = radeon_cs_packet_parse(p, &pkt, p->idx);
771fe6b9
JG		 2041 if (r) {
2042 return r;
2043 }
2044 p->idx += pkt.count + 2;
2045 switch (pkt.type) {
4e872ae2 2046 case RADEON_PACKET_TYPE0:
66b3543e
IH		 2047 if (p->rdev->family >= CHIP_R200)
2048 r = r100_cs_parse_packet0(p, &pkt,
2049 p->rdev->config.r100.reg_safe_bm,
2050 p->rdev->config.r100.reg_safe_bm_size,
2051 &r200_packet0_check);
2052 else
2053 r = r100_cs_parse_packet0(p, &pkt,
2054 p->rdev->config.r100.reg_safe_bm,
2055 p->rdev->config.r100.reg_safe_bm_size,
2056 &r100_packet0_check);
2057 break;
4e872ae2 2058 case RADEON_PACKET_TYPE2:
66b3543e 2059 break;
4e872ae2 2060 case RADEON_PACKET_TYPE3:
66b3543e
IH		 2061 r = r100_packet3_check(p, &pkt);
2062 break;
2063 default:
2064 DRM_ERROR("Unknown packet type %d !\n",
2065 pkt.type);
2066 return -EINVAL;
771fe6b9 2067 }
66b3543e 2068 if (r)
771fe6b9 2069 return r;
6d2d13dd 2070 } while (p->idx < p->chunk_ib->length_dw);
771fe6b9
JG		 2071 return 0;
2072}
2073
0242f74d 2074static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
771fe6b9 2075{
0242f74d
AD		 2076 DRM_ERROR("pitch %d\n", t->pitch);
2077 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2078 DRM_ERROR("width %d\n", t->width);
2079 DRM_ERROR("width_11 %d\n", t->width_11);
2080 DRM_ERROR("height %d\n", t->height);
2081 DRM_ERROR("height_11 %d\n", t->height_11);
2082 DRM_ERROR("num levels %d\n", t->num_levels);
2083 DRM_ERROR("depth %d\n", t->txdepth);
2084 DRM_ERROR("bpp %d\n", t->cpp);
2085 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2086 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2087 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2088 DRM_ERROR("compress format %d\n", t->compress_format);
771fe6b9
JG		 2089}
2090
0242f74d 2091static int r100_track_compress_size(int compress_format, int w, int h)
771fe6b9 2092{
0242f74d
AD		 2093 int block_width, block_height, block_bytes;
2094 int wblocks, hblocks;
2095 int min_wblocks;
2096 int sz;
771fe6b9 2097
0242f74d
AD		 2098 block_width = 4;
2099 block_height = 4;
2100
2101 switch (compress_format) {
2102 case R100_TRACK_COMP_DXT1:
2103 block_bytes = 8;
2104 min_wblocks = 4;
2105 break;
2106 default:
2107 case R100_TRACK_COMP_DXT35:
2108 block_bytes = 16;
2109 min_wblocks = 2;
2110 break;
771fe6b9 2111 }
0242f74d
AD		 2112
2113 hblocks = (h + block_height - 1) / block_height;
2114 wblocks = (w + block_width - 1) / block_width;
2115 if (wblocks < min_wblocks)
2116 wblocks = min_wblocks;
2117 sz = wblocks * hblocks * block_bytes;
2118 return sz;
771fe6b9
JG		 2119}
2120
0242f74d
AD		 2121static int r100_cs_track_cube(struct radeon_device *rdev,
2122 struct r100_cs_track *track, unsigned idx)
771fe6b9 2123{
0242f74d
AD		 2124 unsigned face, w, h;
2125 struct radeon_bo *cube_robj;
2126 unsigned long size;
2127 unsigned compress_format = track->textures[idx].compress_format;
771fe6b9 2128
0242f74d
AD		 2129 for (face = 0; face < 5; face++) {
2130 cube_robj = track->textures[idx].cube_info[face].robj;
2131 w = track->textures[idx].cube_info[face].width;
2132 h = track->textures[idx].cube_info[face].height;
771fe6b9 2133
0242f74d
AD		 2134 if (compress_format) {
2135 size = r100_track_compress_size(compress_format, w, h);
2136 } else
2137 size = w * h;
2138 size *= track->textures[idx].cpp;
2139
2140 size += track->textures[idx].cube_info[face].offset;
2141
2142 if (size > radeon_bo_size(cube_robj)) {
2143 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2144 size, radeon_bo_size(cube_robj));
2145 r100_cs_track_texture_print(&track->textures[idx]);
2146 return -1;
771fe6b9 2147 }
771fe6b9 2148 }
0242f74d 2149 return 0;
771fe6b9
JG		 2150}
2151
0242f74d
AD		 2152static int r100_cs_track_texture_check(struct radeon_device *rdev,
2153 struct r100_cs_track *track)
771fe6b9 2154{
0242f74d
AD		 2155 struct radeon_bo *robj;
2156 unsigned long size;
2157 unsigned u, i, w, h, d;
2158 int ret;
771fe6b9 2159
0242f74d
AD		 2160 for (u = 0; u < track->num_texture; u++) {
2161 if (!track->textures[u].enabled)
2162 continue;
2163 if (track->textures[u].lookup_disable)
2164 continue;
2165 robj = track->textures[u].robj;
2166 if (robj == NULL) {
2167 DRM_ERROR("No texture bound to unit %u\n", u);
2168 return -EINVAL;
771fe6b9 2169 }
0242f74d
AD		 2170 size = 0;
2171 for (i = 0; i <= track->textures[u].num_levels; i++) {
2172 if (track->textures[u].use_pitch) {
2173 if (rdev->family < CHIP_R300)
2174 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2175 else
2176 w = track->textures[u].pitch / (1 << i);
2177 } else {
2178 w = track->textures[u].width;
2179 if (rdev->family >= CHIP_RV515)
2180 w |= track->textures[u].width_11;
2181 w = w / (1 << i);
2182 if (track->textures[u].roundup_w)
2183 w = roundup_pow_of_two(w);
2184 }
2185 h = track->textures[u].height;
2186 if (rdev->family >= CHIP_RV515)
2187 h |= track->textures[u].height_11;
2188 h = h / (1 << i);
2189 if (track->textures[u].roundup_h)
2190 h = roundup_pow_of_two(h);
2191 if (track->textures[u].tex_coord_type == 1) {
2192 d = (1 << track->textures[u].txdepth) / (1 << i);
2193 if (!d)
2194 d = 1;
2195 } else {
2196 d = 1;
2197 }
2198 if (track->textures[u].compress_format) {
771fe6b9 2199
0242f74d
AD		 2200 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2201 /* compressed textures are block based */
2202 } else
2203 size += w * h * d;
2204 }
2205 size *= track->textures[u].cpp;
771fe6b9 2206
0242f74d
AD		 2207 switch (track->textures[u].tex_coord_type) {
2208 case 0:
2209 case 1:
2210 break;
2211 case 2:
2212 if (track->separate_cube) {
2213 ret = r100_cs_track_cube(rdev, track, u);
2214 if (ret)
2215 return ret;
2216 } else
2217 size *= 6;
2218 break;
2219 default:
2220 DRM_ERROR("Invalid texture coordinate type %u for unit "
2221 "%u\n", track->textures[u].tex_coord_type, u);
2222 return -EINVAL;
2223 }
2224 if (size > radeon_bo_size(robj)) {
2225 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2226 "%lu\n", u, size, radeon_bo_size(robj));
2227 r100_cs_track_texture_print(&track->textures[u]);
2228 return -EINVAL;
771fe6b9 2229 }
771fe6b9 2230 }
0242f74d 2231 return 0;
771fe6b9
JG		 2232}
2233
0242f74d 2234int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
771fe6b9
JG		 2235{
2236 unsigned i;
0242f74d
AD		 2237 unsigned long size;
2238 unsigned prim_walk;
2239 unsigned nverts;
2240 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
771fe6b9 2241
0242f74d
AD		 2242 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2243 !track->blend_read_enable)
2244 num_cb = 0;
2245
2246 for (i = 0; i < num_cb; i++) {
2247 if (track->cb[i].robj == NULL) {
2248 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2249 return -EINVAL;
2250 }
2251 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2252 size += track->cb[i].offset;
2253 if (size > radeon_bo_size(track->cb[i].robj)) {
2254 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2255 "(need %lu have %lu) !\n", i, size,
2256 radeon_bo_size(track->cb[i].robj));
2257 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2258 i, track->cb[i].pitch, track->cb[i].cpp,
2259 track->cb[i].offset, track->maxy);
2260 return -EINVAL;
771fe6b9 2261 }
771fe6b9 2262 }
0242f74d 2263 track->cb_dirty = false;
771fe6b9 2264
0242f74d
AD		 2265 if (track->zb_dirty && track->z_enabled) {
2266 if (track->zb.robj == NULL) {
2267 DRM_ERROR("[drm] No buffer for z buffer !\n");
2268 return -EINVAL;
2269 }
2270 size = track->zb.pitch * track->zb.cpp * track->maxy;
2271 size += track->zb.offset;
2272 if (size > radeon_bo_size(track->zb.robj)) {
2273 DRM_ERROR("[drm] Buffer too small for z buffer "
2274 "(need %lu have %lu) !\n", size,
2275 radeon_bo_size(track->zb.robj));
2276 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2277 track->zb.pitch, track->zb.cpp,
2278 track->zb.offset, track->maxy);
2279 return -EINVAL;
2280 }
225758d8 2281 }
0242f74d 2282 track->zb_dirty = false;
771fe6b9 2283
0242f74d
AD		 2284 if (track->aa_dirty && track->aaresolve) {
2285 if (track->aa.robj == NULL) {
2286 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2287 return -EINVAL;
2288 }
2289 /* I believe the format comes from colorbuffer0. */
2290 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2291 size += track->aa.offset;
2292 if (size > radeon_bo_size(track->aa.robj)) {
2293 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2294 "(need %lu have %lu) !\n", i, size,
2295 radeon_bo_size(track->aa.robj));
2296 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2297 i, track->aa.pitch, track->cb[0].cpp,
2298 track->aa.offset, track->maxy);
2299 return -EINVAL;
2300 }
2301 }
2302 track->aa_dirty = false;
771fe6b9 2303
0242f74d
AD		 2304 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2305 if (track->vap_vf_cntl & (1 << 14)) {
2306 nverts = track->vap_alt_nverts;
2307 } else {
2308 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2739d49c 2309 }
0242f74d
AD		 2310 switch (prim_walk) {
2311 case 1:
2312 for (i = 0; i < track->num_arrays; i++) {
2313 size = track->arrays[i].esize * track->max_indx * 4;
2314 if (track->arrays[i].robj == NULL) {
2315 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2316 "bound\n", prim_walk, i);
2317 return -EINVAL;
2318 }
2319 if (size > radeon_bo_size(track->arrays[i].robj)) {
2320 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2321 "need %lu dwords have %lu dwords\n",
2322 prim_walk, i, size >> 2,
2323 radeon_bo_size(track->arrays[i].robj)
2324 >> 2);
2325 DRM_ERROR("Max indices %u\n", track->max_indx);
2326 return -EINVAL;
2327 }
771fe6b9 2328 }
0242f74d
AD		 2329 break;
2330 case 2:
2331 for (i = 0; i < track->num_arrays; i++) {
2332 size = track->arrays[i].esize * (nverts - 1) * 4;
2333 if (track->arrays[i].robj == NULL) {
2334 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2335 "bound\n", prim_walk, i);
2336 return -EINVAL;
2337 }
2338 if (size > radeon_bo_size(track->arrays[i].robj)) {
2339 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2340 "need %lu dwords have %lu dwords\n",
2341 prim_walk, i, size >> 2,
2342 radeon_bo_size(track->arrays[i].robj)
2343 >> 2);
2344 return -EINVAL;
2345 }
771fe6b9 2346 }
0242f74d
AD		 2347 break;
2348 case 3:
2349 size = track->vtx_size * nverts;
2350 if (size != track->immd_dwords) {
2351 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2352 track->immd_dwords, size);
2353 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2354 nverts, track->vtx_size);
2355 return -EINVAL;
771fe6b9 2356 }
0242f74d
AD		 2357 break;
2358 default:
2359 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2360 prim_walk);
2361 return -EINVAL;
2a0f8918
DA		 2362 }
2363
0242f74d
AD		 2364 if (track->tex_dirty) {
2365 track->tex_dirty = false;
2366 return r100_cs_track_texture_check(rdev, track);
2a0f8918 2367 }
0242f74d 2368 return 0;
2a0f8918
DA		 2369}
2370
0242f74d 2371void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2a0f8918 2372{
0242f74d 2373 unsigned i, face;
2a0f8918 2374
0242f74d
AD		 2375 track->cb_dirty = true;
2376 track->zb_dirty = true;
2377 track->tex_dirty = true;
2378 track->aa_dirty = true;
b7d8cce5 2379
0242f74d
AD		 2380 if (rdev->family < CHIP_R300) {
2381 track->num_cb = 1;
2382 if (rdev->family <= CHIP_RS200)
2383 track->num_texture = 3;
7a50f01a 2384 else
0242f74d
AD		 2385 track->num_texture = 6;
2386 track->maxy = 2048;
2387 track->separate_cube = 1;
28d52043 2388 } else {
0242f74d
AD		 2389 track->num_cb = 4;
2390 track->num_texture = 16;
2391 track->maxy = 4096;
2392 track->separate_cube = 0;
2393 track->aaresolve = false;
2394 track->aa.robj = NULL;
28d52043 2395 }
2a0f8918 2396
0242f74d
AD		 2397 for (i = 0; i < track->num_cb; i++) {
2398 track->cb[i].robj = NULL;
2399 track->cb[i].pitch = 8192;
2400 track->cb[i].cpp = 16;
2401 track->cb[i].offset = 0;
771fe6b9 2402 }
0242f74d
AD		 2403 track->z_enabled = true;
2404 track->zb.robj = NULL;
2405 track->zb.pitch = 8192;
2406 track->zb.cpp = 4;
2407 track->zb.offset = 0;
2408 track->vtx_size = 0x7F;
2409 track->immd_dwords = 0xFFFFFFFFUL;
2410 track->num_arrays = 11;
2411 track->max_indx = 0x00FFFFFFUL;
2412 for (i = 0; i < track->num_arrays; i++) {
2413 track->arrays[i].robj = NULL;
2414 track->arrays[i].esize = 0x7F;
771fe6b9 2415 }
0242f74d
AD		 2416 for (i = 0; i < track->num_texture; i++) {
2417 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2418 track->textures[i].pitch = 16536;
2419 track->textures[i].width = 16536;
2420 track->textures[i].height = 16536;
2421 track->textures[i].width_11 = 1 << 11;
2422 track->textures[i].height_11 = 1 << 11;
2423 track->textures[i].num_levels = 12;
2424 if (rdev->family <= CHIP_RS200) {
2425 track->textures[i].tex_coord_type = 0;
2426 track->textures[i].txdepth = 0;
2427 } else {
2428 track->textures[i].txdepth = 16;
2429 track->textures[i].tex_coord_type = 1;
2430 }
2431 track->textures[i].cpp = 64;
2432 track->textures[i].robj = NULL;
2433 /* CS IB emission code makes sure texture unit are disabled */
2434 track->textures[i].enabled = false;
2435 track->textures[i].lookup_disable = false;
2436 track->textures[i].roundup_w = true;
2437 track->textures[i].roundup_h = true;
2438 if (track->separate_cube)
2439 for (face = 0; face < 5; face++) {
2440 track->textures[i].cube_info[face].robj = NULL;
2441 track->textures[i].cube_info[face].width = 16536;
2442 track->textures[i].cube_info[face].height = 16536;
2443 track->textures[i].cube_info[face].offset = 0;
2444 }
771fe6b9
JG		 2445 }
2446}
2447
0242f74d
AD		 2448/*
2449 * Global GPU functions
2450 */
1109ca09 2451static void r100_errata(struct radeon_device *rdev)
771fe6b9 2452{
0242f74d 2453 rdev->pll_errata = 0;
771fe6b9 2454
0242f74d
AD		 2455 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2456 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2457 }
771fe6b9 2458
0242f74d
AD		 2459 if (rdev->family == CHIP_RV100 ||
2460 rdev->family == CHIP_RS100 ||
2461 rdev->family == CHIP_RS200) {
2462 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2463 }
771fe6b9
JG		 2464}
2465
1109ca09 2466static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
771fe6b9 2467{
0242f74d
AD		 2468 unsigned i;
2469 uint32_t tmp;
771fe6b9 2470
0242f74d
AD		 2471 for (i = 0; i < rdev->usec_timeout; i++) {
2472 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2473 if (tmp >= n) {
2474 return 0;
2475 }
2476 DRM_UDELAY(1);
771fe6b9 2477 }
0242f74d 2478 return -1;
771fe6b9
JG		 2479}
2480
0242f74d 2481int r100_gui_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2482{
771fe6b9 2483 unsigned i;
0242f74d 2484 uint32_t tmp;
771fe6b9 2485
0242f74d
AD		 2486 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2487 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2488 " Bad things might happen.\n");
771fe6b9 2489 }
0242f74d
AD		 2490 for (i = 0; i < rdev->usec_timeout; i++) {
2491 tmp = RREG32(RADEON_RBBM_STATUS);
2492 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2493 return 0;
2494 }
2495 DRM_UDELAY(1);
771fe6b9 2496 }
0242f74d 2497 return -1;
771fe6b9
JG		 2498}
2499
0242f74d 2500int r100_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2501{
0242f74d 2502 unsigned i;
771fe6b9
JG		 2503 uint32_t tmp;
2504
0242f74d
AD		 2505 for (i = 0; i < rdev->usec_timeout; i++) {
2506 /* read MC_STATUS */
2507 tmp = RREG32(RADEON_MC_STATUS);
2508 if (tmp & RADEON_MC_IDLE) {
2509 return 0;
2510 }
2511 DRM_UDELAY(1);
2512 }
2513 return -1;
771fe6b9
JG		 2514}
2515
0242f74d 2516bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2517{
0242f74d 2518 u32 rbbm_status;
771fe6b9 2519
0242f74d
AD		 2520 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2521 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
ff212f25 2522 radeon_ring_lockup_update(rdev, ring);
0242f74d
AD		 2523 return false;
2524 }
0242f74d 2525 return radeon_ring_test_lockup(rdev, ring);
771fe6b9
JG		 2526}
2527
74da01dc
AD		 2528/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2529void r100_enable_bm(struct radeon_device *rdev)
2530{
2531 uint32_t tmp;
2532 /* Enable bus mastering */
2533 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2534 WREG32(RADEON_BUS_CNTL, tmp);
2535}
2536
0242f74d 2537void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2538{
0242f74d
AD		 2539 u32 tmp;
2540
2541 /* disable bus mastering */
2542 tmp = RREG32(R_000030_BUS_CNTL);
2543 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2544 mdelay(1);
2545 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2546 mdelay(1);
2547 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2548 tmp = RREG32(RADEON_BUS_CNTL);
2549 mdelay(1);
2550 pci_clear_master(rdev->pdev);
2551 mdelay(1);
771fe6b9 2552}
e024e110 2553
0242f74d 2554int r100_asic_reset(struct radeon_device *rdev)
e024e110 2555{
0242f74d
AD		 2556 struct r100_mc_save save;
2557 u32 status, tmp;
2558 int ret = 0;
e024e110 2559
0242f74d
AD		 2560 status = RREG32(R_000E40_RBBM_STATUS);
2561 if (!G_000E40_GUI_ACTIVE(status)) {
2562 return 0;
e024e110 2563 }
0242f74d
AD		 2564 r100_mc_stop(rdev, &save);
2565 status = RREG32(R_000E40_RBBM_STATUS);
2566 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2567 /* stop CP */
2568 WREG32(RADEON_CP_CSQ_CNTL, 0);
2569 tmp = RREG32(RADEON_CP_RB_CNTL);
2570 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2571 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2572 WREG32(RADEON_CP_RB_WPTR, 0);
2573 WREG32(RADEON_CP_RB_CNTL, tmp);
2574 /* save PCI state */
2575 pci_save_state(rdev->pdev);
2576 /* disable bus mastering */
2577 r100_bm_disable(rdev);
2578 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2579 S_0000F0_SOFT_RESET_RE(1) |
2580 S_0000F0_SOFT_RESET_PP(1) |
2581 S_0000F0_SOFT_RESET_RB(1));
2582 RREG32(R_0000F0_RBBM_SOFT_RESET);
2583 mdelay(500);
2584 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2585 mdelay(1);
2586 status = RREG32(R_000E40_RBBM_STATUS);
2587 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2588 /* reset CP */
2589 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2590 RREG32(R_0000F0_RBBM_SOFT_RESET);
2591 mdelay(500);
2592 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2593 mdelay(1);
2594 status = RREG32(R_000E40_RBBM_STATUS);
2595 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2596 /* restore PCI & busmastering */
2597 pci_restore_state(rdev->pdev);
2598 r100_enable_bm(rdev);
2599 /* Check if GPU is idle */
2600 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2601 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2602 dev_err(rdev->dev, "failed to reset GPU\n");
2603 ret = -1;
2604 } else
2605 dev_info(rdev->dev, "GPU reset succeed\n");
2606 r100_mc_resume(rdev, &save);
2607 return ret;
2608}
e024e110 2609
0242f74d
AD		 2610void r100_set_common_regs(struct radeon_device *rdev)
2611{
2612 struct drm_device *dev = rdev->ddev;
2613 bool force_dac2 = false;
2614 u32 tmp;
f5c5f040 2615
0242f74d
AD		 2616 /* set these so they don't interfere with anything */
2617 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2618 WREG32(RADEON_SUBPIC_CNTL, 0);
2619 WREG32(RADEON_VIPH_CONTROL, 0);
2620 WREG32(RADEON_I2C_CNTL_1, 0);
2621 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2622 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2623 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
f5c5f040 2624
0242f74d
AD		 2625 /* always set up dac2 on rn50 and some rv100 as lots
2626 * of servers seem to wire it up to a VGA port but
2627 * don't report it in the bios connector
2628 * table.
2629 */
2630 switch (dev->pdev->device) {
2631 /* RN50 */
2632 case 0x515e:
2633 case 0x5969:
2634 force_dac2 = true;
2635 break;
2636 /* RV100*/
2637 case 0x5159:
2638 case 0x515a:
2639 /* DELL triple head servers */
2640 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2641 ((dev->pdev->subsystem_device == 0x016c) ||
2642 (dev->pdev->subsystem_device == 0x016d) ||
2643 (dev->pdev->subsystem_device == 0x016e) ||
2644 (dev->pdev->subsystem_device == 0x016f) ||
2645 (dev->pdev->subsystem_device == 0x0170) ||
2646 (dev->pdev->subsystem_device == 0x017d) ||
2647 (dev->pdev->subsystem_device == 0x017e) ||
2648 (dev->pdev->subsystem_device == 0x0183) ||
2649 (dev->pdev->subsystem_device == 0x018a) ||
2650 (dev->pdev->subsystem_device == 0x019a)))
2651 force_dac2 = true;
2652 break;
2653 }
f5c5f040 2654
0242f74d
AD		 2655 if (force_dac2) {
2656 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2657 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2658 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
e024e110 2659
0242f74d
AD		 2660 /* For CRT on DAC2, don't turn it on if BIOS didn't
2661 enable it, even it's detected.
2662 */
c93bb85b 2663
0242f74d
AD		 2664 /* force it to crtc0 */
2665 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2666 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2667 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
c93bb85b 2668
0242f74d
AD		 2669 /* set up the TV DAC */
2670 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2671 RADEON_TV_DAC_STD_MASK |
2672 RADEON_TV_DAC_RDACPD |
2673 RADEON_TV_DAC_GDACPD |
2674 RADEON_TV_DAC_BDACPD |
2675 RADEON_TV_DAC_BGADJ_MASK |
2676 RADEON_TV_DAC_DACADJ_MASK);
2677 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2678 RADEON_TV_DAC_NHOLD |
2679 RADEON_TV_DAC_STD_PS2 |
2680 (0x58 << 16));
f46c0120 2681
0242f74d
AD		 2682 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2683 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2684 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
c93bb85b 2685 }
0242f74d
AD		 2686
2687 /* switch PM block to ACPI mode */
2688 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2689 tmp &= ~RADEON_PM_MODE_SEL;
2690 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2691
2692}
2693
2694/*
2695 * VRAM info
2696 */
2697static void r100_vram_get_type(struct radeon_device *rdev)
2698{
2699 uint32_t tmp;
2700
2701 rdev->mc.vram_is_ddr = false;
2702 if (rdev->flags & RADEON_IS_IGP)
2703 rdev->mc.vram_is_ddr = true;
2704 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2705 rdev->mc.vram_is_ddr = true;
2706 if ((rdev->family == CHIP_RV100) ||
2707 (rdev->family == CHIP_RS100) ||
2708 (rdev->family == CHIP_RS200)) {
2709 tmp = RREG32(RADEON_MEM_CNTL);
2710 if (tmp & RV100_HALF_MODE) {
2711 rdev->mc.vram_width = 32;
2712 } else {
2713 rdev->mc.vram_width = 64;
2714 }
2715 if (rdev->flags & RADEON_SINGLE_CRTC) {
2716 rdev->mc.vram_width /= 4;
2717 rdev->mc.vram_is_ddr = true;
dfee5614 2718 }
0242f74d
AD		 2719 } else if (rdev->family <= CHIP_RV280) {
2720 tmp = RREG32(RADEON_MEM_CNTL);
2721 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2722 rdev->mc.vram_width = 128;
2723 } else {
2724 rdev->mc.vram_width = 64;
2725 }
2726 } else {
2727 /* newer IGPs */
2728 rdev->mc.vram_width = 128;
c93bb85b 2729 }
0242f74d 2730}
c93bb85b 2731
0242f74d
AD		 2732static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2733{
2734 u32 aper_size;
2735 u8 byte;
2736
2737 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2738
2739 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2740 * that is has the 2nd generation multifunction PCI interface
2741 */
2742 if (rdev->family == CHIP_RV280 ||
2743 rdev->family >= CHIP_RV350) {
2744 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2745 ~RADEON_HDP_APER_CNTL);
2746 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2747 return aper_size * 2;
c93bb85b
JG		 2748 }
2749
0242f74d
AD		 2750 /* Older cards have all sorts of funny issues to deal with. First
2751 * check if it's a multifunction card by reading the PCI config
2752 * header type... Limit those to one aperture size
c93bb85b 2753 */
0242f74d
AD		 2754 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2755 if (byte & 0x80) {
2756 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2757 DRM_INFO("Limiting VRAM to one aperture\n");
2758 return aper_size;
2759 }
c93bb85b 2760
0242f74d
AD		 2761 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2762 * have set it up. We don't write this as it's broken on some ASICs but
2763 * we expect the BIOS to have done the right thing (might be too optimistic...)
2764 */
2765 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2766 return aper_size * 2;
2767 return aper_size;
2768}
c93bb85b 2769
0242f74d
AD		 2770void r100_vram_init_sizes(struct radeon_device *rdev)
2771{
2772 u64 config_aper_size;
c93bb85b 2773
0242f74d
AD		 2774 /* work out accessible VRAM */
2775 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2776 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2777 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2778 /* FIXME we don't use the second aperture yet when we could use it */
2779 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2780 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2781 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2782 if (rdev->flags & RADEON_IS_IGP) {
2783 uint32_t tom;
2784 /* read NB_TOM to get the amount of ram stolen for the GPU */
2785 tom = RREG32(RADEON_NB_TOM);
2786 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2787 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2788 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2789 } else {
2790 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2791 /* Some production boards of m6 will report 0
2792 * if it's 8 MB
2793 */
2794 if (rdev->mc.real_vram_size == 0) {
2795 rdev->mc.real_vram_size = 8192 * 1024;
2796 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2797 }
2798 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2799 * Novell bug 204882 + along with lots of ubuntu ones
2800 */
2801 if (rdev->mc.aper_size > config_aper_size)
2802 config_aper_size = rdev->mc.aper_size;
2803
2804 if (config_aper_size > rdev->mc.real_vram_size)
2805 rdev->mc.mc_vram_size = config_aper_size;
2806 else
2807 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
c93bb85b 2808 }
0242f74d 2809}
c93bb85b 2810
0242f74d
AD		 2811void r100_vga_set_state(struct radeon_device *rdev, bool state)
2812{
2813 uint32_t temp;
2814
2815 temp = RREG32(RADEON_CONFIG_CNTL);
2816 if (state == false) {
2817 temp &= ~RADEON_CFG_VGA_RAM_EN;
2818 temp |= RADEON_CFG_VGA_IO_DIS;
2819 } else {
2820 temp &= ~RADEON_CFG_VGA_IO_DIS;
c93bb85b 2821 }
0242f74d
AD		 2822 WREG32(RADEON_CONFIG_CNTL, temp);
2823}
c93bb85b 2824
1109ca09 2825static void r100_mc_init(struct radeon_device *rdev)
0242f74d
AD		 2826{
2827 u64 base;
c93bb85b 2828
0242f74d
AD		 2829 r100_vram_get_type(rdev);
2830 r100_vram_init_sizes(rdev);
2831 base = rdev->mc.aper_base;
2832 if (rdev->flags & RADEON_IS_IGP)
2833 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2834 radeon_vram_location(rdev, &rdev->mc, base);
2835 rdev->mc.gtt_base_align = 0;
2836 if (!(rdev->flags & RADEON_IS_AGP))
2837 radeon_gtt_location(rdev, &rdev->mc);
2838 radeon_update_bandwidth_info(rdev);
2839}
2840
2841
2842/*
2843 * Indirect registers accessor
2844 */
2845void r100_pll_errata_after_index(struct radeon_device *rdev)
2846{
2847 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2848 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2849 (void)RREG32(RADEON_CRTC_GEN_CNTL);
c93bb85b 2850 }
0242f74d 2851}
c93bb85b 2852
0242f74d
AD		 2853static void r100_pll_errata_after_data(struct radeon_device *rdev)
2854{
2855 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2856 * or the chip could hang on a subsequent access
2857 */
2858 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2859 mdelay(5);
c93bb85b
JG		 2860 }
2861
0242f74d
AD		 2862 /* This function is required to workaround a hardware bug in some (all?)
2863 * revisions of the R300. This workaround should be called after every
2864 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2865 * may not be correct.
2866 */
2867 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2868 uint32_t save, tmp;
c93bb85b 2869
0242f74d
AD		 2870 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2871 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2872 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2873 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2874 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
c93bb85b 2875 }
0242f74d 2876}
c93bb85b 2877
0242f74d
AD		 2878uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2879{
0a5b7b0b 2880 unsigned long flags;
0242f74d 2881 uint32_t data;
c93bb85b 2882
0a5b7b0b 2883 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2884 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2885 r100_pll_errata_after_index(rdev);
2886 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2887 r100_pll_errata_after_data(rdev);
0a5b7b0b 2888 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2889 return data;
2890}
c93bb85b 2891
0242f74d
AD		 2892void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2893{
0a5b7b0b
AD		 2894 unsigned long flags;
2895
2896 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2897 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2898 r100_pll_errata_after_index(rdev);
2899 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2900 r100_pll_errata_after_data(rdev);
0a5b7b0b 2901 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2902}
2903
1109ca09 2904static void r100_set_safe_registers(struct radeon_device *rdev)
0242f74d
AD		 2905{
2906 if (ASIC_IS_RN50(rdev)) {
2907 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2908 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2909 } else if (rdev->family < CHIP_R200) {
2910 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2911 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
c93bb85b 2912 } else {
0242f74d 2913 r200_set_safe_registers(rdev);
c93bb85b 2914 }
0242f74d 2915}
c93bb85b 2916
0242f74d
AD		 2917/*
2918 * Debugfs info
2919 */
2920#if defined(CONFIG_DEBUG_FS)
2921static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2922{
2923 struct drm_info_node *node = (struct drm_info_node *) m->private;
2924 struct drm_device *dev = node->minor->dev;
2925 struct radeon_device *rdev = dev->dev_private;
2926 uint32_t reg, value;
2927 unsigned i;
c93bb85b 2928
0242f74d
AD		 2929 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2930 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2931 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2932 for (i = 0; i < 64; i++) {
2933 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2934 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2935 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2936 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2937 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2938 }
2939 return 0;
2940}
c93bb85b 2941
0242f74d
AD		 2942static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2943{
2944 struct drm_info_node *node = (struct drm_info_node *) m->private;
2945 struct drm_device *dev = node->minor->dev;
2946 struct radeon_device *rdev = dev->dev_private;
2947 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2948 uint32_t rdp, wdp;
2949 unsigned count, i, j;
c93bb85b 2950
0242f74d
AD		 2951 radeon_ring_free_size(rdev, ring);
2952 rdp = RREG32(RADEON_CP_RB_RPTR);
2953 wdp = RREG32(RADEON_CP_RB_WPTR);
2954 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2955 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2956 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2957 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2958 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2959 seq_printf(m, "%u dwords in ring\n", count);
0eb3448a
AI		 2960 if (ring->ready) {
2961 for (j = 0; j <= count; j++) {
2962 i = (rdp + j) & ring->ptr_mask;
2963 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2964 }
0242f74d
AD		 2965 }
2966 return 0;
2967}
c93bb85b 2968
c93bb85b 2969
0242f74d
AD		 2970static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2971{
2972 struct drm_info_node *node = (struct drm_info_node *) m->private;
2973 struct drm_device *dev = node->minor->dev;
2974 struct radeon_device *rdev = dev->dev_private;
2975 uint32_t csq_stat, csq2_stat, tmp;
2976 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2977 unsigned i;
c93bb85b 2978
0242f74d
AD		 2979 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2980 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2981 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2982 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2983 r_rptr = (csq_stat >> 0) & 0x3ff;
2984 r_wptr = (csq_stat >> 10) & 0x3ff;
2985 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2986 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2987 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2988 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2989 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2990 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2991 seq_printf(m, "Ring rptr %u\n", r_rptr);
2992 seq_printf(m, "Ring wptr %u\n", r_wptr);
2993 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2994 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2995 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2996 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2997 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2998 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2999 seq_printf(m, "Ring fifo:\n");
3000 for (i = 0; i < 256; i++) {
3001 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3002 tmp = RREG32(RADEON_CP_CSQ_DATA);
3003 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3004 }
3005 seq_printf(m, "Indirect1 fifo:\n");
3006 for (i = 256; i <= 512; i++) {
3007 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3008 tmp = RREG32(RADEON_CP_CSQ_DATA);
3009 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3010 }
3011 seq_printf(m, "Indirect2 fifo:\n");
3012 for (i = 640; i < ib1_wptr; i++) {
3013 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3014 tmp = RREG32(RADEON_CP_CSQ_DATA);
3015 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3016 }
3017 return 0;
3018}
3019
3020static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3021{
3022 struct drm_info_node *node = (struct drm_info_node *) m->private;
3023 struct drm_device *dev = node->minor->dev;
3024 struct radeon_device *rdev = dev->dev_private;
3025 uint32_t tmp;
c93bb85b 3026
0242f74d
AD		 3027 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3028 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3029 tmp = RREG32(RADEON_MC_FB_LOCATION);
3030 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3031 tmp = RREG32(RADEON_BUS_CNTL);
3032 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3033 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3034 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3035 tmp = RREG32(RADEON_AGP_BASE);
3036 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3037 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3038 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3039 tmp = RREG32(0x01D0);
3040 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3041 tmp = RREG32(RADEON_AIC_LO_ADDR);
3042 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3043 tmp = RREG32(RADEON_AIC_HI_ADDR);
3044 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3045 tmp = RREG32(0x01E4);
3046 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3047 return 0;
3048}
c93bb85b 3049
0242f74d
AD		 3050static struct drm_info_list r100_debugfs_rbbm_list[] = {
3051 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3052};
c93bb85b 3053
0242f74d
AD		 3054static struct drm_info_list r100_debugfs_cp_list[] = {
3055 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3056 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3057};
c93bb85b 3058
0242f74d
AD		 3059static struct drm_info_list r100_debugfs_mc_info_list[] = {
3060 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3061};
3062#endif
c93bb85b 3063
0242f74d
AD		 3064int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3065{
3066#if defined(CONFIG_DEBUG_FS)
3067 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3068#else
3069 return 0;
3070#endif
3071}
c93bb85b 3072
0242f74d
AD		 3073int r100_debugfs_cp_init(struct radeon_device *rdev)
3074{
3075#if defined(CONFIG_DEBUG_FS)
3076 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3077#else
3078 return 0;
3079#endif
3080}
c93bb85b 3081
0242f74d
AD		 3082int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3083{
3084#if defined(CONFIG_DEBUG_FS)
3085 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3086#else
3087 return 0;
3088#endif
3089}
c93bb85b 3090
0242f74d
AD		 3091int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3092 uint32_t tiling_flags, uint32_t pitch,
3093 uint32_t offset, uint32_t obj_size)
3094{
3095 int surf_index = reg * 16;
3096 int flags = 0;
c93bb85b 3097
0242f74d
AD		 3098 if (rdev->family <= CHIP_RS200) {
3099 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3100 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3101 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3102 if (tiling_flags & RADEON_TILING_MACRO)
3103 flags |= RADEON_SURF_TILE_COLOR_MACRO;
67d5ced5
AD		 3104 /* setting pitch to 0 disables tiling */
3105 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3106 == 0)
3107 pitch = 0;
0242f74d
AD		 3108 } else if (rdev->family <= CHIP_RV280) {
3109 if (tiling_flags & (RADEON_TILING_MACRO))
3110 flags |= R200_SURF_TILE_COLOR_MACRO;
3111 if (tiling_flags & RADEON_TILING_MICRO)
3112 flags |= R200_SURF_TILE_COLOR_MICRO;
3113 } else {
3114 if (tiling_flags & RADEON_TILING_MACRO)
3115 flags |= R300_SURF_TILE_MACRO;
3116 if (tiling_flags & RADEON_TILING_MICRO)
3117 flags |= R300_SURF_TILE_MICRO;
3118 }
c93bb85b 3119
0242f74d
AD		 3120 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3121 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3122 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3123 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3124
0242f74d
AD		 3125 /* r100/r200 divide by 16 */
3126 if (rdev->family < CHIP_R300)
3127 flags |= pitch / 16;
3128 else
3129 flags |= pitch / 8;
c93bb85b 3130
c93bb85b 3131
0242f74d
AD		 3132 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3133 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3134 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3135 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3136 return 0;
3137}
c93bb85b 3138
0242f74d
AD		 3139void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3140{
3141 int surf_index = reg * 16;
3142 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3143}
c93bb85b 3144
0242f74d
AD		 3145void r100_bandwidth_update(struct radeon_device *rdev)
3146{
3147 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3148 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3149 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3150 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3151 fixed20_12 memtcas_ff[8] = {
3152 dfixed_init(1),
3153 dfixed_init(2),
3154 dfixed_init(3),
3155 dfixed_init(0),
3156 dfixed_init_half(1),
3157 dfixed_init_half(2),
3158 dfixed_init(0),
3159 };
3160 fixed20_12 memtcas_rs480_ff[8] = {
3161 dfixed_init(0),
3162 dfixed_init(1),
3163 dfixed_init(2),
3164 dfixed_init(3),
3165 dfixed_init(0),
3166 dfixed_init_half(1),
3167 dfixed_init_half(2),
3168 dfixed_init_half(3),
3169 };
3170 fixed20_12 memtcas2_ff[8] = {
3171 dfixed_init(0),
3172 dfixed_init(1),
3173 dfixed_init(2),
3174 dfixed_init(3),
3175 dfixed_init(4),
3176 dfixed_init(5),
3177 dfixed_init(6),
3178 dfixed_init(7),
3179 };
3180 fixed20_12 memtrbs[8] = {
3181 dfixed_init(1),
3182 dfixed_init_half(1),
3183 dfixed_init(2),
3184 dfixed_init_half(2),
3185 dfixed_init(3),
3186 dfixed_init_half(3),
3187 dfixed_init(4),
3188 dfixed_init_half(4)
3189 };
3190 fixed20_12 memtrbs_r4xx[8] = {
3191 dfixed_init(4),
3192 dfixed_init(5),
3193 dfixed_init(6),
3194 dfixed_init(7),
3195 dfixed_init(8),
3196 dfixed_init(9),
3197 dfixed_init(10),
3198 dfixed_init(11)
3199 };
3200 fixed20_12 min_mem_eff;
3201 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3202 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3203 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3204 disp_drain_rate2, read_return_rate;
3205 fixed20_12 time_disp1_drop_priority;
3206 int c;
3207 int cur_size = 16; /* in octawords */
3208 int critical_point = 0, critical_point2;
3209/* uint32_t read_return_rate, time_disp1_drop_priority; */
3210 int stop_req, max_stop_req;
3211 struct drm_display_mode *mode1 = NULL;
3212 struct drm_display_mode *mode2 = NULL;
3213 uint32_t pixel_bytes1 = 0;
3214 uint32_t pixel_bytes2 = 0;
c93bb85b 3215
8efe82ca
AD		 3216 if (!rdev->mode_info.mode_config_initialized)
3217 return;
3218
0242f74d 3219 radeon_update_display_priority(rdev);
c93bb85b 3220
0242f74d
AD		 3221 if (rdev->mode_info.crtcs[0]->base.enabled) {
3222 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
f4510a27 3223 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
0242f74d
AD		 3224 }
3225 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3226 if (rdev->mode_info.crtcs[1]->base.enabled) {
3227 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
f4510a27 3228 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
0242f74d
AD		 3229 }
3230 }
c93bb85b 3231
0242f74d
AD		 3232 min_mem_eff.full = dfixed_const_8(0);
3233 /* get modes */
3234 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3235 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3236 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3237 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3238 /* check crtc enables */
3239 if (mode2)
3240 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3241 if (mode1)
3242 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3243 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3244 }
c93bb85b 3245
0242f74d
AD		 3246 /*
3247 * determine is there is enough bw for current mode
3248 */
3249 sclk_ff = rdev->pm.sclk;
3250 mclk_ff = rdev->pm.mclk;
c93bb85b 3251
0242f74d
AD		 3252 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3253 temp_ff.full = dfixed_const(temp);
3254 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b 3255
0242f74d
AD		 3256 pix_clk.full = 0;
3257 pix_clk2.full = 0;
3258 peak_disp_bw.full = 0;
3259 if (mode1) {
3260 temp_ff.full = dfixed_const(1000);
3261 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3262 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3263 temp_ff.full = dfixed_const(pixel_bytes1);
3264 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3265 }
3266 if (mode2) {
3267 temp_ff.full = dfixed_const(1000);
3268 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3269 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3270 temp_ff.full = dfixed_const(pixel_bytes2);
3271 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3272 }
c93bb85b 3273
0242f74d
AD		 3274 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3275 if (peak_disp_bw.full >= mem_bw.full) {
3276 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3277 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3278 }
c93bb85b 3279
0242f74d
AD		 3280 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3281 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3282 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3283 mem_trcd = ((temp >> 2) & 0x3) + 1;
3284 mem_trp = ((temp & 0x3)) + 1;
3285 mem_tras = ((temp & 0x70) >> 4) + 1;
3286 } else if (rdev->family == CHIP_R300 ||
3287 rdev->family == CHIP_R350) { /* r300, r350 */
3288 mem_trcd = (temp & 0x7) + 1;
3289 mem_trp = ((temp >> 8) & 0x7) + 1;
3290 mem_tras = ((temp >> 11) & 0xf) + 4;
3291 } else if (rdev->family == CHIP_RV350 ||
3292 rdev->family <= CHIP_RV380) {
3293 /* rv3x0 */
3294 mem_trcd = (temp & 0x7) + 3;
3295 mem_trp = ((temp >> 8) & 0x7) + 3;
3296 mem_tras = ((temp >> 11) & 0xf) + 6;
3297 } else if (rdev->family == CHIP_R420 ||
3298 rdev->family == CHIP_R423 ||
3299 rdev->family == CHIP_RV410) {
3300 /* r4xx */
3301 mem_trcd = (temp & 0xf) + 3;
3302 if (mem_trcd > 15)
3303 mem_trcd = 15;
3304 mem_trp = ((temp >> 8) & 0xf) + 3;
3305 if (mem_trp > 15)
3306 mem_trp = 15;
3307 mem_tras = ((temp >> 12) & 0x1f) + 6;
3308 if (mem_tras > 31)
3309 mem_tras = 31;
3310 } else { /* RV200, R200 */
3311 mem_trcd = (temp & 0x7) + 1;
3312 mem_trp = ((temp >> 8) & 0x7) + 1;
3313 mem_tras = ((temp >> 12) & 0xf) + 4;
3314 }
3315 /* convert to FF */
3316 trcd_ff.full = dfixed_const(mem_trcd);
3317 trp_ff.full = dfixed_const(mem_trp);
3318 tras_ff.full = dfixed_const(mem_tras);
c93bb85b 3319
0242f74d
AD		 3320 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3321 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3322 data = (temp & (7 << 20)) >> 20;
3323 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3324 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3325 tcas_ff = memtcas_rs480_ff[data];
3326 else
3327 tcas_ff = memtcas_ff[data];
3328 } else
3329 tcas_ff = memtcas2_ff[data];
c93bb85b 3330
0242f74d
AD		 3331 if (rdev->family == CHIP_RS400 ||
3332 rdev->family == CHIP_RS480) {
3333 /* extra cas latency stored in bits 23-25 0-4 clocks */
3334 data = (temp >> 23) & 0x7;
3335 if (data < 5)
3336 tcas_ff.full += dfixed_const(data);
c93bb85b 3337 }
551ebd83 3338
0242f74d
AD		 3339 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3340 /* on the R300, Tcas is included in Trbs.
3341 */
3342 temp = RREG32(RADEON_MEM_CNTL);
3343 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3344 if (data == 1) {
3345 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3346 temp = RREG32(R300_MC_IND_INDEX);
3347 temp &= ~R300_MC_IND_ADDR_MASK;
3348 temp |= R300_MC_READ_CNTL_CD_mcind;
3349 WREG32(R300_MC_IND_INDEX, temp);
3350 temp = RREG32(R300_MC_IND_DATA);
3351 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3352 } else {
3353 temp = RREG32(R300_MC_READ_CNTL_AB);
3354 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3355 }
3356 } else {
3357 temp = RREG32(R300_MC_READ_CNTL_AB);
3358 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3359 }
3360 if (rdev->family == CHIP_RV410 ||
3361 rdev->family == CHIP_R420 ||
3362 rdev->family == CHIP_R423)
3363 trbs_ff = memtrbs_r4xx[data];
3364 else
3365 trbs_ff = memtrbs[data];
3366 tcas_ff.full += trbs_ff.full;
3367 }
551ebd83 3368
0242f74d 3369 sclk_eff_ff.full = sclk_ff.full;
d785d78b 3370
0242f74d
AD		 3371 if (rdev->flags & RADEON_IS_AGP) {
3372 fixed20_12 agpmode_ff;
3373 agpmode_ff.full = dfixed_const(radeon_agpmode);
3374 temp_ff.full = dfixed_const_666(16);
3375 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3376 }
3377 /* TODO PCIE lanes may affect this - agpmode == 16?? */
d785d78b 3378
0242f74d
AD		 3379 if (ASIC_IS_R300(rdev)) {
3380 sclk_delay_ff.full = dfixed_const(250);
3381 } else {
3382 if ((rdev->family == CHIP_RV100) ||
3383 rdev->flags & RADEON_IS_IGP) {
3384 if (rdev->mc.vram_is_ddr)
3385 sclk_delay_ff.full = dfixed_const(41);
3386 else
3387 sclk_delay_ff.full = dfixed_const(33);
3388 } else {
3389 if (rdev->mc.vram_width == 128)
3390 sclk_delay_ff.full = dfixed_const(57);
3391 else
3392 sclk_delay_ff.full = dfixed_const(41);
3393 }
d785d78b
DA		 3394 }
3395
0242f74d 3396 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
d785d78b 3397
0242f74d
AD		 3398 if (rdev->mc.vram_is_ddr) {
3399 if (rdev->mc.vram_width == 32) {
3400 k1.full = dfixed_const(40);
3401 c = 3;
3402 } else {
3403 k1.full = dfixed_const(20);
3404 c = 1;
3405 }
3406 } else {
3407 k1.full = dfixed_const(40);
3408 c = 3;
3409 }
37cf6b03 3410
0242f74d
AD		 3411 temp_ff.full = dfixed_const(2);
3412 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3413 temp_ff.full = dfixed_const(c);
3414 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3415 temp_ff.full = dfixed_const(4);
3416 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3417 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3418 mc_latency_mclk.full += k1.full;
37cf6b03 3419
0242f74d
AD		 3420 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3421 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
37cf6b03 3422
0242f74d
AD		 3423 /*
3424 HW cursor time assuming worst case of full size colour cursor.
3425 */
3426 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3427 temp_ff.full += trcd_ff.full;
3428 if (temp_ff.full < tras_ff.full)
3429 temp_ff.full = tras_ff.full;
3430 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
37cf6b03 3431
0242f74d
AD		 3432 temp_ff.full = dfixed_const(cur_size);
3433 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3434 /*
3435 Find the total latency for the display data.
3436 */
3437 disp_latency_overhead.full = dfixed_const(8);
3438 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3439 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3440 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
37cf6b03 3441
0242f74d
AD		 3442 if (mc_latency_mclk.full > mc_latency_sclk.full)
3443 disp_latency.full = mc_latency_mclk.full;
3444 else
3445 disp_latency.full = mc_latency_sclk.full;
551ebd83 3446
0242f74d
AD		 3447 /* setup Max GRPH_STOP_REQ default value */
3448 if (ASIC_IS_RV100(rdev))
3449 max_stop_req = 0x5c;
3450 else
3451 max_stop_req = 0x7c;
d785d78b 3452
0242f74d
AD		 3453 if (mode1) {
3454 /* CRTC1
3455 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3456 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3457 */
3458 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
d785d78b 3459
0242f74d
AD		 3460 if (stop_req > max_stop_req)
3461 stop_req = max_stop_req;
551ebd83 3462
0242f74d
AD		 3463 /*
3464 Find the drain rate of the display buffer.
3465 */
3466 temp_ff.full = dfixed_const((16/pixel_bytes1));
3467 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
551ebd83 3468
0242f74d
AD		 3469 /*
3470 Find the critical point of the display buffer.
3471 */
3472 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3473 crit_point_ff.full += dfixed_const_half(0);
a41ceb1c 3474
0242f74d
AD		 3475 critical_point = dfixed_trunc(crit_point_ff);
3476
3477 if (rdev->disp_priority == 2) {
3478 critical_point = 0;
551ebd83 3479 }
40b4a759 3480
0242f74d
AD		 3481 /*
3482 The critical point should never be above max_stop_req-4. Setting
3483 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3484 */
3485 if (max_stop_req - critical_point < 4)
3486 critical_point = 0;
3487
3488 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3489 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3490 critical_point = 0x10;
551ebd83 3491 }
0242f74d
AD		 3492
3493 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3494 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3495 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3496 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3497 if ((rdev->family == CHIP_R350) &&
3498 (stop_req > 0x15)) {
3499 stop_req -= 0x10;
551ebd83 3500 }
0242f74d
AD		 3501 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3502 temp |= RADEON_GRPH_BUFFER_SIZE;
3503 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3504 RADEON_GRPH_CRITICAL_AT_SOF |
3505 RADEON_GRPH_STOP_CNTL);
3506 /*
3507 Write the result into the register.
3508 */
3509 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3510 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
40b4a759 3511
0242f74d
AD		 3512#if 0
3513 if ((rdev->family == CHIP_RS400) ||
3514 (rdev->family == CHIP_RS480)) {
3515 /* attempt to program RS400 disp regs correctly ??? */
3516 temp = RREG32(RS400_DISP1_REG_CNTL);
3517 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3518 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3519 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3520 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3521 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3522 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3523 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3524 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3525 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3526 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3527 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
fff1ce4d 3528 }
0242f74d 3529#endif
fff1ce4d 3530
0242f74d
AD		 3531 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3532 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3533 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
cae94b0a 3534 }
0242f74d
AD		 3535
3536 if (mode2) {
3537 u32 grph2_cntl;
3538 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3539
3540 if (stop_req > max_stop_req)
3541 stop_req = max_stop_req;
3542
3543 /*
3544 Find the drain rate of the display buffer.
3545 */
3546 temp_ff.full = dfixed_const((16/pixel_bytes2));
3547 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3548
3549 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3550 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3551 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3552 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3553 if ((rdev->family == CHIP_R350) &&
3554 (stop_req > 0x15)) {
3555 stop_req -= 0x10;
551ebd83 3556 }
0242f74d
AD		 3557 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3558 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3559 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3560 RADEON_GRPH_CRITICAL_AT_SOF |
3561 RADEON_GRPH_STOP_CNTL);
3562
3563 if ((rdev->family == CHIP_RS100) ||
3564 (rdev->family == CHIP_RS200))
3565 critical_point2 = 0;
3566 else {
3567 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3568 temp_ff.full = dfixed_const(temp);
3569 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3570 if (sclk_ff.full < temp_ff.full)
3571 temp_ff.full = sclk_ff.full;
3572
3573 read_return_rate.full = temp_ff.full;
3574
3575 if (mode1) {
3576 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3577 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3578 } else {
3579 time_disp1_drop_priority.full = 0;
551ebd83 3580 }
0242f74d
AD		 3581 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3582 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3583 crit_point_ff.full += dfixed_const_half(0);
3584
3585 critical_point2 = dfixed_trunc(crit_point_ff);
3586
3587 if (rdev->disp_priority == 2) {
3588 critical_point2 = 0;
551ebd83 3589 }
40b4a759 3590
0242f74d
AD		 3591 if (max_stop_req - critical_point2 < 4)
3592 critical_point2 = 0;
551ebd83 3593
0242f74d 3594 }
551ebd83 3595
0242f74d
AD		 3596 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3597 /* some R300 cards have problem with this set to 0 */
3598 critical_point2 = 0x10;
3599 }
40b4a759 3600
0242f74d
AD		 3601 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3602 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
551ebd83 3603
0242f74d
AD		 3604 if ((rdev->family == CHIP_RS400) ||
3605 (rdev->family == CHIP_RS480)) {
3606#if 0
3607 /* attempt to program RS400 disp2 regs correctly ??? */
3608 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3609 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3610 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3611 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3612 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3613 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3614 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3615 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3616 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3617 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3618 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3619 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3620#endif
3621 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3622 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3623 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3624 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
551ebd83 3625 }
0242f74d
AD		 3626
3627 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3628 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
551ebd83
DA		 3629 }
3630}
3ce0a23d 3631
e32eb50d 3632int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3633{
3634 uint32_t scratch;
3635 uint32_t tmp = 0;
3636 unsigned i;
3637 int r;
3638
3639 r = radeon_scratch_get(rdev, &scratch);
3640 if (r) {
3641 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3642 return r;
3643 }
3644 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3645 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3646 if (r) {
3647 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3648 radeon_scratch_free(rdev, scratch);
3649 return r;
3650 }
e32eb50d
CK		 3651 radeon_ring_write(ring, PACKET0(scratch, 0));
3652 radeon_ring_write(ring, 0xDEADBEEF);
1538a9e0 3653 radeon_ring_unlock_commit(rdev, ring, false);
3ce0a23d
JG		 3654 for (i = 0; i < rdev->usec_timeout; i++) {
3655 tmp = RREG32(scratch);
3656 if (tmp == 0xDEADBEEF) {
3657 break;
3658 }
3659 DRM_UDELAY(1);
3660 }
3661 if (i < rdev->usec_timeout) {
3662 DRM_INFO("ring test succeeded in %d usecs\n", i);
3663 } else {
369d7ec1 3664 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3665 scratch, tmp);
3666 r = -EINVAL;
3667 }
3668 radeon_scratch_free(rdev, scratch);
3669 return r;
3670}
3671
3672void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3673{
e32eb50d 3674 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3675
c7eff978
AD		 3676 if (ring->rptr_save_reg) {
3677 u32 next_rptr = ring->wptr + 2 + 3;
3678 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3679 radeon_ring_write(ring, next_rptr);
3680 }
3681
e32eb50d
CK		 3682 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3683 radeon_ring_write(ring, ib->gpu_addr);
3684 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3685}
3686
f712812e 3687int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3688{
f2e39221 3689 struct radeon_ib ib;
3ce0a23d
JG		 3690 uint32_t scratch;
3691 uint32_t tmp = 0;
3692 unsigned i;
3693 int r;
3694
3695 r = radeon_scratch_get(rdev, &scratch);
3696 if (r) {
3697 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3698 return r;
3699 }
3700 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3701 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3ce0a23d 3702 if (r) {
af026c5b
MD		 3703 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3704 goto free_scratch;
3ce0a23d 3705 }
f2e39221
JG		 3706 ib.ptr[0] = PACKET0(scratch, 0);
3707 ib.ptr[1] = 0xDEADBEEF;
3708 ib.ptr[2] = PACKET2(0);
3709 ib.ptr[3] = PACKET2(0);
3710 ib.ptr[4] = PACKET2(0);
3711 ib.ptr[5] = PACKET2(0);
3712 ib.ptr[6] = PACKET2(0);
3713 ib.ptr[7] = PACKET2(0);
3714 ib.length_dw = 8;
1538a9e0 3715 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3ce0a23d 3716 if (r) {
af026c5b
MD		 3717 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3718 goto free_ib;
3ce0a23d 3719 }
f2e39221 3720 r = radeon_fence_wait(ib.fence, false);
3ce0a23d 3721 if (r) {
af026c5b
MD		 3722 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3723 goto free_ib;
3ce0a23d
JG		 3724 }
3725 for (i = 0; i < rdev->usec_timeout; i++) {
3726 tmp = RREG32(scratch);
3727 if (tmp == 0xDEADBEEF) {
3728 break;
3729 }
3730 DRM_UDELAY(1);
3731 }
3732 if (i < rdev->usec_timeout) {
3733 DRM_INFO("ib test succeeded in %u usecs\n", i);
3734 } else {
62f288cf 3735 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3736 scratch, tmp);
3737 r = -EINVAL;
3738 }
af026c5b 3739free_ib:
3ce0a23d 3740 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3741free_scratch:
3742 radeon_scratch_free(rdev, scratch);
3ce0a23d
JG		 3743 return r;
3744}
9f022ddf 3745
9f022ddf
JG		 3746void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3747{
3748 /* Shutdown CP we shouldn't need to do that but better be safe than
3749 * sorry
3750 */
e32eb50d 3751 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3752 WREG32(R_000740_CP_CSQ_CNTL, 0);
3753
3754 /* Save few CRTC registers */
ca6ffc64 3755 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3756 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3757 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3758 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3759 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3760 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3761 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3762 }
3763
3764 /* Disable VGA aperture access */
ca6ffc64 3765 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3766 /* Disable cursor, overlay, crtc */
3767 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3768 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3769 S_000054_CRTC_DISPLAY_DIS(1));
3770 WREG32(R_000050_CRTC_GEN_CNTL,
3771 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3772 S_000050_CRTC_DISP_REQ_EN_B(1));
3773 WREG32(R_000420_OV0_SCALE_CNTL,
3774 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3775 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3776 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3777 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3778 S_000360_CUR2_LOCK(1));
3779 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3780 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3781 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3782 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3783 WREG32(R_000360_CUR2_OFFSET,
3784 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3785 }
3786}
3787
3788void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3789{
3790 /* Update base address for crtc */
d594e46a 3791 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3792 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3793 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3794 }
3795 /* Restore CRTC registers */
ca6ffc64 3796 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3797 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3798 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3799 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3800 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3801 }
3802}
ca6ffc64
JG		 3803
3804void r100_vga_render_disable(struct radeon_device *rdev)
3805{
d4550907 3806 u32 tmp;
ca6ffc64 3807
d4550907 3808 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3809 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3810}
d4550907
JG		 3811
3812static void r100_debugfs(struct radeon_device *rdev)
3813{
3814 int r;
3815
3816 r = r100_debugfs_mc_info_init(rdev);
3817 if (r)
3818 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3819}
3820
3821static void r100_mc_program(struct radeon_device *rdev)
3822{
3823 struct r100_mc_save save;
3824
3825 /* Stops all mc clients */
3826 r100_mc_stop(rdev, &save);
3827 if (rdev->flags & RADEON_IS_AGP) {
3828 WREG32(R_00014C_MC_AGP_LOCATION,
3829 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3830 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3831 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3832 if (rdev->family > CHIP_RV200)
3833 WREG32(R_00015C_AGP_BASE_2,
3834 upper_32_bits(rdev->mc.agp_base) & 0xff);
3835 } else {
3836 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3837 WREG32(R_000170_AGP_BASE, 0);
3838 if (rdev->family > CHIP_RV200)
3839 WREG32(R_00015C_AGP_BASE_2, 0);
3840 }
3841 /* Wait for mc idle */
3842 if (r100_mc_wait_for_idle(rdev))
3843 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3844 /* Program MC, should be a 32bits limited address space */
3845 WREG32(R_000148_MC_FB_LOCATION,
3846 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3847 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3848 r100_mc_resume(rdev, &save);
3849}
3850
1109ca09 3851static void r100_clock_startup(struct radeon_device *rdev)
d4550907
JG		 3852{
3853 u32 tmp;
3854
3855 if (radeon_dynclks != -1 && radeon_dynclks)
3856 radeon_legacy_set_clock_gating(rdev, 1);
3857 /* We need to force on some of the block */
3858 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3859 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3860 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3861 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3862 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3863}
3864
3865static int r100_startup(struct radeon_device *rdev)
3866{
3867 int r;
3868
92cde00c
AD		 3869 /* set common regs */
3870 r100_set_common_regs(rdev);
3871 /* program mc */
d4550907
JG		 3872 r100_mc_program(rdev);
3873 /* Resume clock */
3874 r100_clock_startup(rdev);
d4550907
JG		 3875 /* Initialize GART (initialize after TTM so we can allocate
3876 * memory through TTM but finalize after TTM) */
17e15b0c 3877 r100_enable_bm(rdev);
d4550907
JG		 3878 if (rdev->flags & RADEON_IS_PCI) {
3879 r = r100_pci_gart_enable(rdev);
3880 if (r)
3881 return r;
3882 }
724c80e1
AD		 3883
3884 /* allocate wb buffer */
3885 r = radeon_wb_init(rdev);
3886 if (r)
3887 return r;
3888
30eb77f4
JG		 3889 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3890 if (r) {
3891 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3892 return r;
3893 }
3894
d4550907 3895 /* Enable IRQ */
e49f3959
AH		 3896 if (!rdev->irq.installed) {
3897 r = radeon_irq_kms_init(rdev);
3898 if (r)
3899 return r;
3900 }
3901
d4550907 3902 r100_irq_set(rdev);
cafe6609 3903 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3904 /* 1M ring buffer */
3905 r = r100_cp_init(rdev, 1024 * 1024);
3906 if (r) {
ec4f2ac4 3907 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3908 return r;
3909 }
b15ba512 3910
2898c348
CK		 3911 r = radeon_ib_pool_init(rdev);
3912 if (r) {
3913 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3914 return r;
2898c348 3915 }
b15ba512 3916
d4550907
JG		 3917 return 0;
3918}
3919
3920int r100_resume(struct radeon_device *rdev)
3921{
6b7746e8
JG		 3922 int r;
3923
d4550907
JG		 3924 /* Make sur GART are not working */
3925 if (rdev->flags & RADEON_IS_PCI)
3926 r100_pci_gart_disable(rdev);
3927 /* Resume clock before doing reset */
3928 r100_clock_startup(rdev);
3929 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3930 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3931 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3932 RREG32(R_000E40_RBBM_STATUS),
3933 RREG32(R_0007C0_CP_STAT));
3934 }
3935 /* post */
3936 radeon_combios_asic_init(rdev->ddev);
3937 /* Resume clock after posting */
3938 r100_clock_startup(rdev);
550e2d92
DA		 3939 /* Initialize surface registers */
3940 radeon_surface_init(rdev);
b15ba512
JG		 3941
3942 rdev->accel_working = true;
6b7746e8
JG		 3943 r = r100_startup(rdev);
3944 if (r) {
3945 rdev->accel_working = false;
3946 }
3947 return r;
d4550907
JG		 3948}
3949
3950int r100_suspend(struct radeon_device *rdev)
3951{
6c7bccea 3952 radeon_pm_suspend(rdev);
d4550907 3953 r100_cp_disable(rdev);
724c80e1 3954 radeon_wb_disable(rdev);
d4550907
JG		 3955 r100_irq_disable(rdev);
3956 if (rdev->flags & RADEON_IS_PCI)
3957 r100_pci_gart_disable(rdev);
3958 return 0;
3959}
3960
3961void r100_fini(struct radeon_device *rdev)
3962{
6c7bccea 3963 radeon_pm_fini(rdev);
d4550907 3964 r100_cp_fini(rdev);
724c80e1 3965 radeon_wb_fini(rdev);
2898c348 3966 radeon_ib_pool_fini(rdev);
d4550907
JG		 3967 radeon_gem_fini(rdev);
3968 if (rdev->flags & RADEON_IS_PCI)
3969 r100_pci_gart_fini(rdev);
d0269ed8 3970 radeon_agp_fini(rdev);
d4550907
JG		 3971 radeon_irq_kms_fini(rdev);
3972 radeon_fence_driver_fini(rdev);
4c788679 3973 radeon_bo_fini(rdev);
d4550907
JG		 3974 radeon_atombios_fini(rdev);
3975 kfree(rdev->bios);
3976 rdev->bios = NULL;
3977}
3978
4c712e6c
DA		 3979/*
3980 * Due to how kexec works, it can leave the hw fully initialised when it
3981 * boots the new kernel. However doing our init sequence with the CP and
3982 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3983 * do some quick sanity checks and restore sane values to avoid this
3984 * problem.
3985 */
3986void r100_restore_sanity(struct radeon_device *rdev)
3987{
3988 u32 tmp;
3989
3990 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3991 if (tmp) {
3992 WREG32(RADEON_CP_CSQ_CNTL, 0);
3993 }
3994 tmp = RREG32(RADEON_CP_RB_CNTL);
3995 if (tmp) {
3996 WREG32(RADEON_CP_RB_CNTL, 0);
3997 }
3998 tmp = RREG32(RADEON_SCRATCH_UMSK);
3999 if (tmp) {
4000 WREG32(RADEON_SCRATCH_UMSK, 0);
4001 }
4002}
4003
d4550907
JG		 4004int r100_init(struct radeon_device *rdev)
4005{
4006 int r;
4007
d4550907
JG		 4008 /* Register debugfs file specific to this group of asics */
4009 r100_debugfs(rdev);
4010 /* Disable VGA */
4011 r100_vga_render_disable(rdev);
4012 /* Initialize scratch registers */
4013 radeon_scratch_init(rdev);
4014 /* Initialize surface registers */
4015 radeon_surface_init(rdev);
4c712e6c
DA		 4016 /* sanity check some register to avoid hangs like after kexec */
4017 r100_restore_sanity(rdev);
d4550907
JG		 4018 /* TODO: disable VGA need to use VGA request */
4019 /* BIOS*/
4020 if (!radeon_get_bios(rdev)) {
4021 if (ASIC_IS_AVIVO(rdev))
4022 return -EINVAL;
4023 }
4024 if (rdev->is_atom_bios) {
4025 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4026 return -EINVAL;
4027 } else {
4028 r = radeon_combios_init(rdev);
4029 if (r)
4030 return r;
4031 }
4032 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4033 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4034 dev_warn(rdev->dev,
4035 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4036 RREG32(R_000E40_RBBM_STATUS),
4037 RREG32(R_0007C0_CP_STAT));
4038 }
4039 /* check if cards are posted or not */
72542d77
DA		 4040 if (radeon_boot_test_post_card(rdev) == false)
4041 return -EINVAL;
d4550907
JG		 4042 /* Set asic errata */
4043 r100_errata(rdev);
4044 /* Initialize clocks */
4045 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4046 /* initialize AGP */
4047 if (rdev->flags & RADEON_IS_AGP) {
4048 r = radeon_agp_init(rdev);
4049 if (r) {
4050 radeon_agp_disable(rdev);
4051 }
4052 }
4053 /* initialize VRAM */
4054 r100_mc_init(rdev);
d4550907 4055 /* Fence driver */
30eb77f4 4056 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4057 if (r)
4058 return r;
d4550907 4059 /* Memory manager */
4c788679 4060 r = radeon_bo_init(rdev);
d4550907
JG		 4061 if (r)
4062 return r;
4063 if (rdev->flags & RADEON_IS_PCI) {
4064 r = r100_pci_gart_init(rdev);
4065 if (r)
4066 return r;
4067 }
4068 r100_set_safe_registers(rdev);
b15ba512 4069
6c7bccea
AD		 4070 /* Initialize power management */
4071 radeon_pm_init(rdev);
4072
d4550907
JG		 4073 rdev->accel_working = true;
4074 r = r100_startup(rdev);
4075 if (r) {
4076 /* Somethings want wront with the accel init stop accel */
4077 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4078 r100_cp_fini(rdev);
724c80e1 4079 radeon_wb_fini(rdev);
2898c348 4080 radeon_ib_pool_fini(rdev);
655efd3d 4081 radeon_irq_kms_fini(rdev);
d4550907
JG		 4082 if (rdev->flags & RADEON_IS_PCI)
4083 r100_pci_gart_fini(rdev);
d4550907
JG		 4084 rdev->accel_working = false;
4085 }
4086 return 0;
4087}
6fcbef7a 4088
6fcbef7a
AK		 4089u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4090{
4091 if (reg < rdev->rio_mem_size)
4092 return ioread32(rdev->rio_mem + reg);
4093 else {
4094 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4095 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4096 }
4097}
4098
4099void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4100{
4101 if (reg < rdev->rio_mem_size)
4102 iowrite32(v, rdev->rio_mem + reg);
4103 else {
4104 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4105 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4106 }
4107}
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