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Merge tag 'drm-intel-next-2012-02-16-merge-resolved' of git://people.freedesktop...
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
e0cd3608 44#include <linux/module.h>
70967ab9 45
551ebd83
DA		 46#include "r100_reg_safe.h"
47#include "rn50_reg_safe.h"
48
70967ab9
BH		 49/* Firmware Names */
50#define FIRMWARE_R100 "radeon/R100_cp.bin"
51#define FIRMWARE_R200 "radeon/R200_cp.bin"
52#define FIRMWARE_R300 "radeon/R300_cp.bin"
53#define FIRMWARE_R420 "radeon/R420_cp.bin"
54#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56#define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58MODULE_FIRMWARE(FIRMWARE_R100);
59MODULE_FIRMWARE(FIRMWARE_R200);
60MODULE_FIRMWARE(FIRMWARE_R300);
61MODULE_FIRMWARE(FIRMWARE_R420);
62MODULE_FIRMWARE(FIRMWARE_RS690);
63MODULE_FIRMWARE(FIRMWARE_RS600);
64MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 65
551ebd83
DA		 66#include "r100_track.h"
67
771fe6b9
JG		 68/* This files gather functions specifics to:
69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 70 */
771fe6b9 71
cbdd4501
AK		 72int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
73 struct radeon_cs_packet *pkt,
74 unsigned idx,
75 unsigned reg)
76{
77 int r;
78 u32 tile_flags = 0;
79 u32 tmp;
80 struct radeon_cs_reloc *reloc;
81 u32 value;
82
83 r = r100_cs_packet_next_reloc(p, &reloc);
84 if (r) {
85 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
86 idx, reg);
87 r100_cs_dump_packet(p, pkt);
88 return r;
89 }
c9068eb2 90
cbdd4501
AK		 91 value = radeon_get_ib_value(p, idx);
92 tmp = value & 0x003fffff;
93 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
94
c9068eb2
AD		 95 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
96 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
97 tile_flags |= RADEON_DST_TILE_MACRO;
98 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
99 if (reg == RADEON_SRC_PITCH_OFFSET) {
100 DRM_ERROR("Cannot src blit from microtiled surface\n");
101 r100_cs_dump_packet(p, pkt);
102 return -EINVAL;
103 }
104 tile_flags |= RADEON_DST_TILE_MICRO;
cbdd4501 105 }
cbdd4501 106
c9068eb2
AD		 107 tmp |= tile_flags;
108 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
109 } else
110 p->ib->ptr[idx] = (value & 0xffc00000) | tmp;
cbdd4501
AK		 111 return 0;
112}
113
114int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
115 struct radeon_cs_packet *pkt,
116 int idx)
117{
118 unsigned c, i;
119 struct radeon_cs_reloc *reloc;
120 struct r100_cs_track *track;
121 int r = 0;
122 volatile uint32_t *ib;
123 u32 idx_value;
124
125 ib = p->ib->ptr;
126 track = (struct r100_cs_track *)p->track;
127 c = radeon_get_ib_value(p, idx++) & 0x1F;
128 if (c > 16) {
129 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
130 pkt->opcode);
131 r100_cs_dump_packet(p, pkt);
132 return -EINVAL;
133 }
134 track->num_arrays = c;
135 for (i = 0; i < (c - 1); i+=2, idx+=3) {
136 r = r100_cs_packet_next_reloc(p, &reloc);
137 if (r) {
138 DRM_ERROR("No reloc for packet3 %d\n",
139 pkt->opcode);
140 r100_cs_dump_packet(p, pkt);
141 return r;
142 }
143 idx_value = radeon_get_ib_value(p, idx);
144 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
145
146 track->arrays[i + 0].esize = idx_value >> 8;
147 track->arrays[i + 0].robj = reloc->robj;
148 track->arrays[i + 0].esize &= 0x7F;
149 r = r100_cs_packet_next_reloc(p, &reloc);
150 if (r) {
151 DRM_ERROR("No reloc for packet3 %d\n",
152 pkt->opcode);
153 r100_cs_dump_packet(p, pkt);
154 return r;
155 }
156 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
157 track->arrays[i + 1].robj = reloc->robj;
158 track->arrays[i + 1].esize = idx_value >> 24;
159 track->arrays[i + 1].esize &= 0x7F;
160 }
161 if (c & 1) {
162 r = r100_cs_packet_next_reloc(p, &reloc);
163 if (r) {
164 DRM_ERROR("No reloc for packet3 %d\n",
165 pkt->opcode);
166 r100_cs_dump_packet(p, pkt);
167 return r;
168 }
169 idx_value = radeon_get_ib_value(p, idx);
170 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
171 track->arrays[i + 0].robj = reloc->robj;
172 track->arrays[i + 0].esize = idx_value >> 8;
173 track->arrays[i + 0].esize &= 0x7F;
174 }
175 return r;
176}
177
6f34be50
AD		 178void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
179{
6f34be50
AD		 180 /* enable the pflip int */
181 radeon_irq_kms_pflip_irq_get(rdev, crtc);
182}
183
184void r100_post_page_flip(struct radeon_device *rdev, int crtc)
185{
186 /* disable the pflip int */
187 radeon_irq_kms_pflip_irq_put(rdev, crtc);
188}
189
190u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
191{
192 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
193 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 194 int i;
6f34be50
AD		 195
196 /* Lock the graphics update lock */
197 /* update the scanout addresses */
198 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
199
acb32506 200 /* Wait for update_pending to go high. */
f6496479
AD		 201 for (i = 0; i < rdev->usec_timeout; i++) {
202 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
203 break;
204 udelay(1);
205 }
acb32506 206 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 207
208 /* Unlock the lock, so double-buffering can take place inside vblank */
209 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
210 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
211
212 /* Return current update_pending status: */
213 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
214}
215
ce8f5370 216void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 217{
218 int i;
ce8f5370
AD		 219 rdev->pm.dynpm_can_upclock = true;
220 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 221
ce8f5370
AD		 222 switch (rdev->pm.dynpm_planned_action) {
223 case DYNPM_ACTION_MINIMUM:
a48b9b4e 224 rdev->pm.requested_power_state_index = 0;
ce8f5370 225 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 226 break;
ce8f5370 227 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 228 if (rdev->pm.current_power_state_index == 0) {
229 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 230 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 231 } else {
232 if (rdev->pm.active_crtc_count > 1) {
233 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 234 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 235 continue;
236 else if (i >= rdev->pm.current_power_state_index) {
237 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
238 break;
239 } else {
240 rdev->pm.requested_power_state_index = i;
241 break;
242 }
243 }
244 } else
245 rdev->pm.requested_power_state_index =
246 rdev->pm.current_power_state_index - 1;
247 }
d7311171
AD		 248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
251 RADEON_PM_MODE_NO_DISPLAY)) {
252 rdev->pm.requested_power_state_index++;
253 }
a48b9b4e 254 break;
ce8f5370 255 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 256 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
257 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 258 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 259 } else {
260 if (rdev->pm.active_crtc_count > 1) {
261 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 262 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 263 continue;
264 else if (i <= rdev->pm.current_power_state_index) {
265 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
266 break;
267 } else {
268 rdev->pm.requested_power_state_index = i;
269 break;
270 }
271 }
272 } else
273 rdev->pm.requested_power_state_index =
274 rdev->pm.current_power_state_index + 1;
275 }
276 break;
ce8f5370 277 case DYNPM_ACTION_DEFAULT:
58e21dff 278 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 279 rdev->pm.dynpm_can_upclock = false;
58e21dff 280 break;
ce8f5370 281 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 282 default:
283 DRM_ERROR("Requested mode for not defined action\n");
284 return;
285 }
286 /* only one clock mode per power state */
287 rdev->pm.requested_clock_mode_index = 0;
288
d9fdaafb 289 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 290 rdev->pm.power_state[rdev->pm.requested_power_state_index].
291 clock_info[rdev->pm.requested_clock_mode_index].sclk,
292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
293 clock_info[rdev->pm.requested_clock_mode_index].mclk,
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
295 pcie_lanes);
a48b9b4e
AD		 296}
297
ce8f5370
AD		 298void r100_pm_init_profile(struct radeon_device *rdev)
299{
300 /* default */
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
305 /* low sh */
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 310 /* mid sh */
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 315 /* high sh */
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
320 /* low mh */
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 325 /* mid mh */
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 330 /* high mh */
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 335}
336
49e02b73
AD		 337void r100_pm_misc(struct radeon_device *rdev)
338{
49e02b73
AD		 339 int requested_index = rdev->pm.requested_power_state_index;
340 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
341 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
342 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
343
344 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
345 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
346 tmp = RREG32(voltage->gpio.reg);
347 if (voltage->active_high)
348 tmp |= voltage->gpio.mask;
349 else
350 tmp &= ~(voltage->gpio.mask);
351 WREG32(voltage->gpio.reg, tmp);
352 if (voltage->delay)
353 udelay(voltage->delay);
354 } else {
355 tmp = RREG32(voltage->gpio.reg);
356 if (voltage->active_high)
357 tmp &= ~voltage->gpio.mask;
358 else
359 tmp |= voltage->gpio.mask;
360 WREG32(voltage->gpio.reg, tmp);
361 if (voltage->delay)
362 udelay(voltage->delay);
363 }
364 }
365
366 sclk_cntl = RREG32_PLL(SCLK_CNTL);
367 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
368 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
369 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
370 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
371 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
372 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
373 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
374 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
375 else
376 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
377 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
378 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
379 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
380 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
381 } else
382 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
383
384 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
385 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
386 if (voltage->delay) {
387 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
388 switch (voltage->delay) {
389 case 33:
390 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
391 break;
392 case 66:
393 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
394 break;
395 case 99:
396 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
397 break;
398 case 132:
399 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
400 break;
401 }
402 } else
403 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
404 } else
405 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
406
407 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
408 sclk_cntl &= ~FORCE_HDP;
409 else
410 sclk_cntl |= FORCE_HDP;
411
412 WREG32_PLL(SCLK_CNTL, sclk_cntl);
413 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
414 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
415
416 /* set pcie lanes */
417 if ((rdev->flags & RADEON_IS_PCIE) &&
418 !(rdev->flags & RADEON_IS_IGP) &&
419 rdev->asic->set_pcie_lanes &&
420 (ps->pcie_lanes !=
421 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
422 radeon_set_pcie_lanes(rdev,
423 ps->pcie_lanes);
d9fdaafb 424 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 425 }
49e02b73
AD		 426}
427
428void r100_pm_prepare(struct radeon_device *rdev)
429{
430 struct drm_device *ddev = rdev->ddev;
431 struct drm_crtc *crtc;
432 struct radeon_crtc *radeon_crtc;
433 u32 tmp;
434
435 /* disable any active CRTCs */
436 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
437 radeon_crtc = to_radeon_crtc(crtc);
438 if (radeon_crtc->enabled) {
439 if (radeon_crtc->crtc_id) {
440 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
441 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
442 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
443 } else {
444 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
445 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
446 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
447 }
448 }
449 }
450}
451
452void r100_pm_finish(struct radeon_device *rdev)
453{
454 struct drm_device *ddev = rdev->ddev;
455 struct drm_crtc *crtc;
456 struct radeon_crtc *radeon_crtc;
457 u32 tmp;
458
459 /* enable any active CRTCs */
460 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
461 radeon_crtc = to_radeon_crtc(crtc);
462 if (radeon_crtc->enabled) {
463 if (radeon_crtc->crtc_id) {
464 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
465 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
466 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
467 } else {
468 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
469 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
470 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
471 }
472 }
473 }
474}
475
def9ba9c
AD		 476bool r100_gui_idle(struct radeon_device *rdev)
477{
478 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
479 return false;
480 else
481 return true;
482}
483
05a05c50
AD		 484/* hpd for digital panel detect/disconnect */
485bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
486{
487 bool connected = false;
488
489 switch (hpd) {
490 case RADEON_HPD_1:
491 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
492 connected = true;
493 break;
494 case RADEON_HPD_2:
495 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
496 connected = true;
497 break;
498 default:
499 break;
500 }
501 return connected;
502}
503
504void r100_hpd_set_polarity(struct radeon_device *rdev,
505 enum radeon_hpd_id hpd)
506{
507 u32 tmp;
508 bool connected = r100_hpd_sense(rdev, hpd);
509
510 switch (hpd) {
511 case RADEON_HPD_1:
512 tmp = RREG32(RADEON_FP_GEN_CNTL);
513 if (connected)
514 tmp &= ~RADEON_FP_DETECT_INT_POL;
515 else
516 tmp |= RADEON_FP_DETECT_INT_POL;
517 WREG32(RADEON_FP_GEN_CNTL, tmp);
518 break;
519 case RADEON_HPD_2:
520 tmp = RREG32(RADEON_FP2_GEN_CNTL);
521 if (connected)
522 tmp &= ~RADEON_FP2_DETECT_INT_POL;
523 else
524 tmp |= RADEON_FP2_DETECT_INT_POL;
525 WREG32(RADEON_FP2_GEN_CNTL, tmp);
526 break;
527 default:
528 break;
529 }
530}
531
532void r100_hpd_init(struct radeon_device *rdev)
533{
534 struct drm_device *dev = rdev->ddev;
535 struct drm_connector *connector;
536
537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
538 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
539 switch (radeon_connector->hpd.hpd) {
540 case RADEON_HPD_1:
541 rdev->irq.hpd[0] = true;
542 break;
543 case RADEON_HPD_2:
544 rdev->irq.hpd[1] = true;
545 break;
546 default:
547 break;
548 }
64912e99 549 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 550 }
003e69f9
JG		 551 if (rdev->irq.installed)
552 r100_irq_set(rdev);
05a05c50
AD		 553}
554
555void r100_hpd_fini(struct radeon_device *rdev)
556{
557 struct drm_device *dev = rdev->ddev;
558 struct drm_connector *connector;
559
560 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
561 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
562 switch (radeon_connector->hpd.hpd) {
563 case RADEON_HPD_1:
564 rdev->irq.hpd[0] = false;
565 break;
566 case RADEON_HPD_2:
567 rdev->irq.hpd[1] = false;
568 break;
569 default:
570 break;
571 }
572 }
573}
574
771fe6b9
JG		 575/*
576 * PCI GART
577 */
578void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
579{
580 /* TODO: can we do somethings here ? */
581 /* It seems hw only cache one entry so we should discard this
582 * entry otherwise if first GPU GART read hit this entry it
583 * could end up in wrong address. */
584}
585
4aac0473 586int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 587{
771fe6b9
JG		 588 int r;
589
c9a1be96 590 if (rdev->gart.ptr) {
fce7d61b 591 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 592 return 0;
593 }
771fe6b9
JG		 594 /* Initialize common gart structure */
595 r = radeon_gart_init(rdev);
4aac0473 596 if (r)
771fe6b9 597 return r;
4aac0473
JG		 598 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
599 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
600 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
601 return radeon_gart_table_ram_alloc(rdev);
602}
603
17e15b0c
DA		 604/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
605void r100_enable_bm(struct radeon_device *rdev)
606{
607 uint32_t tmp;
608 /* Enable bus mastering */
609 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
610 WREG32(RADEON_BUS_CNTL, tmp);
611}
612
4aac0473
JG		 613int r100_pci_gart_enable(struct radeon_device *rdev)
614{
615 uint32_t tmp;
616
82568565 617 radeon_gart_restore(rdev);
771fe6b9
JG		 618 /* discard memory request outside of configured range */
619 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
620 WREG32(RADEON_AIC_CNTL, tmp);
621 /* set address range for PCI address translate */
d594e46a
JG		 622 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
623 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 624 /* set PCI GART page-table base address */
625 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
626 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
627 WREG32(RADEON_AIC_CNTL, tmp);
628 r100_pci_gart_tlb_flush(rdev);
fcf4de5a
TV		 629 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
630 (unsigned)(rdev->mc.gtt_size >> 20),
631 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 632 rdev->gart.ready = true;
633 return 0;
634}
635
636void r100_pci_gart_disable(struct radeon_device *rdev)
637{
638 uint32_t tmp;
639
640 /* discard memory request outside of configured range */
641 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
642 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
643 WREG32(RADEON_AIC_LO_ADDR, 0);
644 WREG32(RADEON_AIC_HI_ADDR, 0);
645}
646
647int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
648{
c9a1be96
JG		 649 u32 *gtt = rdev->gart.ptr;
650
771fe6b9
JG		 651 if (i < 0 || i > rdev->gart.num_gpu_pages) {
652 return -EINVAL;
653 }
c9a1be96 654 gtt[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 655 return 0;
656}
657
4aac0473 658void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 659{
f9274562 660 radeon_gart_fini(rdev);
4aac0473
JG		 661 r100_pci_gart_disable(rdev);
662 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 663}
664
7ed220d7
MD		 665int r100_irq_set(struct radeon_device *rdev)
666{
667 uint32_t tmp = 0;
668
003e69f9 669 if (!rdev->irq.installed) {
fce7d61b 670 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 671 WREG32(R_000040_GEN_INT_CNTL, 0);
672 return -EINVAL;
673 }
1b37078b 674 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
7ed220d7
MD		 675 tmp |= RADEON_SW_INT_ENABLE;
676 }
2031f77c
AD		 677 if (rdev->irq.gui_idle) {
678 tmp |= RADEON_GUI_IDLE_MASK;
679 }
6f34be50
AD		 680 if (rdev->irq.crtc_vblank_int[0] ||
681 rdev->irq.pflip[0]) {
7ed220d7
MD		 682 tmp |= RADEON_CRTC_VBLANK_MASK;
683 }
6f34be50
AD		 684 if (rdev->irq.crtc_vblank_int[1] ||
685 rdev->irq.pflip[1]) {
7ed220d7
MD		 686 tmp |= RADEON_CRTC2_VBLANK_MASK;
687 }
05a05c50
AD		 688 if (rdev->irq.hpd[0]) {
689 tmp |= RADEON_FP_DETECT_MASK;
690 }
691 if (rdev->irq.hpd[1]) {
692 tmp |= RADEON_FP2_DETECT_MASK;
693 }
7ed220d7
MD		 694 WREG32(RADEON_GEN_INT_CNTL, tmp);
695 return 0;
696}
697
9f022ddf
JG		 698void r100_irq_disable(struct radeon_device *rdev)
699{
700 u32 tmp;
701
702 WREG32(R_000040_GEN_INT_CNTL, 0);
703 /* Wait and acknowledge irq */
704 mdelay(1);
705 tmp = RREG32(R_000044_GEN_INT_STATUS);
706 WREG32(R_000044_GEN_INT_STATUS, tmp);
707}
708
cbdd4501 709static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 710{
711 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 712 uint32_t irq_mask = RADEON_SW_INT_TEST |
713 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
714 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7 715
2031f77c
AD		 716 /* the interrupt works, but the status bit is permanently asserted */
717 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
718 if (!rdev->irq.gui_idle_acked)
719 irq_mask |= RADEON_GUI_IDLE_STAT;
720 }
721
7ed220d7
MD		 722 if (irqs) {
723 WREG32(RADEON_GEN_INT_STATUS, irqs);
724 }
725 return irqs & irq_mask;
726}
727
728int r100_irq_process(struct radeon_device *rdev)
729{
3e5cb98d 730 uint32_t status, msi_rearm;
d4877cf2 731 bool queue_hotplug = false;
7ed220d7 732
2031f77c
AD		 733 /* reset gui idle ack. the status bit is broken */
734 rdev->irq.gui_idle_acked = false;
735
7ed220d7
MD		 736 status = r100_irq_ack(rdev);
737 if (!status) {
738 return IRQ_NONE;
739 }
a513c184
JG		 740 if (rdev->shutdown) {
741 return IRQ_NONE;
742 }
7ed220d7
MD		 743 while (status) {
744 /* SW interrupt */
745 if (status & RADEON_SW_INT_TEST) {
7465280c 746 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7 747 }
2031f77c
AD		 748 /* gui idle interrupt */
749 if (status & RADEON_GUI_IDLE_STAT) {
750 rdev->irq.gui_idle_acked = true;
751 rdev->pm.gui_idle = true;
752 wake_up(&rdev->irq.idle_queue);
753 }
7ed220d7
MD		 754 /* Vertical blank interrupts */
755 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 756 if (rdev->irq.crtc_vblank_int[0]) {
757 drm_handle_vblank(rdev->ddev, 0);
758 rdev->pm.vblank_sync = true;
759 wake_up(&rdev->irq.vblank_queue);
760 }
3e4ea742
MK		 761 if (rdev->irq.pflip[0])
762 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 763 }
764 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 765 if (rdev->irq.crtc_vblank_int[1]) {
766 drm_handle_vblank(rdev->ddev, 1);
767 rdev->pm.vblank_sync = true;
768 wake_up(&rdev->irq.vblank_queue);
769 }
3e4ea742
MK		 770 if (rdev->irq.pflip[1])
771 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 772 }
05a05c50 773 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 774 queue_hotplug = true;
775 DRM_DEBUG("HPD1\n");
05a05c50
AD		 776 }
777 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 778 queue_hotplug = true;
779 DRM_DEBUG("HPD2\n");
05a05c50 780 }
7ed220d7
MD		 781 status = r100_irq_ack(rdev);
782 }
2031f77c
AD		 783 /* reset gui idle ack. the status bit is broken */
784 rdev->irq.gui_idle_acked = false;
d4877cf2 785 if (queue_hotplug)
32c87fca 786 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 787 if (rdev->msi_enabled) {
788 switch (rdev->family) {
789 case CHIP_RS400:
790 case CHIP_RS480:
791 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
792 WREG32(RADEON_AIC_CNTL, msi_rearm);
793 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
794 break;
795 default:
796 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
797 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
798 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
799 break;
800 }
801 }
7ed220d7
MD		 802 return IRQ_HANDLED;
803}
804
805u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
806{
807 if (crtc == 0)
808 return RREG32(RADEON_CRTC_CRNT_FRAME);
809 else
810 return RREG32(RADEON_CRTC2_CRNT_FRAME);
811}
812
9e5b2af7
PN		 813/* Who ever call radeon_fence_emit should call ring_lock and ask
814 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 815void r100_fence_ring_emit(struct radeon_device *rdev,
816 struct radeon_fence *fence)
817{
e32eb50d 818 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 819
9e5b2af7
PN		 820 /* We have to make sure that caches are flushed before
821 * CPU might read something from VRAM. */
e32eb50d
CK		 822 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
823 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
824 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
825 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 826 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 827 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
828 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
829 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
830 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
cafe6609 831 RADEON_HDP_READ_BUFFER_INVALIDATE);
e32eb50d
CK		 832 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
833 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
771fe6b9 834 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 835 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
836 radeon_ring_write(ring, fence->seq);
837 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
838 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 839}
840
15d3332f 841void r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 842 struct radeon_ring *ring,
15d3332f 843 struct radeon_semaphore *semaphore,
7b1f2485 844 bool emit_wait)
15d3332f
CK		 845{
846 /* Unused on older asics, since we don't have semaphores or multiple rings */
847 BUG();
848}
849
771fe6b9
JG		 850int r100_copy_blit(struct radeon_device *rdev,
851 uint64_t src_offset,
852 uint64_t dst_offset,
003cefe0 853 unsigned num_gpu_pages,
771fe6b9
JG		 854 struct radeon_fence *fence)
855{
e32eb50d 856 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9 857 uint32_t cur_pages;
003cefe0 858 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 859 uint32_t pitch;
860 uint32_t stride_pixels;
861 unsigned ndw;
862 int num_loops;
863 int r = 0;
864
865 /* radeon limited to 16k stride */
866 stride_bytes &= 0x3fff;
867 /* radeon pitch is /64 */
868 pitch = stride_bytes / 64;
869 stride_pixels = stride_bytes / 4;
003cefe0 870 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 871
872 /* Ask for enough room for blit + flush + fence */
873 ndw = 64 + (10 * num_loops);
e32eb50d 874 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 875 if (r) {
876 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
877 return -EINVAL;
878 }
003cefe0
AD		 879 while (num_gpu_pages > 0) {
880 cur_pages = num_gpu_pages;
771fe6b9
JG		 881 if (cur_pages > 8191) {
882 cur_pages = 8191;
883 }
003cefe0 884 num_gpu_pages -= cur_pages;
771fe6b9
JG		 885
886 /* pages are in Y direction - height
887 page width in X direction - width */
e32eb50d
CK		 888 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
889 radeon_ring_write(ring,
771fe6b9
JG		 890 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
891 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
892 RADEON_GMC_SRC_CLIPPING |
893 RADEON_GMC_DST_CLIPPING |
894 RADEON_GMC_BRUSH_NONE |
895 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
896 RADEON_GMC_SRC_DATATYPE_COLOR |
897 RADEON_ROP3_S |
898 RADEON_DP_SRC_SOURCE_MEMORY |
899 RADEON_GMC_CLR_CMP_CNTL_DIS |
900 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 901 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
902 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
903 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
904 radeon_ring_write(ring, 0);
905 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
906 radeon_ring_write(ring, num_gpu_pages);
907 radeon_ring_write(ring, num_gpu_pages);
908 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
909 }
910 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
911 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
912 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
913 radeon_ring_write(ring,
771fe6b9
JG		 914 RADEON_WAIT_2D_IDLECLEAN |
915 RADEON_WAIT_HOST_IDLECLEAN |
916 RADEON_WAIT_DMA_GUI_IDLE);
917 if (fence) {
918 r = radeon_fence_emit(rdev, fence);
919 }
e32eb50d 920 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 921 return r;
922}
923
45600232
JG		 924static int r100_cp_wait_for_idle(struct radeon_device *rdev)
925{
926 unsigned i;
927 u32 tmp;
928
929 for (i = 0; i < rdev->usec_timeout; i++) {
930 tmp = RREG32(R_000E40_RBBM_STATUS);
931 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
932 return 0;
933 }
934 udelay(1);
935 }
936 return -1;
937}
938
771fe6b9
JG		 939void r100_ring_start(struct radeon_device *rdev)
940{
e32eb50d 941 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 942 int r;
943
e32eb50d 944 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 945 if (r) {
946 return;
947 }
e32eb50d
CK		 948 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
949 radeon_ring_write(ring,
771fe6b9
JG		 950 RADEON_ISYNC_ANY2D_IDLE3D |
951 RADEON_ISYNC_ANY3D_IDLE2D |
952 RADEON_ISYNC_WAIT_IDLEGUI |
953 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
e32eb50d 954 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 955}
956
70967ab9
BH		 957
958/* Load the microcode for the CP */
959static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 960{
70967ab9
BH		 961 struct platform_device *pdev;
962 const char *fw_name = NULL;
963 int err;
771fe6b9 964
d9fdaafb 965 DRM_DEBUG_KMS("\n");
771fe6b9 966
70967ab9
BH		 967 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
968 err = IS_ERR(pdev);
969 if (err) {
970 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
971 return -EINVAL;
972 }
771fe6b9
JG		 973 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
974 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
975 (rdev->family == CHIP_RS200)) {
976 DRM_INFO("Loading R100 Microcode\n");
70967ab9 977 fw_name = FIRMWARE_R100;
771fe6b9
JG		 978 } else if ((rdev->family == CHIP_R200) ||
979 (rdev->family == CHIP_RV250) ||
980 (rdev->family == CHIP_RV280) ||
981 (rdev->family == CHIP_RS300)) {
982 DRM_INFO("Loading R200 Microcode\n");
70967ab9 983 fw_name = FIRMWARE_R200;
771fe6b9
JG		 984 } else if ((rdev->family == CHIP_R300) ||
985 (rdev->family == CHIP_R350) ||
986 (rdev->family == CHIP_RV350) ||
987 (rdev->family == CHIP_RV380) ||
988 (rdev->family == CHIP_RS400) ||
989 (rdev->family == CHIP_RS480)) {
990 DRM_INFO("Loading R300 Microcode\n");
70967ab9 991 fw_name = FIRMWARE_R300;
771fe6b9
JG		 992 } else if ((rdev->family == CHIP_R420) ||
993 (rdev->family == CHIP_R423) ||
994 (rdev->family == CHIP_RV410)) {
995 DRM_INFO("Loading R400 Microcode\n");
70967ab9 996 fw_name = FIRMWARE_R420;
771fe6b9
JG		 997 } else if ((rdev->family == CHIP_RS690) ||
998 (rdev->family == CHIP_RS740)) {
999 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1000 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1001 } else if (rdev->family == CHIP_RS600) {
1002 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1003 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1004 } else if ((rdev->family == CHIP_RV515) ||
1005 (rdev->family == CHIP_R520) ||
1006 (rdev->family == CHIP_RV530) ||
1007 (rdev->family == CHIP_R580) ||
1008 (rdev->family == CHIP_RV560) ||
1009 (rdev->family == CHIP_RV570)) {
1010 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1011 fw_name = FIRMWARE_R520;
1012 }
1013
3ce0a23d 1014 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 1015 platform_device_unregister(pdev);
1016 if (err) {
1017 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1018 fw_name);
3ce0a23d 1019 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1020 printk(KERN_ERR
1021 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1022 rdev->me_fw->size, fw_name);
70967ab9 1023 err = -EINVAL;
3ce0a23d
JG		 1024 release_firmware(rdev->me_fw);
1025 rdev->me_fw = NULL;
70967ab9
BH		 1026 }
1027 return err;
1028}
d4550907 1029
70967ab9
BH		 1030static void r100_cp_load_microcode(struct radeon_device *rdev)
1031{
1032 const __be32 *fw_data;
1033 int i, size;
1034
1035 if (r100_gui_wait_for_idle(rdev)) {
1036 printk(KERN_WARNING "Failed to wait GUI idle while "
1037 "programming pipes. Bad things might happen.\n");
1038 }
1039
3ce0a23d
JG		 1040 if (rdev->me_fw) {
1041 size = rdev->me_fw->size / 4;
1042 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1043 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1044 for (i = 0; i < size; i += 2) {
1045 WREG32(RADEON_CP_ME_RAM_DATAH,
1046 be32_to_cpup(&fw_data[i]));
1047 WREG32(RADEON_CP_ME_RAM_DATAL,
1048 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1049 }
1050 }
1051}
1052
1053int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1054{
e32eb50d 1055 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1056 unsigned rb_bufsz;
1057 unsigned rb_blksz;
1058 unsigned max_fetch;
1059 unsigned pre_write_timer;
1060 unsigned pre_write_limit;
1061 unsigned indirect2_start;
1062 unsigned indirect1_start;
1063 uint32_t tmp;
1064 int r;
1065
1066 if (r100_debugfs_cp_init(rdev)) {
1067 DRM_ERROR("Failed to register debugfs file for CP !\n");
1068 }
3ce0a23d 1069 if (!rdev->me_fw) {
70967ab9
BH		 1070 r = r100_cp_init_microcode(rdev);
1071 if (r) {
1072 DRM_ERROR("Failed to load firmware!\n");
1073 return r;
1074 }
1075 }
1076
771fe6b9
JG		 1077 /* Align ring size */
1078 rb_bufsz = drm_order(ring_size / 8);
1079 ring_size = (1 << (rb_bufsz + 1)) * 4;
1080 r100_cp_load_microcode(rdev);
e32eb50d 1081 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1082 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1083 0, 0x7fffff, RADEON_CP_PACKET2);
771fe6b9
JG		 1084 if (r) {
1085 return r;
1086 }
1087 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1088 * the rptr copy in system ram */
1089 rb_blksz = 9;
1090 /* cp will read 128bytes at a time (4 dwords) */
1091 max_fetch = 1;
e32eb50d 1092 ring->align_mask = 16 - 1;
771fe6b9
JG		 1093 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1094 pre_write_timer = 64;
1095 /* Force CP_RB_WPTR write if written more than one time before the
1096 * delay expire
1097 */
1098 pre_write_limit = 0;
1099 /* Setup the cp cache like this (cache size is 96 dwords) :
1100 * RING 0 to 15
1101 * INDIRECT1 16 to 79
1102 * INDIRECT2 80 to 95
1103 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1104 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1105 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1106 * Idea being that most of the gpu cmd will be through indirect1 buffer
1107 * so it gets the bigger cache.
1108 */
1109 indirect2_start = 80;
1110 indirect1_start = 16;
1111 /* cp setup */
1112 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1113 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1114 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1115 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1116#ifdef __BIG_ENDIAN
1117 tmp |= RADEON_BUF_SWAP_32BIT;
1118#endif
724c80e1 1119 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1120
771fe6b9 1121 /* Set ring address */
e32eb50d
CK		 1122 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1123 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1124 /* Force read & write ptr to 0 */
724c80e1 1125 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1126 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1127 ring->wptr = 0;
1128 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1129
1130 /* set the wb address whether it's enabled or not */
1131 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1132 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1133 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1134
1135 if (rdev->wb.enabled)
1136 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1137 else {
1138 tmp |= RADEON_RB_NO_UPDATE;
1139 WREG32(R_000770_SCRATCH_UMSK, 0);
1140 }
1141
771fe6b9
JG		 1142 WREG32(RADEON_CP_RB_CNTL, tmp);
1143 udelay(10);
e32eb50d 1144 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
771fe6b9
JG		 1145 /* Set cp mode to bus mastering & enable cp*/
1146 WREG32(RADEON_CP_CSQ_MODE,
1147 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1148 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1149 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1150 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9
JG		 1151 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1152 radeon_ring_start(rdev);
e32eb50d 1153 r = radeon_ring_test(rdev, ring);
771fe6b9
JG		 1154 if (r) {
1155 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1156 return r;
1157 }
e32eb50d 1158 ring->ready = true;
53595338 1159 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
771fe6b9
JG		 1160 return 0;
1161}
1162
1163void r100_cp_fini(struct radeon_device *rdev)
1164{
45600232
JG		 1165 if (r100_cp_wait_for_idle(rdev)) {
1166 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1167 }
771fe6b9 1168 /* Disable ring */
a18d7ea1 1169 r100_cp_disable(rdev);
e32eb50d 1170 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1171 DRM_INFO("radeon: cp finalized\n");
1172}
1173
1174void r100_cp_disable(struct radeon_device *rdev)
1175{
1176 /* Disable ring */
53595338 1177 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1178 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1179 WREG32(RADEON_CP_CSQ_MODE, 0);
1180 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1181 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1182 if (r100_gui_wait_for_idle(rdev)) {
1183 printk(KERN_WARNING "Failed to wait GUI idle while "
1184 "programming pipes. Bad things might happen.\n");
1185 }
1186}
1187
771fe6b9
JG		 1188/*
1189 * CS functions
1190 */
1191int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1192 struct radeon_cs_packet *pkt,
068a117c 1193 const unsigned *auth, unsigned n,
771fe6b9
JG		 1194 radeon_packet0_check_t check)
1195{
1196 unsigned reg;
1197 unsigned i, j, m;
1198 unsigned idx;
1199 int r;
1200
1201 idx = pkt->idx + 1;
1202 reg = pkt->reg;
068a117c
JG		 1203 /* Check that register fall into register range
1204 * determined by the number of entry (n) in the
1205 * safe register bitmap.
1206 */
771fe6b9
JG		 1207 if (pkt->one_reg_wr) {
1208 if ((reg >> 7) > n) {
1209 return -EINVAL;
1210 }
1211 } else {
1212 if (((reg + (pkt->count << 2)) >> 7) > n) {
1213 return -EINVAL;
1214 }
1215 }
1216 for (i = 0; i <= pkt->count; i++, idx++) {
1217 j = (reg >> 7);
1218 m = 1 << ((reg >> 2) & 31);
1219 if (auth[j] & m) {
1220 r = check(p, pkt, idx, reg);
1221 if (r) {
1222 return r;
1223 }
1224 }
1225 if (pkt->one_reg_wr) {
1226 if (!(auth[j] & m)) {
1227 break;
1228 }
1229 } else {
1230 reg += 4;
1231 }
1232 }
1233 return 0;
1234}
1235
771fe6b9
JG		 1236void r100_cs_dump_packet(struct radeon_cs_parser *p,
1237 struct radeon_cs_packet *pkt)
1238{
771fe6b9
JG		 1239 volatile uint32_t *ib;
1240 unsigned i;
1241 unsigned idx;
1242
1243 ib = p->ib->ptr;
771fe6b9
JG		 1244 idx = pkt->idx;
1245 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1246 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1247 }
1248}
1249
1250/**
1251 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1252 * @parser: parser structure holding parsing context.
1253 * @pkt: where to store packet informations
1254 *
1255 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1256 * if packet is bigger than remaining ib size. or if packets is unknown.
1257 **/
1258int r100_cs_packet_parse(struct radeon_cs_parser *p,
1259 struct radeon_cs_packet *pkt,
1260 unsigned idx)
1261{
1262 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1263 uint32_t header;
771fe6b9
JG		 1264
1265 if (idx >= ib_chunk->length_dw) {
1266 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1267 idx, ib_chunk->length_dw);
1268 return -EINVAL;
1269 }
513bcb46 1270 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1271 pkt->idx = idx;
1272 pkt->type = CP_PACKET_GET_TYPE(header);
1273 pkt->count = CP_PACKET_GET_COUNT(header);
1274 switch (pkt->type) {
1275 case PACKET_TYPE0:
1276 pkt->reg = CP_PACKET0_GET_REG(header);
1277 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1278 break;
1279 case PACKET_TYPE3:
1280 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1281 break;
1282 case PACKET_TYPE2:
1283 pkt->count = -1;
1284 break;
1285 default:
1286 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1287 return -EINVAL;
1288 }
1289 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1290 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1291 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1292 return -EINVAL;
1293 }
1294 return 0;
1295}
1296
531369e6
DA		 1297/**
1298 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1299 * @parser: parser structure holding parsing context.
1300 *
1301 * Userspace sends a special sequence for VLINE waits.
1302 * PACKET0 - VLINE_START_END + value
1303 * PACKET0 - WAIT_UNTIL +_value
1304 * RELOC (P3) - crtc_id in reloc.
1305 *
1306 * This function parses this and relocates the VLINE START END
1307 * and WAIT UNTIL packets to the correct crtc.
1308 * It also detects a switched off crtc and nulls out the
1309 * wait in that case.
1310 */
1311int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1312{
531369e6
DA		 1313 struct drm_mode_object *obj;
1314 struct drm_crtc *crtc;
1315 struct radeon_crtc *radeon_crtc;
1316 struct radeon_cs_packet p3reloc, waitreloc;
1317 int crtc_id;
1318 int r;
1319 uint32_t header, h_idx, reg;
513bcb46 1320 volatile uint32_t *ib;
531369e6 1321
513bcb46 1322 ib = p->ib->ptr;
531369e6
DA		 1323
1324 /* parse the wait until */
1325 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1326 if (r)
1327 return r;
1328
1329 /* check its a wait until and only 1 count */
1330 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1331 waitreloc.count != 0) {
1332 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1333 return -EINVAL;
531369e6
DA		 1334 }
1335
513bcb46 1336 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1337 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1338 return -EINVAL;
531369e6
DA		 1339 }
1340
1341 /* jump over the NOP */
90ebd065 1342 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1343 if (r)
1344 return r;
1345
1346 h_idx = p->idx - 2;
90ebd065
AD		 1347 p->idx += waitreloc.count + 2;
1348 p->idx += p3reloc.count + 2;
531369e6 1349
513bcb46
DA		 1350 header = radeon_get_ib_value(p, h_idx);
1351 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1352 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1353 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1354 if (!obj) {
1355 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1356 return -EINVAL;
531369e6
DA		 1357 }
1358 crtc = obj_to_crtc(obj);
1359 radeon_crtc = to_radeon_crtc(crtc);
1360 crtc_id = radeon_crtc->crtc_id;
1361
1362 if (!crtc->enabled) {
1363 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1364 ib[h_idx + 2] = PACKET2(0);
1365 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1366 } else if (crtc_id == 1) {
1367 switch (reg) {
1368 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1369 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1370 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1371 break;
1372 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1373 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1374 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1375 break;
1376 default:
1377 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1378 return -EINVAL;
531369e6 1379 }
513bcb46
DA		 1380 ib[h_idx] = header;
1381 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1382 }
a3a88a66
PB		 1383
1384 return 0;
531369e6
DA		 1385}
1386
771fe6b9
JG		 1387/**
1388 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1389 * @parser: parser structure holding parsing context.
1390 * @data: pointer to relocation data
1391 * @offset_start: starting offset
1392 * @offset_mask: offset mask (to align start offset on)
1393 * @reloc: reloc informations
1394 *
1395 * Check next packet is relocation packet3, do bo validation and compute
1396 * GPU offset using the provided start.
1397 **/
1398int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1399 struct radeon_cs_reloc **cs_reloc)
1400{
771fe6b9
JG		 1401 struct radeon_cs_chunk *relocs_chunk;
1402 struct radeon_cs_packet p3reloc;
1403 unsigned idx;
1404 int r;
1405
1406 if (p->chunk_relocs_idx == -1) {
1407 DRM_ERROR("No relocation chunk !\n");
1408 return -EINVAL;
1409 }
1410 *cs_reloc = NULL;
771fe6b9
JG		 1411 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1412 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1413 if (r) {
1414 return r;
1415 }
1416 p->idx += p3reloc.count + 2;
1417 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1418 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1419 p3reloc.idx);
1420 r100_cs_dump_packet(p, &p3reloc);
1421 return -EINVAL;
1422 }
513bcb46 1423 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1424 if (idx >= relocs_chunk->length_dw) {
1425 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1426 idx, relocs_chunk->length_dw);
1427 r100_cs_dump_packet(p, &p3reloc);
1428 return -EINVAL;
1429 }
1430 /* FIXME: we assume reloc size is 4 dwords */
1431 *cs_reloc = p->relocs_ptr[(idx / 4)];
1432 return 0;
1433}
1434
551ebd83
DA		 1435static int r100_get_vtx_size(uint32_t vtx_fmt)
1436{
1437 int vtx_size;
1438 vtx_size = 2;
1439 /* ordered according to bits in spec */
1440 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1441 vtx_size++;
1442 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1443 vtx_size += 3;
1444 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1445 vtx_size++;
1446 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1447 vtx_size++;
1448 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1449 vtx_size += 3;
1450 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1451 vtx_size++;
1452 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1453 vtx_size++;
1454 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1455 vtx_size += 2;
1456 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1457 vtx_size += 2;
1458 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1459 vtx_size++;
1460 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1461 vtx_size += 2;
1462 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1463 vtx_size++;
1464 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1465 vtx_size += 2;
1466 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1467 vtx_size++;
1468 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1469 vtx_size++;
1470 /* blend weight */
1471 if (vtx_fmt & (0x7 << 15))
1472 vtx_size += (vtx_fmt >> 15) & 0x7;
1473 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1474 vtx_size += 3;
1475 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1476 vtx_size += 2;
1477 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1478 vtx_size++;
1479 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1480 vtx_size++;
1481 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1482 vtx_size++;
1483 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1484 vtx_size++;
1485 return vtx_size;
1486}
1487
771fe6b9 1488static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1489 struct radeon_cs_packet *pkt,
1490 unsigned idx, unsigned reg)
771fe6b9 1491{
771fe6b9 1492 struct radeon_cs_reloc *reloc;
551ebd83 1493 struct r100_cs_track *track;
771fe6b9
JG		 1494 volatile uint32_t *ib;
1495 uint32_t tmp;
771fe6b9 1496 int r;
551ebd83 1497 int i, face;
e024e110 1498 u32 tile_flags = 0;
513bcb46 1499 u32 idx_value;
771fe6b9
JG		 1500
1501 ib = p->ib->ptr;
551ebd83
DA		 1502 track = (struct r100_cs_track *)p->track;
1503
513bcb46
DA		 1504 idx_value = radeon_get_ib_value(p, idx);
1505
551ebd83
DA		 1506 switch (reg) {
1507 case RADEON_CRTC_GUI_TRIG_VLINE:
1508 r = r100_cs_packet_parse_vline(p);
1509 if (r) {
1510 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1511 idx, reg);
1512 r100_cs_dump_packet(p, pkt);
1513 return r;
1514 }
1515 break;
771fe6b9
JG		 1516 /* FIXME: only allow PACKET3 blit? easier to check for out of
1517 * range access */
551ebd83
DA		 1518 case RADEON_DST_PITCH_OFFSET:
1519 case RADEON_SRC_PITCH_OFFSET:
1520 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1521 if (r)
1522 return r;
1523 break;
1524 case RADEON_RB3D_DEPTHOFFSET:
1525 r = r100_cs_packet_next_reloc(p, &reloc);
1526 if (r) {
1527 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1528 idx, reg);
1529 r100_cs_dump_packet(p, pkt);
1530 return r;
1531 }
1532 track->zb.robj = reloc->robj;
513bcb46 1533 track->zb.offset = idx_value;
40b4a759 1534 track->zb_dirty = true;
513bcb46 1535 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1536 break;
1537 case RADEON_RB3D_COLOROFFSET:
1538 r = r100_cs_packet_next_reloc(p, &reloc);
1539 if (r) {
1540 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1541 idx, reg);
1542 r100_cs_dump_packet(p, pkt);
1543 return r;
1544 }
1545 track->cb[0].robj = reloc->robj;
513bcb46 1546 track->cb[0].offset = idx_value;
40b4a759 1547 track->cb_dirty = true;
513bcb46 1548 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1549 break;
1550 case RADEON_PP_TXOFFSET_0:
1551 case RADEON_PP_TXOFFSET_1:
1552 case RADEON_PP_TXOFFSET_2:
1553 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1554 r = r100_cs_packet_next_reloc(p, &reloc);
1555 if (r) {
1556 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1557 idx, reg);
1558 r100_cs_dump_packet(p, pkt);
1559 return r;
1560 }
f2746f83
AD		 1561 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1562 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1563 tile_flags |= RADEON_TXO_MACRO_TILE;
1564 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1565 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1566
1567 tmp = idx_value & ~(0x7 << 2);
1568 tmp |= tile_flags;
1569 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1570 } else
1571 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1572 track->textures[i].robj = reloc->robj;
40b4a759 1573 track->tex_dirty = true;
551ebd83
DA		 1574 break;
1575 case RADEON_PP_CUBIC_OFFSET_T0_0:
1576 case RADEON_PP_CUBIC_OFFSET_T0_1:
1577 case RADEON_PP_CUBIC_OFFSET_T0_2:
1578 case RADEON_PP_CUBIC_OFFSET_T0_3:
1579 case RADEON_PP_CUBIC_OFFSET_T0_4:
1580 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1581 r = r100_cs_packet_next_reloc(p, &reloc);
1582 if (r) {
1583 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1584 idx, reg);
1585 r100_cs_dump_packet(p, pkt);
1586 return r;
1587 }
513bcb46
DA		 1588 track->textures[0].cube_info[i].offset = idx_value;
1589 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1590 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1591 track->tex_dirty = true;
551ebd83
DA		 1592 break;
1593 case RADEON_PP_CUBIC_OFFSET_T1_0:
1594 case RADEON_PP_CUBIC_OFFSET_T1_1:
1595 case RADEON_PP_CUBIC_OFFSET_T1_2:
1596 case RADEON_PP_CUBIC_OFFSET_T1_3:
1597 case RADEON_PP_CUBIC_OFFSET_T1_4:
1598 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1599 r = r100_cs_packet_next_reloc(p, &reloc);
1600 if (r) {
1601 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1602 idx, reg);
1603 r100_cs_dump_packet(p, pkt);
1604 return r;
1605 }
513bcb46
DA		 1606 track->textures[1].cube_info[i].offset = idx_value;
1607 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1608 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1609 track->tex_dirty = true;
551ebd83
DA		 1610 break;
1611 case RADEON_PP_CUBIC_OFFSET_T2_0:
1612 case RADEON_PP_CUBIC_OFFSET_T2_1:
1613 case RADEON_PP_CUBIC_OFFSET_T2_2:
1614 case RADEON_PP_CUBIC_OFFSET_T2_3:
1615 case RADEON_PP_CUBIC_OFFSET_T2_4:
1616 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1617 r = r100_cs_packet_next_reloc(p, &reloc);
1618 if (r) {
1619 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1620 idx, reg);
1621 r100_cs_dump_packet(p, pkt);
1622 return r;
1623 }
513bcb46
DA		 1624 track->textures[2].cube_info[i].offset = idx_value;
1625 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1626 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1627 track->tex_dirty = true;
551ebd83
DA		 1628 break;
1629 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1630 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1631 track->cb_dirty = true;
1632 track->zb_dirty = true;
551ebd83
DA		 1633 break;
1634 case RADEON_RB3D_COLORPITCH:
1635 r = r100_cs_packet_next_reloc(p, &reloc);
1636 if (r) {
1637 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1638 idx, reg);
1639 r100_cs_dump_packet(p, pkt);
1640 return r;
1641 }
c9068eb2
AD		 1642 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1643 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1644 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1645 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1646 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1647
1648 tmp = idx_value & ~(0x7 << 16);
1649 tmp |= tile_flags;
1650 ib[idx] = tmp;
1651 } else
1652 ib[idx] = idx_value;
e024e110 1653
513bcb46 1654 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1655 track->cb_dirty = true;
551ebd83
DA		 1656 break;
1657 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1658 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1659 track->zb_dirty = true;
551ebd83
DA		 1660 break;
1661 case RADEON_RB3D_CNTL:
513bcb46 1662 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1663 case 7:
1664 case 8:
1665 case 9:
1666 case 11:
1667 case 12:
1668 track->cb[0].cpp = 1;
e024e110 1669 break;
551ebd83
DA		 1670 case 3:
1671 case 4:
1672 case 15:
1673 track->cb[0].cpp = 2;
1674 break;
1675 case 6:
1676 track->cb[0].cpp = 4;
1677 break;
1678 default:
1679 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1680 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1681 return -EINVAL;
1682 }
513bcb46 1683 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1684 track->cb_dirty = true;
1685 track->zb_dirty = true;
551ebd83
DA		 1686 break;
1687 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1688 switch (idx_value & 0xf) {
551ebd83
DA		 1689 case 0:
1690 track->zb.cpp = 2;
1691 break;
1692 case 2:
1693 case 3:
1694 case 4:
1695 case 5:
1696 case 9:
1697 case 11:
1698 track->zb.cpp = 4;
17782d99 1699 break;
771fe6b9 1700 default:
771fe6b9
JG		 1701 break;
1702 }
40b4a759 1703 track->zb_dirty = true;
551ebd83
DA		 1704 break;
1705 case RADEON_RB3D_ZPASS_ADDR:
1706 r = r100_cs_packet_next_reloc(p, &reloc);
1707 if (r) {
1708 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1709 idx, reg);
1710 r100_cs_dump_packet(p, pkt);
1711 return r;
1712 }
513bcb46 1713 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1714 break;
1715 case RADEON_PP_CNTL:
1716 {
513bcb46 1717 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1718 for (i = 0; i < track->num_texture; i++)
1719 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1720 track->tex_dirty = true;
551ebd83
DA		 1721 }
1722 break;
1723 case RADEON_SE_VF_CNTL:
513bcb46 1724 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1725 break;
1726 case RADEON_SE_VTX_FMT:
513bcb46 1727 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1728 break;
1729 case RADEON_PP_TEX_SIZE_0:
1730 case RADEON_PP_TEX_SIZE_1:
1731 case RADEON_PP_TEX_SIZE_2:
1732 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1733 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1734 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1735 track->tex_dirty = true;
551ebd83
DA		 1736 break;
1737 case RADEON_PP_TEX_PITCH_0:
1738 case RADEON_PP_TEX_PITCH_1:
1739 case RADEON_PP_TEX_PITCH_2:
1740 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1741 track->textures[i].pitch = idx_value + 32;
40b4a759 1742 track->tex_dirty = true;
551ebd83
DA		 1743 break;
1744 case RADEON_PP_TXFILTER_0:
1745 case RADEON_PP_TXFILTER_1:
1746 case RADEON_PP_TXFILTER_2:
1747 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1748 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1749 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1750 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1751 if (tmp == 2 || tmp == 6)
1752 track->textures[i].roundup_w = false;
513bcb46 1753 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1754 if (tmp == 2 || tmp == 6)
1755 track->textures[i].roundup_h = false;
40b4a759 1756 track->tex_dirty = true;
551ebd83
DA		 1757 break;
1758 case RADEON_PP_TXFORMAT_0:
1759 case RADEON_PP_TXFORMAT_1:
1760 case RADEON_PP_TXFORMAT_2:
1761 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1762 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1763 track->textures[i].use_pitch = 1;
1764 } else {
1765 track->textures[i].use_pitch = 0;
513bcb46
DA		 1766 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1767 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1768 }
513bcb46 1769 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1770 track->textures[i].tex_coord_type = 2;
513bcb46 1771 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1772 case RADEON_TXFORMAT_I8:
1773 case RADEON_TXFORMAT_RGB332:
1774 case RADEON_TXFORMAT_Y8:
1775 track->textures[i].cpp = 1;
f9da52d5 1776 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1777 break;
1778 case RADEON_TXFORMAT_AI88:
1779 case RADEON_TXFORMAT_ARGB1555:
1780 case RADEON_TXFORMAT_RGB565:
1781 case RADEON_TXFORMAT_ARGB4444:
1782 case RADEON_TXFORMAT_VYUY422:
1783 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1784 case RADEON_TXFORMAT_SHADOW16:
1785 case RADEON_TXFORMAT_LDUDV655:
1786 case RADEON_TXFORMAT_DUDV88:
1787 track->textures[i].cpp = 2;
f9da52d5 1788 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1789 break;
551ebd83
DA		 1790 case RADEON_TXFORMAT_ARGB8888:
1791 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1792 case RADEON_TXFORMAT_SHADOW32:
1793 case RADEON_TXFORMAT_LDUDUV8888:
1794 track->textures[i].cpp = 4;
f9da52d5 1795 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1796 break;
d785d78b
DA		 1797 case RADEON_TXFORMAT_DXT1:
1798 track->textures[i].cpp = 1;
1799 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1800 break;
1801 case RADEON_TXFORMAT_DXT23:
1802 case RADEON_TXFORMAT_DXT45:
1803 track->textures[i].cpp = 1;
1804 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1805 break;
551ebd83 1806 }
513bcb46
DA		 1807 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1808 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1809 track->tex_dirty = true;
551ebd83
DA		 1810 break;
1811 case RADEON_PP_CUBIC_FACES_0:
1812 case RADEON_PP_CUBIC_FACES_1:
1813 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1814 tmp = idx_value;
551ebd83
DA		 1815 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1816 for (face = 0; face < 4; face++) {
1817 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1818 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1819 }
40b4a759 1820 track->tex_dirty = true;
551ebd83
DA		 1821 break;
1822 default:
1823 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1824 reg, idx);
1825 return -EINVAL;
771fe6b9
JG		 1826 }
1827 return 0;
1828}
1829
068a117c
JG		 1830int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1831 struct radeon_cs_packet *pkt,
4c788679 1832 struct radeon_bo *robj)
068a117c 1833{
068a117c 1834 unsigned idx;
513bcb46 1835 u32 value;
068a117c 1836 idx = pkt->idx + 1;
513bcb46 1837 value = radeon_get_ib_value(p, idx + 2);
4c788679 1838 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1839 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1840 "(need %u have %lu) !\n",
513bcb46 1841 value + 1,
4c788679 1842 radeon_bo_size(robj));
068a117c
JG		 1843 return -EINVAL;
1844 }
1845 return 0;
1846}
1847
771fe6b9
JG		 1848static int r100_packet3_check(struct radeon_cs_parser *p,
1849 struct radeon_cs_packet *pkt)
1850{
771fe6b9 1851 struct radeon_cs_reloc *reloc;
551ebd83 1852 struct r100_cs_track *track;
771fe6b9 1853 unsigned idx;
771fe6b9
JG		 1854 volatile uint32_t *ib;
1855 int r;
1856
1857 ib = p->ib->ptr;
771fe6b9 1858 idx = pkt->idx + 1;
551ebd83 1859 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1860 switch (pkt->opcode) {
1861 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1862 r = r100_packet3_load_vbpntr(p, pkt, idx);
1863 if (r)
1864 return r;
771fe6b9
JG		 1865 break;
1866 case PACKET3_INDX_BUFFER:
1867 r = r100_cs_packet_next_reloc(p, &reloc);
1868 if (r) {
1869 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1870 r100_cs_dump_packet(p, pkt);
1871 return r;
1872 }
513bcb46 1873 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1874 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1875 if (r) {
1876 return r;
1877 }
771fe6b9
JG		 1878 break;
1879 case 0x23:
771fe6b9
JG		 1880 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1881 r = r100_cs_packet_next_reloc(p, &reloc);
1882 if (r) {
1883 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1884 r100_cs_dump_packet(p, pkt);
1885 return r;
1886 }
513bcb46 1887 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1888 track->num_arrays = 1;
513bcb46 1889 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1890
1891 track->arrays[0].robj = reloc->robj;
1892 track->arrays[0].esize = track->vtx_size;
1893
513bcb46 1894 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1895
513bcb46 1896 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1897 track->immd_dwords = pkt->count - 1;
1898 r = r100_cs_track_check(p->rdev, track);
1899 if (r)
1900 return r;
771fe6b9
JG		 1901 break;
1902 case PACKET3_3D_DRAW_IMMD:
513bcb46 1903 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1904 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1905 return -EINVAL;
1906 }
cf57fc7a 1907 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1908 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1909 track->immd_dwords = pkt->count - 1;
1910 r = r100_cs_track_check(p->rdev, track);
1911 if (r)
1912 return r;
1913 break;
771fe6b9
JG		 1914 /* triggers drawing using in-packet vertex data */
1915 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1916 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1917 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1918 return -EINVAL;
1919 }
513bcb46 1920 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1921 track->immd_dwords = pkt->count;
1922 r = r100_cs_track_check(p->rdev, track);
1923 if (r)
1924 return r;
1925 break;
771fe6b9
JG		 1926 /* triggers drawing using in-packet vertex data */
1927 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1928 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1929 r = r100_cs_track_check(p->rdev, track);
1930 if (r)
1931 return r;
1932 break;
771fe6b9
JG		 1933 /* triggers drawing of vertex buffers setup elsewhere */
1934 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1935 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1936 r = r100_cs_track_check(p->rdev, track);
1937 if (r)
1938 return r;
1939 break;
771fe6b9
JG		 1940 /* triggers drawing using indices to vertex buffer */
1941 case PACKET3_3D_DRAW_VBUF:
513bcb46 1942 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1943 r = r100_cs_track_check(p->rdev, track);
1944 if (r)
1945 return r;
1946 break;
771fe6b9
JG		 1947 /* triggers drawing of vertex buffers setup elsewhere */
1948 case PACKET3_3D_DRAW_INDX:
513bcb46 1949 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1950 r = r100_cs_track_check(p->rdev, track);
1951 if (r)
1952 return r;
1953 break;
771fe6b9 1954 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 1955 case PACKET3_3D_CLEAR_HIZ:
1956 case PACKET3_3D_CLEAR_ZMASK:
1957 if (p->rdev->hyperz_filp != p->filp)
1958 return -EINVAL;
1959 break;
771fe6b9
JG		 1960 case PACKET3_NOP:
1961 break;
1962 default:
1963 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1964 return -EINVAL;
1965 }
1966 return 0;
1967}
1968
1969int r100_cs_parse(struct radeon_cs_parser *p)
1970{
1971 struct radeon_cs_packet pkt;
9f022ddf 1972 struct r100_cs_track *track;
771fe6b9
JG		 1973 int r;
1974
9f022ddf
JG		 1975 track = kzalloc(sizeof(*track), GFP_KERNEL);
1976 r100_cs_track_clear(p->rdev, track);
1977 p->track = track;
771fe6b9
JG		 1978 do {
1979 r = r100_cs_packet_parse(p, &pkt, p->idx);
1980 if (r) {
1981 return r;
1982 }
1983 p->idx += pkt.count + 2;
1984 switch (pkt.type) {
068a117c 1985 case PACKET_TYPE0:
551ebd83
DA		 1986 if (p->rdev->family >= CHIP_R200)
1987 r = r100_cs_parse_packet0(p, &pkt,
1988 p->rdev->config.r100.reg_safe_bm,
1989 p->rdev->config.r100.reg_safe_bm_size,
1990 &r200_packet0_check);
1991 else
1992 r = r100_cs_parse_packet0(p, &pkt,
1993 p->rdev->config.r100.reg_safe_bm,
1994 p->rdev->config.r100.reg_safe_bm_size,
1995 &r100_packet0_check);
068a117c
JG		 1996 break;
1997 case PACKET_TYPE2:
1998 break;
1999 case PACKET_TYPE3:
2000 r = r100_packet3_check(p, &pkt);
2001 break;
2002 default:
2003 DRM_ERROR("Unknown packet type %d !\n",
2004 pkt.type);
2005 return -EINVAL;
771fe6b9
JG		 2006 }
2007 if (r) {
2008 return r;
2009 }
2010 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2011 return 0;
2012}
2013
2014
2015/*
2016 * Global GPU functions
2017 */
2018void r100_errata(struct radeon_device *rdev)
2019{
2020 rdev->pll_errata = 0;
2021
2022 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2023 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2024 }
2025
2026 if (rdev->family == CHIP_RV100 ||
2027 rdev->family == CHIP_RS100 ||
2028 rdev->family == CHIP_RS200) {
2029 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2030 }
2031}
2032
2033/* Wait for vertical sync on primary CRTC */
2034void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2035{
2036 uint32_t crtc_gen_cntl, tmp;
2037 int i;
2038
2039 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2040 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2041 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2042 return;
2043 }
2044 /* Clear the CRTC_VBLANK_SAVE bit */
2045 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2046 for (i = 0; i < rdev->usec_timeout; i++) {
2047 tmp = RREG32(RADEON_CRTC_STATUS);
2048 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2049 return;
2050 }
2051 DRM_UDELAY(1);
2052 }
2053}
2054
2055/* Wait for vertical sync on secondary CRTC */
2056void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2057{
2058 uint32_t crtc2_gen_cntl, tmp;
2059 int i;
2060
2061 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2062 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2063 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2064 return;
2065
2066 /* Clear the CRTC_VBLANK_SAVE bit */
2067 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2068 for (i = 0; i < rdev->usec_timeout; i++) {
2069 tmp = RREG32(RADEON_CRTC2_STATUS);
2070 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2071 return;
2072 }
2073 DRM_UDELAY(1);
2074 }
2075}
2076
2077int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2078{
2079 unsigned i;
2080 uint32_t tmp;
2081
2082 for (i = 0; i < rdev->usec_timeout; i++) {
2083 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2084 if (tmp >= n) {
2085 return 0;
2086 }
2087 DRM_UDELAY(1);
2088 }
2089 return -1;
2090}
2091
2092int r100_gui_wait_for_idle(struct radeon_device *rdev)
2093{
2094 unsigned i;
2095 uint32_t tmp;
2096
2097 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2098 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2099 " Bad things might happen.\n");
2100 }
2101 for (i = 0; i < rdev->usec_timeout; i++) {
2102 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 2103 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 2104 return 0;
2105 }
2106 DRM_UDELAY(1);
2107 }
2108 return -1;
2109}
2110
2111int r100_mc_wait_for_idle(struct radeon_device *rdev)
2112{
2113 unsigned i;
2114 uint32_t tmp;
2115
2116 for (i = 0; i < rdev->usec_timeout; i++) {
2117 /* read MC_STATUS */
4612dc97
AD		 2118 tmp = RREG32(RADEON_MC_STATUS);
2119 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 2120 return 0;
2121 }
2122 DRM_UDELAY(1);
2123 }
2124 return -1;
2125}
2126
e32eb50d 2127void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
771fe6b9 2128{
e32eb50d 2129 lockup->last_cp_rptr = ring->rptr;
225758d8
JG		 2130 lockup->last_jiffies = jiffies;
2131}
2132
2133/**
2134 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2135 * @rdev: radeon device structure
2136 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2137 * @cp: radeon_cp structure holding CP information
2138 *
2139 * We don't need to initialize the lockup tracking information as we will either
2140 * have CP rptr to a different value of jiffies wrap around which will force
2141 * initialization of the lockup tracking informations.
2142 *
2143 * A possible false positivie is if we get call after while and last_cp_rptr ==
2144 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2145 * if the elapsed time since last call is bigger than 2 second than we return
2146 * false and update the tracking information. Due to this the caller must call
2147 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2148 * the fencing code should be cautious about that.
2149 *
2150 * Caller should write to the ring to force CP to do something so we don't get
2151 * false positive when CP is just gived nothing to do.
2152 *
2153 **/
e32eb50d 2154bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
225758d8
JG		 2155{
2156 unsigned long cjiffies, elapsed;
2157
2158 cjiffies = jiffies;
2159 if (!time_after(cjiffies, lockup->last_jiffies)) {
2160 /* likely a wrap around */
e32eb50d 2161 lockup->last_cp_rptr = ring->rptr;
225758d8
JG		 2162 lockup->last_jiffies = jiffies;
2163 return false;
2164 }
e32eb50d 2165 if (ring->rptr != lockup->last_cp_rptr) {
225758d8 2166 /* CP is still working no lockup */
e32eb50d 2167 lockup->last_cp_rptr = ring->rptr;
225758d8
JG		 2168 lockup->last_jiffies = jiffies;
2169 return false;
2170 }
2171 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
ec00efb7 2172 if (elapsed >= 10000) {
225758d8
JG		 2173 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2174 return true;
2175 }
2176 /* give a chance to the GPU ... */
2177 return false;
771fe6b9
JG		 2178}
2179
e32eb50d 2180bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2181{
225758d8
JG		 2182 u32 rbbm_status;
2183 int r;
771fe6b9 2184
225758d8
JG		 2185 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2186 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
e32eb50d 2187 r100_gpu_lockup_update(&rdev->config.r100.lockup, ring);
225758d8
JG		 2188 return false;
2189 }
2190 /* force CP activities */
e32eb50d 2191 r = radeon_ring_lock(rdev, ring, 2);
225758d8
JG		 2192 if (!r) {
2193 /* PACKET2 NOP */
e32eb50d
CK		 2194 radeon_ring_write(ring, 0x80000000);
2195 radeon_ring_write(ring, 0x80000000);
2196 radeon_ring_unlock_commit(rdev, ring);
225758d8 2197 }
e32eb50d
CK		 2198 ring->rptr = RREG32(ring->rptr_reg);
2199 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, ring);
771fe6b9
JG		 2200}
2201
90aca4d2 2202void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2203{
90aca4d2 2204 u32 tmp;
771fe6b9 2205
90aca4d2
JG		 2206 /* disable bus mastering */
2207 tmp = RREG32(R_000030_BUS_CNTL);
2208 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2209 mdelay(1);
2210 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2211 mdelay(1);
2212 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2213 tmp = RREG32(RADEON_BUS_CNTL);
2214 mdelay(1);
642ce525 2215 pci_clear_master(rdev->pdev);
771fe6b9 2216 mdelay(1);
771fe6b9
JG		 2217}
2218
a2d07b74 2219int r100_asic_reset(struct radeon_device *rdev)
771fe6b9 2220{
90aca4d2
JG		 2221 struct r100_mc_save save;
2222 u32 status, tmp;
25b2ec5b 2223 int ret = 0;
771fe6b9 2224
90aca4d2
JG		 2225 status = RREG32(R_000E40_RBBM_STATUS);
2226 if (!G_000E40_GUI_ACTIVE(status)) {
2227 return 0;
771fe6b9 2228 }
25b2ec5b 2229 r100_mc_stop(rdev, &save);
90aca4d2
JG		 2230 status = RREG32(R_000E40_RBBM_STATUS);
2231 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2232 /* stop CP */
2233 WREG32(RADEON_CP_CSQ_CNTL, 0);
2234 tmp = RREG32(RADEON_CP_RB_CNTL);
2235 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2236 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2237 WREG32(RADEON_CP_RB_WPTR, 0);
2238 WREG32(RADEON_CP_RB_CNTL, tmp);
2239 /* save PCI state */
2240 pci_save_state(rdev->pdev);
2241 /* disable bus mastering */
2242 r100_bm_disable(rdev);
2243 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2244 S_0000F0_SOFT_RESET_RE(1) |
2245 S_0000F0_SOFT_RESET_PP(1) |
2246 S_0000F0_SOFT_RESET_RB(1));
2247 RREG32(R_0000F0_RBBM_SOFT_RESET);
2248 mdelay(500);
2249 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2250 mdelay(1);
2251 status = RREG32(R_000E40_RBBM_STATUS);
2252 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
771fe6b9 2253 /* reset CP */
90aca4d2
JG		 2254 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2255 RREG32(R_0000F0_RBBM_SOFT_RESET);
2256 mdelay(500);
2257 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2258 mdelay(1);
2259 status = RREG32(R_000E40_RBBM_STATUS);
2260 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2261 /* restore PCI & busmastering */
2262 pci_restore_state(rdev->pdev);
2263 r100_enable_bm(rdev);
771fe6b9 2264 /* Check if GPU is idle */
90aca4d2
JG		 2265 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2266 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2267 dev_err(rdev->dev, "failed to reset GPU\n");
2268 rdev->gpu_lockup = true;
25b2ec5b
AD		 2269 ret = -1;
2270 } else
2271 dev_info(rdev->dev, "GPU reset succeed\n");
90aca4d2 2272 r100_mc_resume(rdev, &save);
25b2ec5b 2273 return ret;
771fe6b9
JG		 2274}
2275
92cde00c
AD		 2276void r100_set_common_regs(struct radeon_device *rdev)
2277{
2739d49c
AD		 2278 struct drm_device *dev = rdev->ddev;
2279 bool force_dac2 = false;
d668046c 2280 u32 tmp;
2739d49c 2281
92cde00c
AD		 2282 /* set these so they don't interfere with anything */
2283 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2284 WREG32(RADEON_SUBPIC_CNTL, 0);
2285 WREG32(RADEON_VIPH_CONTROL, 0);
2286 WREG32(RADEON_I2C_CNTL_1, 0);
2287 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2288 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2289 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 2290
2291 /* always set up dac2 on rn50 and some rv100 as lots
2292 * of servers seem to wire it up to a VGA port but
2293 * don't report it in the bios connector
2294 * table.
2295 */
2296 switch (dev->pdev->device) {
2297 /* RN50 */
2298 case 0x515e:
2299 case 0x5969:
2300 force_dac2 = true;
2301 break;
2302 /* RV100*/
2303 case 0x5159:
2304 case 0x515a:
2305 /* DELL triple head servers */
2306 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2307 ((dev->pdev->subsystem_device == 0x016c) ||
2308 (dev->pdev->subsystem_device == 0x016d) ||
2309 (dev->pdev->subsystem_device == 0x016e) ||
2310 (dev->pdev->subsystem_device == 0x016f) ||
2311 (dev->pdev->subsystem_device == 0x0170) ||
2312 (dev->pdev->subsystem_device == 0x017d) ||
2313 (dev->pdev->subsystem_device == 0x017e) ||
2314 (dev->pdev->subsystem_device == 0x0183) ||
2315 (dev->pdev->subsystem_device == 0x018a) ||
2316 (dev->pdev->subsystem_device == 0x019a)))
2317 force_dac2 = true;
2318 break;
2319 }
2320
2321 if (force_dac2) {
2322 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2323 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2324 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2325
2326 /* For CRT on DAC2, don't turn it on if BIOS didn't
2327 enable it, even it's detected.
2328 */
2329
2330 /* force it to crtc0 */
2331 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2332 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2333 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2334
2335 /* set up the TV DAC */
2336 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2337 RADEON_TV_DAC_STD_MASK |
2338 RADEON_TV_DAC_RDACPD |
2339 RADEON_TV_DAC_GDACPD |
2340 RADEON_TV_DAC_BDACPD |
2341 RADEON_TV_DAC_BGADJ_MASK |
2342 RADEON_TV_DAC_DACADJ_MASK);
2343 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2344 RADEON_TV_DAC_NHOLD |
2345 RADEON_TV_DAC_STD_PS2 |
2346 (0x58 << 16));
2347
2348 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2349 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2350 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2351 }
d668046c
DA		 2352
2353 /* switch PM block to ACPI mode */
2354 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2355 tmp &= ~RADEON_PM_MODE_SEL;
2356 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2357
92cde00c 2358}
771fe6b9
JG		 2359
2360/*
2361 * VRAM info
2362 */
2363static void r100_vram_get_type(struct radeon_device *rdev)
2364{
2365 uint32_t tmp;
2366
2367 rdev->mc.vram_is_ddr = false;
2368 if (rdev->flags & RADEON_IS_IGP)
2369 rdev->mc.vram_is_ddr = true;
2370 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2371 rdev->mc.vram_is_ddr = true;
2372 if ((rdev->family == CHIP_RV100) ||
2373 (rdev->family == CHIP_RS100) ||
2374 (rdev->family == CHIP_RS200)) {
2375 tmp = RREG32(RADEON_MEM_CNTL);
2376 if (tmp & RV100_HALF_MODE) {
2377 rdev->mc.vram_width = 32;
2378 } else {
2379 rdev->mc.vram_width = 64;
2380 }
2381 if (rdev->flags & RADEON_SINGLE_CRTC) {
2382 rdev->mc.vram_width /= 4;
2383 rdev->mc.vram_is_ddr = true;
2384 }
2385 } else if (rdev->family <= CHIP_RV280) {
2386 tmp = RREG32(RADEON_MEM_CNTL);
2387 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2388 rdev->mc.vram_width = 128;
2389 } else {
2390 rdev->mc.vram_width = 64;
2391 }
2392 } else {
2393 /* newer IGPs */
2394 rdev->mc.vram_width = 128;
2395 }
2396}
2397
2a0f8918 2398static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 2399{
2a0f8918
DA		 2400 u32 aper_size;
2401 u8 byte;
2402
2403 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2404
2405 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2406 * that is has the 2nd generation multifunction PCI interface
2407 */
2408 if (rdev->family == CHIP_RV280 ||
2409 rdev->family >= CHIP_RV350) {
2410 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2411 ~RADEON_HDP_APER_CNTL);
2412 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2413 return aper_size * 2;
2414 }
2415
2416 /* Older cards have all sorts of funny issues to deal with. First
2417 * check if it's a multifunction card by reading the PCI config
2418 * header type... Limit those to one aperture size
2419 */
2420 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2421 if (byte & 0x80) {
2422 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2423 DRM_INFO("Limiting VRAM to one aperture\n");
2424 return aper_size;
2425 }
2426
2427 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2428 * have set it up. We don't write this as it's broken on some ASICs but
2429 * we expect the BIOS to have done the right thing (might be too optimistic...)
2430 */
2431 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2432 return aper_size * 2;
2433 return aper_size;
2434}
2435
2436void r100_vram_init_sizes(struct radeon_device *rdev)
2437{
2438 u64 config_aper_size;
2a0f8918 2439
d594e46a 2440 /* work out accessible VRAM */
01d73a69
JC		 2441 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2442 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
51e5fcd3
JG		 2443 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2444 /* FIXME we don't use the second aperture yet when we could use it */
2445 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2446 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 2447 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 2448 if (rdev->flags & RADEON_IS_IGP) {
2449 uint32_t tom;
2450 /* read NB_TOM to get the amount of ram stolen for the GPU */
2451 tom = RREG32(RADEON_NB_TOM);
7a50f01a 2452 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 2453 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2454 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2455 } else {
7a50f01a 2456 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 2457 /* Some production boards of m6 will report 0
2458 * if it's 8 MB
2459 */
7a50f01a
DA		 2460 if (rdev->mc.real_vram_size == 0) {
2461 rdev->mc.real_vram_size = 8192 * 1024;
2462 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 2463 }
d594e46a
JG		 2464 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2465 * Novell bug 204882 + along with lots of ubuntu ones
2466 */
b7d8cce5
AD		 2467 if (rdev->mc.aper_size > config_aper_size)
2468 config_aper_size = rdev->mc.aper_size;
2469
7a50f01a
DA		 2470 if (config_aper_size > rdev->mc.real_vram_size)
2471 rdev->mc.mc_vram_size = config_aper_size;
2472 else
2473 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2474 }
2a0f8918
DA		 2475}
2476
28d52043
DA		 2477void r100_vga_set_state(struct radeon_device *rdev, bool state)
2478{
2479 uint32_t temp;
2480
2481 temp = RREG32(RADEON_CONFIG_CNTL);
2482 if (state == false) {
d75ee3be
AD		 2483 temp &= ~RADEON_CFG_VGA_RAM_EN;
2484 temp |= RADEON_CFG_VGA_IO_DIS;
28d52043 2485 } else {
d75ee3be 2486 temp &= ~RADEON_CFG_VGA_IO_DIS;
28d52043
DA		 2487 }
2488 WREG32(RADEON_CONFIG_CNTL, temp);
2489}
2490
d594e46a 2491void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2492{
d594e46a 2493 u64 base;
2a0f8918 2494
d594e46a 2495 r100_vram_get_type(rdev);
2a0f8918 2496 r100_vram_init_sizes(rdev);
d594e46a
JG		 2497 base = rdev->mc.aper_base;
2498 if (rdev->flags & RADEON_IS_IGP)
2499 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2500 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 2501 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 2502 if (!(rdev->flags & RADEON_IS_AGP))
2503 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2504 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2505}
2506
2507
2508/*
2509 * Indirect registers accessor
2510 */
2511void r100_pll_errata_after_index(struct radeon_device *rdev)
2512{
4ce9198e
AD		 2513 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2514 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2515 (void)RREG32(RADEON_CRTC_GEN_CNTL);
771fe6b9 2516 }
771fe6b9
JG		 2517}
2518
2519static void r100_pll_errata_after_data(struct radeon_device *rdev)
2520{
2521 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2522 * or the chip could hang on a subsequent access
2523 */
2524 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2525 udelay(5000);
2526 }
2527
2528 /* This function is required to workaround a hardware bug in some (all?)
2529 * revisions of the R300. This workaround should be called after every
2530 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2531 * may not be correct.
2532 */
2533 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2534 uint32_t save, tmp;
2535
2536 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2537 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2538 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2539 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2540 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2541 }
2542}
2543
2544uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2545{
2546 uint32_t data;
2547
2548 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2549 r100_pll_errata_after_index(rdev);
2550 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2551 r100_pll_errata_after_data(rdev);
2552 return data;
2553}
2554
2555void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2556{
2557 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2558 r100_pll_errata_after_index(rdev);
2559 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2560 r100_pll_errata_after_data(rdev);
2561}
2562
d4550907 2563void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2564{
551ebd83
DA		 2565 if (ASIC_IS_RN50(rdev)) {
2566 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2567 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2568 } else if (rdev->family < CHIP_R200) {
2569 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2570 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2571 } else {
d4550907 2572 r200_set_safe_registers(rdev);
551ebd83 2573 }
068a117c
JG		 2574}
2575
771fe6b9
JG		 2576/*
2577 * Debugfs info
2578 */
2579#if defined(CONFIG_DEBUG_FS)
2580static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2581{
2582 struct drm_info_node *node = (struct drm_info_node *) m->private;
2583 struct drm_device *dev = node->minor->dev;
2584 struct radeon_device *rdev = dev->dev_private;
2585 uint32_t reg, value;
2586 unsigned i;
2587
2588 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2589 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2590 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2591 for (i = 0; i < 64; i++) {
2592 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2593 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2594 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2595 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2596 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2597 }
2598 return 0;
2599}
2600
2601static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2602{
2603 struct drm_info_node *node = (struct drm_info_node *) m->private;
2604 struct drm_device *dev = node->minor->dev;
2605 struct radeon_device *rdev = dev->dev_private;
e32eb50d 2606 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 2607 uint32_t rdp, wdp;
2608 unsigned count, i, j;
2609
e32eb50d 2610 radeon_ring_free_size(rdev, ring);
771fe6b9
JG		 2611 rdp = RREG32(RADEON_CP_RB_RPTR);
2612 wdp = RREG32(RADEON_CP_RB_WPTR);
e32eb50d 2613 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
771fe6b9
JG		 2614 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2615 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2616 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
e32eb50d 2617 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
771fe6b9
JG		 2618 seq_printf(m, "%u dwords in ring\n", count);
2619 for (j = 0; j <= count; j++) {
e32eb50d
CK		 2620 i = (rdp + j) & ring->ptr_mask;
2621 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
771fe6b9
JG		 2622 }
2623 return 0;
2624}
2625
2626
2627static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2628{
2629 struct drm_info_node *node = (struct drm_info_node *) m->private;
2630 struct drm_device *dev = node->minor->dev;
2631 struct radeon_device *rdev = dev->dev_private;
2632 uint32_t csq_stat, csq2_stat, tmp;
2633 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2634 unsigned i;
2635
2636 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2637 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2638 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2639 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2640 r_rptr = (csq_stat >> 0) & 0x3ff;
2641 r_wptr = (csq_stat >> 10) & 0x3ff;
2642 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2643 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2644 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2645 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2646 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2647 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2648 seq_printf(m, "Ring rptr %u\n", r_rptr);
2649 seq_printf(m, "Ring wptr %u\n", r_wptr);
2650 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2651 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2652 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2653 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2654 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2655 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2656 seq_printf(m, "Ring fifo:\n");
2657 for (i = 0; i < 256; i++) {
2658 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2659 tmp = RREG32(RADEON_CP_CSQ_DATA);
2660 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2661 }
2662 seq_printf(m, "Indirect1 fifo:\n");
2663 for (i = 256; i <= 512; i++) {
2664 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2665 tmp = RREG32(RADEON_CP_CSQ_DATA);
2666 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2667 }
2668 seq_printf(m, "Indirect2 fifo:\n");
2669 for (i = 640; i < ib1_wptr; i++) {
2670 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2671 tmp = RREG32(RADEON_CP_CSQ_DATA);
2672 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2673 }
2674 return 0;
2675}
2676
2677static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2678{
2679 struct drm_info_node *node = (struct drm_info_node *) m->private;
2680 struct drm_device *dev = node->minor->dev;
2681 struct radeon_device *rdev = dev->dev_private;
2682 uint32_t tmp;
2683
2684 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2685 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2686 tmp = RREG32(RADEON_MC_FB_LOCATION);
2687 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2688 tmp = RREG32(RADEON_BUS_CNTL);
2689 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2690 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2691 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2692 tmp = RREG32(RADEON_AGP_BASE);
2693 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2694 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2695 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2696 tmp = RREG32(0x01D0);
2697 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2698 tmp = RREG32(RADEON_AIC_LO_ADDR);
2699 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2700 tmp = RREG32(RADEON_AIC_HI_ADDR);
2701 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2702 tmp = RREG32(0x01E4);
2703 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2704 return 0;
2705}
2706
2707static struct drm_info_list r100_debugfs_rbbm_list[] = {
2708 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2709};
2710
2711static struct drm_info_list r100_debugfs_cp_list[] = {
2712 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2713 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2714};
2715
2716static struct drm_info_list r100_debugfs_mc_info_list[] = {
2717 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2718};
2719#endif
2720
2721int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2722{
2723#if defined(CONFIG_DEBUG_FS)
2724 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2725#else
2726 return 0;
2727#endif
2728}
2729
2730int r100_debugfs_cp_init(struct radeon_device *rdev)
2731{
2732#if defined(CONFIG_DEBUG_FS)
2733 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2734#else
2735 return 0;
2736#endif
2737}
2738
2739int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2740{
2741#if defined(CONFIG_DEBUG_FS)
2742 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2743#else
2744 return 0;
2745#endif
2746}
e024e110
DA		 2747
2748int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2749 uint32_t tiling_flags, uint32_t pitch,
2750 uint32_t offset, uint32_t obj_size)
2751{
2752 int surf_index = reg * 16;
2753 int flags = 0;
2754
e024e110
DA		 2755 if (rdev->family <= CHIP_RS200) {
2756 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2757 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2758 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2759 if (tiling_flags & RADEON_TILING_MACRO)
2760 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2761 } else if (rdev->family <= CHIP_RV280) {
2762 if (tiling_flags & (RADEON_TILING_MACRO))
2763 flags |= R200_SURF_TILE_COLOR_MACRO;
2764 if (tiling_flags & RADEON_TILING_MICRO)
2765 flags |= R200_SURF_TILE_COLOR_MICRO;
2766 } else {
2767 if (tiling_flags & RADEON_TILING_MACRO)
2768 flags |= R300_SURF_TILE_MACRO;
2769 if (tiling_flags & RADEON_TILING_MICRO)
2770 flags |= R300_SURF_TILE_MICRO;
2771 }
2772
c88f9f0c
MD		 2773 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2774 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2775 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2776 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2777
f5c5f040
DA		 2778 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2779 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2780 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2781 if (ASIC_IS_RN50(rdev))
2782 pitch /= 16;
2783 }
2784
2785 /* r100/r200 divide by 16 */
2786 if (rdev->family < CHIP_R300)
2787 flags |= pitch / 16;
2788 else
2789 flags |= pitch / 8;
2790
2791
d9fdaafb 2792 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
e024e110
DA		 2793 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2794 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2795 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2796 return 0;
2797}
2798
2799void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2800{
2801 int surf_index = reg * 16;
2802 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2803}
c93bb85b
JG		 2804
2805void r100_bandwidth_update(struct radeon_device *rdev)
2806{
2807 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2808 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2809 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2810 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2811 fixed20_12 memtcas_ff[8] = {
68adac5e
BS		 2812 dfixed_init(1),
2813 dfixed_init(2),
2814 dfixed_init(3),
2815 dfixed_init(0),
2816 dfixed_init_half(1),
2817 dfixed_init_half(2),
2818 dfixed_init(0),
c93bb85b
JG		 2819 };
2820 fixed20_12 memtcas_rs480_ff[8] = {
68adac5e
BS		 2821 dfixed_init(0),
2822 dfixed_init(1),
2823 dfixed_init(2),
2824 dfixed_init(3),
2825 dfixed_init(0),
2826 dfixed_init_half(1),
2827 dfixed_init_half(2),
2828 dfixed_init_half(3),
c93bb85b
JG		 2829 };
2830 fixed20_12 memtcas2_ff[8] = {
68adac5e
BS		 2831 dfixed_init(0),
2832 dfixed_init(1),
2833 dfixed_init(2),
2834 dfixed_init(3),
2835 dfixed_init(4),
2836 dfixed_init(5),
2837 dfixed_init(6),
2838 dfixed_init(7),
c93bb85b
JG		 2839 };
2840 fixed20_12 memtrbs[8] = {
68adac5e
BS		 2841 dfixed_init(1),
2842 dfixed_init_half(1),
2843 dfixed_init(2),
2844 dfixed_init_half(2),
2845 dfixed_init(3),
2846 dfixed_init_half(3),
2847 dfixed_init(4),
2848 dfixed_init_half(4)
c93bb85b
JG		 2849 };
2850 fixed20_12 memtrbs_r4xx[8] = {
68adac5e
BS		 2851 dfixed_init(4),
2852 dfixed_init(5),
2853 dfixed_init(6),
2854 dfixed_init(7),
2855 dfixed_init(8),
2856 dfixed_init(9),
2857 dfixed_init(10),
2858 dfixed_init(11)
c93bb85b
JG		 2859 };
2860 fixed20_12 min_mem_eff;
2861 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2862 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2863 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2864 disp_drain_rate2, read_return_rate;
2865 fixed20_12 time_disp1_drop_priority;
2866 int c;
2867 int cur_size = 16; /* in octawords */
2868 int critical_point = 0, critical_point2;
2869/* uint32_t read_return_rate, time_disp1_drop_priority; */
2870 int stop_req, max_stop_req;
2871 struct drm_display_mode *mode1 = NULL;
2872 struct drm_display_mode *mode2 = NULL;
2873 uint32_t pixel_bytes1 = 0;
2874 uint32_t pixel_bytes2 = 0;
2875
f46c0120
AD		 2876 radeon_update_display_priority(rdev);
2877
c93bb85b
JG		 2878 if (rdev->mode_info.crtcs[0]->base.enabled) {
2879 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2880 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2881 }
dfee5614
DA		 2882 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2883 if (rdev->mode_info.crtcs[1]->base.enabled) {
2884 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2885 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2886 }
c93bb85b
JG		 2887 }
2888
68adac5e 2889 min_mem_eff.full = dfixed_const_8(0);
c93bb85b
JG		 2890 /* get modes */
2891 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2892 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2893 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2894 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2895 /* check crtc enables */
2896 if (mode2)
2897 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2898 if (mode1)
2899 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2900 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2901 }
2902
2903 /*
2904 * determine is there is enough bw for current mode
2905 */
f47299c5
AD		 2906 sclk_ff = rdev->pm.sclk;
2907 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2908
2909 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
68adac5e
BS		 2910 temp_ff.full = dfixed_const(temp);
2911 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 2912
2913 pix_clk.full = 0;
2914 pix_clk2.full = 0;
2915 peak_disp_bw.full = 0;
2916 if (mode1) {
68adac5e
BS		 2917 temp_ff.full = dfixed_const(1000);
2918 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2919 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2920 temp_ff.full = dfixed_const(pixel_bytes1);
2921 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
c93bb85b
JG		 2922 }
2923 if (mode2) {
68adac5e
BS		 2924 temp_ff.full = dfixed_const(1000);
2925 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2926 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2927 temp_ff.full = dfixed_const(pixel_bytes2);
2928 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
c93bb85b
JG		 2929 }
2930
68adac5e 2931 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
c93bb85b
JG		 2932 if (peak_disp_bw.full >= mem_bw.full) {
2933 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2934 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2935 }
2936
2937 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2938 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2939 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2940 mem_trcd = ((temp >> 2) & 0x3) + 1;
2941 mem_trp = ((temp & 0x3)) + 1;
2942 mem_tras = ((temp & 0x70) >> 4) + 1;
2943 } else if (rdev->family == CHIP_R300 ||
2944 rdev->family == CHIP_R350) { /* r300, r350 */
2945 mem_trcd = (temp & 0x7) + 1;
2946 mem_trp = ((temp >> 8) & 0x7) + 1;
2947 mem_tras = ((temp >> 11) & 0xf) + 4;
2948 } else if (rdev->family == CHIP_RV350 ||
2949 rdev->family <= CHIP_RV380) {
2950 /* rv3x0 */
2951 mem_trcd = (temp & 0x7) + 3;
2952 mem_trp = ((temp >> 8) & 0x7) + 3;
2953 mem_tras = ((temp >> 11) & 0xf) + 6;
2954 } else if (rdev->family == CHIP_R420 ||
2955 rdev->family == CHIP_R423 ||
2956 rdev->family == CHIP_RV410) {
2957 /* r4xx */
2958 mem_trcd = (temp & 0xf) + 3;
2959 if (mem_trcd > 15)
2960 mem_trcd = 15;
2961 mem_trp = ((temp >> 8) & 0xf) + 3;
2962 if (mem_trp > 15)
2963 mem_trp = 15;
2964 mem_tras = ((temp >> 12) & 0x1f) + 6;
2965 if (mem_tras > 31)
2966 mem_tras = 31;
2967 } else { /* RV200, R200 */
2968 mem_trcd = (temp & 0x7) + 1;
2969 mem_trp = ((temp >> 8) & 0x7) + 1;
2970 mem_tras = ((temp >> 12) & 0xf) + 4;
2971 }
2972 /* convert to FF */
68adac5e
BS		 2973 trcd_ff.full = dfixed_const(mem_trcd);
2974 trp_ff.full = dfixed_const(mem_trp);
2975 tras_ff.full = dfixed_const(mem_tras);
c93bb85b
JG		 2976
2977 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2978 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2979 data = (temp & (7 << 20)) >> 20;
2980 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2981 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2982 tcas_ff = memtcas_rs480_ff[data];
2983 else
2984 tcas_ff = memtcas_ff[data];
2985 } else
2986 tcas_ff = memtcas2_ff[data];
2987
2988 if (rdev->family == CHIP_RS400 ||
2989 rdev->family == CHIP_RS480) {
2990 /* extra cas latency stored in bits 23-25 0-4 clocks */
2991 data = (temp >> 23) & 0x7;
2992 if (data < 5)
68adac5e 2993 tcas_ff.full += dfixed_const(data);
c93bb85b
JG		 2994 }
2995
2996 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2997 /* on the R300, Tcas is included in Trbs.
2998 */
2999 temp = RREG32(RADEON_MEM_CNTL);
3000 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3001 if (data == 1) {
3002 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3003 temp = RREG32(R300_MC_IND_INDEX);
3004 temp &= ~R300_MC_IND_ADDR_MASK;
3005 temp |= R300_MC_READ_CNTL_CD_mcind;
3006 WREG32(R300_MC_IND_INDEX, temp);
3007 temp = RREG32(R300_MC_IND_DATA);
3008 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3009 } else {
3010 temp = RREG32(R300_MC_READ_CNTL_AB);
3011 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3012 }
3013 } else {
3014 temp = RREG32(R300_MC_READ_CNTL_AB);
3015 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3016 }
3017 if (rdev->family == CHIP_RV410 ||
3018 rdev->family == CHIP_R420 ||
3019 rdev->family == CHIP_R423)
3020 trbs_ff = memtrbs_r4xx[data];
3021 else
3022 trbs_ff = memtrbs[data];
3023 tcas_ff.full += trbs_ff.full;
3024 }
3025
3026 sclk_eff_ff.full = sclk_ff.full;
3027
3028 if (rdev->flags & RADEON_IS_AGP) {
3029 fixed20_12 agpmode_ff;
68adac5e
BS		 3030 agpmode_ff.full = dfixed_const(radeon_agpmode);
3031 temp_ff.full = dfixed_const_666(16);
3032 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
c93bb85b
JG		 3033 }
3034 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3035
3036 if (ASIC_IS_R300(rdev)) {
68adac5e 3037 sclk_delay_ff.full = dfixed_const(250);
c93bb85b
JG		 3038 } else {
3039 if ((rdev->family == CHIP_RV100) ||
3040 rdev->flags & RADEON_IS_IGP) {
3041 if (rdev->mc.vram_is_ddr)
68adac5e 3042 sclk_delay_ff.full = dfixed_const(41);
c93bb85b 3043 else
68adac5e 3044 sclk_delay_ff.full = dfixed_const(33);
c93bb85b
JG		 3045 } else {
3046 if (rdev->mc.vram_width == 128)
68adac5e 3047 sclk_delay_ff.full = dfixed_const(57);
c93bb85b 3048 else
68adac5e 3049 sclk_delay_ff.full = dfixed_const(41);
c93bb85b
JG		 3050 }
3051 }
3052
68adac5e 3053 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
c93bb85b
JG		 3054
3055 if (rdev->mc.vram_is_ddr) {
3056 if (rdev->mc.vram_width == 32) {
68adac5e 3057 k1.full = dfixed_const(40);
c93bb85b
JG		 3058 c = 3;
3059 } else {
68adac5e 3060 k1.full = dfixed_const(20);
c93bb85b
JG		 3061 c = 1;
3062 }
3063 } else {
68adac5e 3064 k1.full = dfixed_const(40);
c93bb85b
JG		 3065 c = 3;
3066 }
3067
68adac5e
BS		 3068 temp_ff.full = dfixed_const(2);
3069 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3070 temp_ff.full = dfixed_const(c);
3071 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3072 temp_ff.full = dfixed_const(4);
3073 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3074 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
c93bb85b
JG		 3075 mc_latency_mclk.full += k1.full;
3076
68adac5e
BS		 3077 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3078 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3079
3080 /*
3081 HW cursor time assuming worst case of full size colour cursor.
3082 */
68adac5e 3083 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
c93bb85b
JG		 3084 temp_ff.full += trcd_ff.full;
3085 if (temp_ff.full < tras_ff.full)
3086 temp_ff.full = tras_ff.full;
68adac5e 3087 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
c93bb85b 3088
68adac5e
BS		 3089 temp_ff.full = dfixed_const(cur_size);
3090 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 3091 /*
3092 Find the total latency for the display data.
3093 */
68adac5e
BS		 3094 disp_latency_overhead.full = dfixed_const(8);
3095 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
c93bb85b
JG		 3096 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3097 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3098
3099 if (mc_latency_mclk.full > mc_latency_sclk.full)
3100 disp_latency.full = mc_latency_mclk.full;
3101 else
3102 disp_latency.full = mc_latency_sclk.full;
3103
3104 /* setup Max GRPH_STOP_REQ default value */
3105 if (ASIC_IS_RV100(rdev))
3106 max_stop_req = 0x5c;
3107 else
3108 max_stop_req = 0x7c;
3109
3110 if (mode1) {
3111 /* CRTC1
3112 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3113 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3114 */
3115 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3116
3117 if (stop_req > max_stop_req)
3118 stop_req = max_stop_req;
3119
3120 /*
3121 Find the drain rate of the display buffer.
3122 */
68adac5e
BS		 3123 temp_ff.full = dfixed_const((16/pixel_bytes1));
3124 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
c93bb85b
JG		 3125
3126 /*
3127 Find the critical point of the display buffer.
3128 */
68adac5e
BS		 3129 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3130 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3131
68adac5e 3132 critical_point = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3133
3134 if (rdev->disp_priority == 2) {
3135 critical_point = 0;
3136 }
3137
3138 /*
3139 The critical point should never be above max_stop_req-4. Setting
3140 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3141 */
3142 if (max_stop_req - critical_point < 4)
3143 critical_point = 0;
3144
3145 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3146 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3147 critical_point = 0x10;
3148 }
3149
3150 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3151 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3152 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3153 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3154 if ((rdev->family == CHIP_R350) &&
3155 (stop_req > 0x15)) {
3156 stop_req -= 0x10;
3157 }
3158 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3159 temp |= RADEON_GRPH_BUFFER_SIZE;
3160 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3161 RADEON_GRPH_CRITICAL_AT_SOF |
3162 RADEON_GRPH_STOP_CNTL);
3163 /*
3164 Write the result into the register.
3165 */
3166 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3167 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3168
3169#if 0
3170 if ((rdev->family == CHIP_RS400) ||
3171 (rdev->family == CHIP_RS480)) {
3172 /* attempt to program RS400 disp regs correctly ??? */
3173 temp = RREG32(RS400_DISP1_REG_CNTL);
3174 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3175 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3176 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3177 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3178 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3179 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3180 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3181 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3182 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3183 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3184 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3185 }
3186#endif
3187
d9fdaafb 3188 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3189 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3190 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3191 }
3192
3193 if (mode2) {
3194 u32 grph2_cntl;
3195 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3196
3197 if (stop_req > max_stop_req)
3198 stop_req = max_stop_req;
3199
3200 /*
3201 Find the drain rate of the display buffer.
3202 */
68adac5e
BS		 3203 temp_ff.full = dfixed_const((16/pixel_bytes2));
3204 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
c93bb85b
JG		 3205
3206 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3207 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3208 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3209 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3210 if ((rdev->family == CHIP_R350) &&
3211 (stop_req > 0x15)) {
3212 stop_req -= 0x10;
3213 }
3214 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3215 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3216 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3217 RADEON_GRPH_CRITICAL_AT_SOF |
3218 RADEON_GRPH_STOP_CNTL);
3219
3220 if ((rdev->family == CHIP_RS100) ||
3221 (rdev->family == CHIP_RS200))
3222 critical_point2 = 0;
3223 else {
3224 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
68adac5e
BS		 3225 temp_ff.full = dfixed_const(temp);
3226 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 3227 if (sclk_ff.full < temp_ff.full)
3228 temp_ff.full = sclk_ff.full;
3229
3230 read_return_rate.full = temp_ff.full;
3231
3232 if (mode1) {
3233 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
68adac5e 3234 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
c93bb85b
JG		 3235 } else {
3236 time_disp1_drop_priority.full = 0;
3237 }
3238 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
68adac5e
BS		 3239 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3240 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3241
68adac5e 3242 critical_point2 = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3243
3244 if (rdev->disp_priority == 2) {
3245 critical_point2 = 0;
3246 }
3247
3248 if (max_stop_req - critical_point2 < 4)
3249 critical_point2 = 0;
3250
3251 }
3252
3253 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3254 /* some R300 cards have problem with this set to 0 */
3255 critical_point2 = 0x10;
3256 }
3257
3258 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3259 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3260
3261 if ((rdev->family == CHIP_RS400) ||
3262 (rdev->family == CHIP_RS480)) {
3263#if 0
3264 /* attempt to program RS400 disp2 regs correctly ??? */
3265 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3266 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3267 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3268 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3269 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3270 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3271 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3272 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3273 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3274 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3275 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3276 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3277#endif
3278 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3279 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3280 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3281 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3282 }
3283
d9fdaafb 3284 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3285 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3286 }
3287}
551ebd83 3288
cbdd4501 3289static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
551ebd83
DA		 3290{
3291 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 3292 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 3293 DRM_ERROR("width %d\n", t->width);
ceb776bc 3294 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 3295 DRM_ERROR("height %d\n", t->height);
ceb776bc 3296 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 3297 DRM_ERROR("num levels %d\n", t->num_levels);
3298 DRM_ERROR("depth %d\n", t->txdepth);
3299 DRM_ERROR("bpp %d\n", t->cpp);
3300 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3301 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3302 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 3303 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 3304}
3305
d785d78b
DA		 3306static int r100_track_compress_size(int compress_format, int w, int h)
3307{
3308 int block_width, block_height, block_bytes;
3309 int wblocks, hblocks;
3310 int min_wblocks;
3311 int sz;
3312
3313 block_width = 4;
3314 block_height = 4;
3315
3316 switch (compress_format) {
3317 case R100_TRACK_COMP_DXT1:
3318 block_bytes = 8;
3319 min_wblocks = 4;
3320 break;
3321 default:
3322 case R100_TRACK_COMP_DXT35:
3323 block_bytes = 16;
3324 min_wblocks = 2;
3325 break;
3326 }
3327
3328 hblocks = (h + block_height - 1) / block_height;
3329 wblocks = (w + block_width - 1) / block_width;
3330 if (wblocks < min_wblocks)
3331 wblocks = min_wblocks;
3332 sz = wblocks * hblocks * block_bytes;
3333 return sz;
3334}
3335
37cf6b03
RS		 3336static int r100_cs_track_cube(struct radeon_device *rdev,
3337 struct r100_cs_track *track, unsigned idx)
3338{
3339 unsigned face, w, h;
3340 struct radeon_bo *cube_robj;
3341 unsigned long size;
3342 unsigned compress_format = track->textures[idx].compress_format;
3343
3344 for (face = 0; face < 5; face++) {
3345 cube_robj = track->textures[idx].cube_info[face].robj;
3346 w = track->textures[idx].cube_info[face].width;
3347 h = track->textures[idx].cube_info[face].height;
3348
3349 if (compress_format) {
3350 size = r100_track_compress_size(compress_format, w, h);
3351 } else
3352 size = w * h;
3353 size *= track->textures[idx].cpp;
3354
3355 size += track->textures[idx].cube_info[face].offset;
3356
3357 if (size > radeon_bo_size(cube_robj)) {
3358 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3359 size, radeon_bo_size(cube_robj));
3360 r100_cs_track_texture_print(&track->textures[idx]);
3361 return -1;
3362 }
3363 }
3364 return 0;
3365}
3366
551ebd83
DA		 3367static int r100_cs_track_texture_check(struct radeon_device *rdev,
3368 struct r100_cs_track *track)
3369{
4c788679 3370 struct radeon_bo *robj;
551ebd83 3371 unsigned long size;
b73c5f8b 3372 unsigned u, i, w, h, d;
551ebd83
DA		 3373 int ret;
3374
3375 for (u = 0; u < track->num_texture; u++) {
3376 if (!track->textures[u].enabled)
3377 continue;
43b93fbf
AD		 3378 if (track->textures[u].lookup_disable)
3379 continue;
551ebd83
DA		 3380 robj = track->textures[u].robj;
3381 if (robj == NULL) {
3382 DRM_ERROR("No texture bound to unit %u\n", u);
3383 return -EINVAL;
3384 }
3385 size = 0;
3386 for (i = 0; i <= track->textures[u].num_levels; i++) {
3387 if (track->textures[u].use_pitch) {
3388 if (rdev->family < CHIP_R300)
3389 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3390 else
3391 w = track->textures[u].pitch / (1 << i);
3392 } else {
ceb776bc 3393 w = track->textures[u].width;
551ebd83
DA		 3394 if (rdev->family >= CHIP_RV515)
3395 w |= track->textures[u].width_11;
ceb776bc 3396 w = w / (1 << i);
551ebd83
DA		 3397 if (track->textures[u].roundup_w)
3398 w = roundup_pow_of_two(w);
3399 }
ceb776bc 3400 h = track->textures[u].height;
551ebd83
DA		 3401 if (rdev->family >= CHIP_RV515)
3402 h |= track->textures[u].height_11;
ceb776bc 3403 h = h / (1 << i);
551ebd83
DA		 3404 if (track->textures[u].roundup_h)
3405 h = roundup_pow_of_two(h);
b73c5f8b
MO		 3406 if (track->textures[u].tex_coord_type == 1) {
3407 d = (1 << track->textures[u].txdepth) / (1 << i);
3408 if (!d)
3409 d = 1;
3410 } else {
3411 d = 1;
3412 }
d785d78b
DA		 3413 if (track->textures[u].compress_format) {
3414
b73c5f8b 3415 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
d785d78b
DA		 3416 /* compressed textures are block based */
3417 } else
b73c5f8b 3418 size += w * h * d;
551ebd83
DA		 3419 }
3420 size *= track->textures[u].cpp;
d785d78b 3421
551ebd83
DA		 3422 switch (track->textures[u].tex_coord_type) {
3423 case 0:
551ebd83 3424 case 1:
551ebd83
DA		 3425 break;
3426 case 2:
3427 if (track->separate_cube) {
3428 ret = r100_cs_track_cube(rdev, track, u);
3429 if (ret)
3430 return ret;
3431 } else
3432 size *= 6;
3433 break;
3434 default:
3435 DRM_ERROR("Invalid texture coordinate type %u for unit "
3436 "%u\n", track->textures[u].tex_coord_type, u);
3437 return -EINVAL;
3438 }
4c788679 3439 if (size > radeon_bo_size(robj)) {
551ebd83 3440 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 3441 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 3442 r100_cs_track_texture_print(&track->textures[u]);
3443 return -EINVAL;
3444 }
3445 }
3446 return 0;
3447}
3448
3449int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3450{
3451 unsigned i;
3452 unsigned long size;
3453 unsigned prim_walk;
3454 unsigned nverts;
40b4a759 3455 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
551ebd83 3456
40b4a759 3457 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
a41ceb1c
MO		 3458 !track->blend_read_enable)
3459 num_cb = 0;
3460
3461 for (i = 0; i < num_cb; i++) {
551ebd83
DA		 3462 if (track->cb[i].robj == NULL) {
3463 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3464 return -EINVAL;
3465 }
3466 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3467 size += track->cb[i].offset;
4c788679 3468 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 3469 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3470 "(need %lu have %lu) !\n", i, size,
4c788679 3471 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 3472 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3473 i, track->cb[i].pitch, track->cb[i].cpp,
3474 track->cb[i].offset, track->maxy);
3475 return -EINVAL;
3476 }
3477 }
40b4a759
MO		 3478 track->cb_dirty = false;
3479
3480 if (track->zb_dirty && track->z_enabled) {
551ebd83
DA		 3481 if (track->zb.robj == NULL) {
3482 DRM_ERROR("[drm] No buffer for z buffer !\n");
3483 return -EINVAL;
3484 }
3485 size = track->zb.pitch * track->zb.cpp * track->maxy;
3486 size += track->zb.offset;
4c788679 3487 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 3488 DRM_ERROR("[drm] Buffer too small for z buffer "
3489 "(need %lu have %lu) !\n", size,
4c788679 3490 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3491 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3492 track->zb.pitch, track->zb.cpp,
3493 track->zb.offset, track->maxy);
3494 return -EINVAL;
3495 }
3496 }
40b4a759
MO		 3497 track->zb_dirty = false;
3498
fff1ce4d
MO		 3499 if (track->aa_dirty && track->aaresolve) {
3500 if (track->aa.robj == NULL) {
3501 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3502 return -EINVAL;
3503 }
3504 /* I believe the format comes from colorbuffer0. */
3505 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3506 size += track->aa.offset;
3507 if (size > radeon_bo_size(track->aa.robj)) {
3508 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3509 "(need %lu have %lu) !\n", i, size,
3510 radeon_bo_size(track->aa.robj));
3511 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3512 i, track->aa.pitch, track->cb[0].cpp,
3513 track->aa.offset, track->maxy);
3514 return -EINVAL;
3515 }
3516 }
3517 track->aa_dirty = false;
3518
551ebd83 3519 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
cae94b0a
MO		 3520 if (track->vap_vf_cntl & (1 << 14)) {
3521 nverts = track->vap_alt_nverts;
3522 } else {
3523 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3524 }
551ebd83
DA		 3525 switch (prim_walk) {
3526 case 1:
3527 for (i = 0; i < track->num_arrays; i++) {
3528 size = track->arrays[i].esize * track->max_indx * 4;
3529 if (track->arrays[i].robj == NULL) {
3530 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3531 "bound\n", prim_walk, i);
3532 return -EINVAL;
3533 }
4c788679
JG		 3534 if (size > radeon_bo_size(track->arrays[i].robj)) {
3535 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3536 "need %lu dwords have %lu dwords\n",
3537 prim_walk, i, size >> 2,
3538 radeon_bo_size(track->arrays[i].robj)
3539 >> 2);
551ebd83
DA		 3540 DRM_ERROR("Max indices %u\n", track->max_indx);
3541 return -EINVAL;
3542 }
3543 }
3544 break;
3545 case 2:
3546 for (i = 0; i < track->num_arrays; i++) {
3547 size = track->arrays[i].esize * (nverts - 1) * 4;
3548 if (track->arrays[i].robj == NULL) {
3549 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3550 "bound\n", prim_walk, i);
3551 return -EINVAL;
3552 }
4c788679
JG		 3553 if (size > radeon_bo_size(track->arrays[i].robj)) {
3554 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3555 "need %lu dwords have %lu dwords\n",
3556 prim_walk, i, size >> 2,
3557 radeon_bo_size(track->arrays[i].robj)
3558 >> 2);
551ebd83
DA		 3559 return -EINVAL;
3560 }
3561 }
3562 break;
3563 case 3:
3564 size = track->vtx_size * nverts;
3565 if (size != track->immd_dwords) {
3566 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3567 track->immd_dwords, size);
3568 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3569 nverts, track->vtx_size);
3570 return -EINVAL;
3571 }
3572 break;
3573 default:
3574 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3575 prim_walk);
3576 return -EINVAL;
3577 }
40b4a759
MO		 3578
3579 if (track->tex_dirty) {
3580 track->tex_dirty = false;
3581 return r100_cs_track_texture_check(rdev, track);
3582 }
3583 return 0;
551ebd83
DA		 3584}
3585
3586void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3587{
3588 unsigned i, face;
3589
40b4a759
MO		 3590 track->cb_dirty = true;
3591 track->zb_dirty = true;
3592 track->tex_dirty = true;
fff1ce4d 3593 track->aa_dirty = true;
40b4a759 3594
551ebd83
DA		 3595 if (rdev->family < CHIP_R300) {
3596 track->num_cb = 1;
3597 if (rdev->family <= CHIP_RS200)
3598 track->num_texture = 3;
3599 else
3600 track->num_texture = 6;
3601 track->maxy = 2048;
3602 track->separate_cube = 1;
3603 } else {
3604 track->num_cb = 4;
3605 track->num_texture = 16;
3606 track->maxy = 4096;
3607 track->separate_cube = 0;
45e4039c 3608 track->aaresolve = false;
fff1ce4d 3609 track->aa.robj = NULL;
551ebd83
DA		 3610 }
3611
3612 for (i = 0; i < track->num_cb; i++) {
3613 track->cb[i].robj = NULL;
3614 track->cb[i].pitch = 8192;
3615 track->cb[i].cpp = 16;
3616 track->cb[i].offset = 0;
3617 }
3618 track->z_enabled = true;
3619 track->zb.robj = NULL;
3620 track->zb.pitch = 8192;
3621 track->zb.cpp = 4;
3622 track->zb.offset = 0;
3623 track->vtx_size = 0x7F;
3624 track->immd_dwords = 0xFFFFFFFFUL;
3625 track->num_arrays = 11;
3626 track->max_indx = 0x00FFFFFFUL;
3627 for (i = 0; i < track->num_arrays; i++) {
3628 track->arrays[i].robj = NULL;
3629 track->arrays[i].esize = 0x7F;
3630 }
3631 for (i = 0; i < track->num_texture; i++) {
d785d78b 3632 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3633 track->textures[i].pitch = 16536;
3634 track->textures[i].width = 16536;
3635 track->textures[i].height = 16536;
3636 track->textures[i].width_11 = 1 << 11;
3637 track->textures[i].height_11 = 1 << 11;
3638 track->textures[i].num_levels = 12;
3639 if (rdev->family <= CHIP_RS200) {
3640 track->textures[i].tex_coord_type = 0;
3641 track->textures[i].txdepth = 0;
3642 } else {
3643 track->textures[i].txdepth = 16;
3644 track->textures[i].tex_coord_type = 1;
3645 }
3646 track->textures[i].cpp = 64;
3647 track->textures[i].robj = NULL;
3648 /* CS IB emission code makes sure texture unit are disabled */
3649 track->textures[i].enabled = false;
43b93fbf 3650 track->textures[i].lookup_disable = false;
551ebd83
DA		 3651 track->textures[i].roundup_w = true;
3652 track->textures[i].roundup_h = true;
3653 if (track->separate_cube)
3654 for (face = 0; face < 5; face++) {
3655 track->textures[i].cube_info[face].robj = NULL;
3656 track->textures[i].cube_info[face].width = 16536;
3657 track->textures[i].cube_info[face].height = 16536;
3658 track->textures[i].cube_info[face].offset = 0;
3659 }
3660 }
3661}
3ce0a23d 3662
e32eb50d 3663int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3664{
3665 uint32_t scratch;
3666 uint32_t tmp = 0;
3667 unsigned i;
3668 int r;
3669
3670 r = radeon_scratch_get(rdev, &scratch);
3671 if (r) {
3672 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3673 return r;
3674 }
3675 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3676 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3677 if (r) {
3678 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3679 radeon_scratch_free(rdev, scratch);
3680 return r;
3681 }
e32eb50d
CK		 3682 radeon_ring_write(ring, PACKET0(scratch, 0));
3683 radeon_ring_write(ring, 0xDEADBEEF);
3684 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 3685 for (i = 0; i < rdev->usec_timeout; i++) {
3686 tmp = RREG32(scratch);
3687 if (tmp == 0xDEADBEEF) {
3688 break;
3689 }
3690 DRM_UDELAY(1);
3691 }
3692 if (i < rdev->usec_timeout) {
3693 DRM_INFO("ring test succeeded in %d usecs\n", i);
3694 } else {
369d7ec1 3695 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3696 scratch, tmp);
3697 r = -EINVAL;
3698 }
3699 radeon_scratch_free(rdev, scratch);
3700 return r;
3701}
3702
3703void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3704{
e32eb50d 3705 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3706
e32eb50d
CK		 3707 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3708 radeon_ring_write(ring, ib->gpu_addr);
3709 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3710}
3711
3712int r100_ib_test(struct radeon_device *rdev)
3713{
3714 struct radeon_ib *ib;
3715 uint32_t scratch;
3716 uint32_t tmp = 0;
3717 unsigned i;
3718 int r;
3719
3720 r = radeon_scratch_get(rdev, &scratch);
3721 if (r) {
3722 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3723 return r;
3724 }
3725 WREG32(scratch, 0xCAFEDEAD);
69e130a6 3726 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3ce0a23d
JG		 3727 if (r) {
3728 return r;
3729 }
3730 ib->ptr[0] = PACKET0(scratch, 0);
3731 ib->ptr[1] = 0xDEADBEEF;
3732 ib->ptr[2] = PACKET2(0);
3733 ib->ptr[3] = PACKET2(0);
3734 ib->ptr[4] = PACKET2(0);
3735 ib->ptr[5] = PACKET2(0);
3736 ib->ptr[6] = PACKET2(0);
3737 ib->ptr[7] = PACKET2(0);
3738 ib->length_dw = 8;
3739 r = radeon_ib_schedule(rdev, ib);
3740 if (r) {
3741 radeon_scratch_free(rdev, scratch);
3742 radeon_ib_free(rdev, &ib);
3743 return r;
3744 }
3745 r = radeon_fence_wait(ib->fence, false);
3746 if (r) {
3747 return r;
3748 }
3749 for (i = 0; i < rdev->usec_timeout; i++) {
3750 tmp = RREG32(scratch);
3751 if (tmp == 0xDEADBEEF) {
3752 break;
3753 }
3754 DRM_UDELAY(1);
3755 }
3756 if (i < rdev->usec_timeout) {
3757 DRM_INFO("ib test succeeded in %u usecs\n", i);
3758 } else {
62f288cf 3759 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3760 scratch, tmp);
3761 r = -EINVAL;
3762 }
3763 radeon_scratch_free(rdev, scratch);
3764 radeon_ib_free(rdev, &ib);
3765 return r;
3766}
9f022ddf
JG		 3767
3768void r100_ib_fini(struct radeon_device *rdev)
3769{
b15ba512 3770 radeon_ib_pool_suspend(rdev);
9f022ddf
JG		 3771 radeon_ib_pool_fini(rdev);
3772}
3773
9f022ddf
JG		 3774void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3775{
3776 /* Shutdown CP we shouldn't need to do that but better be safe than
3777 * sorry
3778 */
e32eb50d 3779 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3780 WREG32(R_000740_CP_CSQ_CNTL, 0);
3781
3782 /* Save few CRTC registers */
ca6ffc64 3783 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3784 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3785 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3786 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3787 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3788 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3789 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3790 }
3791
3792 /* Disable VGA aperture access */
ca6ffc64 3793 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3794 /* Disable cursor, overlay, crtc */
3795 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3796 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3797 S_000054_CRTC_DISPLAY_DIS(1));
3798 WREG32(R_000050_CRTC_GEN_CNTL,
3799 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3800 S_000050_CRTC_DISP_REQ_EN_B(1));
3801 WREG32(R_000420_OV0_SCALE_CNTL,
3802 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3803 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3804 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3805 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3806 S_000360_CUR2_LOCK(1));
3807 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3808 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3809 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3810 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3811 WREG32(R_000360_CUR2_OFFSET,
3812 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3813 }
3814}
3815
3816void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3817{
3818 /* Update base address for crtc */
d594e46a 3819 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3820 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3821 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3822 }
3823 /* Restore CRTC registers */
ca6ffc64 3824 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3825 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3826 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3827 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3828 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3829 }
3830}
ca6ffc64
JG		 3831
3832void r100_vga_render_disable(struct radeon_device *rdev)
3833{
d4550907 3834 u32 tmp;
ca6ffc64 3835
d4550907 3836 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3837 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3838}
d4550907
JG		 3839
3840static void r100_debugfs(struct radeon_device *rdev)
3841{
3842 int r;
3843
3844 r = r100_debugfs_mc_info_init(rdev);
3845 if (r)
3846 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3847}
3848
3849static void r100_mc_program(struct radeon_device *rdev)
3850{
3851 struct r100_mc_save save;
3852
3853 /* Stops all mc clients */
3854 r100_mc_stop(rdev, &save);
3855 if (rdev->flags & RADEON_IS_AGP) {
3856 WREG32(R_00014C_MC_AGP_LOCATION,
3857 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3858 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3859 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3860 if (rdev->family > CHIP_RV200)
3861 WREG32(R_00015C_AGP_BASE_2,
3862 upper_32_bits(rdev->mc.agp_base) & 0xff);
3863 } else {
3864 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3865 WREG32(R_000170_AGP_BASE, 0);
3866 if (rdev->family > CHIP_RV200)
3867 WREG32(R_00015C_AGP_BASE_2, 0);
3868 }
3869 /* Wait for mc idle */
3870 if (r100_mc_wait_for_idle(rdev))
3871 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3872 /* Program MC, should be a 32bits limited address space */
3873 WREG32(R_000148_MC_FB_LOCATION,
3874 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3875 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3876 r100_mc_resume(rdev, &save);
3877}
3878
3879void r100_clock_startup(struct radeon_device *rdev)
3880{
3881 u32 tmp;
3882
3883 if (radeon_dynclks != -1 && radeon_dynclks)
3884 radeon_legacy_set_clock_gating(rdev, 1);
3885 /* We need to force on some of the block */
3886 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3887 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3888 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3889 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3890 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3891}
3892
3893static int r100_startup(struct radeon_device *rdev)
3894{
3895 int r;
3896
92cde00c
AD		 3897 /* set common regs */
3898 r100_set_common_regs(rdev);
3899 /* program mc */
d4550907
JG		 3900 r100_mc_program(rdev);
3901 /* Resume clock */
3902 r100_clock_startup(rdev);
d4550907
JG		 3903 /* Initialize GART (initialize after TTM so we can allocate
3904 * memory through TTM but finalize after TTM) */
17e15b0c 3905 r100_enable_bm(rdev);
d4550907
JG		 3906 if (rdev->flags & RADEON_IS_PCI) {
3907 r = r100_pci_gart_enable(rdev);
3908 if (r)
3909 return r;
3910 }
724c80e1
AD		 3911
3912 /* allocate wb buffer */
3913 r = radeon_wb_init(rdev);
3914 if (r)
3915 return r;
3916
30eb77f4
JG		 3917 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3918 if (r) {
3919 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3920 return r;
3921 }
3922
d4550907 3923 /* Enable IRQ */
d4550907 3924 r100_irq_set(rdev);
cafe6609 3925 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3926 /* 1M ring buffer */
3927 r = r100_cp_init(rdev, 1024 * 1024);
3928 if (r) {
ec4f2ac4 3929 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3930 return r;
3931 }
b15ba512
JG		 3932
3933 r = radeon_ib_pool_start(rdev);
3934 if (r)
3935 return r;
3936
3937 r = r100_ib_test(rdev);
d4550907 3938 if (r) {
b15ba512
JG		 3939 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3940 rdev->accel_working = false;
d4550907
JG		 3941 return r;
3942 }
b15ba512 3943
d4550907
JG		 3944 return 0;
3945}
3946
3947int r100_resume(struct radeon_device *rdev)
3948{
3949 /* Make sur GART are not working */
3950 if (rdev->flags & RADEON_IS_PCI)
3951 r100_pci_gart_disable(rdev);
3952 /* Resume clock before doing reset */
3953 r100_clock_startup(rdev);
3954 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3955 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3956 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3957 RREG32(R_000E40_RBBM_STATUS),
3958 RREG32(R_0007C0_CP_STAT));
3959 }
3960 /* post */
3961 radeon_combios_asic_init(rdev->ddev);
3962 /* Resume clock after posting */
3963 r100_clock_startup(rdev);
550e2d92
DA		 3964 /* Initialize surface registers */
3965 radeon_surface_init(rdev);
b15ba512
JG		 3966
3967 rdev->accel_working = true;
d4550907
JG		 3968 return r100_startup(rdev);
3969}
3970
3971int r100_suspend(struct radeon_device *rdev)
3972{
b15ba512 3973 radeon_ib_pool_suspend(rdev);
d4550907 3974 r100_cp_disable(rdev);
724c80e1 3975 radeon_wb_disable(rdev);
d4550907
JG		 3976 r100_irq_disable(rdev);
3977 if (rdev->flags & RADEON_IS_PCI)
3978 r100_pci_gart_disable(rdev);
3979 return 0;
3980}
3981
3982void r100_fini(struct radeon_device *rdev)
3983{
d4550907 3984 r100_cp_fini(rdev);
724c80e1 3985 radeon_wb_fini(rdev);
d4550907
JG		 3986 r100_ib_fini(rdev);
3987 radeon_gem_fini(rdev);
3988 if (rdev->flags & RADEON_IS_PCI)
3989 r100_pci_gart_fini(rdev);
d0269ed8 3990 radeon_agp_fini(rdev);
d4550907
JG		 3991 radeon_irq_kms_fini(rdev);
3992 radeon_fence_driver_fini(rdev);
4c788679 3993 radeon_bo_fini(rdev);
d4550907
JG		 3994 radeon_atombios_fini(rdev);
3995 kfree(rdev->bios);
3996 rdev->bios = NULL;
3997}
3998
4c712e6c
DA		 3999/*
4000 * Due to how kexec works, it can leave the hw fully initialised when it
4001 * boots the new kernel. However doing our init sequence with the CP and
4002 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4003 * do some quick sanity checks and restore sane values to avoid this
4004 * problem.
4005 */
4006void r100_restore_sanity(struct radeon_device *rdev)
4007{
4008 u32 tmp;
4009
4010 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4011 if (tmp) {
4012 WREG32(RADEON_CP_CSQ_CNTL, 0);
4013 }
4014 tmp = RREG32(RADEON_CP_RB_CNTL);
4015 if (tmp) {
4016 WREG32(RADEON_CP_RB_CNTL, 0);
4017 }
4018 tmp = RREG32(RADEON_SCRATCH_UMSK);
4019 if (tmp) {
4020 WREG32(RADEON_SCRATCH_UMSK, 0);
4021 }
4022}
4023
d4550907
JG		 4024int r100_init(struct radeon_device *rdev)
4025{
4026 int r;
4027
d4550907
JG		 4028 /* Register debugfs file specific to this group of asics */
4029 r100_debugfs(rdev);
4030 /* Disable VGA */
4031 r100_vga_render_disable(rdev);
4032 /* Initialize scratch registers */
4033 radeon_scratch_init(rdev);
4034 /* Initialize surface registers */
4035 radeon_surface_init(rdev);
4c712e6c
DA		 4036 /* sanity check some register to avoid hangs like after kexec */
4037 r100_restore_sanity(rdev);
d4550907
JG		 4038 /* TODO: disable VGA need to use VGA request */
4039 /* BIOS*/
4040 if (!radeon_get_bios(rdev)) {
4041 if (ASIC_IS_AVIVO(rdev))
4042 return -EINVAL;
4043 }
4044 if (rdev->is_atom_bios) {
4045 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4046 return -EINVAL;
4047 } else {
4048 r = radeon_combios_init(rdev);
4049 if (r)
4050 return r;
4051 }
4052 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4053 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4054 dev_warn(rdev->dev,
4055 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4056 RREG32(R_000E40_RBBM_STATUS),
4057 RREG32(R_0007C0_CP_STAT));
4058 }
4059 /* check if cards are posted or not */
72542d77
DA		 4060 if (radeon_boot_test_post_card(rdev) == false)
4061 return -EINVAL;
d4550907
JG		 4062 /* Set asic errata */
4063 r100_errata(rdev);
4064 /* Initialize clocks */
4065 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4066 /* initialize AGP */
4067 if (rdev->flags & RADEON_IS_AGP) {
4068 r = radeon_agp_init(rdev);
4069 if (r) {
4070 radeon_agp_disable(rdev);
4071 }
4072 }
4073 /* initialize VRAM */
4074 r100_mc_init(rdev);
d4550907 4075 /* Fence driver */
30eb77f4 4076 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4077 if (r)
4078 return r;
4079 r = radeon_irq_kms_init(rdev);
4080 if (r)
4081 return r;
4082 /* Memory manager */
4c788679 4083 r = radeon_bo_init(rdev);
d4550907
JG		 4084 if (r)
4085 return r;
4086 if (rdev->flags & RADEON_IS_PCI) {
4087 r = r100_pci_gart_init(rdev);
4088 if (r)
4089 return r;
4090 }
4091 r100_set_safe_registers(rdev);
b15ba512
JG		 4092
4093 r = radeon_ib_pool_init(rdev);
d4550907 4094 rdev->accel_working = true;
b15ba512
JG		 4095 if (r) {
4096 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4097 rdev->accel_working = false;
4098 }
4099
d4550907
JG		 4100 r = r100_startup(rdev);
4101 if (r) {
4102 /* Somethings want wront with the accel init stop accel */
4103 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4104 r100_cp_fini(rdev);
724c80e1 4105 radeon_wb_fini(rdev);
d4550907 4106 r100_ib_fini(rdev);
655efd3d 4107 radeon_irq_kms_fini(rdev);
d4550907
JG		 4108 if (rdev->flags & RADEON_IS_PCI)
4109 r100_pci_gart_fini(rdev);
d4550907
JG		 4110 rdev->accel_working = false;
4111 }
4112 return 0;
4113}
6fcbef7a
AK		 4114
4115uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4116{
4117 if (reg < rdev->rmmio_size)
4118 return readl(((void __iomem *)rdev->rmmio) + reg);
4119 else {
4120 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4121 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4122 }
4123}
4124
4125void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4126{
4127 if (reg < rdev->rmmio_size)
4128 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4129 else {
4130 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4131 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4132 }
4133}
4134
4135u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4136{
4137 if (reg < rdev->rio_mem_size)
4138 return ioread32(rdev->rio_mem + reg);
4139 else {
4140 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4141 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4142 }
4143}
4144
4145void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4146{
4147 if (reg < rdev->rio_mem_size)
4148 iowrite32(v, rdev->rio_mem + reg);
4149 else {
4150 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4151 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4152 }
4153}
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