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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
225758d8 JG |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
e6990375 | 35 | #include "radeon_asic.h" |
e024e110 | 36 | #include "radeon_drm.h" |
551ebd83 | 37 | #include "r100_track.h" |
3ce0a23d | 38 | #include "r300d.h" |
ca6ffc64 | 39 | #include "rv350d.h" |
50f15303 DA |
40 | #include "r300_reg_safe.h" |
41 | ||
cafe6609 JG |
42 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 |
43 | * | |
44 | * GPU Errata: | |
45 | * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL | |
46 | * using MMIO to flush host path read cache, this lead to HARDLOCKUP. | |
47 | * However, scheduling such write to the ring seems harmless, i suspect | |
48 | * the CP read collide with the flush somehow, or maybe the MC, hard to | |
49 | * tell. (Jerome Glisse) | |
50 | */ | |
771fe6b9 JG |
51 | |
52 | /* | |
53 | * rv370,rv380 PCIE GART | |
54 | */ | |
207bf9e9 JG |
55 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
56 | ||
771fe6b9 JG |
57 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
58 | { | |
59 | uint32_t tmp; | |
60 | int i; | |
61 | ||
62 | /* Workaround HW bug do flush 2 times */ | |
63 | for (i = 0; i < 2; i++) { | |
64 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
65 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); | |
66 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
67 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
771fe6b9 | 68 | } |
de1b2898 | 69 | mb(); |
771fe6b9 JG |
70 | } |
71 | ||
d75ee3be AD |
72 | #define R300_PTE_WRITEABLE (1 << 2) |
73 | #define R300_PTE_READABLE (1 << 3) | |
74 | ||
4aac0473 JG |
75 | int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
76 | { | |
77 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; | |
78 | ||
79 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
80 | return -EINVAL; | |
81 | } | |
82 | addr = (lower_32_bits(addr) >> 8) | | |
83 | ((upper_32_bits(addr) & 0xff) << 24) | | |
d75ee3be | 84 | R300_PTE_WRITEABLE | R300_PTE_READABLE; |
4aac0473 JG |
85 | /* on x86 we want this to be CPU endian, on powerpc |
86 | * on powerpc without HW swappers, it'll get swapped on way | |
87 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ | |
88 | writel(addr, ((void __iomem *)ptr) + (i * 4)); | |
89 | return 0; | |
90 | } | |
91 | ||
92 | int rv370_pcie_gart_init(struct radeon_device *rdev) | |
771fe6b9 | 93 | { |
771fe6b9 JG |
94 | int r; |
95 | ||
4aac0473 | 96 | if (rdev->gart.table.vram.robj) { |
fce7d61b | 97 | WARN(1, "RV370 PCIE GART already initialized\n"); |
4aac0473 JG |
98 | return 0; |
99 | } | |
771fe6b9 JG |
100 | /* Initialize common gart structure */ |
101 | r = radeon_gart_init(rdev); | |
4aac0473 | 102 | if (r) |
771fe6b9 | 103 | return r; |
771fe6b9 | 104 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
4aac0473 | 105 | if (r) |
771fe6b9 | 106 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
771fe6b9 | 107 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
4aac0473 JG |
108 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
109 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; | |
110 | return radeon_gart_table_vram_alloc(rdev); | |
111 | } | |
112 | ||
113 | int rv370_pcie_gart_enable(struct radeon_device *rdev) | |
114 | { | |
115 | uint32_t table_addr; | |
116 | uint32_t tmp; | |
117 | int r; | |
118 | ||
119 | if (rdev->gart.table.vram.robj == NULL) { | |
120 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
121 | return -EINVAL; | |
771fe6b9 | 122 | } |
4aac0473 JG |
123 | r = radeon_gart_table_vram_pin(rdev); |
124 | if (r) | |
125 | return r; | |
82568565 | 126 | radeon_gart_restore(rdev); |
771fe6b9 JG |
127 | /* discard memory request outside of configured range */ |
128 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
129 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
d594e46a JG |
130 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); |
131 | tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; | |
771fe6b9 JG |
132 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
133 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); | |
134 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); | |
135 | table_addr = rdev->gart.table_addr; | |
136 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); | |
137 | /* FIXME: setup default page */ | |
d594e46a | 138 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
771fe6b9 JG |
139 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
140 | /* Clear error */ | |
d75ee3be | 141 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
771fe6b9 JG |
142 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
143 | tmp |= RADEON_PCIE_TX_GART_EN; | |
144 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
145 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
146 | rv370_pcie_gart_tlb_flush(rdev); | |
147 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n", | |
3ce0a23d | 148 | (unsigned)(rdev->mc.gtt_size >> 20), table_addr); |
771fe6b9 JG |
149 | rdev->gart.ready = true; |
150 | return 0; | |
151 | } | |
152 | ||
153 | void rv370_pcie_gart_disable(struct radeon_device *rdev) | |
154 | { | |
4c788679 JG |
155 | u32 tmp; |
156 | int r; | |
771fe6b9 | 157 | |
90aca4d2 JG |
158 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); |
159 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); | |
160 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); | |
161 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); | |
771fe6b9 JG |
162 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
163 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
164 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); | |
165 | if (rdev->gart.table.vram.robj) { | |
4c788679 JG |
166 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
167 | if (likely(r == 0)) { | |
168 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
169 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
170 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
171 | } | |
771fe6b9 JG |
172 | } |
173 | } | |
174 | ||
4aac0473 | 175 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
771fe6b9 | 176 | { |
f9274562 | 177 | radeon_gart_fini(rdev); |
4aac0473 JG |
178 | rv370_pcie_gart_disable(rdev); |
179 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
180 | } |
181 | ||
771fe6b9 JG |
182 | void r300_fence_ring_emit(struct radeon_device *rdev, |
183 | struct radeon_fence *fence) | |
184 | { | |
185 | /* Who ever call radeon_fence_emit should call ring_lock and ask | |
186 | * for enough space (today caller are ib schedule and buffer move) */ | |
187 | /* Write SC register so SC & US assert idle */ | |
4612dc97 | 188 | radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0)); |
771fe6b9 | 189 | radeon_ring_write(rdev, 0); |
4612dc97 | 190 | radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0)); |
771fe6b9 JG |
191 | radeon_ring_write(rdev, 0); |
192 | /* Flush 3D cache */ | |
4612dc97 AD |
193 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
194 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH); | |
195 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
196 | radeon_ring_write(rdev, R300_ZC_FLUSH); | |
771fe6b9 | 197 | /* Wait until IDLE & CLEAN */ |
4612dc97 AD |
198 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
199 | radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN | | |
200 | RADEON_WAIT_2D_IDLECLEAN | | |
201 | RADEON_WAIT_DMA_GUI_IDLE)); | |
cafe6609 JG |
202 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
203 | radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | | |
204 | RADEON_HDP_READ_BUFFER_INVALIDATE); | |
205 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); | |
206 | radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); | |
771fe6b9 JG |
207 | /* Emit fence sequence & fire IRQ */ |
208 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); | |
209 | radeon_ring_write(rdev, fence->seq); | |
210 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); | |
211 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); | |
212 | } | |
213 | ||
771fe6b9 JG |
214 | void r300_ring_start(struct radeon_device *rdev) |
215 | { | |
216 | unsigned gb_tile_config; | |
217 | int r; | |
218 | ||
219 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ | |
220 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); | |
068a117c | 221 | switch(rdev->num_gb_pipes) { |
771fe6b9 JG |
222 | case 2: |
223 | gb_tile_config |= R300_PIPE_COUNT_R300; | |
224 | break; | |
225 | case 3: | |
226 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; | |
227 | break; | |
228 | case 4: | |
229 | gb_tile_config |= R300_PIPE_COUNT_R420; | |
230 | break; | |
231 | case 1: | |
232 | default: | |
233 | gb_tile_config |= R300_PIPE_COUNT_RV350; | |
234 | break; | |
235 | } | |
236 | ||
237 | r = radeon_ring_lock(rdev, 64); | |
238 | if (r) { | |
239 | return; | |
240 | } | |
241 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); | |
242 | radeon_ring_write(rdev, | |
243 | RADEON_ISYNC_ANY2D_IDLE3D | | |
244 | RADEON_ISYNC_ANY3D_IDLE2D | | |
245 | RADEON_ISYNC_WAIT_IDLEGUI | | |
246 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
247 | radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); | |
248 | radeon_ring_write(rdev, gb_tile_config); | |
249 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
250 | radeon_ring_write(rdev, | |
251 | RADEON_WAIT_2D_IDLECLEAN | | |
252 | RADEON_WAIT_3D_IDLECLEAN); | |
4612dc97 AD |
253 | radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
254 | radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); | |
771fe6b9 JG |
255 | radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
256 | radeon_ring_write(rdev, 0); | |
257 | radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); | |
258 | radeon_ring_write(rdev, 0); | |
259 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
260 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | |
261 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
262 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); | |
263 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
264 | radeon_ring_write(rdev, | |
265 | RADEON_WAIT_2D_IDLECLEAN | | |
266 | RADEON_WAIT_3D_IDLECLEAN); | |
267 | radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); | |
268 | radeon_ring_write(rdev, 0); | |
269 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
270 | radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | |
271 | radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
272 | radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); | |
273 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); | |
274 | radeon_ring_write(rdev, | |
275 | ((6 << R300_MS_X0_SHIFT) | | |
276 | (6 << R300_MS_Y0_SHIFT) | | |
277 | (6 << R300_MS_X1_SHIFT) | | |
278 | (6 << R300_MS_Y1_SHIFT) | | |
279 | (6 << R300_MS_X2_SHIFT) | | |
280 | (6 << R300_MS_Y2_SHIFT) | | |
281 | (6 << R300_MSBD0_Y_SHIFT) | | |
282 | (6 << R300_MSBD0_X_SHIFT))); | |
283 | radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); | |
284 | radeon_ring_write(rdev, | |
285 | ((6 << R300_MS_X3_SHIFT) | | |
286 | (6 << R300_MS_Y3_SHIFT) | | |
287 | (6 << R300_MS_X4_SHIFT) | | |
288 | (6 << R300_MS_Y4_SHIFT) | | |
289 | (6 << R300_MS_X5_SHIFT) | | |
290 | (6 << R300_MS_Y5_SHIFT) | | |
291 | (6 << R300_MSBD1_SHIFT))); | |
292 | radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); | |
293 | radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); | |
294 | radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); | |
295 | radeon_ring_write(rdev, | |
296 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); | |
297 | radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); | |
298 | radeon_ring_write(rdev, | |
299 | R300_GEOMETRY_ROUND_NEAREST | | |
300 | R300_COLOR_ROUND_NEAREST); | |
301 | radeon_ring_unlock_commit(rdev); | |
302 | } | |
303 | ||
304 | void r300_errata(struct radeon_device *rdev) | |
305 | { | |
306 | rdev->pll_errata = 0; | |
307 | ||
308 | if (rdev->family == CHIP_R300 && | |
309 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { | |
310 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; | |
311 | } | |
312 | } | |
313 | ||
314 | int r300_mc_wait_for_idle(struct radeon_device *rdev) | |
315 | { | |
316 | unsigned i; | |
317 | uint32_t tmp; | |
318 | ||
319 | for (i = 0; i < rdev->usec_timeout; i++) { | |
320 | /* read MC_STATUS */ | |
4612dc97 AD |
321 | tmp = RREG32(RADEON_MC_STATUS); |
322 | if (tmp & R300_MC_IDLE) { | |
771fe6b9 JG |
323 | return 0; |
324 | } | |
325 | DRM_UDELAY(1); | |
326 | } | |
327 | return -1; | |
328 | } | |
329 | ||
330 | void r300_gpu_init(struct radeon_device *rdev) | |
331 | { | |
332 | uint32_t gb_tile_config, tmp; | |
333 | ||
57b54ea6 | 334 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || |
94f7bf64 | 335 | (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { |
771fe6b9 JG |
336 | /* r300,r350 */ |
337 | rdev->num_gb_pipes = 2; | |
338 | } else { | |
94f7bf64 | 339 | /* rv350,rv370,rv380,r300 AD, r350 AH */ |
771fe6b9 JG |
340 | rdev->num_gb_pipes = 1; |
341 | } | |
f779b3e5 | 342 | rdev->num_z_pipes = 1; |
771fe6b9 JG |
343 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
344 | switch (rdev->num_gb_pipes) { | |
345 | case 2: | |
346 | gb_tile_config |= R300_PIPE_COUNT_R300; | |
347 | break; | |
348 | case 3: | |
349 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; | |
350 | break; | |
351 | case 4: | |
352 | gb_tile_config |= R300_PIPE_COUNT_R420; | |
353 | break; | |
771fe6b9 | 354 | default: |
068a117c | 355 | case 1: |
771fe6b9 JG |
356 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
357 | break; | |
358 | } | |
359 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); | |
360 | ||
361 | if (r100_gui_wait_for_idle(rdev)) { | |
362 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
363 | "programming pipes. Bad things might happen.\n"); | |
364 | } | |
365 | ||
4612dc97 AD |
366 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
367 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); | |
771fe6b9 JG |
368 | |
369 | WREG32(R300_RB2D_DSTCACHE_MODE, | |
370 | R300_DC_AUTOFLUSH_ENABLE | | |
371 | R300_DC_DC_DISABLE_IGNORE_PE); | |
372 | ||
373 | if (r100_gui_wait_for_idle(rdev)) { | |
374 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
375 | "programming pipes. Bad things might happen.\n"); | |
376 | } | |
377 | if (r300_mc_wait_for_idle(rdev)) { | |
378 | printk(KERN_WARNING "Failed to wait MC idle while " | |
379 | "programming pipes. Bad things might happen.\n"); | |
380 | } | |
f779b3e5 AD |
381 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
382 | rdev->num_gb_pipes, rdev->num_z_pipes); | |
771fe6b9 JG |
383 | } |
384 | ||
225758d8 | 385 | bool r300_gpu_is_lockup(struct radeon_device *rdev) |
771fe6b9 | 386 | { |
225758d8 JG |
387 | u32 rbbm_status; |
388 | int r; | |
771fe6b9 | 389 | |
225758d8 JG |
390 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
391 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { | |
392 | r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); | |
393 | return false; | |
771fe6b9 | 394 | } |
225758d8 JG |
395 | /* force CP activities */ |
396 | r = radeon_ring_lock(rdev, 2); | |
397 | if (!r) { | |
398 | /* PACKET2 NOP */ | |
399 | radeon_ring_write(rdev, 0x80000000); | |
400 | radeon_ring_write(rdev, 0x80000000); | |
401 | radeon_ring_unlock_commit(rdev); | |
771fe6b9 | 402 | } |
225758d8 JG |
403 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
404 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); | |
771fe6b9 JG |
405 | } |
406 | ||
a2d07b74 | 407 | int r300_asic_reset(struct radeon_device *rdev) |
771fe6b9 | 408 | { |
90aca4d2 JG |
409 | struct r100_mc_save save; |
410 | u32 status, tmp; | |
25b2ec5b | 411 | int ret = 0; |
771fe6b9 | 412 | |
90aca4d2 JG |
413 | status = RREG32(R_000E40_RBBM_STATUS); |
414 | if (!G_000E40_GUI_ACTIVE(status)) { | |
415 | return 0; | |
771fe6b9 | 416 | } |
25b2ec5b | 417 | r100_mc_stop(rdev, &save); |
90aca4d2 JG |
418 | status = RREG32(R_000E40_RBBM_STATUS); |
419 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
420 | /* stop CP */ | |
421 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
422 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
423 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
424 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
425 | WREG32(RADEON_CP_RB_WPTR, 0); | |
426 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
427 | /* save PCI state */ | |
428 | pci_save_state(rdev->pdev); | |
429 | /* disable bus mastering */ | |
430 | r100_bm_disable(rdev); | |
431 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | | |
432 | S_0000F0_SOFT_RESET_GA(1)); | |
433 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
434 | mdelay(500); | |
435 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
436 | mdelay(1); | |
437 | status = RREG32(R_000E40_RBBM_STATUS); | |
438 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
439 | /* resetting the CP seems to be problematic sometimes it end up | |
440 | * hard locking the computer, but it's necessary for successfull | |
441 | * reset more test & playing is needed on R3XX/R4XX to find a | |
442 | * reliable (if any solution) | |
443 | */ | |
444 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); | |
445 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
446 | mdelay(500); | |
447 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
448 | mdelay(1); | |
449 | status = RREG32(R_000E40_RBBM_STATUS); | |
450 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
90aca4d2 JG |
451 | /* restore PCI & busmastering */ |
452 | pci_restore_state(rdev->pdev); | |
453 | r100_enable_bm(rdev); | |
771fe6b9 | 454 | /* Check if GPU is idle */ |
90aca4d2 JG |
455 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
456 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
457 | rdev->gpu_lockup = true; | |
25b2ec5b AD |
458 | ret = -1; |
459 | } else | |
460 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
90aca4d2 | 461 | r100_mc_resume(rdev, &save); |
25b2ec5b | 462 | return ret; |
771fe6b9 JG |
463 | } |
464 | ||
771fe6b9 JG |
465 | /* |
466 | * r300,r350,rv350,rv380 VRAM info | |
467 | */ | |
d594e46a | 468 | void r300_mc_init(struct radeon_device *rdev) |
771fe6b9 | 469 | { |
8e361130 JG |
470 | u64 base; |
471 | u32 tmp; | |
771fe6b9 JG |
472 | |
473 | /* DDR for all card after R300 & IGP */ | |
474 | rdev->mc.vram_is_ddr = true; | |
475 | tmp = RREG32(RADEON_MEM_CNTL); | |
5ff55717 DA |
476 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
477 | switch (tmp) { | |
478 | case 0: rdev->mc.vram_width = 64; break; | |
479 | case 1: rdev->mc.vram_width = 128; break; | |
480 | case 2: rdev->mc.vram_width = 256; break; | |
481 | default: rdev->mc.vram_width = 128; break; | |
771fe6b9 | 482 | } |
2a0f8918 | 483 | r100_vram_init_sizes(rdev); |
8e361130 JG |
484 | base = rdev->mc.aper_base; |
485 | if (rdev->flags & RADEON_IS_IGP) | |
486 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | |
487 | radeon_vram_location(rdev, &rdev->mc, base); | |
8d369bb1 | 488 | rdev->mc.gtt_base_align = 0; |
d594e46a JG |
489 | if (!(rdev->flags & RADEON_IS_AGP)) |
490 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 491 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
492 | } |
493 | ||
771fe6b9 JG |
494 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
495 | { | |
496 | uint32_t link_width_cntl, mask; | |
497 | ||
498 | if (rdev->flags & RADEON_IS_IGP) | |
499 | return; | |
500 | ||
501 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
502 | return; | |
503 | ||
504 | /* FIXME wait for idle */ | |
505 | ||
506 | switch (lanes) { | |
507 | case 0: | |
508 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; | |
509 | break; | |
510 | case 1: | |
511 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; | |
512 | break; | |
513 | case 2: | |
514 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; | |
515 | break; | |
516 | case 4: | |
517 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; | |
518 | break; | |
519 | case 8: | |
520 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; | |
521 | break; | |
522 | case 12: | |
523 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; | |
524 | break; | |
525 | case 16: | |
526 | default: | |
527 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; | |
528 | break; | |
529 | } | |
530 | ||
531 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
532 | ||
533 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == | |
534 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) | |
535 | return; | |
536 | ||
537 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | | |
538 | RADEON_PCIE_LC_RECONFIG_NOW | | |
539 | RADEON_PCIE_LC_RECONFIG_LATER | | |
540 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); | |
541 | link_width_cntl |= mask; | |
542 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
543 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | | |
544 | RADEON_PCIE_LC_RECONFIG_NOW)); | |
545 | ||
546 | /* wait for lane set to complete */ | |
547 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
548 | while (link_width_cntl == 0xffffffff) | |
549 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
550 | ||
551 | } | |
552 | ||
c836a412 AD |
553 | int rv370_get_pcie_lanes(struct radeon_device *rdev) |
554 | { | |
555 | u32 link_width_cntl; | |
556 | ||
557 | if (rdev->flags & RADEON_IS_IGP) | |
558 | return 0; | |
559 | ||
560 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
561 | return 0; | |
562 | ||
563 | /* FIXME wait for idle */ | |
564 | ||
3313e3d4 | 565 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
c836a412 AD |
566 | |
567 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { | |
568 | case RADEON_PCIE_LC_LINK_WIDTH_X0: | |
569 | return 0; | |
570 | case RADEON_PCIE_LC_LINK_WIDTH_X1: | |
571 | return 1; | |
572 | case RADEON_PCIE_LC_LINK_WIDTH_X2: | |
573 | return 2; | |
574 | case RADEON_PCIE_LC_LINK_WIDTH_X4: | |
575 | return 4; | |
576 | case RADEON_PCIE_LC_LINK_WIDTH_X8: | |
577 | return 8; | |
578 | case RADEON_PCIE_LC_LINK_WIDTH_X16: | |
579 | default: | |
580 | return 16; | |
581 | } | |
582 | } | |
583 | ||
771fe6b9 JG |
584 | #if defined(CONFIG_DEBUG_FS) |
585 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) | |
586 | { | |
587 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
588 | struct drm_device *dev = node->minor->dev; | |
589 | struct radeon_device *rdev = dev->dev_private; | |
590 | uint32_t tmp; | |
591 | ||
592 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
593 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); | |
594 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); | |
595 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); | |
596 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); | |
597 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); | |
598 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); | |
599 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); | |
600 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); | |
601 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); | |
602 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); | |
603 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); | |
604 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); | |
605 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); | |
606 | return 0; | |
607 | } | |
608 | ||
609 | static struct drm_info_list rv370_pcie_gart_info_list[] = { | |
610 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, | |
611 | }; | |
612 | #endif | |
613 | ||
207bf9e9 | 614 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
771fe6b9 JG |
615 | { |
616 | #if defined(CONFIG_DEBUG_FS) | |
617 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); | |
618 | #else | |
619 | return 0; | |
620 | #endif | |
621 | } | |
622 | ||
771fe6b9 JG |
623 | static int r300_packet0_check(struct radeon_cs_parser *p, |
624 | struct radeon_cs_packet *pkt, | |
625 | unsigned idx, unsigned reg) | |
626 | { | |
771fe6b9 | 627 | struct radeon_cs_reloc *reloc; |
551ebd83 | 628 | struct r100_cs_track *track; |
771fe6b9 | 629 | volatile uint32_t *ib; |
e024e110 | 630 | uint32_t tmp, tile_flags = 0; |
771fe6b9 JG |
631 | unsigned i; |
632 | int r; | |
513bcb46 | 633 | u32 idx_value; |
771fe6b9 JG |
634 | |
635 | ib = p->ib->ptr; | |
551ebd83 | 636 | track = (struct r100_cs_track *)p->track; |
513bcb46 DA |
637 | idx_value = radeon_get_ib_value(p, idx); |
638 | ||
068a117c | 639 | switch(reg) { |
531369e6 DA |
640 | case AVIVO_D1MODE_VLINE_START_END: |
641 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
642 | r = r100_cs_packet_parse_vline(p); | |
643 | if (r) { | |
644 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
645 | idx, reg); | |
646 | r100_cs_dump_packet(p, pkt); | |
647 | return r; | |
648 | } | |
649 | break; | |
771fe6b9 JG |
650 | case RADEON_DST_PITCH_OFFSET: |
651 | case RADEON_SRC_PITCH_OFFSET: | |
551ebd83 DA |
652 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
653 | if (r) | |
771fe6b9 | 654 | return r; |
771fe6b9 JG |
655 | break; |
656 | case R300_RB3D_COLOROFFSET0: | |
657 | case R300_RB3D_COLOROFFSET1: | |
658 | case R300_RB3D_COLOROFFSET2: | |
659 | case R300_RB3D_COLOROFFSET3: | |
660 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; | |
661 | r = r100_cs_packet_next_reloc(p, &reloc); | |
662 | if (r) { | |
663 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
664 | idx, reg); | |
665 | r100_cs_dump_packet(p, pkt); | |
666 | return r; | |
667 | } | |
668 | track->cb[i].robj = reloc->robj; | |
513bcb46 | 669 | track->cb[i].offset = idx_value; |
40b4a759 | 670 | track->cb_dirty = true; |
513bcb46 | 671 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
771fe6b9 JG |
672 | break; |
673 | case R300_ZB_DEPTHOFFSET: | |
674 | r = r100_cs_packet_next_reloc(p, &reloc); | |
675 | if (r) { | |
676 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
677 | idx, reg); | |
678 | r100_cs_dump_packet(p, pkt); | |
679 | return r; | |
680 | } | |
681 | track->zb.robj = reloc->robj; | |
513bcb46 | 682 | track->zb.offset = idx_value; |
40b4a759 | 683 | track->zb_dirty = true; |
513bcb46 | 684 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
771fe6b9 JG |
685 | break; |
686 | case R300_TX_OFFSET_0: | |
687 | case R300_TX_OFFSET_0+4: | |
688 | case R300_TX_OFFSET_0+8: | |
689 | case R300_TX_OFFSET_0+12: | |
690 | case R300_TX_OFFSET_0+16: | |
691 | case R300_TX_OFFSET_0+20: | |
692 | case R300_TX_OFFSET_0+24: | |
693 | case R300_TX_OFFSET_0+28: | |
694 | case R300_TX_OFFSET_0+32: | |
695 | case R300_TX_OFFSET_0+36: | |
696 | case R300_TX_OFFSET_0+40: | |
697 | case R300_TX_OFFSET_0+44: | |
698 | case R300_TX_OFFSET_0+48: | |
699 | case R300_TX_OFFSET_0+52: | |
700 | case R300_TX_OFFSET_0+56: | |
701 | case R300_TX_OFFSET_0+60: | |
068a117c | 702 | i = (reg - R300_TX_OFFSET_0) >> 2; |
771fe6b9 JG |
703 | r = r100_cs_packet_next_reloc(p, &reloc); |
704 | if (r) { | |
705 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
706 | idx, reg); | |
707 | r100_cs_dump_packet(p, pkt); | |
708 | return r; | |
709 | } | |
6e726772 MC |
710 | |
711 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | |
712 | tile_flags |= R300_TXO_MACRO_TILE; | |
713 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
714 | tile_flags |= R300_TXO_MICRO_TILE; | |
939461d5 MO |
715 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
716 | tile_flags |= R300_TXO_MICRO_TILE_SQUARE; | |
6e726772 MC |
717 | |
718 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); | |
719 | tmp |= tile_flags; | |
720 | ib[idx] = tmp; | |
068a117c | 721 | track->textures[i].robj = reloc->robj; |
40b4a759 | 722 | track->tex_dirty = true; |
771fe6b9 JG |
723 | break; |
724 | /* Tracked registers */ | |
068a117c JG |
725 | case 0x2084: |
726 | /* VAP_VF_CNTL */ | |
513bcb46 | 727 | track->vap_vf_cntl = idx_value; |
068a117c JG |
728 | break; |
729 | case 0x20B4: | |
730 | /* VAP_VTX_SIZE */ | |
513bcb46 | 731 | track->vtx_size = idx_value & 0x7F; |
068a117c JG |
732 | break; |
733 | case 0x2134: | |
734 | /* VAP_VF_MAX_VTX_INDX */ | |
513bcb46 | 735 | track->max_indx = idx_value & 0x00FFFFFFUL; |
068a117c | 736 | break; |
cae94b0a MO |
737 | case 0x2088: |
738 | /* VAP_ALT_NUM_VERTICES - only valid on r500 */ | |
739 | if (p->rdev->family < CHIP_RV515) | |
740 | goto fail; | |
741 | track->vap_alt_nverts = idx_value & 0xFFFFFF; | |
742 | break; | |
771fe6b9 JG |
743 | case 0x43E4: |
744 | /* SC_SCISSOR1 */ | |
513bcb46 | 745 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
771fe6b9 JG |
746 | if (p->rdev->family < CHIP_RV515) { |
747 | track->maxy -= 1440; | |
748 | } | |
40b4a759 MO |
749 | track->cb_dirty = true; |
750 | track->zb_dirty = true; | |
771fe6b9 JG |
751 | break; |
752 | case 0x4E00: | |
753 | /* RB3D_CCTL */ | |
9eba4a93 MO |
754 | if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ |
755 | p->rdev->cmask_filp != p->filp) { | |
756 | DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); | |
757 | return -EINVAL; | |
758 | } | |
513bcb46 | 759 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
40b4a759 | 760 | track->cb_dirty = true; |
771fe6b9 JG |
761 | break; |
762 | case 0x4E38: | |
763 | case 0x4E3C: | |
764 | case 0x4E40: | |
765 | case 0x4E44: | |
766 | /* RB3D_COLORPITCH0 */ | |
767 | /* RB3D_COLORPITCH1 */ | |
768 | /* RB3D_COLORPITCH2 */ | |
769 | /* RB3D_COLORPITCH3 */ | |
e024e110 DA |
770 | r = r100_cs_packet_next_reloc(p, &reloc); |
771 | if (r) { | |
772 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
773 | idx, reg); | |
774 | r100_cs_dump_packet(p, pkt); | |
775 | return r; | |
776 | } | |
777 | ||
778 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | |
779 | tile_flags |= R300_COLOR_TILE_ENABLE; | |
780 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
781 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; | |
939461d5 MO |
782 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) |
783 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; | |
e024e110 | 784 | |
513bcb46 | 785 | tmp = idx_value & ~(0x7 << 16); |
e024e110 DA |
786 | tmp |= tile_flags; |
787 | ib[idx] = tmp; | |
771fe6b9 | 788 | i = (reg - 0x4E38) >> 2; |
513bcb46 DA |
789 | track->cb[i].pitch = idx_value & 0x3FFE; |
790 | switch (((idx_value >> 21) & 0xF)) { | |
771fe6b9 JG |
791 | case 9: |
792 | case 11: | |
793 | case 12: | |
794 | track->cb[i].cpp = 1; | |
795 | break; | |
796 | case 3: | |
797 | case 4: | |
798 | case 13: | |
799 | case 15: | |
800 | track->cb[i].cpp = 2; | |
801 | break; | |
204663c4 MO |
802 | case 5: |
803 | if (p->rdev->family < CHIP_RV515) { | |
804 | DRM_ERROR("Invalid color buffer format (%d)!\n", | |
805 | ((idx_value >> 21) & 0xF)); | |
806 | return -EINVAL; | |
807 | } | |
808 | /* Pass through. */ | |
771fe6b9 JG |
809 | case 6: |
810 | track->cb[i].cpp = 4; | |
811 | break; | |
812 | case 10: | |
813 | track->cb[i].cpp = 8; | |
814 | break; | |
815 | case 7: | |
816 | track->cb[i].cpp = 16; | |
817 | break; | |
818 | default: | |
819 | DRM_ERROR("Invalid color buffer format (%d) !\n", | |
513bcb46 | 820 | ((idx_value >> 21) & 0xF)); |
771fe6b9 JG |
821 | return -EINVAL; |
822 | } | |
40b4a759 | 823 | track->cb_dirty = true; |
771fe6b9 JG |
824 | break; |
825 | case 0x4F00: | |
826 | /* ZB_CNTL */ | |
513bcb46 | 827 | if (idx_value & 2) { |
771fe6b9 JG |
828 | track->z_enabled = true; |
829 | } else { | |
830 | track->z_enabled = false; | |
831 | } | |
40b4a759 | 832 | track->zb_dirty = true; |
771fe6b9 JG |
833 | break; |
834 | case 0x4F10: | |
835 | /* ZB_FORMAT */ | |
513bcb46 | 836 | switch ((idx_value & 0xF)) { |
771fe6b9 JG |
837 | case 0: |
838 | case 1: | |
839 | track->zb.cpp = 2; | |
840 | break; | |
841 | case 2: | |
842 | track->zb.cpp = 4; | |
843 | break; | |
844 | default: | |
845 | DRM_ERROR("Invalid z buffer format (%d) !\n", | |
513bcb46 | 846 | (idx_value & 0xF)); |
771fe6b9 JG |
847 | return -EINVAL; |
848 | } | |
40b4a759 | 849 | track->zb_dirty = true; |
771fe6b9 JG |
850 | break; |
851 | case 0x4F24: | |
852 | /* ZB_DEPTHPITCH */ | |
e024e110 DA |
853 | r = r100_cs_packet_next_reloc(p, &reloc); |
854 | if (r) { | |
855 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
856 | idx, reg); | |
857 | r100_cs_dump_packet(p, pkt); | |
858 | return r; | |
859 | } | |
860 | ||
861 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | |
862 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; | |
863 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
939461d5 MO |
864 | tile_flags |= R300_DEPTHMICROTILE_TILED; |
865 | else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) | |
866 | tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; | |
e024e110 | 867 | |
513bcb46 | 868 | tmp = idx_value & ~(0x7 << 16); |
e024e110 DA |
869 | tmp |= tile_flags; |
870 | ib[idx] = tmp; | |
871 | ||
513bcb46 | 872 | track->zb.pitch = idx_value & 0x3FFC; |
40b4a759 | 873 | track->zb_dirty = true; |
771fe6b9 | 874 | break; |
068a117c | 875 | case 0x4104: |
50183434 | 876 | /* TX_ENABLE */ |
068a117c JG |
877 | for (i = 0; i < 16; i++) { |
878 | bool enabled; | |
879 | ||
513bcb46 | 880 | enabled = !!(idx_value & (1 << i)); |
068a117c JG |
881 | track->textures[i].enabled = enabled; |
882 | } | |
40b4a759 | 883 | track->tex_dirty = true; |
068a117c JG |
884 | break; |
885 | case 0x44C0: | |
886 | case 0x44C4: | |
887 | case 0x44C8: | |
888 | case 0x44CC: | |
889 | case 0x44D0: | |
890 | case 0x44D4: | |
891 | case 0x44D8: | |
892 | case 0x44DC: | |
893 | case 0x44E0: | |
894 | case 0x44E4: | |
895 | case 0x44E8: | |
896 | case 0x44EC: | |
897 | case 0x44F0: | |
898 | case 0x44F4: | |
899 | case 0x44F8: | |
900 | case 0x44FC: | |
901 | /* TX_FORMAT1_[0-15] */ | |
902 | i = (reg - 0x44C0) >> 2; | |
513bcb46 | 903 | tmp = (idx_value >> 25) & 0x3; |
068a117c | 904 | track->textures[i].tex_coord_type = tmp; |
513bcb46 | 905 | switch ((idx_value & 0x1F)) { |
551ebd83 DA |
906 | case R300_TX_FORMAT_X8: |
907 | case R300_TX_FORMAT_Y4X4: | |
908 | case R300_TX_FORMAT_Z3Y3X2: | |
068a117c | 909 | track->textures[i].cpp = 1; |
f9da52d5 | 910 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 911 | break; |
551ebd83 | 912 | case R300_TX_FORMAT_X16: |
16e4b8a6 | 913 | case R300_TX_FORMAT_FL_I16: |
551ebd83 DA |
914 | case R300_TX_FORMAT_Y8X8: |
915 | case R300_TX_FORMAT_Z5Y6X5: | |
916 | case R300_TX_FORMAT_Z6Y5X5: | |
917 | case R300_TX_FORMAT_W4Z4Y4X4: | |
918 | case R300_TX_FORMAT_W1Z5Y5X5: | |
551ebd83 DA |
919 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
920 | case R300_TX_FORMAT_B8G8_B8G8: | |
921 | case R300_TX_FORMAT_G8R8_G8B8: | |
068a117c | 922 | track->textures[i].cpp = 2; |
f9da52d5 | 923 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 924 | break; |
551ebd83 | 925 | case R300_TX_FORMAT_Y16X16: |
16e4b8a6 | 926 | case R300_TX_FORMAT_FL_I16A16: |
551ebd83 DA |
927 | case R300_TX_FORMAT_Z11Y11X10: |
928 | case R300_TX_FORMAT_Z10Y11X11: | |
929 | case R300_TX_FORMAT_W8Z8Y8X8: | |
930 | case R300_TX_FORMAT_W2Z10Y10X10: | |
931 | case 0x17: | |
932 | case R300_TX_FORMAT_FL_I32: | |
933 | case 0x1e: | |
068a117c | 934 | track->textures[i].cpp = 4; |
f9da52d5 | 935 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 936 | break; |
551ebd83 DA |
937 | case R300_TX_FORMAT_W16Z16Y16X16: |
938 | case R300_TX_FORMAT_FL_R16G16B16A16: | |
939 | case R300_TX_FORMAT_FL_I32A32: | |
068a117c | 940 | track->textures[i].cpp = 8; |
f9da52d5 | 941 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 942 | break; |
551ebd83 | 943 | case R300_TX_FORMAT_FL_R32G32B32A32: |
068a117c | 944 | track->textures[i].cpp = 16; |
f9da52d5 | 945 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 946 | break; |
d785d78b DA |
947 | case R300_TX_FORMAT_DXT1: |
948 | track->textures[i].cpp = 1; | |
949 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | |
950 | break; | |
512889f4 MO |
951 | case R300_TX_FORMAT_ATI2N: |
952 | if (p->rdev->family < CHIP_R420) { | |
953 | DRM_ERROR("Invalid texture format %u\n", | |
954 | (idx_value & 0x1F)); | |
955 | return -EINVAL; | |
956 | } | |
957 | /* The same rules apply as for DXT3/5. */ | |
958 | /* Pass through. */ | |
d785d78b DA |
959 | case R300_TX_FORMAT_DXT3: |
960 | case R300_TX_FORMAT_DXT5: | |
961 | track->textures[i].cpp = 1; | |
962 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | |
963 | break; | |
068a117c JG |
964 | default: |
965 | DRM_ERROR("Invalid texture format %u\n", | |
513bcb46 | 966 | (idx_value & 0x1F)); |
068a117c | 967 | return -EINVAL; |
068a117c | 968 | } |
40b4a759 | 969 | track->tex_dirty = true; |
068a117c JG |
970 | break; |
971 | case 0x4400: | |
972 | case 0x4404: | |
973 | case 0x4408: | |
974 | case 0x440C: | |
975 | case 0x4410: | |
976 | case 0x4414: | |
977 | case 0x4418: | |
978 | case 0x441C: | |
979 | case 0x4420: | |
980 | case 0x4424: | |
981 | case 0x4428: | |
982 | case 0x442C: | |
983 | case 0x4430: | |
984 | case 0x4434: | |
985 | case 0x4438: | |
986 | case 0x443C: | |
987 | /* TX_FILTER0_[0-15] */ | |
988 | i = (reg - 0x4400) >> 2; | |
513bcb46 | 989 | tmp = idx_value & 0x7; |
068a117c JG |
990 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
991 | track->textures[i].roundup_w = false; | |
992 | } | |
513bcb46 | 993 | tmp = (idx_value >> 3) & 0x7; |
068a117c JG |
994 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
995 | track->textures[i].roundup_h = false; | |
996 | } | |
40b4a759 | 997 | track->tex_dirty = true; |
068a117c JG |
998 | break; |
999 | case 0x4500: | |
1000 | case 0x4504: | |
1001 | case 0x4508: | |
1002 | case 0x450C: | |
1003 | case 0x4510: | |
1004 | case 0x4514: | |
1005 | case 0x4518: | |
1006 | case 0x451C: | |
1007 | case 0x4520: | |
1008 | case 0x4524: | |
1009 | case 0x4528: | |
1010 | case 0x452C: | |
1011 | case 0x4530: | |
1012 | case 0x4534: | |
1013 | case 0x4538: | |
1014 | case 0x453C: | |
1015 | /* TX_FORMAT2_[0-15] */ | |
1016 | i = (reg - 0x4500) >> 2; | |
513bcb46 | 1017 | tmp = idx_value & 0x3FFF; |
068a117c JG |
1018 | track->textures[i].pitch = tmp + 1; |
1019 | if (p->rdev->family >= CHIP_RV515) { | |
513bcb46 | 1020 | tmp = ((idx_value >> 15) & 1) << 11; |
068a117c | 1021 | track->textures[i].width_11 = tmp; |
513bcb46 | 1022 | tmp = ((idx_value >> 16) & 1) << 11; |
068a117c | 1023 | track->textures[i].height_11 = tmp; |
512889f4 MO |
1024 | |
1025 | /* ATI1N */ | |
1026 | if (idx_value & (1 << 14)) { | |
1027 | /* The same rules apply as for DXT1. */ | |
1028 | track->textures[i].compress_format = | |
1029 | R100_TRACK_COMP_DXT1; | |
1030 | } | |
1031 | } else if (idx_value & (1 << 14)) { | |
1032 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); | |
1033 | return -EINVAL; | |
068a117c | 1034 | } |
40b4a759 | 1035 | track->tex_dirty = true; |
068a117c JG |
1036 | break; |
1037 | case 0x4480: | |
1038 | case 0x4484: | |
1039 | case 0x4488: | |
1040 | case 0x448C: | |
1041 | case 0x4490: | |
1042 | case 0x4494: | |
1043 | case 0x4498: | |
1044 | case 0x449C: | |
1045 | case 0x44A0: | |
1046 | case 0x44A4: | |
1047 | case 0x44A8: | |
1048 | case 0x44AC: | |
1049 | case 0x44B0: | |
1050 | case 0x44B4: | |
1051 | case 0x44B8: | |
1052 | case 0x44BC: | |
1053 | /* TX_FORMAT0_[0-15] */ | |
1054 | i = (reg - 0x4480) >> 2; | |
513bcb46 | 1055 | tmp = idx_value & 0x7FF; |
068a117c | 1056 | track->textures[i].width = tmp + 1; |
513bcb46 | 1057 | tmp = (idx_value >> 11) & 0x7FF; |
068a117c | 1058 | track->textures[i].height = tmp + 1; |
513bcb46 | 1059 | tmp = (idx_value >> 26) & 0xF; |
068a117c | 1060 | track->textures[i].num_levels = tmp; |
513bcb46 | 1061 | tmp = idx_value & (1 << 31); |
068a117c | 1062 | track->textures[i].use_pitch = !!tmp; |
513bcb46 | 1063 | tmp = (idx_value >> 22) & 0xF; |
068a117c | 1064 | track->textures[i].txdepth = tmp; |
40b4a759 | 1065 | track->tex_dirty = true; |
068a117c | 1066 | break; |
3f8befec DA |
1067 | case R300_ZB_ZPASS_ADDR: |
1068 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1069 | if (r) { | |
1070 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1071 | idx, reg); | |
1072 | r100_cs_dump_packet(p, pkt); | |
1073 | return r; | |
1074 | } | |
513bcb46 | 1075 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
3f8befec | 1076 | break; |
46c64d4b MO |
1077 | case 0x4e0c: |
1078 | /* RB3D_COLOR_CHANNEL_MASK */ | |
1079 | track->color_channel_mask = idx_value; | |
40b4a759 | 1080 | track->cb_dirty = true; |
46c64d4b | 1081 | break; |
ab9e1f59 DA |
1082 | case 0x43a4: |
1083 | /* SC_HYPERZ_EN */ | |
1084 | /* r300c emits this register - we need to disable hyperz for it | |
1085 | * without complaining */ | |
1086 | if (p->rdev->hyperz_filp != p->filp) { | |
1087 | if (idx_value & 0x1) | |
1088 | ib[idx] = idx_value & ~1; | |
1089 | } | |
1090 | break; | |
1091 | case 0x4f1c: | |
46c64d4b | 1092 | /* ZB_BW_CNTL */ |
797fd5b9 | 1093 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
40b4a759 MO |
1094 | track->cb_dirty = true; |
1095 | track->zb_dirty = true; | |
ab9e1f59 DA |
1096 | if (p->rdev->hyperz_filp != p->filp) { |
1097 | if (idx_value & (R300_HIZ_ENABLE | | |
1098 | R300_RD_COMP_ENABLE | | |
1099 | R300_WR_COMP_ENABLE | | |
1100 | R300_FAST_FILL_ENABLE)) | |
1101 | goto fail; | |
1102 | } | |
46c64d4b MO |
1103 | break; |
1104 | case 0x4e04: | |
1105 | /* RB3D_BLENDCNTL */ | |
1106 | track->blend_read_enable = !!(idx_value & (1 << 2)); | |
40b4a759 | 1107 | track->cb_dirty = true; |
46c64d4b | 1108 | break; |
fff1ce4d MO |
1109 | case R300_RB3D_AARESOLVE_OFFSET: |
1110 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1111 | if (r) { | |
1112 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1113 | idx, reg); | |
1114 | r100_cs_dump_packet(p, pkt); | |
1115 | return r; | |
1116 | } | |
1117 | track->aa.robj = reloc->robj; | |
1118 | track->aa.offset = idx_value; | |
1119 | track->aa_dirty = true; | |
1120 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
1121 | break; | |
1122 | case R300_RB3D_AARESOLVE_PITCH: | |
1123 | track->aa.pitch = idx_value & 0x3FFE; | |
1124 | track->aa_dirty = true; | |
1125 | break; | |
1126 | case R300_RB3D_AARESOLVE_CTL: | |
1127 | track->aaresolve = idx_value & 0x1; | |
1128 | track->aa_dirty = true; | |
1129 | break; | |
ab9e1f59 DA |
1130 | case 0x4f30: /* ZB_MASK_OFFSET */ |
1131 | case 0x4f34: /* ZB_ZMASK_PITCH */ | |
1132 | case 0x4f44: /* ZB_HIZ_OFFSET */ | |
1133 | case 0x4f54: /* ZB_HIZ_PITCH */ | |
1134 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | |
1135 | goto fail; | |
1136 | break; | |
1137 | case 0x4028: | |
1138 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | |
1139 | goto fail; | |
1140 | /* GB_Z_PEQ_CONFIG */ | |
1141 | if (p->rdev->family >= CHIP_RV350) | |
1142 | break; | |
1143 | goto fail; | |
1144 | break; | |
3f8befec DA |
1145 | case 0x4be8: |
1146 | /* valid register only on RV530 */ | |
1147 | if (p->rdev->family == CHIP_RV530) | |
1148 | break; | |
1149 | /* fallthrough do not move */ | |
771fe6b9 | 1150 | default: |
cae94b0a | 1151 | goto fail; |
771fe6b9 JG |
1152 | } |
1153 | return 0; | |
cae94b0a | 1154 | fail: |
ab9e1f59 DA |
1155 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", |
1156 | reg, idx, idx_value); | |
cae94b0a | 1157 | return -EINVAL; |
771fe6b9 JG |
1158 | } |
1159 | ||
1160 | static int r300_packet3_check(struct radeon_cs_parser *p, | |
1161 | struct radeon_cs_packet *pkt) | |
1162 | { | |
771fe6b9 | 1163 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1164 | struct r100_cs_track *track; |
771fe6b9 JG |
1165 | volatile uint32_t *ib; |
1166 | unsigned idx; | |
771fe6b9 JG |
1167 | int r; |
1168 | ||
1169 | ib = p->ib->ptr; | |
771fe6b9 | 1170 | idx = pkt->idx + 1; |
551ebd83 | 1171 | track = (struct r100_cs_track *)p->track; |
068a117c | 1172 | switch(pkt->opcode) { |
771fe6b9 | 1173 | case PACKET3_3D_LOAD_VBPNTR: |
513bcb46 DA |
1174 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1175 | if (r) | |
1176 | return r; | |
771fe6b9 JG |
1177 | break; |
1178 | case PACKET3_INDX_BUFFER: | |
1179 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1180 | if (r) { | |
1181 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
1182 | r100_cs_dump_packet(p, pkt); | |
1183 | return r; | |
1184 | } | |
513bcb46 | 1185 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
068a117c JG |
1186 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1187 | if (r) { | |
1188 | return r; | |
1189 | } | |
771fe6b9 JG |
1190 | break; |
1191 | /* Draw packet */ | |
771fe6b9 | 1192 | case PACKET3_3D_DRAW_IMMD: |
068a117c JG |
1193 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1194 | * PRIM_WALK must be equal to 3 vertex data in embedded | |
1195 | * in cmd stream */ | |
513bcb46 | 1196 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
068a117c JG |
1197 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1198 | return -EINVAL; | |
1199 | } | |
513bcb46 | 1200 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
068a117c | 1201 | track->immd_dwords = pkt->count - 1; |
551ebd83 | 1202 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1203 | if (r) { |
1204 | return r; | |
1205 | } | |
1206 | break; | |
771fe6b9 | 1207 | case PACKET3_3D_DRAW_IMMD_2: |
068a117c JG |
1208 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1209 | * PRIM_WALK must be equal to 3 vertex data in embedded | |
1210 | * in cmd stream */ | |
513bcb46 | 1211 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
068a117c JG |
1212 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1213 | return -EINVAL; | |
1214 | } | |
513bcb46 | 1215 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
068a117c | 1216 | track->immd_dwords = pkt->count; |
551ebd83 | 1217 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1218 | if (r) { |
1219 | return r; | |
1220 | } | |
1221 | break; | |
1222 | case PACKET3_3D_DRAW_VBUF: | |
513bcb46 | 1223 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 | 1224 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1225 | if (r) { |
1226 | return r; | |
1227 | } | |
1228 | break; | |
1229 | case PACKET3_3D_DRAW_VBUF_2: | |
513bcb46 | 1230 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 | 1231 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1232 | if (r) { |
1233 | return r; | |
1234 | } | |
1235 | break; | |
1236 | case PACKET3_3D_DRAW_INDX: | |
513bcb46 | 1237 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 | 1238 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1239 | if (r) { |
1240 | return r; | |
1241 | } | |
1242 | break; | |
771fe6b9 | 1243 | case PACKET3_3D_DRAW_INDX_2: |
513bcb46 | 1244 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 | 1245 | r = r100_cs_track_check(p->rdev, track); |
771fe6b9 JG |
1246 | if (r) { |
1247 | return r; | |
1248 | } | |
1249 | break; | |
ab9e1f59 DA |
1250 | case PACKET3_3D_CLEAR_HIZ: |
1251 | case PACKET3_3D_CLEAR_ZMASK: | |
1252 | if (p->rdev->hyperz_filp != p->filp) | |
1253 | return -EINVAL; | |
1254 | break; | |
9eba4a93 MO |
1255 | case PACKET3_3D_CLEAR_CMASK: |
1256 | if (p->rdev->cmask_filp != p->filp) | |
1257 | return -EINVAL; | |
1258 | break; | |
771fe6b9 JG |
1259 | case PACKET3_NOP: |
1260 | break; | |
1261 | default: | |
1262 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
1263 | return -EINVAL; | |
1264 | } | |
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | int r300_cs_parse(struct radeon_cs_parser *p) | |
1269 | { | |
1270 | struct radeon_cs_packet pkt; | |
9f022ddf | 1271 | struct r100_cs_track *track; |
771fe6b9 JG |
1272 | int r; |
1273 | ||
9f022ddf | 1274 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
bbb642f9 KV |
1275 | if (track == NULL) |
1276 | return -ENOMEM; | |
9f022ddf JG |
1277 | r100_cs_track_clear(p->rdev, track); |
1278 | p->track = track; | |
771fe6b9 JG |
1279 | do { |
1280 | r = r100_cs_packet_parse(p, &pkt, p->idx); | |
1281 | if (r) { | |
1282 | return r; | |
1283 | } | |
1284 | p->idx += pkt.count + 2; | |
1285 | switch (pkt.type) { | |
1286 | case PACKET_TYPE0: | |
1287 | r = r100_cs_parse_packet0(p, &pkt, | |
068a117c JG |
1288 | p->rdev->config.r300.reg_safe_bm, |
1289 | p->rdev->config.r300.reg_safe_bm_size, | |
771fe6b9 JG |
1290 | &r300_packet0_check); |
1291 | break; | |
1292 | case PACKET_TYPE2: | |
1293 | break; | |
1294 | case PACKET_TYPE3: | |
1295 | r = r300_packet3_check(p, &pkt); | |
1296 | break; | |
1297 | default: | |
1298 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); | |
1299 | return -EINVAL; | |
1300 | } | |
1301 | if (r) { | |
1302 | return r; | |
1303 | } | |
1304 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); | |
1305 | return 0; | |
1306 | } | |
068a117c | 1307 | |
9f022ddf | 1308 | void r300_set_reg_safe(struct radeon_device *rdev) |
068a117c JG |
1309 | { |
1310 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; | |
1311 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); | |
9f022ddf JG |
1312 | } |
1313 | ||
9f022ddf JG |
1314 | void r300_mc_program(struct radeon_device *rdev) |
1315 | { | |
1316 | struct r100_mc_save save; | |
1317 | int r; | |
1318 | ||
1319 | r = r100_debugfs_mc_info_init(rdev); | |
1320 | if (r) { | |
1321 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); | |
1322 | } | |
1323 | ||
1324 | /* Stops all mc clients */ | |
1325 | r100_mc_stop(rdev, &save); | |
9f022ddf JG |
1326 | if (rdev->flags & RADEON_IS_AGP) { |
1327 | WREG32(R_00014C_MC_AGP_LOCATION, | |
1328 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
1329 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
1330 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
1331 | WREG32(R_00015C_AGP_BASE_2, | |
1332 | upper_32_bits(rdev->mc.agp_base) & 0xff); | |
1333 | } else { | |
1334 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); | |
1335 | WREG32(R_000170_AGP_BASE, 0); | |
1336 | WREG32(R_00015C_AGP_BASE_2, 0); | |
1337 | } | |
1338 | /* Wait for mc idle */ | |
1339 | if (r300_mc_wait_for_idle(rdev)) | |
1340 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); | |
1341 | /* Program MC, should be a 32bits limited address space */ | |
1342 | WREG32(R_000148_MC_FB_LOCATION, | |
1343 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | | |
1344 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
1345 | r100_mc_resume(rdev, &save); | |
1346 | } | |
ca6ffc64 JG |
1347 | |
1348 | void r300_clock_startup(struct radeon_device *rdev) | |
1349 | { | |
1350 | u32 tmp; | |
1351 | ||
1352 | if (radeon_dynclks != -1 && radeon_dynclks) | |
1353 | radeon_legacy_set_clock_gating(rdev, 1); | |
1354 | /* We need to force on some of the block */ | |
1355 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | |
1356 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
1357 | if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) | |
1358 | tmp |= S_00000D_FORCE_VAP(1); | |
1359 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | |
1360 | } | |
207bf9e9 JG |
1361 | |
1362 | static int r300_startup(struct radeon_device *rdev) | |
1363 | { | |
1364 | int r; | |
1365 | ||
92cde00c AD |
1366 | /* set common regs */ |
1367 | r100_set_common_regs(rdev); | |
1368 | /* program mc */ | |
207bf9e9 JG |
1369 | r300_mc_program(rdev); |
1370 | /* Resume clock */ | |
1371 | r300_clock_startup(rdev); | |
1372 | /* Initialize GPU configuration (# pipes, ...) */ | |
1373 | r300_gpu_init(rdev); | |
1374 | /* Initialize GART (initialize after TTM so we can allocate | |
1375 | * memory through TTM but finalize after TTM) */ | |
1376 | if (rdev->flags & RADEON_IS_PCIE) { | |
1377 | r = rv370_pcie_gart_enable(rdev); | |
1378 | if (r) | |
1379 | return r; | |
1380 | } | |
17e15b0c DA |
1381 | |
1382 | if (rdev->family == CHIP_R300 || | |
1383 | rdev->family == CHIP_R350 || | |
1384 | rdev->family == CHIP_RV350) | |
1385 | r100_enable_bm(rdev); | |
1386 | ||
207bf9e9 JG |
1387 | if (rdev->flags & RADEON_IS_PCI) { |
1388 | r = r100_pci_gart_enable(rdev); | |
1389 | if (r) | |
1390 | return r; | |
1391 | } | |
724c80e1 AD |
1392 | |
1393 | /* allocate wb buffer */ | |
1394 | r = radeon_wb_init(rdev); | |
1395 | if (r) | |
1396 | return r; | |
1397 | ||
207bf9e9 | 1398 | /* Enable IRQ */ |
207bf9e9 | 1399 | r100_irq_set(rdev); |
cafe6609 | 1400 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
207bf9e9 JG |
1401 | /* 1M ring buffer */ |
1402 | r = r100_cp_init(rdev, 1024 * 1024); | |
1403 | if (r) { | |
1404 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
1405 | return r; | |
1406 | } | |
207bf9e9 JG |
1407 | r = r100_ib_init(rdev); |
1408 | if (r) { | |
1409 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
1410 | return r; | |
1411 | } | |
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | int r300_resume(struct radeon_device *rdev) | |
1416 | { | |
1417 | /* Make sur GART are not working */ | |
1418 | if (rdev->flags & RADEON_IS_PCIE) | |
1419 | rv370_pcie_gart_disable(rdev); | |
1420 | if (rdev->flags & RADEON_IS_PCI) | |
1421 | r100_pci_gart_disable(rdev); | |
1422 | /* Resume clock before doing reset */ | |
1423 | r300_clock_startup(rdev); | |
1424 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1425 | if (radeon_asic_reset(rdev)) { |
207bf9e9 JG |
1426 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1427 | RREG32(R_000E40_RBBM_STATUS), | |
1428 | RREG32(R_0007C0_CP_STAT)); | |
1429 | } | |
1430 | /* post */ | |
1431 | radeon_combios_asic_init(rdev->ddev); | |
1432 | /* Resume clock after posting */ | |
1433 | r300_clock_startup(rdev); | |
550e2d92 DA |
1434 | /* Initialize surface registers */ |
1435 | radeon_surface_init(rdev); | |
207bf9e9 JG |
1436 | return r300_startup(rdev); |
1437 | } | |
1438 | ||
1439 | int r300_suspend(struct radeon_device *rdev) | |
1440 | { | |
1441 | r100_cp_disable(rdev); | |
724c80e1 | 1442 | radeon_wb_disable(rdev); |
207bf9e9 JG |
1443 | r100_irq_disable(rdev); |
1444 | if (rdev->flags & RADEON_IS_PCIE) | |
1445 | rv370_pcie_gart_disable(rdev); | |
1446 | if (rdev->flags & RADEON_IS_PCI) | |
1447 | r100_pci_gart_disable(rdev); | |
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | void r300_fini(struct radeon_device *rdev) | |
1452 | { | |
207bf9e9 | 1453 | r100_cp_fini(rdev); |
724c80e1 | 1454 | radeon_wb_fini(rdev); |
207bf9e9 JG |
1455 | r100_ib_fini(rdev); |
1456 | radeon_gem_fini(rdev); | |
1457 | if (rdev->flags & RADEON_IS_PCIE) | |
1458 | rv370_pcie_gart_fini(rdev); | |
1459 | if (rdev->flags & RADEON_IS_PCI) | |
1460 | r100_pci_gart_fini(rdev); | |
d0269ed8 | 1461 | radeon_agp_fini(rdev); |
207bf9e9 JG |
1462 | radeon_irq_kms_fini(rdev); |
1463 | radeon_fence_driver_fini(rdev); | |
4c788679 | 1464 | radeon_bo_fini(rdev); |
207bf9e9 JG |
1465 | radeon_atombios_fini(rdev); |
1466 | kfree(rdev->bios); | |
1467 | rdev->bios = NULL; | |
1468 | } | |
1469 | ||
1470 | int r300_init(struct radeon_device *rdev) | |
1471 | { | |
1472 | int r; | |
1473 | ||
207bf9e9 JG |
1474 | /* Disable VGA */ |
1475 | r100_vga_render_disable(rdev); | |
1476 | /* Initialize scratch registers */ | |
1477 | radeon_scratch_init(rdev); | |
1478 | /* Initialize surface registers */ | |
1479 | radeon_surface_init(rdev); | |
1480 | /* TODO: disable VGA need to use VGA request */ | |
4c712e6c DA |
1481 | /* restore some register to sane defaults */ |
1482 | r100_restore_sanity(rdev); | |
207bf9e9 JG |
1483 | /* BIOS*/ |
1484 | if (!radeon_get_bios(rdev)) { | |
1485 | if (ASIC_IS_AVIVO(rdev)) | |
1486 | return -EINVAL; | |
1487 | } | |
1488 | if (rdev->is_atom_bios) { | |
1489 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); | |
1490 | return -EINVAL; | |
1491 | } else { | |
1492 | r = radeon_combios_init(rdev); | |
1493 | if (r) | |
1494 | return r; | |
1495 | } | |
1496 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1497 | if (radeon_asic_reset(rdev)) { |
207bf9e9 JG |
1498 | dev_warn(rdev->dev, |
1499 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
1500 | RREG32(R_000E40_RBBM_STATUS), | |
1501 | RREG32(R_0007C0_CP_STAT)); | |
1502 | } | |
1503 | /* check if cards are posted or not */ | |
72542d77 DA |
1504 | if (radeon_boot_test_post_card(rdev) == false) |
1505 | return -EINVAL; | |
207bf9e9 JG |
1506 | /* Set asic errata */ |
1507 | r300_errata(rdev); | |
1508 | /* Initialize clocks */ | |
1509 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
1510 | /* initialize AGP */ |
1511 | if (rdev->flags & RADEON_IS_AGP) { | |
1512 | r = radeon_agp_init(rdev); | |
1513 | if (r) { | |
1514 | radeon_agp_disable(rdev); | |
1515 | } | |
1516 | } | |
1517 | /* initialize memory controller */ | |
1518 | r300_mc_init(rdev); | |
207bf9e9 JG |
1519 | /* Fence driver */ |
1520 | r = radeon_fence_driver_init(rdev); | |
1521 | if (r) | |
1522 | return r; | |
1523 | r = radeon_irq_kms_init(rdev); | |
1524 | if (r) | |
1525 | return r; | |
1526 | /* Memory manager */ | |
4c788679 | 1527 | r = radeon_bo_init(rdev); |
207bf9e9 JG |
1528 | if (r) |
1529 | return r; | |
1530 | if (rdev->flags & RADEON_IS_PCIE) { | |
1531 | r = rv370_pcie_gart_init(rdev); | |
1532 | if (r) | |
1533 | return r; | |
1534 | } | |
1535 | if (rdev->flags & RADEON_IS_PCI) { | |
1536 | r = r100_pci_gart_init(rdev); | |
1537 | if (r) | |
1538 | return r; | |
1539 | } | |
1540 | r300_set_reg_safe(rdev); | |
1541 | rdev->accel_working = true; | |
1542 | r = r300_startup(rdev); | |
1543 | if (r) { | |
1544 | /* Somethings want wront with the accel init stop accel */ | |
1545 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
207bf9e9 | 1546 | r100_cp_fini(rdev); |
724c80e1 | 1547 | radeon_wb_fini(rdev); |
207bf9e9 | 1548 | r100_ib_fini(rdev); |
655efd3d | 1549 | radeon_irq_kms_fini(rdev); |
207bf9e9 JG |
1550 | if (rdev->flags & RADEON_IS_PCIE) |
1551 | rv370_pcie_gart_fini(rdev); | |
1552 | if (rdev->flags & RADEON_IS_PCI) | |
1553 | r100_pci_gart_fini(rdev); | |
655efd3d | 1554 | radeon_agp_fini(rdev); |
207bf9e9 JG |
1555 | rdev->accel_working = false; |
1556 | } | |
1557 | return 0; | |
1558 | } |