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Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
225758d8 JG |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
e6990375 | 35 | #include "radeon_asic.h" |
760285e7 | 36 | #include <drm/radeon_drm.h> |
551ebd83 | 37 | #include "r100_track.h" |
3ce0a23d | 38 | #include "r300d.h" |
ca6ffc64 | 39 | #include "rv350d.h" |
50f15303 DA |
40 | #include "r300_reg_safe.h" |
41 | ||
cafe6609 JG |
42 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 |
43 | * | |
44 | * GPU Errata: | |
45 | * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL | |
46 | * using MMIO to flush host path read cache, this lead to HARDLOCKUP. | |
47 | * However, scheduling such write to the ring seems harmless, i suspect | |
48 | * the CP read collide with the flush somehow, or maybe the MC, hard to | |
49 | * tell. (Jerome Glisse) | |
50 | */ | |
771fe6b9 | 51 | |
9e5acbc2 DV |
52 | /* |
53 | * Indirect registers accessor | |
54 | */ | |
55 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
56 | { | |
57 | unsigned long flags; | |
58 | uint32_t r; | |
59 | ||
60 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); | |
61 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
62 | r = RREG32(RADEON_PCIE_DATA); | |
63 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); | |
64 | return r; | |
65 | } | |
66 | ||
67 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
68 | { | |
69 | unsigned long flags; | |
70 | ||
71 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); | |
72 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
73 | WREG32(RADEON_PCIE_DATA, (v)); | |
74 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); | |
75 | } | |
76 | ||
771fe6b9 JG |
77 | /* |
78 | * rv370,rv380 PCIE GART | |
79 | */ | |
207bf9e9 JG |
80 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
81 | ||
771fe6b9 JG |
82 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
83 | { | |
84 | uint32_t tmp; | |
85 | int i; | |
86 | ||
87 | /* Workaround HW bug do flush 2 times */ | |
88 | for (i = 0; i < 2; i++) { | |
89 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
90 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); | |
91 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
92 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
771fe6b9 | 93 | } |
de1b2898 | 94 | mb(); |
771fe6b9 JG |
95 | } |
96 | ||
77497f27 | 97 | #define R300_PTE_UNSNOOPED (1 << 0) |
d75ee3be AD |
98 | #define R300_PTE_WRITEABLE (1 << 2) |
99 | #define R300_PTE_READABLE (1 << 3) | |
100 | ||
cb658906 | 101 | uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) |
4aac0473 | 102 | { |
4aac0473 | 103 | addr = (lower_32_bits(addr) >> 8) | |
77497f27 MD |
104 | ((upper_32_bits(addr) & 0xff) << 24); |
105 | if (flags & RADEON_GART_PAGE_READ) | |
106 | addr |= R300_PTE_READABLE; | |
107 | if (flags & RADEON_GART_PAGE_WRITE) | |
108 | addr |= R300_PTE_WRITEABLE; | |
109 | if (!(flags & RADEON_GART_PAGE_SNOOP)) | |
110 | addr |= R300_PTE_UNSNOOPED; | |
cb658906 MD |
111 | return addr; |
112 | } | |
113 | ||
114 | void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, | |
115 | uint64_t entry) | |
116 | { | |
117 | void __iomem *ptr = rdev->gart.ptr; | |
118 | ||
4aac0473 JG |
119 | /* on x86 we want this to be CPU endian, on powerpc |
120 | * on powerpc without HW swappers, it'll get swapped on way | |
121 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ | |
cb658906 | 122 | writel(entry, ((void __iomem *)ptr) + (i * 4)); |
4aac0473 JG |
123 | } |
124 | ||
125 | int rv370_pcie_gart_init(struct radeon_device *rdev) | |
771fe6b9 | 126 | { |
771fe6b9 JG |
127 | int r; |
128 | ||
c9a1be96 | 129 | if (rdev->gart.robj) { |
fce7d61b | 130 | WARN(1, "RV370 PCIE GART already initialized\n"); |
4aac0473 JG |
131 | return 0; |
132 | } | |
771fe6b9 JG |
133 | /* Initialize common gart structure */ |
134 | r = radeon_gart_init(rdev); | |
4aac0473 | 135 | if (r) |
771fe6b9 | 136 | return r; |
771fe6b9 | 137 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
4aac0473 | 138 | if (r) |
771fe6b9 | 139 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
771fe6b9 | 140 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
c5b3b850 | 141 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
cb658906 | 142 | rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; |
c5b3b850 | 143 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
4aac0473 JG |
144 | return radeon_gart_table_vram_alloc(rdev); |
145 | } | |
146 | ||
147 | int rv370_pcie_gart_enable(struct radeon_device *rdev) | |
148 | { | |
149 | uint32_t table_addr; | |
150 | uint32_t tmp; | |
151 | int r; | |
152 | ||
c9a1be96 | 153 | if (rdev->gart.robj == NULL) { |
4aac0473 JG |
154 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
155 | return -EINVAL; | |
771fe6b9 | 156 | } |
4aac0473 JG |
157 | r = radeon_gart_table_vram_pin(rdev); |
158 | if (r) | |
159 | return r; | |
771fe6b9 JG |
160 | /* discard memory request outside of configured range */ |
161 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
162 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
d594e46a JG |
163 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); |
164 | tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; | |
771fe6b9 JG |
165 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
166 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); | |
167 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); | |
168 | table_addr = rdev->gart.table_addr; | |
169 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); | |
170 | /* FIXME: setup default page */ | |
d594e46a | 171 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
771fe6b9 JG |
172 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
173 | /* Clear error */ | |
d75ee3be | 174 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
771fe6b9 JG |
175 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
176 | tmp |= RADEON_PCIE_TX_GART_EN; | |
177 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
178 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
179 | rv370_pcie_gart_tlb_flush(rdev); | |
fcf4de5a TV |
180 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
181 | (unsigned)(rdev->mc.gtt_size >> 20), | |
182 | (unsigned long long)table_addr); | |
771fe6b9 JG |
183 | rdev->gart.ready = true; |
184 | return 0; | |
185 | } | |
186 | ||
187 | void rv370_pcie_gart_disable(struct radeon_device *rdev) | |
188 | { | |
4c788679 | 189 | u32 tmp; |
771fe6b9 | 190 | |
90aca4d2 JG |
191 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); |
192 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); | |
193 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); | |
194 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); | |
771fe6b9 JG |
195 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
196 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
197 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); | |
c9a1be96 | 198 | radeon_gart_table_vram_unpin(rdev); |
771fe6b9 JG |
199 | } |
200 | ||
4aac0473 | 201 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
771fe6b9 | 202 | { |
f9274562 | 203 | radeon_gart_fini(rdev); |
4aac0473 JG |
204 | rv370_pcie_gart_disable(rdev); |
205 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
206 | } |
207 | ||
771fe6b9 JG |
208 | void r300_fence_ring_emit(struct radeon_device *rdev, |
209 | struct radeon_fence *fence) | |
210 | { | |
e32eb50d | 211 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
7b1f2485 | 212 | |
771fe6b9 JG |
213 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
214 | * for enough space (today caller are ib schedule and buffer move) */ | |
215 | /* Write SC register so SC & US assert idle */ | |
e32eb50d CK |
216 | radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); |
217 | radeon_ring_write(ring, 0); | |
218 | radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); | |
219 | radeon_ring_write(ring, 0); | |
771fe6b9 | 220 | /* Flush 3D cache */ |
e32eb50d CK |
221 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
222 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH); | |
223 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
224 | radeon_ring_write(ring, R300_ZC_FLUSH); | |
771fe6b9 | 225 | /* Wait until IDLE & CLEAN */ |
e32eb50d CK |
226 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
227 | radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | | |
4612dc97 AD |
228 | RADEON_WAIT_2D_IDLECLEAN | |
229 | RADEON_WAIT_DMA_GUI_IDLE)); | |
e32eb50d CK |
230 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
231 | radeon_ring_write(ring, rdev->config.r300.hdp_cntl | | |
cafe6609 | 232 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
e32eb50d CK |
233 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
234 | radeon_ring_write(ring, rdev->config.r300.hdp_cntl); | |
771fe6b9 | 235 | /* Emit fence sequence & fire IRQ */ |
e32eb50d CK |
236 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
237 | radeon_ring_write(ring, fence->seq); | |
238 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); | |
239 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); | |
771fe6b9 JG |
240 | } |
241 | ||
f712812e | 242 | void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 JG |
243 | { |
244 | unsigned gb_tile_config; | |
245 | int r; | |
246 | ||
247 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ | |
248 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); | |
068a117c | 249 | switch(rdev->num_gb_pipes) { |
771fe6b9 JG |
250 | case 2: |
251 | gb_tile_config |= R300_PIPE_COUNT_R300; | |
252 | break; | |
253 | case 3: | |
254 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; | |
255 | break; | |
256 | case 4: | |
257 | gb_tile_config |= R300_PIPE_COUNT_R420; | |
258 | break; | |
259 | case 1: | |
260 | default: | |
261 | gb_tile_config |= R300_PIPE_COUNT_RV350; | |
262 | break; | |
263 | } | |
264 | ||
e32eb50d | 265 | r = radeon_ring_lock(rdev, ring, 64); |
771fe6b9 JG |
266 | if (r) { |
267 | return; | |
268 | } | |
e32eb50d CK |
269 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
270 | radeon_ring_write(ring, | |
771fe6b9 JG |
271 | RADEON_ISYNC_ANY2D_IDLE3D | |
272 | RADEON_ISYNC_ANY3D_IDLE2D | | |
273 | RADEON_ISYNC_WAIT_IDLEGUI | | |
274 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
e32eb50d CK |
275 | radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); |
276 | radeon_ring_write(ring, gb_tile_config); | |
277 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
278 | radeon_ring_write(ring, | |
771fe6b9 JG |
279 | RADEON_WAIT_2D_IDLECLEAN | |
280 | RADEON_WAIT_3D_IDLECLEAN); | |
e32eb50d CK |
281 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
282 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); | |
283 | radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); | |
284 | radeon_ring_write(ring, 0); | |
285 | radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); | |
286 | radeon_ring_write(ring, 0); | |
287 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
288 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | |
289 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
290 | radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); | |
291 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
292 | radeon_ring_write(ring, | |
771fe6b9 JG |
293 | RADEON_WAIT_2D_IDLECLEAN | |
294 | RADEON_WAIT_3D_IDLECLEAN); | |
e32eb50d CK |
295 | radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); |
296 | radeon_ring_write(ring, 0); | |
297 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
298 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | |
299 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
300 | radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); | |
301 | radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); | |
302 | radeon_ring_write(ring, | |
771fe6b9 JG |
303 | ((6 << R300_MS_X0_SHIFT) | |
304 | (6 << R300_MS_Y0_SHIFT) | | |
305 | (6 << R300_MS_X1_SHIFT) | | |
306 | (6 << R300_MS_Y1_SHIFT) | | |
307 | (6 << R300_MS_X2_SHIFT) | | |
308 | (6 << R300_MS_Y2_SHIFT) | | |
309 | (6 << R300_MSBD0_Y_SHIFT) | | |
310 | (6 << R300_MSBD0_X_SHIFT))); | |
e32eb50d CK |
311 | radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); |
312 | radeon_ring_write(ring, | |
771fe6b9 JG |
313 | ((6 << R300_MS_X3_SHIFT) | |
314 | (6 << R300_MS_Y3_SHIFT) | | |
315 | (6 << R300_MS_X4_SHIFT) | | |
316 | (6 << R300_MS_Y4_SHIFT) | | |
317 | (6 << R300_MS_X5_SHIFT) | | |
318 | (6 << R300_MS_Y5_SHIFT) | | |
319 | (6 << R300_MSBD1_SHIFT))); | |
e32eb50d CK |
320 | radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); |
321 | radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); | |
322 | radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); | |
323 | radeon_ring_write(ring, | |
771fe6b9 | 324 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
e32eb50d CK |
325 | radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); |
326 | radeon_ring_write(ring, | |
771fe6b9 JG |
327 | R300_GEOMETRY_ROUND_NEAREST | |
328 | R300_COLOR_ROUND_NEAREST); | |
1538a9e0 | 329 | radeon_ring_unlock_commit(rdev, ring, false); |
771fe6b9 JG |
330 | } |
331 | ||
1109ca09 | 332 | static void r300_errata(struct radeon_device *rdev) |
771fe6b9 JG |
333 | { |
334 | rdev->pll_errata = 0; | |
335 | ||
336 | if (rdev->family == CHIP_R300 && | |
337 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { | |
338 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; | |
339 | } | |
340 | } | |
341 | ||
342 | int r300_mc_wait_for_idle(struct radeon_device *rdev) | |
343 | { | |
344 | unsigned i; | |
345 | uint32_t tmp; | |
346 | ||
347 | for (i = 0; i < rdev->usec_timeout; i++) { | |
348 | /* read MC_STATUS */ | |
4612dc97 AD |
349 | tmp = RREG32(RADEON_MC_STATUS); |
350 | if (tmp & R300_MC_IDLE) { | |
771fe6b9 JG |
351 | return 0; |
352 | } | |
353 | DRM_UDELAY(1); | |
354 | } | |
355 | return -1; | |
356 | } | |
357 | ||
1109ca09 | 358 | static void r300_gpu_init(struct radeon_device *rdev) |
771fe6b9 JG |
359 | { |
360 | uint32_t gb_tile_config, tmp; | |
361 | ||
57b54ea6 | 362 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || |
94f7bf64 | 363 | (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { |
771fe6b9 JG |
364 | /* r300,r350 */ |
365 | rdev->num_gb_pipes = 2; | |
366 | } else { | |
94f7bf64 | 367 | /* rv350,rv370,rv380,r300 AD, r350 AH */ |
771fe6b9 JG |
368 | rdev->num_gb_pipes = 1; |
369 | } | |
f779b3e5 | 370 | rdev->num_z_pipes = 1; |
771fe6b9 JG |
371 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
372 | switch (rdev->num_gb_pipes) { | |
373 | case 2: | |
374 | gb_tile_config |= R300_PIPE_COUNT_R300; | |
375 | break; | |
376 | case 3: | |
377 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; | |
378 | break; | |
379 | case 4: | |
380 | gb_tile_config |= R300_PIPE_COUNT_R420; | |
381 | break; | |
771fe6b9 | 382 | default: |
068a117c | 383 | case 1: |
771fe6b9 JG |
384 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
385 | break; | |
386 | } | |
387 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); | |
388 | ||
389 | if (r100_gui_wait_for_idle(rdev)) { | |
390 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
391 | "programming pipes. Bad things might happen.\n"); | |
392 | } | |
393 | ||
4612dc97 AD |
394 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
395 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); | |
771fe6b9 JG |
396 | |
397 | WREG32(R300_RB2D_DSTCACHE_MODE, | |
398 | R300_DC_AUTOFLUSH_ENABLE | | |
399 | R300_DC_DC_DISABLE_IGNORE_PE); | |
400 | ||
401 | if (r100_gui_wait_for_idle(rdev)) { | |
402 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
403 | "programming pipes. Bad things might happen.\n"); | |
404 | } | |
405 | if (r300_mc_wait_for_idle(rdev)) { | |
406 | printk(KERN_WARNING "Failed to wait MC idle while " | |
407 | "programming pipes. Bad things might happen.\n"); | |
408 | } | |
f779b3e5 AD |
409 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", |
410 | rdev->num_gb_pipes, rdev->num_z_pipes); | |
771fe6b9 JG |
411 | } |
412 | ||
71fe2899 | 413 | int r300_asic_reset(struct radeon_device *rdev, bool hard) |
771fe6b9 | 414 | { |
90aca4d2 JG |
415 | struct r100_mc_save save; |
416 | u32 status, tmp; | |
25b2ec5b | 417 | int ret = 0; |
771fe6b9 | 418 | |
90aca4d2 JG |
419 | status = RREG32(R_000E40_RBBM_STATUS); |
420 | if (!G_000E40_GUI_ACTIVE(status)) { | |
421 | return 0; | |
771fe6b9 | 422 | } |
25b2ec5b | 423 | r100_mc_stop(rdev, &save); |
90aca4d2 JG |
424 | status = RREG32(R_000E40_RBBM_STATUS); |
425 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
426 | /* stop CP */ | |
427 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
428 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
429 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
430 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
431 | WREG32(RADEON_CP_RB_WPTR, 0); | |
432 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
433 | /* save PCI state */ | |
434 | pci_save_state(rdev->pdev); | |
435 | /* disable bus mastering */ | |
436 | r100_bm_disable(rdev); | |
437 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | | |
438 | S_0000F0_SOFT_RESET_GA(1)); | |
439 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
440 | mdelay(500); | |
441 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
442 | mdelay(1); | |
443 | status = RREG32(R_000E40_RBBM_STATUS); | |
444 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
445 | /* resetting the CP seems to be problematic sometimes it end up | |
25985edc | 446 | * hard locking the computer, but it's necessary for successful |
90aca4d2 JG |
447 | * reset more test & playing is needed on R3XX/R4XX to find a |
448 | * reliable (if any solution) | |
449 | */ | |
450 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); | |
451 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
452 | mdelay(500); | |
453 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
454 | mdelay(1); | |
455 | status = RREG32(R_000E40_RBBM_STATUS); | |
456 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
90aca4d2 JG |
457 | /* restore PCI & busmastering */ |
458 | pci_restore_state(rdev->pdev); | |
459 | r100_enable_bm(rdev); | |
771fe6b9 | 460 | /* Check if GPU is idle */ |
90aca4d2 JG |
461 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
462 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
25b2ec5b AD |
463 | ret = -1; |
464 | } else | |
465 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
90aca4d2 | 466 | r100_mc_resume(rdev, &save); |
25b2ec5b | 467 | return ret; |
771fe6b9 JG |
468 | } |
469 | ||
771fe6b9 JG |
470 | /* |
471 | * r300,r350,rv350,rv380 VRAM info | |
472 | */ | |
d594e46a | 473 | void r300_mc_init(struct radeon_device *rdev) |
771fe6b9 | 474 | { |
8e361130 JG |
475 | u64 base; |
476 | u32 tmp; | |
771fe6b9 JG |
477 | |
478 | /* DDR for all card after R300 & IGP */ | |
479 | rdev->mc.vram_is_ddr = true; | |
480 | tmp = RREG32(RADEON_MEM_CNTL); | |
5ff55717 DA |
481 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
482 | switch (tmp) { | |
483 | case 0: rdev->mc.vram_width = 64; break; | |
484 | case 1: rdev->mc.vram_width = 128; break; | |
485 | case 2: rdev->mc.vram_width = 256; break; | |
486 | default: rdev->mc.vram_width = 128; break; | |
771fe6b9 | 487 | } |
2a0f8918 | 488 | r100_vram_init_sizes(rdev); |
8e361130 JG |
489 | base = rdev->mc.aper_base; |
490 | if (rdev->flags & RADEON_IS_IGP) | |
491 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | |
492 | radeon_vram_location(rdev, &rdev->mc, base); | |
8d369bb1 | 493 | rdev->mc.gtt_base_align = 0; |
d594e46a JG |
494 | if (!(rdev->flags & RADEON_IS_AGP)) |
495 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 496 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
497 | } |
498 | ||
771fe6b9 JG |
499 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
500 | { | |
501 | uint32_t link_width_cntl, mask; | |
502 | ||
503 | if (rdev->flags & RADEON_IS_IGP) | |
504 | return; | |
505 | ||
506 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
507 | return; | |
508 | ||
509 | /* FIXME wait for idle */ | |
510 | ||
511 | switch (lanes) { | |
512 | case 0: | |
513 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; | |
514 | break; | |
515 | case 1: | |
516 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; | |
517 | break; | |
518 | case 2: | |
519 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; | |
520 | break; | |
521 | case 4: | |
522 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; | |
523 | break; | |
524 | case 8: | |
525 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; | |
526 | break; | |
527 | case 12: | |
528 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; | |
529 | break; | |
530 | case 16: | |
531 | default: | |
532 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; | |
533 | break; | |
534 | } | |
535 | ||
536 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
537 | ||
538 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == | |
539 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) | |
540 | return; | |
541 | ||
542 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | | |
543 | RADEON_PCIE_LC_RECONFIG_NOW | | |
544 | RADEON_PCIE_LC_RECONFIG_LATER | | |
545 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); | |
546 | link_width_cntl |= mask; | |
547 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
548 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | | |
549 | RADEON_PCIE_LC_RECONFIG_NOW)); | |
550 | ||
551 | /* wait for lane set to complete */ | |
552 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
553 | while (link_width_cntl == 0xffffffff) | |
554 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
555 | ||
556 | } | |
557 | ||
c836a412 AD |
558 | int rv370_get_pcie_lanes(struct radeon_device *rdev) |
559 | { | |
560 | u32 link_width_cntl; | |
561 | ||
562 | if (rdev->flags & RADEON_IS_IGP) | |
563 | return 0; | |
564 | ||
565 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
566 | return 0; | |
567 | ||
568 | /* FIXME wait for idle */ | |
569 | ||
3313e3d4 | 570 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
c836a412 AD |
571 | |
572 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { | |
573 | case RADEON_PCIE_LC_LINK_WIDTH_X0: | |
574 | return 0; | |
575 | case RADEON_PCIE_LC_LINK_WIDTH_X1: | |
576 | return 1; | |
577 | case RADEON_PCIE_LC_LINK_WIDTH_X2: | |
578 | return 2; | |
579 | case RADEON_PCIE_LC_LINK_WIDTH_X4: | |
580 | return 4; | |
581 | case RADEON_PCIE_LC_LINK_WIDTH_X8: | |
582 | return 8; | |
583 | case RADEON_PCIE_LC_LINK_WIDTH_X16: | |
584 | default: | |
585 | return 16; | |
586 | } | |
587 | } | |
588 | ||
771fe6b9 JG |
589 | #if defined(CONFIG_DEBUG_FS) |
590 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) | |
591 | { | |
592 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
593 | struct drm_device *dev = node->minor->dev; | |
594 | struct radeon_device *rdev = dev->dev_private; | |
595 | uint32_t tmp; | |
596 | ||
597 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
598 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); | |
599 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); | |
600 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); | |
601 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); | |
602 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); | |
603 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); | |
604 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); | |
605 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); | |
606 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); | |
607 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); | |
608 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); | |
609 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); | |
610 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); | |
611 | return 0; | |
612 | } | |
613 | ||
614 | static struct drm_info_list rv370_pcie_gart_info_list[] = { | |
615 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, | |
616 | }; | |
617 | #endif | |
618 | ||
207bf9e9 | 619 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
771fe6b9 JG |
620 | { |
621 | #if defined(CONFIG_DEBUG_FS) | |
622 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); | |
623 | #else | |
624 | return 0; | |
625 | #endif | |
626 | } | |
627 | ||
771fe6b9 JG |
628 | static int r300_packet0_check(struct radeon_cs_parser *p, |
629 | struct radeon_cs_packet *pkt, | |
630 | unsigned idx, unsigned reg) | |
631 | { | |
1d0c0942 | 632 | struct radeon_bo_list *reloc; |
551ebd83 | 633 | struct r100_cs_track *track; |
771fe6b9 | 634 | volatile uint32_t *ib; |
e024e110 | 635 | uint32_t tmp, tile_flags = 0; |
771fe6b9 JG |
636 | unsigned i; |
637 | int r; | |
513bcb46 | 638 | u32 idx_value; |
771fe6b9 | 639 | |
f2e39221 | 640 | ib = p->ib.ptr; |
551ebd83 | 641 | track = (struct r100_cs_track *)p->track; |
513bcb46 DA |
642 | idx_value = radeon_get_ib_value(p, idx); |
643 | ||
068a117c | 644 | switch(reg) { |
531369e6 DA |
645 | case AVIVO_D1MODE_VLINE_START_END: |
646 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
647 | r = r100_cs_packet_parse_vline(p); | |
648 | if (r) { | |
649 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
650 | idx, reg); | |
c3ad63af | 651 | radeon_cs_dump_packet(p, pkt); |
531369e6 DA |
652 | return r; |
653 | } | |
654 | break; | |
771fe6b9 JG |
655 | case RADEON_DST_PITCH_OFFSET: |
656 | case RADEON_SRC_PITCH_OFFSET: | |
551ebd83 DA |
657 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
658 | if (r) | |
771fe6b9 | 659 | return r; |
771fe6b9 JG |
660 | break; |
661 | case R300_RB3D_COLOROFFSET0: | |
662 | case R300_RB3D_COLOROFFSET1: | |
663 | case R300_RB3D_COLOROFFSET2: | |
664 | case R300_RB3D_COLOROFFSET3: | |
665 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; | |
012e976d | 666 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
667 | if (r) { |
668 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
669 | idx, reg); | |
c3ad63af | 670 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
671 | return r; |
672 | } | |
673 | track->cb[i].robj = reloc->robj; | |
513bcb46 | 674 | track->cb[i].offset = idx_value; |
40b4a759 | 675 | track->cb_dirty = true; |
df0af440 | 676 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
771fe6b9 JG |
677 | break; |
678 | case R300_ZB_DEPTHOFFSET: | |
012e976d | 679 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
680 | if (r) { |
681 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
682 | idx, reg); | |
c3ad63af | 683 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
684 | return r; |
685 | } | |
686 | track->zb.robj = reloc->robj; | |
513bcb46 | 687 | track->zb.offset = idx_value; |
40b4a759 | 688 | track->zb_dirty = true; |
df0af440 | 689 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
771fe6b9 JG |
690 | break; |
691 | case R300_TX_OFFSET_0: | |
692 | case R300_TX_OFFSET_0+4: | |
693 | case R300_TX_OFFSET_0+8: | |
694 | case R300_TX_OFFSET_0+12: | |
695 | case R300_TX_OFFSET_0+16: | |
696 | case R300_TX_OFFSET_0+20: | |
697 | case R300_TX_OFFSET_0+24: | |
698 | case R300_TX_OFFSET_0+28: | |
699 | case R300_TX_OFFSET_0+32: | |
700 | case R300_TX_OFFSET_0+36: | |
701 | case R300_TX_OFFSET_0+40: | |
702 | case R300_TX_OFFSET_0+44: | |
703 | case R300_TX_OFFSET_0+48: | |
704 | case R300_TX_OFFSET_0+52: | |
705 | case R300_TX_OFFSET_0+56: | |
706 | case R300_TX_OFFSET_0+60: | |
068a117c | 707 | i = (reg - R300_TX_OFFSET_0) >> 2; |
012e976d | 708 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
709 | if (r) { |
710 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
711 | idx, reg); | |
c3ad63af | 712 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
713 | return r; |
714 | } | |
6e726772 | 715 | |
721604a1 | 716 | if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { |
e70f224c | 717 | ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ |
df0af440 | 718 | ((idx_value & ~31) + (u32)reloc->gpu_offset); |
e70f224c | 719 | } else { |
df0af440 | 720 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
e70f224c | 721 | tile_flags |= R300_TXO_MACRO_TILE; |
df0af440 | 722 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
e70f224c | 723 | tile_flags |= R300_TXO_MICRO_TILE; |
df0af440 | 724 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
e70f224c MO |
725 | tile_flags |= R300_TXO_MICRO_TILE_SQUARE; |
726 | ||
df0af440 | 727 | tmp = idx_value + ((u32)reloc->gpu_offset); |
e70f224c MO |
728 | tmp |= tile_flags; |
729 | ib[idx] = tmp; | |
730 | } | |
068a117c | 731 | track->textures[i].robj = reloc->robj; |
40b4a759 | 732 | track->tex_dirty = true; |
771fe6b9 JG |
733 | break; |
734 | /* Tracked registers */ | |
068a117c JG |
735 | case 0x2084: |
736 | /* VAP_VF_CNTL */ | |
513bcb46 | 737 | track->vap_vf_cntl = idx_value; |
068a117c JG |
738 | break; |
739 | case 0x20B4: | |
740 | /* VAP_VTX_SIZE */ | |
513bcb46 | 741 | track->vtx_size = idx_value & 0x7F; |
068a117c JG |
742 | break; |
743 | case 0x2134: | |
744 | /* VAP_VF_MAX_VTX_INDX */ | |
513bcb46 | 745 | track->max_indx = idx_value & 0x00FFFFFFUL; |
068a117c | 746 | break; |
cae94b0a MO |
747 | case 0x2088: |
748 | /* VAP_ALT_NUM_VERTICES - only valid on r500 */ | |
749 | if (p->rdev->family < CHIP_RV515) | |
750 | goto fail; | |
751 | track->vap_alt_nverts = idx_value & 0xFFFFFF; | |
752 | break; | |
771fe6b9 JG |
753 | case 0x43E4: |
754 | /* SC_SCISSOR1 */ | |
513bcb46 | 755 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
771fe6b9 JG |
756 | if (p->rdev->family < CHIP_RV515) { |
757 | track->maxy -= 1440; | |
758 | } | |
40b4a759 MO |
759 | track->cb_dirty = true; |
760 | track->zb_dirty = true; | |
771fe6b9 JG |
761 | break; |
762 | case 0x4E00: | |
763 | /* RB3D_CCTL */ | |
9eba4a93 MO |
764 | if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ |
765 | p->rdev->cmask_filp != p->filp) { | |
766 | DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); | |
767 | return -EINVAL; | |
768 | } | |
513bcb46 | 769 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
40b4a759 | 770 | track->cb_dirty = true; |
771fe6b9 JG |
771 | break; |
772 | case 0x4E38: | |
773 | case 0x4E3C: | |
774 | case 0x4E40: | |
775 | case 0x4E44: | |
776 | /* RB3D_COLORPITCH0 */ | |
777 | /* RB3D_COLORPITCH1 */ | |
778 | /* RB3D_COLORPITCH2 */ | |
779 | /* RB3D_COLORPITCH3 */ | |
721604a1 | 780 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
012e976d | 781 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
e70f224c MO |
782 | if (r) { |
783 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
784 | idx, reg); | |
c3ad63af | 785 | radeon_cs_dump_packet(p, pkt); |
e70f224c MO |
786 | return r; |
787 | } | |
e024e110 | 788 | |
df0af440 | 789 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
e70f224c | 790 | tile_flags |= R300_COLOR_TILE_ENABLE; |
df0af440 | 791 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
e70f224c | 792 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
df0af440 | 793 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
e70f224c | 794 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
e024e110 | 795 | |
e70f224c MO |
796 | tmp = idx_value & ~(0x7 << 16); |
797 | tmp |= tile_flags; | |
798 | ib[idx] = tmp; | |
799 | } | |
771fe6b9 | 800 | i = (reg - 0x4E38) >> 2; |
513bcb46 DA |
801 | track->cb[i].pitch = idx_value & 0x3FFE; |
802 | switch (((idx_value >> 21) & 0xF)) { | |
771fe6b9 JG |
803 | case 9: |
804 | case 11: | |
805 | case 12: | |
806 | track->cb[i].cpp = 1; | |
807 | break; | |
808 | case 3: | |
809 | case 4: | |
810 | case 13: | |
811 | case 15: | |
812 | track->cb[i].cpp = 2; | |
813 | break; | |
204663c4 MO |
814 | case 5: |
815 | if (p->rdev->family < CHIP_RV515) { | |
816 | DRM_ERROR("Invalid color buffer format (%d)!\n", | |
817 | ((idx_value >> 21) & 0xF)); | |
818 | return -EINVAL; | |
819 | } | |
820 | /* Pass through. */ | |
771fe6b9 JG |
821 | case 6: |
822 | track->cb[i].cpp = 4; | |
823 | break; | |
824 | case 10: | |
825 | track->cb[i].cpp = 8; | |
826 | break; | |
827 | case 7: | |
828 | track->cb[i].cpp = 16; | |
829 | break; | |
830 | default: | |
831 | DRM_ERROR("Invalid color buffer format (%d) !\n", | |
513bcb46 | 832 | ((idx_value >> 21) & 0xF)); |
771fe6b9 JG |
833 | return -EINVAL; |
834 | } | |
40b4a759 | 835 | track->cb_dirty = true; |
771fe6b9 JG |
836 | break; |
837 | case 0x4F00: | |
838 | /* ZB_CNTL */ | |
513bcb46 | 839 | if (idx_value & 2) { |
771fe6b9 JG |
840 | track->z_enabled = true; |
841 | } else { | |
842 | track->z_enabled = false; | |
843 | } | |
40b4a759 | 844 | track->zb_dirty = true; |
771fe6b9 JG |
845 | break; |
846 | case 0x4F10: | |
847 | /* ZB_FORMAT */ | |
513bcb46 | 848 | switch ((idx_value & 0xF)) { |
771fe6b9 JG |
849 | case 0: |
850 | case 1: | |
851 | track->zb.cpp = 2; | |
852 | break; | |
853 | case 2: | |
854 | track->zb.cpp = 4; | |
855 | break; | |
856 | default: | |
857 | DRM_ERROR("Invalid z buffer format (%d) !\n", | |
513bcb46 | 858 | (idx_value & 0xF)); |
771fe6b9 JG |
859 | return -EINVAL; |
860 | } | |
40b4a759 | 861 | track->zb_dirty = true; |
771fe6b9 JG |
862 | break; |
863 | case 0x4F24: | |
864 | /* ZB_DEPTHPITCH */ | |
721604a1 | 865 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
012e976d | 866 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
e70f224c MO |
867 | if (r) { |
868 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
869 | idx, reg); | |
c3ad63af | 870 | radeon_cs_dump_packet(p, pkt); |
e70f224c MO |
871 | return r; |
872 | } | |
e024e110 | 873 | |
df0af440 | 874 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
e70f224c | 875 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
df0af440 | 876 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
e70f224c | 877 | tile_flags |= R300_DEPTHMICROTILE_TILED; |
df0af440 | 878 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
e70f224c | 879 | tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; |
e024e110 | 880 | |
e70f224c MO |
881 | tmp = idx_value & ~(0x7 << 16); |
882 | tmp |= tile_flags; | |
883 | ib[idx] = tmp; | |
884 | } | |
513bcb46 | 885 | track->zb.pitch = idx_value & 0x3FFC; |
40b4a759 | 886 | track->zb_dirty = true; |
771fe6b9 | 887 | break; |
068a117c | 888 | case 0x4104: |
50183434 | 889 | /* TX_ENABLE */ |
068a117c JG |
890 | for (i = 0; i < 16; i++) { |
891 | bool enabled; | |
892 | ||
513bcb46 | 893 | enabled = !!(idx_value & (1 << i)); |
068a117c JG |
894 | track->textures[i].enabled = enabled; |
895 | } | |
40b4a759 | 896 | track->tex_dirty = true; |
068a117c JG |
897 | break; |
898 | case 0x44C0: | |
899 | case 0x44C4: | |
900 | case 0x44C8: | |
901 | case 0x44CC: | |
902 | case 0x44D0: | |
903 | case 0x44D4: | |
904 | case 0x44D8: | |
905 | case 0x44DC: | |
906 | case 0x44E0: | |
907 | case 0x44E4: | |
908 | case 0x44E8: | |
909 | case 0x44EC: | |
910 | case 0x44F0: | |
911 | case 0x44F4: | |
912 | case 0x44F8: | |
913 | case 0x44FC: | |
914 | /* TX_FORMAT1_[0-15] */ | |
915 | i = (reg - 0x44C0) >> 2; | |
513bcb46 | 916 | tmp = (idx_value >> 25) & 0x3; |
068a117c | 917 | track->textures[i].tex_coord_type = tmp; |
513bcb46 | 918 | switch ((idx_value & 0x1F)) { |
551ebd83 DA |
919 | case R300_TX_FORMAT_X8: |
920 | case R300_TX_FORMAT_Y4X4: | |
921 | case R300_TX_FORMAT_Z3Y3X2: | |
068a117c | 922 | track->textures[i].cpp = 1; |
f9da52d5 | 923 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 924 | break; |
551ebd83 | 925 | case R300_TX_FORMAT_X16: |
16e4b8a6 | 926 | case R300_TX_FORMAT_FL_I16: |
551ebd83 DA |
927 | case R300_TX_FORMAT_Y8X8: |
928 | case R300_TX_FORMAT_Z5Y6X5: | |
929 | case R300_TX_FORMAT_Z6Y5X5: | |
930 | case R300_TX_FORMAT_W4Z4Y4X4: | |
931 | case R300_TX_FORMAT_W1Z5Y5X5: | |
551ebd83 DA |
932 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
933 | case R300_TX_FORMAT_B8G8_B8G8: | |
934 | case R300_TX_FORMAT_G8R8_G8B8: | |
068a117c | 935 | track->textures[i].cpp = 2; |
f9da52d5 | 936 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 937 | break; |
551ebd83 | 938 | case R300_TX_FORMAT_Y16X16: |
16e4b8a6 | 939 | case R300_TX_FORMAT_FL_I16A16: |
551ebd83 DA |
940 | case R300_TX_FORMAT_Z11Y11X10: |
941 | case R300_TX_FORMAT_Z10Y11X11: | |
942 | case R300_TX_FORMAT_W8Z8Y8X8: | |
943 | case R300_TX_FORMAT_W2Z10Y10X10: | |
944 | case 0x17: | |
945 | case R300_TX_FORMAT_FL_I32: | |
946 | case 0x1e: | |
068a117c | 947 | track->textures[i].cpp = 4; |
f9da52d5 | 948 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 949 | break; |
551ebd83 DA |
950 | case R300_TX_FORMAT_W16Z16Y16X16: |
951 | case R300_TX_FORMAT_FL_R16G16B16A16: | |
952 | case R300_TX_FORMAT_FL_I32A32: | |
068a117c | 953 | track->textures[i].cpp = 8; |
f9da52d5 | 954 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 955 | break; |
551ebd83 | 956 | case R300_TX_FORMAT_FL_R32G32B32A32: |
068a117c | 957 | track->textures[i].cpp = 16; |
f9da52d5 | 958 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 959 | break; |
d785d78b DA |
960 | case R300_TX_FORMAT_DXT1: |
961 | track->textures[i].cpp = 1; | |
962 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | |
963 | break; | |
512889f4 MO |
964 | case R300_TX_FORMAT_ATI2N: |
965 | if (p->rdev->family < CHIP_R420) { | |
966 | DRM_ERROR("Invalid texture format %u\n", | |
967 | (idx_value & 0x1F)); | |
968 | return -EINVAL; | |
969 | } | |
970 | /* The same rules apply as for DXT3/5. */ | |
971 | /* Pass through. */ | |
d785d78b DA |
972 | case R300_TX_FORMAT_DXT3: |
973 | case R300_TX_FORMAT_DXT5: | |
974 | track->textures[i].cpp = 1; | |
975 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | |
976 | break; | |
068a117c JG |
977 | default: |
978 | DRM_ERROR("Invalid texture format %u\n", | |
513bcb46 | 979 | (idx_value & 0x1F)); |
068a117c | 980 | return -EINVAL; |
068a117c | 981 | } |
40b4a759 | 982 | track->tex_dirty = true; |
068a117c JG |
983 | break; |
984 | case 0x4400: | |
985 | case 0x4404: | |
986 | case 0x4408: | |
987 | case 0x440C: | |
988 | case 0x4410: | |
989 | case 0x4414: | |
990 | case 0x4418: | |
991 | case 0x441C: | |
992 | case 0x4420: | |
993 | case 0x4424: | |
994 | case 0x4428: | |
995 | case 0x442C: | |
996 | case 0x4430: | |
997 | case 0x4434: | |
998 | case 0x4438: | |
999 | case 0x443C: | |
1000 | /* TX_FILTER0_[0-15] */ | |
1001 | i = (reg - 0x4400) >> 2; | |
513bcb46 | 1002 | tmp = idx_value & 0x7; |
068a117c JG |
1003 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
1004 | track->textures[i].roundup_w = false; | |
1005 | } | |
513bcb46 | 1006 | tmp = (idx_value >> 3) & 0x7; |
068a117c JG |
1007 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
1008 | track->textures[i].roundup_h = false; | |
1009 | } | |
40b4a759 | 1010 | track->tex_dirty = true; |
068a117c JG |
1011 | break; |
1012 | case 0x4500: | |
1013 | case 0x4504: | |
1014 | case 0x4508: | |
1015 | case 0x450C: | |
1016 | case 0x4510: | |
1017 | case 0x4514: | |
1018 | case 0x4518: | |
1019 | case 0x451C: | |
1020 | case 0x4520: | |
1021 | case 0x4524: | |
1022 | case 0x4528: | |
1023 | case 0x452C: | |
1024 | case 0x4530: | |
1025 | case 0x4534: | |
1026 | case 0x4538: | |
1027 | case 0x453C: | |
1028 | /* TX_FORMAT2_[0-15] */ | |
1029 | i = (reg - 0x4500) >> 2; | |
513bcb46 | 1030 | tmp = idx_value & 0x3FFF; |
068a117c JG |
1031 | track->textures[i].pitch = tmp + 1; |
1032 | if (p->rdev->family >= CHIP_RV515) { | |
513bcb46 | 1033 | tmp = ((idx_value >> 15) & 1) << 11; |
068a117c | 1034 | track->textures[i].width_11 = tmp; |
513bcb46 | 1035 | tmp = ((idx_value >> 16) & 1) << 11; |
068a117c | 1036 | track->textures[i].height_11 = tmp; |
512889f4 MO |
1037 | |
1038 | /* ATI1N */ | |
1039 | if (idx_value & (1 << 14)) { | |
1040 | /* The same rules apply as for DXT1. */ | |
1041 | track->textures[i].compress_format = | |
1042 | R100_TRACK_COMP_DXT1; | |
1043 | } | |
1044 | } else if (idx_value & (1 << 14)) { | |
1045 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); | |
1046 | return -EINVAL; | |
068a117c | 1047 | } |
40b4a759 | 1048 | track->tex_dirty = true; |
068a117c JG |
1049 | break; |
1050 | case 0x4480: | |
1051 | case 0x4484: | |
1052 | case 0x4488: | |
1053 | case 0x448C: | |
1054 | case 0x4490: | |
1055 | case 0x4494: | |
1056 | case 0x4498: | |
1057 | case 0x449C: | |
1058 | case 0x44A0: | |
1059 | case 0x44A4: | |
1060 | case 0x44A8: | |
1061 | case 0x44AC: | |
1062 | case 0x44B0: | |
1063 | case 0x44B4: | |
1064 | case 0x44B8: | |
1065 | case 0x44BC: | |
1066 | /* TX_FORMAT0_[0-15] */ | |
1067 | i = (reg - 0x4480) >> 2; | |
513bcb46 | 1068 | tmp = idx_value & 0x7FF; |
068a117c | 1069 | track->textures[i].width = tmp + 1; |
513bcb46 | 1070 | tmp = (idx_value >> 11) & 0x7FF; |
068a117c | 1071 | track->textures[i].height = tmp + 1; |
513bcb46 | 1072 | tmp = (idx_value >> 26) & 0xF; |
068a117c | 1073 | track->textures[i].num_levels = tmp; |
513bcb46 | 1074 | tmp = idx_value & (1 << 31); |
068a117c | 1075 | track->textures[i].use_pitch = !!tmp; |
513bcb46 | 1076 | tmp = (idx_value >> 22) & 0xF; |
068a117c | 1077 | track->textures[i].txdepth = tmp; |
40b4a759 | 1078 | track->tex_dirty = true; |
068a117c | 1079 | break; |
3f8befec | 1080 | case R300_ZB_ZPASS_ADDR: |
012e976d | 1081 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
3f8befec DA |
1082 | if (r) { |
1083 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1084 | idx, reg); | |
c3ad63af | 1085 | radeon_cs_dump_packet(p, pkt); |
3f8befec DA |
1086 | return r; |
1087 | } | |
df0af440 | 1088 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
3f8befec | 1089 | break; |
46c64d4b MO |
1090 | case 0x4e0c: |
1091 | /* RB3D_COLOR_CHANNEL_MASK */ | |
1092 | track->color_channel_mask = idx_value; | |
40b4a759 | 1093 | track->cb_dirty = true; |
46c64d4b | 1094 | break; |
ab9e1f59 DA |
1095 | case 0x43a4: |
1096 | /* SC_HYPERZ_EN */ | |
1097 | /* r300c emits this register - we need to disable hyperz for it | |
1098 | * without complaining */ | |
1099 | if (p->rdev->hyperz_filp != p->filp) { | |
1100 | if (idx_value & 0x1) | |
1101 | ib[idx] = idx_value & ~1; | |
1102 | } | |
1103 | break; | |
1104 | case 0x4f1c: | |
46c64d4b | 1105 | /* ZB_BW_CNTL */ |
797fd5b9 | 1106 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
40b4a759 MO |
1107 | track->cb_dirty = true; |
1108 | track->zb_dirty = true; | |
ab9e1f59 DA |
1109 | if (p->rdev->hyperz_filp != p->filp) { |
1110 | if (idx_value & (R300_HIZ_ENABLE | | |
1111 | R300_RD_COMP_ENABLE | | |
1112 | R300_WR_COMP_ENABLE | | |
1113 | R300_FAST_FILL_ENABLE)) | |
1114 | goto fail; | |
1115 | } | |
46c64d4b MO |
1116 | break; |
1117 | case 0x4e04: | |
1118 | /* RB3D_BLENDCNTL */ | |
1119 | track->blend_read_enable = !!(idx_value & (1 << 2)); | |
40b4a759 | 1120 | track->cb_dirty = true; |
46c64d4b | 1121 | break; |
fff1ce4d | 1122 | case R300_RB3D_AARESOLVE_OFFSET: |
012e976d | 1123 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
fff1ce4d MO |
1124 | if (r) { |
1125 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1126 | idx, reg); | |
c3ad63af | 1127 | radeon_cs_dump_packet(p, pkt); |
fff1ce4d MO |
1128 | return r; |
1129 | } | |
1130 | track->aa.robj = reloc->robj; | |
1131 | track->aa.offset = idx_value; | |
1132 | track->aa_dirty = true; | |
df0af440 | 1133 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
fff1ce4d MO |
1134 | break; |
1135 | case R300_RB3D_AARESOLVE_PITCH: | |
1136 | track->aa.pitch = idx_value & 0x3FFE; | |
1137 | track->aa_dirty = true; | |
1138 | break; | |
1139 | case R300_RB3D_AARESOLVE_CTL: | |
1140 | track->aaresolve = idx_value & 0x1; | |
1141 | track->aa_dirty = true; | |
1142 | break; | |
ab9e1f59 DA |
1143 | case 0x4f30: /* ZB_MASK_OFFSET */ |
1144 | case 0x4f34: /* ZB_ZMASK_PITCH */ | |
1145 | case 0x4f44: /* ZB_HIZ_OFFSET */ | |
1146 | case 0x4f54: /* ZB_HIZ_PITCH */ | |
1147 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | |
1148 | goto fail; | |
1149 | break; | |
1150 | case 0x4028: | |
1151 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | |
1152 | goto fail; | |
1153 | /* GB_Z_PEQ_CONFIG */ | |
1154 | if (p->rdev->family >= CHIP_RV350) | |
1155 | break; | |
1156 | goto fail; | |
1157 | break; | |
3f8befec DA |
1158 | case 0x4be8: |
1159 | /* valid register only on RV530 */ | |
1160 | if (p->rdev->family == CHIP_RV530) | |
1161 | break; | |
1162 | /* fallthrough do not move */ | |
771fe6b9 | 1163 | default: |
cae94b0a | 1164 | goto fail; |
771fe6b9 JG |
1165 | } |
1166 | return 0; | |
cae94b0a | 1167 | fail: |
ab9e1f59 DA |
1168 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", |
1169 | reg, idx, idx_value); | |
cae94b0a | 1170 | return -EINVAL; |
771fe6b9 JG |
1171 | } |
1172 | ||
1173 | static int r300_packet3_check(struct radeon_cs_parser *p, | |
1174 | struct radeon_cs_packet *pkt) | |
1175 | { | |
1d0c0942 | 1176 | struct radeon_bo_list *reloc; |
551ebd83 | 1177 | struct r100_cs_track *track; |
771fe6b9 JG |
1178 | volatile uint32_t *ib; |
1179 | unsigned idx; | |
771fe6b9 JG |
1180 | int r; |
1181 | ||
f2e39221 | 1182 | ib = p->ib.ptr; |
771fe6b9 | 1183 | idx = pkt->idx + 1; |
551ebd83 | 1184 | track = (struct r100_cs_track *)p->track; |
068a117c | 1185 | switch(pkt->opcode) { |
771fe6b9 | 1186 | case PACKET3_3D_LOAD_VBPNTR: |
513bcb46 DA |
1187 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1188 | if (r) | |
1189 | return r; | |
771fe6b9 JG |
1190 | break; |
1191 | case PACKET3_INDX_BUFFER: | |
012e976d | 1192 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
1193 | if (r) { |
1194 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
c3ad63af | 1195 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
1196 | return r; |
1197 | } | |
df0af440 | 1198 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
068a117c JG |
1199 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1200 | if (r) { | |
1201 | return r; | |
1202 | } | |
771fe6b9 JG |
1203 | break; |
1204 | /* Draw packet */ | |
771fe6b9 | 1205 | case PACKET3_3D_DRAW_IMMD: |
068a117c JG |
1206 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1207 | * PRIM_WALK must be equal to 3 vertex data in embedded | |
1208 | * in cmd stream */ | |
513bcb46 | 1209 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
068a117c JG |
1210 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1211 | return -EINVAL; | |
1212 | } | |
513bcb46 | 1213 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
068a117c | 1214 | track->immd_dwords = pkt->count - 1; |
551ebd83 | 1215 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1216 | if (r) { |
1217 | return r; | |
1218 | } | |
1219 | break; | |
771fe6b9 | 1220 | case PACKET3_3D_DRAW_IMMD_2: |
068a117c JG |
1221 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1222 | * PRIM_WALK must be equal to 3 vertex data in embedded | |
1223 | * in cmd stream */ | |
513bcb46 | 1224 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
068a117c JG |
1225 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1226 | return -EINVAL; | |
1227 | } | |
513bcb46 | 1228 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
068a117c | 1229 | track->immd_dwords = pkt->count; |
551ebd83 | 1230 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1231 | if (r) { |
1232 | return r; | |
1233 | } | |
1234 | break; | |
1235 | case PACKET3_3D_DRAW_VBUF: | |
513bcb46 | 1236 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 | 1237 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1238 | if (r) { |
1239 | return r; | |
1240 | } | |
1241 | break; | |
1242 | case PACKET3_3D_DRAW_VBUF_2: | |
513bcb46 | 1243 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 | 1244 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1245 | if (r) { |
1246 | return r; | |
1247 | } | |
1248 | break; | |
1249 | case PACKET3_3D_DRAW_INDX: | |
513bcb46 | 1250 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 | 1251 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1252 | if (r) { |
1253 | return r; | |
1254 | } | |
1255 | break; | |
771fe6b9 | 1256 | case PACKET3_3D_DRAW_INDX_2: |
513bcb46 | 1257 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 | 1258 | r = r100_cs_track_check(p->rdev, track); |
771fe6b9 JG |
1259 | if (r) { |
1260 | return r; | |
1261 | } | |
1262 | break; | |
ab9e1f59 DA |
1263 | case PACKET3_3D_CLEAR_HIZ: |
1264 | case PACKET3_3D_CLEAR_ZMASK: | |
1265 | if (p->rdev->hyperz_filp != p->filp) | |
1266 | return -EINVAL; | |
1267 | break; | |
9eba4a93 MO |
1268 | case PACKET3_3D_CLEAR_CMASK: |
1269 | if (p->rdev->cmask_filp != p->filp) | |
1270 | return -EINVAL; | |
1271 | break; | |
771fe6b9 JG |
1272 | case PACKET3_NOP: |
1273 | break; | |
1274 | default: | |
1275 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
1276 | return -EINVAL; | |
1277 | } | |
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | int r300_cs_parse(struct radeon_cs_parser *p) | |
1282 | { | |
1283 | struct radeon_cs_packet pkt; | |
9f022ddf | 1284 | struct r100_cs_track *track; |
771fe6b9 JG |
1285 | int r; |
1286 | ||
9f022ddf | 1287 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
bbb642f9 KV |
1288 | if (track == NULL) |
1289 | return -ENOMEM; | |
9f022ddf JG |
1290 | r100_cs_track_clear(p->rdev, track); |
1291 | p->track = track; | |
771fe6b9 | 1292 | do { |
c38f34b5 | 1293 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
771fe6b9 JG |
1294 | if (r) { |
1295 | return r; | |
1296 | } | |
1297 | p->idx += pkt.count + 2; | |
1298 | switch (pkt.type) { | |
4e872ae2 | 1299 | case RADEON_PACKET_TYPE0: |
771fe6b9 | 1300 | r = r100_cs_parse_packet0(p, &pkt, |
068a117c JG |
1301 | p->rdev->config.r300.reg_safe_bm, |
1302 | p->rdev->config.r300.reg_safe_bm_size, | |
771fe6b9 JG |
1303 | &r300_packet0_check); |
1304 | break; | |
4e872ae2 | 1305 | case RADEON_PACKET_TYPE2: |
771fe6b9 | 1306 | break; |
4e872ae2 | 1307 | case RADEON_PACKET_TYPE3: |
771fe6b9 JG |
1308 | r = r300_packet3_check(p, &pkt); |
1309 | break; | |
1310 | default: | |
1311 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); | |
1312 | return -EINVAL; | |
1313 | } | |
1314 | if (r) { | |
1315 | return r; | |
1316 | } | |
6d2d13dd | 1317 | } while (p->idx < p->chunk_ib->length_dw); |
771fe6b9 JG |
1318 | return 0; |
1319 | } | |
068a117c | 1320 | |
9f022ddf | 1321 | void r300_set_reg_safe(struct radeon_device *rdev) |
068a117c JG |
1322 | { |
1323 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; | |
1324 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); | |
9f022ddf JG |
1325 | } |
1326 | ||
9f022ddf JG |
1327 | void r300_mc_program(struct radeon_device *rdev) |
1328 | { | |
1329 | struct r100_mc_save save; | |
1330 | int r; | |
1331 | ||
1332 | r = r100_debugfs_mc_info_init(rdev); | |
1333 | if (r) { | |
1334 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); | |
1335 | } | |
1336 | ||
1337 | /* Stops all mc clients */ | |
1338 | r100_mc_stop(rdev, &save); | |
9f022ddf JG |
1339 | if (rdev->flags & RADEON_IS_AGP) { |
1340 | WREG32(R_00014C_MC_AGP_LOCATION, | |
1341 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
1342 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
1343 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
1344 | WREG32(R_00015C_AGP_BASE_2, | |
1345 | upper_32_bits(rdev->mc.agp_base) & 0xff); | |
1346 | } else { | |
1347 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); | |
1348 | WREG32(R_000170_AGP_BASE, 0); | |
1349 | WREG32(R_00015C_AGP_BASE_2, 0); | |
1350 | } | |
1351 | /* Wait for mc idle */ | |
1352 | if (r300_mc_wait_for_idle(rdev)) | |
1353 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); | |
1354 | /* Program MC, should be a 32bits limited address space */ | |
1355 | WREG32(R_000148_MC_FB_LOCATION, | |
1356 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | | |
1357 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
1358 | r100_mc_resume(rdev, &save); | |
1359 | } | |
ca6ffc64 JG |
1360 | |
1361 | void r300_clock_startup(struct radeon_device *rdev) | |
1362 | { | |
1363 | u32 tmp; | |
1364 | ||
1365 | if (radeon_dynclks != -1 && radeon_dynclks) | |
1366 | radeon_legacy_set_clock_gating(rdev, 1); | |
1367 | /* We need to force on some of the block */ | |
1368 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | |
1369 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
1370 | if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) | |
1371 | tmp |= S_00000D_FORCE_VAP(1); | |
1372 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | |
1373 | } | |
207bf9e9 JG |
1374 | |
1375 | static int r300_startup(struct radeon_device *rdev) | |
1376 | { | |
1377 | int r; | |
1378 | ||
92cde00c AD |
1379 | /* set common regs */ |
1380 | r100_set_common_regs(rdev); | |
1381 | /* program mc */ | |
207bf9e9 JG |
1382 | r300_mc_program(rdev); |
1383 | /* Resume clock */ | |
1384 | r300_clock_startup(rdev); | |
1385 | /* Initialize GPU configuration (# pipes, ...) */ | |
1386 | r300_gpu_init(rdev); | |
1387 | /* Initialize GART (initialize after TTM so we can allocate | |
1388 | * memory through TTM but finalize after TTM) */ | |
1389 | if (rdev->flags & RADEON_IS_PCIE) { | |
1390 | r = rv370_pcie_gart_enable(rdev); | |
1391 | if (r) | |
1392 | return r; | |
1393 | } | |
17e15b0c DA |
1394 | |
1395 | if (rdev->family == CHIP_R300 || | |
1396 | rdev->family == CHIP_R350 || | |
1397 | rdev->family == CHIP_RV350) | |
1398 | r100_enable_bm(rdev); | |
1399 | ||
207bf9e9 JG |
1400 | if (rdev->flags & RADEON_IS_PCI) { |
1401 | r = r100_pci_gart_enable(rdev); | |
1402 | if (r) | |
1403 | return r; | |
1404 | } | |
724c80e1 AD |
1405 | |
1406 | /* allocate wb buffer */ | |
1407 | r = radeon_wb_init(rdev); | |
1408 | if (r) | |
1409 | return r; | |
1410 | ||
30eb77f4 JG |
1411 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
1412 | if (r) { | |
1413 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
1414 | return r; | |
1415 | } | |
1416 | ||
207bf9e9 | 1417 | /* Enable IRQ */ |
e49f3959 AH |
1418 | if (!rdev->irq.installed) { |
1419 | r = radeon_irq_kms_init(rdev); | |
1420 | if (r) | |
1421 | return r; | |
1422 | } | |
1423 | ||
207bf9e9 | 1424 | r100_irq_set(rdev); |
cafe6609 | 1425 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
207bf9e9 JG |
1426 | /* 1M ring buffer */ |
1427 | r = r100_cp_init(rdev, 1024 * 1024); | |
1428 | if (r) { | |
ec4f2ac4 | 1429 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
207bf9e9 JG |
1430 | return r; |
1431 | } | |
b15ba512 | 1432 | |
2898c348 CK |
1433 | r = radeon_ib_pool_init(rdev); |
1434 | if (r) { | |
1435 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 1436 | return r; |
2898c348 | 1437 | } |
b15ba512 | 1438 | |
207bf9e9 JG |
1439 | return 0; |
1440 | } | |
1441 | ||
1442 | int r300_resume(struct radeon_device *rdev) | |
1443 | { | |
6b7746e8 JG |
1444 | int r; |
1445 | ||
207bf9e9 JG |
1446 | /* Make sur GART are not working */ |
1447 | if (rdev->flags & RADEON_IS_PCIE) | |
1448 | rv370_pcie_gart_disable(rdev); | |
1449 | if (rdev->flags & RADEON_IS_PCI) | |
1450 | r100_pci_gart_disable(rdev); | |
1451 | /* Resume clock before doing reset */ | |
1452 | r300_clock_startup(rdev); | |
1453 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1454 | if (radeon_asic_reset(rdev)) { |
207bf9e9 JG |
1455 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1456 | RREG32(R_000E40_RBBM_STATUS), | |
1457 | RREG32(R_0007C0_CP_STAT)); | |
1458 | } | |
1459 | /* post */ | |
1460 | radeon_combios_asic_init(rdev->ddev); | |
1461 | /* Resume clock after posting */ | |
1462 | r300_clock_startup(rdev); | |
550e2d92 DA |
1463 | /* Initialize surface registers */ |
1464 | radeon_surface_init(rdev); | |
b15ba512 JG |
1465 | |
1466 | rdev->accel_working = true; | |
6b7746e8 JG |
1467 | r = r300_startup(rdev); |
1468 | if (r) { | |
1469 | rdev->accel_working = false; | |
1470 | } | |
1471 | return r; | |
207bf9e9 JG |
1472 | } |
1473 | ||
1474 | int r300_suspend(struct radeon_device *rdev) | |
1475 | { | |
6c7bccea | 1476 | radeon_pm_suspend(rdev); |
207bf9e9 | 1477 | r100_cp_disable(rdev); |
724c80e1 | 1478 | radeon_wb_disable(rdev); |
207bf9e9 JG |
1479 | r100_irq_disable(rdev); |
1480 | if (rdev->flags & RADEON_IS_PCIE) | |
1481 | rv370_pcie_gart_disable(rdev); | |
1482 | if (rdev->flags & RADEON_IS_PCI) | |
1483 | r100_pci_gart_disable(rdev); | |
1484 | return 0; | |
1485 | } | |
1486 | ||
1487 | void r300_fini(struct radeon_device *rdev) | |
1488 | { | |
6c7bccea | 1489 | radeon_pm_fini(rdev); |
207bf9e9 | 1490 | r100_cp_fini(rdev); |
724c80e1 | 1491 | radeon_wb_fini(rdev); |
2898c348 | 1492 | radeon_ib_pool_fini(rdev); |
207bf9e9 JG |
1493 | radeon_gem_fini(rdev); |
1494 | if (rdev->flags & RADEON_IS_PCIE) | |
1495 | rv370_pcie_gart_fini(rdev); | |
1496 | if (rdev->flags & RADEON_IS_PCI) | |
1497 | r100_pci_gart_fini(rdev); | |
d0269ed8 | 1498 | radeon_agp_fini(rdev); |
207bf9e9 JG |
1499 | radeon_irq_kms_fini(rdev); |
1500 | radeon_fence_driver_fini(rdev); | |
4c788679 | 1501 | radeon_bo_fini(rdev); |
207bf9e9 JG |
1502 | radeon_atombios_fini(rdev); |
1503 | kfree(rdev->bios); | |
1504 | rdev->bios = NULL; | |
1505 | } | |
1506 | ||
1507 | int r300_init(struct radeon_device *rdev) | |
1508 | { | |
1509 | int r; | |
1510 | ||
207bf9e9 JG |
1511 | /* Disable VGA */ |
1512 | r100_vga_render_disable(rdev); | |
1513 | /* Initialize scratch registers */ | |
1514 | radeon_scratch_init(rdev); | |
1515 | /* Initialize surface registers */ | |
1516 | radeon_surface_init(rdev); | |
1517 | /* TODO: disable VGA need to use VGA request */ | |
4c712e6c DA |
1518 | /* restore some register to sane defaults */ |
1519 | r100_restore_sanity(rdev); | |
207bf9e9 JG |
1520 | /* BIOS*/ |
1521 | if (!radeon_get_bios(rdev)) { | |
1522 | if (ASIC_IS_AVIVO(rdev)) | |
1523 | return -EINVAL; | |
1524 | } | |
1525 | if (rdev->is_atom_bios) { | |
1526 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); | |
1527 | return -EINVAL; | |
1528 | } else { | |
1529 | r = radeon_combios_init(rdev); | |
1530 | if (r) | |
1531 | return r; | |
1532 | } | |
1533 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1534 | if (radeon_asic_reset(rdev)) { |
207bf9e9 JG |
1535 | dev_warn(rdev->dev, |
1536 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
1537 | RREG32(R_000E40_RBBM_STATUS), | |
1538 | RREG32(R_0007C0_CP_STAT)); | |
1539 | } | |
1540 | /* check if cards are posted or not */ | |
72542d77 DA |
1541 | if (radeon_boot_test_post_card(rdev) == false) |
1542 | return -EINVAL; | |
207bf9e9 JG |
1543 | /* Set asic errata */ |
1544 | r300_errata(rdev); | |
1545 | /* Initialize clocks */ | |
1546 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
1547 | /* initialize AGP */ |
1548 | if (rdev->flags & RADEON_IS_AGP) { | |
1549 | r = radeon_agp_init(rdev); | |
1550 | if (r) { | |
1551 | radeon_agp_disable(rdev); | |
1552 | } | |
1553 | } | |
1554 | /* initialize memory controller */ | |
1555 | r300_mc_init(rdev); | |
207bf9e9 | 1556 | /* Fence driver */ |
30eb77f4 | 1557 | r = radeon_fence_driver_init(rdev); |
207bf9e9 JG |
1558 | if (r) |
1559 | return r; | |
1560 | /* Memory manager */ | |
4c788679 | 1561 | r = radeon_bo_init(rdev); |
207bf9e9 JG |
1562 | if (r) |
1563 | return r; | |
1564 | if (rdev->flags & RADEON_IS_PCIE) { | |
1565 | r = rv370_pcie_gart_init(rdev); | |
1566 | if (r) | |
1567 | return r; | |
1568 | } | |
1569 | if (rdev->flags & RADEON_IS_PCI) { | |
1570 | r = r100_pci_gart_init(rdev); | |
1571 | if (r) | |
1572 | return r; | |
1573 | } | |
1574 | r300_set_reg_safe(rdev); | |
b15ba512 | 1575 | |
6c7bccea AD |
1576 | /* Initialize power management */ |
1577 | radeon_pm_init(rdev); | |
1578 | ||
207bf9e9 JG |
1579 | rdev->accel_working = true; |
1580 | r = r300_startup(rdev); | |
1581 | if (r) { | |
0dc5d4f7 | 1582 | /* Something went wrong with the accel init, so stop accel */ |
207bf9e9 | 1583 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
207bf9e9 | 1584 | r100_cp_fini(rdev); |
724c80e1 | 1585 | radeon_wb_fini(rdev); |
2898c348 | 1586 | radeon_ib_pool_fini(rdev); |
655efd3d | 1587 | radeon_irq_kms_fini(rdev); |
207bf9e9 JG |
1588 | if (rdev->flags & RADEON_IS_PCIE) |
1589 | rv370_pcie_gart_fini(rdev); | |
1590 | if (rdev->flags & RADEON_IS_PCI) | |
1591 | r100_pci_gart_fini(rdev); | |
655efd3d | 1592 | radeon_agp_fini(rdev); |
207bf9e9 JG |
1593 | rdev->accel_working = false; |
1594 | } | |
1595 | return 0; | |
1596 | } |