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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include "drmP.h" |
31 | #include "radeon_reg.h" | |
32 | #include "radeon.h" | |
9f022ddf | 33 | #include "atom.h" |
62cdc0c2 | 34 | #include "r100d.h" |
905b6822 | 35 | #include "r420d.h" |
804c7559 AD |
36 | #include "r420_reg_safe.h" |
37 | ||
38 | static void r420_set_reg_safe(struct radeon_device *rdev) | |
39 | { | |
40 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; | |
41 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); | |
42 | } | |
771fe6b9 | 43 | |
771fe6b9 JG |
44 | void r420_pipes_init(struct radeon_device *rdev) |
45 | { | |
46 | unsigned tmp; | |
47 | unsigned gb_pipe_select; | |
48 | unsigned num_pipes; | |
49 | ||
50 | /* GA_ENHANCE workaround TCL deadlock issue */ | |
4612dc97 AD |
51 | WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | |
52 | (1 << 2) | (1 << 3)); | |
18a4cd2e DA |
53 | /* add idle wait as per freedesktop.org bug 24041 */ |
54 | if (r100_gui_wait_for_idle(rdev)) { | |
55 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
56 | "programming pipes. Bad things might happen.\n"); | |
57 | } | |
771fe6b9 JG |
58 | /* get max number of pipes */ |
59 | gb_pipe_select = RREG32(0x402C); | |
60 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; | |
61 | rdev->num_gb_pipes = num_pipes; | |
62 | tmp = 0; | |
63 | switch (num_pipes) { | |
64 | default: | |
65 | /* force to 1 pipe */ | |
66 | num_pipes = 1; | |
67 | case 1: | |
68 | tmp = (0 << 1); | |
69 | break; | |
70 | case 2: | |
71 | tmp = (3 << 1); | |
72 | break; | |
73 | case 3: | |
74 | tmp = (6 << 1); | |
75 | break; | |
76 | case 4: | |
77 | tmp = (7 << 1); | |
78 | break; | |
79 | } | |
4612dc97 | 80 | WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); |
771fe6b9 | 81 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
4612dc97 AD |
82 | tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; |
83 | WREG32(R300_GB_TILE_CONFIG, tmp); | |
771fe6b9 JG |
84 | if (r100_gui_wait_for_idle(rdev)) { |
85 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
86 | "programming pipes. Bad things might happen.\n"); | |
87 | } | |
88 | ||
4612dc97 AD |
89 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
90 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); | |
771fe6b9 JG |
91 | |
92 | WREG32(R300_RB2D_DSTCACHE_MODE, | |
93 | RREG32(R300_RB2D_DSTCACHE_MODE) | | |
94 | R300_DC_AUTOFLUSH_ENABLE | | |
95 | R300_DC_DC_DISABLE_IGNORE_PE); | |
96 | ||
97 | if (r100_gui_wait_for_idle(rdev)) { | |
98 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
99 | "programming pipes. Bad things might happen.\n"); | |
100 | } | |
f779b3e5 AD |
101 | |
102 | if (rdev->family == CHIP_RV530) { | |
103 | tmp = RREG32(RV530_GB_PIPE_SELECT2); | |
104 | if ((tmp & 3) == 3) | |
105 | rdev->num_z_pipes = 2; | |
106 | else | |
107 | rdev->num_z_pipes = 1; | |
108 | } else | |
109 | rdev->num_z_pipes = 1; | |
110 | ||
111 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", | |
112 | rdev->num_gb_pipes, rdev->num_z_pipes); | |
771fe6b9 JG |
113 | } |
114 | ||
9f022ddf | 115 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
771fe6b9 | 116 | { |
9f022ddf JG |
117 | u32 r; |
118 | ||
119 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); | |
120 | r = RREG32(R_0001FC_MC_IND_DATA); | |
121 | return r; | |
122 | } | |
123 | ||
124 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
125 | { | |
126 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | | |
127 | S_0001F8_MC_IND_WR_EN(1)); | |
128 | WREG32(R_0001FC_MC_IND_DATA, v); | |
129 | } | |
130 | ||
131 | static void r420_debugfs(struct radeon_device *rdev) | |
132 | { | |
133 | if (r100_debugfs_rbbm_init(rdev)) { | |
134 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
135 | } | |
136 | if (r420_debugfs_pipes_info_init(rdev)) { | |
137 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
138 | } | |
139 | } | |
140 | ||
141 | static void r420_clock_resume(struct radeon_device *rdev) | |
142 | { | |
143 | u32 sclk_cntl; | |
ca6ffc64 JG |
144 | |
145 | if (radeon_dynclks != -1 && radeon_dynclks) | |
146 | radeon_atom_set_clock_gating(rdev, 1); | |
9f022ddf JG |
147 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
148 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
149 | if (rdev->family == CHIP_R420) | |
150 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); | |
151 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); | |
152 | } | |
153 | ||
62cdc0c2 CS |
154 | static void r420_cp_errata_init(struct radeon_device *rdev) |
155 | { | |
156 | /* RV410 and R420 can lock up if CP DMA to host memory happens | |
157 | * while the 2D engine is busy. | |
158 | * | |
159 | * The proper workaround is to queue a RESYNC at the beginning | |
160 | * of the CP init, apparently. | |
161 | */ | |
162 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); | |
163 | radeon_ring_lock(rdev, 8); | |
164 | radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1)); | |
165 | radeon_ring_write(rdev, rdev->config.r300.resync_scratch); | |
166 | radeon_ring_write(rdev, 0xDEADBEEF); | |
167 | radeon_ring_unlock_commit(rdev); | |
168 | } | |
169 | ||
170 | static void r420_cp_errata_fini(struct radeon_device *rdev) | |
171 | { | |
172 | /* Catch the RESYNC we dispatched all the way back, | |
173 | * at the very beginning of the CP init. | |
174 | */ | |
175 | radeon_ring_lock(rdev, 8); | |
176 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
177 | radeon_ring_write(rdev, R300_RB3D_DC_FINISH); | |
178 | radeon_ring_unlock_commit(rdev); | |
179 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); | |
180 | } | |
181 | ||
fc30b8ef | 182 | static int r420_startup(struct radeon_device *rdev) |
9f022ddf JG |
183 | { |
184 | int r; | |
185 | ||
92cde00c AD |
186 | /* set common regs */ |
187 | r100_set_common_regs(rdev); | |
188 | /* program mc */ | |
9f022ddf | 189 | r300_mc_program(rdev); |
ca6ffc64 JG |
190 | /* Resume clock */ |
191 | r420_clock_resume(rdev); | |
9f022ddf JG |
192 | /* Initialize GART (initialize after TTM so we can allocate |
193 | * memory through TTM but finalize after TTM) */ | |
4aac0473 JG |
194 | if (rdev->flags & RADEON_IS_PCIE) { |
195 | r = rv370_pcie_gart_enable(rdev); | |
196 | if (r) | |
197 | return r; | |
198 | } | |
199 | if (rdev->flags & RADEON_IS_PCI) { | |
200 | r = r100_pci_gart_enable(rdev); | |
201 | if (r) | |
202 | return r; | |
9f022ddf | 203 | } |
771fe6b9 | 204 | r420_pipes_init(rdev); |
9f022ddf | 205 | /* Enable IRQ */ |
9f022ddf | 206 | r100_irq_set(rdev); |
cafe6609 | 207 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
9f022ddf JG |
208 | /* 1M ring buffer */ |
209 | r = r100_cp_init(rdev, 1024 * 1024); | |
210 | if (r) { | |
211 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
212 | return r; | |
213 | } | |
62cdc0c2 | 214 | r420_cp_errata_init(rdev); |
9f022ddf JG |
215 | r = r100_wb_init(rdev); |
216 | if (r) { | |
217 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
771fe6b9 | 218 | } |
9f022ddf JG |
219 | r = r100_ib_init(rdev); |
220 | if (r) { | |
221 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
222 | return r; | |
223 | } | |
224 | return 0; | |
771fe6b9 JG |
225 | } |
226 | ||
fc30b8ef DA |
227 | int r420_resume(struct radeon_device *rdev) |
228 | { | |
229 | /* Make sur GART are not working */ | |
230 | if (rdev->flags & RADEON_IS_PCIE) | |
231 | rv370_pcie_gart_disable(rdev); | |
232 | if (rdev->flags & RADEON_IS_PCI) | |
233 | r100_pci_gart_disable(rdev); | |
234 | /* Resume clock before doing reset */ | |
235 | r420_clock_resume(rdev); | |
236 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
237 | if (radeon_gpu_reset(rdev)) { | |
238 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
239 | RREG32(R_000E40_RBBM_STATUS), | |
240 | RREG32(R_0007C0_CP_STAT)); | |
241 | } | |
242 | /* check if cards are posted or not */ | |
243 | if (rdev->is_atom_bios) { | |
244 | atom_asic_init(rdev->mode_info.atom_context); | |
245 | } else { | |
246 | radeon_combios_asic_init(rdev->ddev); | |
247 | } | |
248 | /* Resume clock after posting */ | |
249 | r420_clock_resume(rdev); | |
550e2d92 DA |
250 | /* Initialize surface registers */ |
251 | radeon_surface_init(rdev); | |
fc30b8ef DA |
252 | return r420_startup(rdev); |
253 | } | |
254 | ||
9f022ddf JG |
255 | int r420_suspend(struct radeon_device *rdev) |
256 | { | |
62cdc0c2 | 257 | r420_cp_errata_fini(rdev); |
9f022ddf JG |
258 | r100_cp_disable(rdev); |
259 | r100_wb_disable(rdev); | |
260 | r100_irq_disable(rdev); | |
4aac0473 JG |
261 | if (rdev->flags & RADEON_IS_PCIE) |
262 | rv370_pcie_gart_disable(rdev); | |
263 | if (rdev->flags & RADEON_IS_PCI) | |
264 | r100_pci_gart_disable(rdev); | |
9f022ddf JG |
265 | return 0; |
266 | } | |
771fe6b9 | 267 | |
9f022ddf | 268 | void r420_fini(struct radeon_device *rdev) |
771fe6b9 | 269 | { |
9f022ddf JG |
270 | r100_cp_fini(rdev); |
271 | r100_wb_fini(rdev); | |
272 | r100_ib_fini(rdev); | |
273 | radeon_gem_fini(rdev); | |
4aac0473 JG |
274 | if (rdev->flags & RADEON_IS_PCIE) |
275 | rv370_pcie_gart_fini(rdev); | |
276 | if (rdev->flags & RADEON_IS_PCI) | |
277 | r100_pci_gart_fini(rdev); | |
9f022ddf JG |
278 | radeon_agp_fini(rdev); |
279 | radeon_irq_kms_fini(rdev); | |
280 | radeon_fence_driver_fini(rdev); | |
4c788679 | 281 | radeon_bo_fini(rdev); |
9f022ddf JG |
282 | if (rdev->is_atom_bios) { |
283 | radeon_atombios_fini(rdev); | |
284 | } else { | |
285 | radeon_combios_fini(rdev); | |
286 | } | |
287 | kfree(rdev->bios); | |
288 | rdev->bios = NULL; | |
771fe6b9 JG |
289 | } |
290 | ||
9f022ddf JG |
291 | int r420_init(struct radeon_device *rdev) |
292 | { | |
293 | int r; | |
294 | ||
9f022ddf JG |
295 | /* Initialize scratch registers */ |
296 | radeon_scratch_init(rdev); | |
297 | /* Initialize surface registers */ | |
298 | radeon_surface_init(rdev); | |
299 | /* TODO: disable VGA need to use VGA request */ | |
300 | /* BIOS*/ | |
301 | if (!radeon_get_bios(rdev)) { | |
302 | if (ASIC_IS_AVIVO(rdev)) | |
303 | return -EINVAL; | |
304 | } | |
305 | if (rdev->is_atom_bios) { | |
306 | r = radeon_atombios_init(rdev); | |
307 | if (r) { | |
308 | return r; | |
309 | } | |
310 | } else { | |
311 | r = radeon_combios_init(rdev); | |
312 | if (r) { | |
313 | return r; | |
314 | } | |
315 | } | |
316 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
317 | if (radeon_gpu_reset(rdev)) { | |
318 | dev_warn(rdev->dev, | |
319 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
320 | RREG32(R_000E40_RBBM_STATUS), | |
321 | RREG32(R_0007C0_CP_STAT)); | |
322 | } | |
323 | /* check if cards are posted or not */ | |
72542d77 DA |
324 | if (radeon_boot_test_post_card(rdev) == false) |
325 | return -EINVAL; | |
326 | ||
9f022ddf JG |
327 | /* Initialize clocks */ |
328 | radeon_get_clock_info(rdev->ddev); | |
7433874e RM |
329 | /* Initialize power management */ |
330 | radeon_pm_init(rdev); | |
d594e46a JG |
331 | /* initialize AGP */ |
332 | if (rdev->flags & RADEON_IS_AGP) { | |
333 | r = radeon_agp_init(rdev); | |
334 | if (r) { | |
335 | radeon_agp_disable(rdev); | |
336 | } | |
9f022ddf | 337 | } |
d594e46a JG |
338 | /* initialize memory controller */ |
339 | r300_mc_init(rdev); | |
9f022ddf JG |
340 | r420_debugfs(rdev); |
341 | /* Fence driver */ | |
342 | r = radeon_fence_driver_init(rdev); | |
343 | if (r) { | |
344 | return r; | |
345 | } | |
346 | r = radeon_irq_kms_init(rdev); | |
347 | if (r) { | |
348 | return r; | |
349 | } | |
350 | /* Memory manager */ | |
4c788679 | 351 | r = radeon_bo_init(rdev); |
9f022ddf JG |
352 | if (r) { |
353 | return r; | |
354 | } | |
17e15b0c DA |
355 | if (rdev->family == CHIP_R420) |
356 | r100_enable_bm(rdev); | |
357 | ||
4aac0473 JG |
358 | if (rdev->flags & RADEON_IS_PCIE) { |
359 | r = rv370_pcie_gart_init(rdev); | |
360 | if (r) | |
361 | return r; | |
362 | } | |
363 | if (rdev->flags & RADEON_IS_PCI) { | |
364 | r = r100_pci_gart_init(rdev); | |
365 | if (r) | |
366 | return r; | |
367 | } | |
804c7559 | 368 | r420_set_reg_safe(rdev); |
733289c2 | 369 | rdev->accel_working = true; |
fc30b8ef | 370 | r = r420_startup(rdev); |
9f022ddf JG |
371 | if (r) { |
372 | /* Somethings want wront with the accel init stop accel */ | |
373 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
9f022ddf JG |
374 | r100_cp_fini(rdev); |
375 | r100_wb_fini(rdev); | |
376 | r100_ib_fini(rdev); | |
655efd3d | 377 | radeon_irq_kms_fini(rdev); |
4aac0473 JG |
378 | if (rdev->flags & RADEON_IS_PCIE) |
379 | rv370_pcie_gart_fini(rdev); | |
380 | if (rdev->flags & RADEON_IS_PCI) | |
381 | r100_pci_gart_fini(rdev); | |
9f022ddf | 382 | radeon_agp_fini(rdev); |
733289c2 | 383 | rdev->accel_working = false; |
9f022ddf JG |
384 | } |
385 | return 0; | |
386 | } | |
771fe6b9 JG |
387 | |
388 | /* | |
389 | * Debugfs info | |
390 | */ | |
391 | #if defined(CONFIG_DEBUG_FS) | |
392 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) | |
393 | { | |
394 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
395 | struct drm_device *dev = node->minor->dev; | |
396 | struct radeon_device *rdev = dev->dev_private; | |
397 | uint32_t tmp; | |
398 | ||
399 | tmp = RREG32(R400_GB_PIPE_SELECT); | |
400 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); | |
401 | tmp = RREG32(R300_GB_TILE_CONFIG); | |
402 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); | |
403 | tmp = RREG32(R300_DST_PIPE_CONFIG); | |
404 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static struct drm_info_list r420_pipes_info_list[] = { | |
409 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, | |
410 | }; | |
411 | #endif | |
412 | ||
413 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) | |
414 | { | |
415 | #if defined(CONFIG_DEBUG_FS) | |
416 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); | |
417 | #else | |
418 | return 0; | |
419 | #endif | |
420 | } |