[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / r520.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "r520d.h"

/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */

static int r520_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;
	uint32_t tmp;

	for (i = 0; i < rdev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32_MC(R520_MC_STATUS);
		if (tmp & R520_MC_STATUS_IDLE) {
			return 0;
		}
		DRM_UDELAY(1);
	}
	return -1;
}

static void r520_gpu_init(struct radeon_device *rdev)
{
	unsigned pipe_select_current, gb_pipe_select, tmp;

	r100_hdp_reset(rdev);
	rv515_vga_render_disable(rdev);
	/*
	 * DST_PIPE_CONFIG		0x170C
	 * GB_TILE_CONFIG		0x4018
	 * GB_FIFO_SIZE			0x4024
	 * GB_PIPE_SELECT		0x402C
	 * GB_PIPE_SELECT2              0x4124
	 *	Z_PIPE_SHIFT			0
	 *	Z_PIPE_MASK			0x000000003
	 * GB_FIFO_SIZE2                0x4128
	 *	SC_SFIFO_SIZE_SHIFT		0
	 *	SC_SFIFO_SIZE_MASK		0x000000003
	 *	SC_MFIFO_SIZE_SHIFT		2
	 *	SC_MFIFO_SIZE_MASK		0x00000000C
	 *	FG_SFIFO_SIZE_SHIFT		4
	 *	FG_SFIFO_SIZE_MASK		0x000000030
	 *	ZB_MFIFO_SIZE_SHIFT		6
	 *	ZB_MFIFO_SIZE_MASK		0x0000000C0
	 * GA_ENHANCE			0x4274
	 * SU_REG_DEST			0x42C8
	 */
	/* workaround for RV530 */
	if (rdev->family == CHIP_RV530) {
		WREG32(0x4128, 0xFF);
	}
	r420_pipes_init(rdev);
	gb_pipe_select = RREG32(0x402C);
	tmp = RREG32(0x170C);
	pipe_select_current = (tmp >> 2) & 3;
	tmp = (1 << pipe_select_current) |
	      (((gb_pipe_select >> 8) & 0xF) << 4);
	WREG32_PLL(0x000D, tmp);
	if (r520_mc_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait MC idle while "
		       "programming pipes. Bad things might happen.\n");
	}
}

static void r520_vram_get_type(struct radeon_device *rdev)
{
	uint32_t tmp;

	rdev->mc.vram_width = 128;
	rdev->mc.vram_is_ddr = true;
	tmp = RREG32_MC(R520_MC_CNTL0);
	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
	case 0:
		rdev->mc.vram_width = 32;
		break;
	case 1:
		rdev->mc.vram_width = 64;
		break;
	case 2:
		rdev->mc.vram_width = 128;
		break;
	case 3:
		rdev->mc.vram_width = 256;
		break;
	default:
		rdev->mc.vram_width = 128;
		break;
	}
	if (tmp & R520_MC_CHANNEL_SIZE)
		rdev->mc.vram_width *= 2;
}

void r520_mc_init(struct radeon_device *rdev)
{

	r520_vram_get_type(rdev);
	r100_vram_init_sizes(rdev);
	radeon_vram_location(rdev, &rdev->mc, 0);
	if (!(rdev->flags & RADEON_IS_AGP))
		radeon_gtt_location(rdev, &rdev->mc);
	radeon_update_bandwidth_info(rdev);
}

void r520_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;

	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);

	/* Wait for mc idle */
	if (r520_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
	/* Write VRAM size in case we are limiting it */
	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
	/* Program MC, should be a 32bits limited address space */
	WREG32_MC(R_000004_MC_FB_LOCATION,
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
	if (rdev->flags & RADEON_IS_AGP) {
		WREG32_MC(R_000005_MC_AGP_LOCATION,
			S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
			S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
		WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
		WREG32_MC(R_000007_AGP_BASE_2,
			S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
	} else {
		WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
		WREG32_MC(R_000006_AGP_BASE, 0);
		WREG32_MC(R_000007_AGP_BASE_2, 0);
	}

	rv515_mc_resume(rdev, &save);
}

static int r520_startup(struct radeon_device *rdev)
{
	int r;

	r520_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	r520_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	/* Enable IRQ */
	rs600_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		return r;
	}
	r = r100_wb_init(rdev);
	if (r)
		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	r = r100_ib_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		return r;
	}
	return 0;
}

int r520_resume(struct radeon_device *rdev)
{
	/* Make sur GART are not working */
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_disable(rdev);
	/* Resume clock before doing reset */
	rv515_clock_startup(rdev);
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* post */
	atom_asic_init(rdev->mode_info.atom_context);
	/* Resume clock after posting */
	rv515_clock_startup(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	return r520_startup(rdev);
}

int r520_init(struct radeon_device *rdev)
{
	int r;

	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;

	if (!radeon_card_posted(rdev) && rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		atom_asic_init(rdev->mode_info.atom_context);
	}
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* Initialize power management */
	radeon_pm_init(rdev);
	/* initialize AGP */
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r) {
			radeon_agp_disable(rdev);
		}
	}
	/* initialize memory controller */
	r520_mc_init(rdev);
	rv515_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
		return r;
	r = radeon_irq_kms_init(rdev);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r)
		return r;
	r = rv370_pcie_gart_init(rdev);
	if (r)
		return r;
	rv515_set_safe_registers(rdev);
	rdev->accel_working = true;
	r = r520_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		r100_cp_fini(rdev);
		r100_wb_fini(rdev);
		r100_ib_fini(rdev);
		radeon_irq_kms_fini(rdev);
		rv370_pcie_gart_fini(rdev);
		radeon_agp_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
771fe6b9	29	#include "radeon.h"
e6990375	30	#include "radeon_asic.h"
f0ed1f65 JG	31	#include "atom.h"
f0ed1f65 JG	32	#include "r520d.h"
771fe6b9	33
f0ed1f65	34	/* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
771fe6b9	35
f0ed1f65	36	static int r520_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9 JG	37	{
	38	unsigned i;
	39	uint32_t tmp;
	40
	41	for (i = 0; i < rdev->usec_timeout; i++) {
	42	/* read MC_STATUS */
	43	tmp = RREG32_MC(R520_MC_STATUS);
	44	if (tmp & R520_MC_STATUS_IDLE) {
	45	return 0;
	46	}
	47	DRM_UDELAY(1);
	48	}
	49	return -1;
	50	}
	51
f0ed1f65	52	static void r520_gpu_init(struct radeon_device *rdev)
771fe6b9 JG	53	{
	54	unsigned pipe_select_current, gb_pipe_select, tmp;
	55
	56	r100_hdp_reset(rdev);
d39c3b89	57	rv515_vga_render_disable(rdev);
771fe6b9 JG	58	/*
	59	* DST_PIPE_CONFIG 0x170C
	60	* GB_TILE_CONFIG 0x4018
	61	* GB_FIFO_SIZE 0x4024
	62	* GB_PIPE_SELECT 0x402C
	63	* GB_PIPE_SELECT2 0x4124
	64	* Z_PIPE_SHIFT 0
	65	* Z_PIPE_MASK 0x000000003
	66	* GB_FIFO_SIZE2 0x4128
	67	* SC_SFIFO_SIZE_SHIFT 0
	68	* SC_SFIFO_SIZE_MASK 0x000000003
	69	* SC_MFIFO_SIZE_SHIFT 2
	70	* SC_MFIFO_SIZE_MASK 0x00000000C
	71	* FG_SFIFO_SIZE_SHIFT 4
	72	* FG_SFIFO_SIZE_MASK 0x000000030
	73	* ZB_MFIFO_SIZE_SHIFT 6
	74	* ZB_MFIFO_SIZE_MASK 0x0000000C0
	75	* GA_ENHANCE 0x4274
	76	* SU_REG_DEST 0x42C8
	77	*/
	78	/* workaround for RV530 */
	79	if (rdev->family == CHIP_RV530) {
771fe6b9 JG	80	WREG32(0x4128, 0xFF);
	81	}
	82	r420_pipes_init(rdev);
	83	gb_pipe_select = RREG32(0x402C);
	84	tmp = RREG32(0x170C);
	85	pipe_select_current = (tmp >> 2) & 3;
	86	tmp = (1 << pipe_select_current) \|
	87	(((gb_pipe_select >> 8) & 0xF) << 4);
	88	WREG32_PLL(0x000D, tmp);
	89	if (r520_mc_wait_for_idle(rdev)) {
	90	printk(KERN_WARNING "Failed to wait MC idle while "
	91	"programming pipes. Bad things might happen.\n");
	92	}
	93	}
	94
771fe6b9 JG	95	static void r520_vram_get_type(struct radeon_device *rdev)
	96	{
	97	uint32_t tmp;
	98
	99	rdev->mc.vram_width = 128;
	100	rdev->mc.vram_is_ddr = true;
	101	tmp = RREG32_MC(R520_MC_CNTL0);
	102	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
	103	case 0:
	104	rdev->mc.vram_width = 32;
	105	break;
	106	case 1:
	107	rdev->mc.vram_width = 64;
	108	break;
	109	case 2:
	110	rdev->mc.vram_width = 128;
	111	break;
	112	case 3:
	113	rdev->mc.vram_width = 256;
	114	break;
	115	default:
	116	rdev->mc.vram_width = 128;
	117	break;
	118	}
	119	if (tmp & R520_MC_CHANNEL_SIZE)
	120	rdev->mc.vram_width *= 2;
	121	}
	122
d594e46a	123	void r520_mc_init(struct radeon_device *rdev)
771fe6b9	124	{
c93bb85b	125
771fe6b9	126	r520_vram_get_type(rdev);
2a0f8918	127	r100_vram_init_sizes(rdev);
d594e46a JG	128	radeon_vram_location(rdev, &rdev->mc, 0);
	129	if (!(rdev->flags & RADEON_IS_AGP))
	130	radeon_gtt_location(rdev, &rdev->mc);
f47299c5	131	radeon_update_bandwidth_info(rdev);
c93bb85b JG	132	}
c93bb85b JG	133
f0ed1f65 JG	134	void r520_mc_program(struct radeon_device *rdev)
	135	{
	136	struct rv515_mc_save save;
	137
	138	/* Stops all mc clients */
	139	rv515_mc_stop(rdev, &save);
	140
	141	/* Wait for mc idle */
	142	if (r520_mc_wait_for_idle(rdev))
	143	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
	144	/* Write VRAM size in case we are limiting it */
	145	WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
	146	/* Program MC, should be a 32bits limited address space */
	147	WREG32_MC(R_000004_MC_FB_LOCATION,
	148	S_000004_MC_FB_START(rdev->mc.vram_start >> 16) \|
	149	S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	150	WREG32(R_000134_HDP_FB_LOCATION,
	151	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
	152	if (rdev->flags & RADEON_IS_AGP) {
	153	WREG32_MC(R_000005_MC_AGP_LOCATION,
	154	S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) \|
	155	S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
	156	WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
	157	WREG32_MC(R_000007_AGP_BASE_2,
	158	S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
	159	} else {
	160	WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
	161	WREG32_MC(R_000006_AGP_BASE, 0);
	162	WREG32_MC(R_000007_AGP_BASE_2, 0);
	163	}
	164
	165	rv515_mc_resume(rdev, &save);
	166	}
	167
	168	static int r520_startup(struct radeon_device *rdev)
	169	{
	170	int r;
	171
	172	r520_mc_program(rdev);
	173	/* Resume clock */
	174	rv515_clock_startup(rdev);
	175	/* Initialize GPU configuration (# pipes, ...) */
	176	r520_gpu_init(rdev);
	177	/* Initialize GART (initialize after TTM so we can allocate
	178	* memory through TTM but finalize after TTM) */
	179	if (rdev->flags & RADEON_IS_PCIE) {
	180	r = rv370_pcie_gart_enable(rdev);
	181	if (r)
	182	return r;
	183	}
	184	/* Enable IRQ */
ac447df4	185	rs600_irq_set(rdev);
cafe6609	186	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
f0ed1f65 JG	187	/* 1M ring buffer */
	188	r = r100_cp_init(rdev, 1024 * 1024);
	189	if (r) {
	190	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
	191	return r;
	192	}
	193	r = r100_wb_init(rdev);
	194	if (r)
	195	dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	196	r = r100_ib_init(rdev);
	197	if (r) {
	198	dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
	199	return r;
	200	}
	201	return 0;
	202	}
	203
	204	int r520_resume(struct radeon_device *rdev)
c93bb85b	205	{
f0ed1f65 JG	206	/* Make sur GART are not working */
	207	if (rdev->flags & RADEON_IS_PCIE)
	208	rv370_pcie_gart_disable(rdev);
	209	/* Resume clock before doing reset */
	210	rv515_clock_startup(rdev);
	211	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	212	if (radeon_gpu_reset(rdev)) {
	213	dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	214	RREG32(R_000E40_RBBM_STATUS),
	215	RREG32(R_0007C0_CP_STAT));
	216	}
	217	/* post */
	218	atom_asic_init(rdev->mode_info.atom_context);
	219	/* Resume clock after posting */
	220	rv515_clock_startup(rdev);
550e2d92 DA	221	/* Initialize surface registers */
550e2d92 DA	222	radeon_surface_init(rdev);
f0ed1f65	223	return r520_startup(rdev);
771fe6b9	224	}
d39c3b89 JG	225
	226	int r520_init(struct radeon_device *rdev)
	227	{
f0ed1f65 JG	228	int r;
f0ed1f65 JG	229
f0ed1f65 JG	230	/* Initialize scratch registers */
	231	radeon_scratch_init(rdev);
	232	/* Initialize surface registers */
	233	radeon_surface_init(rdev);
	234	/* TODO: disable VGA need to use VGA request */
	235	/* BIOS*/
	236	if (!radeon_get_bios(rdev)) {
	237	if (ASIC_IS_AVIVO(rdev))
	238	return -EINVAL;
	239	}
	240	if (rdev->is_atom_bios) {
	241	r = radeon_atombios_init(rdev);
	242	if (r)
	243	return r;
	244	} else {
	245	dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
	246	return -EINVAL;
	247	}
	248	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	249	if (radeon_gpu_reset(rdev)) {
	250	dev_warn(rdev->dev,
	251	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	252	RREG32(R_000E40_RBBM_STATUS),
	253	RREG32(R_0007C0_CP_STAT));
	254	}
	255	/* check if cards are posted or not */
72542d77 DA	256	if (radeon_boot_test_post_card(rdev) == false)
	257	return -EINVAL;
	258
f0ed1f65 JG	259	if (!radeon_card_posted(rdev) && rdev->bios) {
	260	DRM_INFO("GPU not posted. posting now...\n");
	261	atom_asic_init(rdev->mode_info.atom_context);
	262	}
	263	/* Initialize clocks */
	264	radeon_get_clock_info(rdev->ddev);
7433874e RM	265	/* Initialize power management */
7433874e RM	266	radeon_pm_init(rdev);
d594e46a JG	267	/* initialize AGP */
	268	if (rdev->flags & RADEON_IS_AGP) {
	269	r = radeon_agp_init(rdev);
	270	if (r) {
	271	radeon_agp_disable(rdev);
	272	}
	273	}
	274	/* initialize memory controller */
	275	r520_mc_init(rdev);
f0ed1f65 JG	276	rv515_debugfs(rdev);
	277	/* Fence driver */
	278	r = radeon_fence_driver_init(rdev);
	279	if (r)
	280	return r;
	281	r = radeon_irq_kms_init(rdev);
	282	if (r)
	283	return r;
	284	/* Memory manager */
4c788679	285	r = radeon_bo_init(rdev);
f0ed1f65 JG	286	if (r)
	287	return r;
	288	r = rv370_pcie_gart_init(rdev);
	289	if (r)
	290	return r;
d39c3b89	291	rv515_set_safe_registers(rdev);
f0ed1f65 JG	292	rdev->accel_working = true;
	293	r = r520_startup(rdev);
	294	if (r) {
	295	/* Somethings want wront with the accel init stop accel */
	296	dev_err(rdev->dev, "Disabling GPU acceleration\n");
f0ed1f65 JG	297	r100_cp_fini(rdev);
	298	r100_wb_fini(rdev);
	299	r100_ib_fini(rdev);
655efd3d	300	radeon_irq_kms_fini(rdev);
f0ed1f65 JG	301	rv370_pcie_gart_fini(rdev);
f0ed1f65 JG	302	radeon_agp_fini(rdev);
f0ed1f65 JG	303	rdev->accel_working = false;
f0ed1f65 JG	304	}
d39c3b89 JG	305	return 0;
d39c3b89 JG	306	}