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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
29 | #include "radeon_reg.h" | |
30 | #include "radeon.h" | |
31 | ||
32 | /* r520,rv530,rv560,rv570,r580 depends on : */ | |
33 | void r100_hdp_reset(struct radeon_device *rdev); | |
34 | int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
35 | void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
36 | void r420_pipes_init(struct radeon_device *rdev); | |
37 | void rs600_mc_disable_clients(struct radeon_device *rdev); | |
38 | void rs600_disable_vga(struct radeon_device *rdev); | |
39 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); | |
40 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); | |
41 | ||
42 | /* This files gather functions specifics to: | |
43 | * r520,rv530,rv560,rv570,r580 | |
44 | * | |
45 | * Some of these functions might be used by newer ASICs. | |
46 | */ | |
47 | void r520_gpu_init(struct radeon_device *rdev); | |
48 | int r520_mc_wait_for_idle(struct radeon_device *rdev); | |
49 | ||
50 | ||
51 | /* | |
52 | * MC | |
53 | */ | |
54 | int r520_mc_init(struct radeon_device *rdev) | |
55 | { | |
56 | uint32_t tmp; | |
57 | int r; | |
58 | ||
59 | if (r100_debugfs_rbbm_init(rdev)) { | |
60 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | |
61 | } | |
62 | if (rv515_debugfs_pipes_info_init(rdev)) { | |
63 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
64 | } | |
65 | if (rv515_debugfs_ga_info_init(rdev)) { | |
66 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | |
67 | } | |
68 | ||
69 | r520_gpu_init(rdev); | |
70 | rv370_pcie_gart_disable(rdev); | |
71 | ||
72 | /* Setup GPU memory space */ | |
73 | rdev->mc.vram_location = 0xFFFFFFFFUL; | |
74 | rdev->mc.gtt_location = 0xFFFFFFFFUL; | |
75 | if (rdev->flags & RADEON_IS_AGP) { | |
76 | r = radeon_agp_init(rdev); | |
77 | if (r) { | |
78 | printk(KERN_WARNING "[drm] Disabling AGP\n"); | |
79 | rdev->flags &= ~RADEON_IS_AGP; | |
80 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
81 | } else { | |
82 | rdev->mc.gtt_location = rdev->mc.agp_base; | |
83 | } | |
84 | } | |
85 | r = radeon_mc_setup(rdev); | |
86 | if (r) { | |
87 | return r; | |
88 | } | |
89 | ||
90 | /* Program GPU memory space */ | |
91 | rs600_mc_disable_clients(rdev); | |
92 | if (r520_mc_wait_for_idle(rdev)) { | |
93 | printk(KERN_WARNING "Failed to wait MC idle while " | |
94 | "programming pipes. Bad things might happen.\n"); | |
95 | } | |
96 | /* Write VRAM size in case we are limiting it */ | |
97 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); | |
98 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; | |
99 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); | |
100 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); | |
101 | WREG32_MC(R520_MC_FB_LOCATION, tmp); | |
102 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); | |
103 | WREG32(0x310, rdev->mc.vram_location); | |
104 | if (rdev->flags & RADEON_IS_AGP) { | |
105 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; | |
106 | tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); | |
107 | tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); | |
108 | WREG32_MC(R520_MC_AGP_LOCATION, tmp); | |
109 | WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); | |
110 | WREG32_MC(R520_MC_AGP_BASE_2, 0); | |
111 | } else { | |
112 | WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); | |
113 | WREG32_MC(R520_MC_AGP_BASE, 0); | |
114 | WREG32_MC(R520_MC_AGP_BASE_2, 0); | |
115 | } | |
116 | return 0; | |
117 | } | |
118 | ||
119 | void r520_mc_fini(struct radeon_device *rdev) | |
120 | { | |
121 | rv370_pcie_gart_disable(rdev); | |
122 | radeon_gart_table_vram_free(rdev); | |
123 | radeon_gart_fini(rdev); | |
124 | } | |
125 | ||
126 | ||
127 | /* | |
128 | * Global GPU functions | |
129 | */ | |
130 | void r520_errata(struct radeon_device *rdev) | |
131 | { | |
132 | rdev->pll_errata = 0; | |
133 | } | |
134 | ||
135 | int r520_mc_wait_for_idle(struct radeon_device *rdev) | |
136 | { | |
137 | unsigned i; | |
138 | uint32_t tmp; | |
139 | ||
140 | for (i = 0; i < rdev->usec_timeout; i++) { | |
141 | /* read MC_STATUS */ | |
142 | tmp = RREG32_MC(R520_MC_STATUS); | |
143 | if (tmp & R520_MC_STATUS_IDLE) { | |
144 | return 0; | |
145 | } | |
146 | DRM_UDELAY(1); | |
147 | } | |
148 | return -1; | |
149 | } | |
150 | ||
151 | void r520_gpu_init(struct radeon_device *rdev) | |
152 | { | |
153 | unsigned pipe_select_current, gb_pipe_select, tmp; | |
154 | ||
155 | r100_hdp_reset(rdev); | |
156 | rs600_disable_vga(rdev); | |
157 | /* | |
158 | * DST_PIPE_CONFIG 0x170C | |
159 | * GB_TILE_CONFIG 0x4018 | |
160 | * GB_FIFO_SIZE 0x4024 | |
161 | * GB_PIPE_SELECT 0x402C | |
162 | * GB_PIPE_SELECT2 0x4124 | |
163 | * Z_PIPE_SHIFT 0 | |
164 | * Z_PIPE_MASK 0x000000003 | |
165 | * GB_FIFO_SIZE2 0x4128 | |
166 | * SC_SFIFO_SIZE_SHIFT 0 | |
167 | * SC_SFIFO_SIZE_MASK 0x000000003 | |
168 | * SC_MFIFO_SIZE_SHIFT 2 | |
169 | * SC_MFIFO_SIZE_MASK 0x00000000C | |
170 | * FG_SFIFO_SIZE_SHIFT 4 | |
171 | * FG_SFIFO_SIZE_MASK 0x000000030 | |
172 | * ZB_MFIFO_SIZE_SHIFT 6 | |
173 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 | |
174 | * GA_ENHANCE 0x4274 | |
175 | * SU_REG_DEST 0x42C8 | |
176 | */ | |
177 | /* workaround for RV530 */ | |
178 | if (rdev->family == CHIP_RV530) { | |
179 | WREG32(0x4124, 1); | |
180 | WREG32(0x4128, 0xFF); | |
181 | } | |
182 | r420_pipes_init(rdev); | |
183 | gb_pipe_select = RREG32(0x402C); | |
184 | tmp = RREG32(0x170C); | |
185 | pipe_select_current = (tmp >> 2) & 3; | |
186 | tmp = (1 << pipe_select_current) | | |
187 | (((gb_pipe_select >> 8) & 0xF) << 4); | |
188 | WREG32_PLL(0x000D, tmp); | |
189 | if (r520_mc_wait_for_idle(rdev)) { | |
190 | printk(KERN_WARNING "Failed to wait MC idle while " | |
191 | "programming pipes. Bad things might happen.\n"); | |
192 | } | |
193 | } | |
194 | ||
195 | ||
196 | /* | |
197 | * VRAM info | |
198 | */ | |
199 | static void r520_vram_get_type(struct radeon_device *rdev) | |
200 | { | |
201 | uint32_t tmp; | |
202 | ||
203 | rdev->mc.vram_width = 128; | |
204 | rdev->mc.vram_is_ddr = true; | |
205 | tmp = RREG32_MC(R520_MC_CNTL0); | |
206 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { | |
207 | case 0: | |
208 | rdev->mc.vram_width = 32; | |
209 | break; | |
210 | case 1: | |
211 | rdev->mc.vram_width = 64; | |
212 | break; | |
213 | case 2: | |
214 | rdev->mc.vram_width = 128; | |
215 | break; | |
216 | case 3: | |
217 | rdev->mc.vram_width = 256; | |
218 | break; | |
219 | default: | |
220 | rdev->mc.vram_width = 128; | |
221 | break; | |
222 | } | |
223 | if (tmp & R520_MC_CHANNEL_SIZE) | |
224 | rdev->mc.vram_width *= 2; | |
225 | } | |
226 | ||
227 | void r520_vram_info(struct radeon_device *rdev) | |
228 | { | |
229 | r520_vram_get_type(rdev); | |
230 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); | |
231 | ||
232 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | |
233 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
234 | } |