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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
3ce0a23d JG |
29 | #include <linux/seq_file.h> |
30 | #include <linux/firmware.h> | |
31 | #include <linux/platform_device.h> | |
771fe6b9 | 32 | #include "drmP.h" |
3ce0a23d | 33 | #include "radeon_drm.h" |
771fe6b9 | 34 | #include "radeon.h" |
e6990375 | 35 | #include "radeon_asic.h" |
3ce0a23d | 36 | #include "radeon_mode.h" |
3ce0a23d | 37 | #include "r600d.h" |
3ce0a23d | 38 | #include "atom.h" |
d39c3b89 | 39 | #include "avivod.h" |
771fe6b9 | 40 | |
3ce0a23d JG |
41 | #define PFP_UCODE_SIZE 576 |
42 | #define PM4_UCODE_SIZE 1792 | |
d8f60cfc | 43 | #define RLC_UCODE_SIZE 768 |
3ce0a23d JG |
44 | #define R700_PFP_UCODE_SIZE 848 |
45 | #define R700_PM4_UCODE_SIZE 1360 | |
d8f60cfc | 46 | #define R700_RLC_UCODE_SIZE 1024 |
3ce0a23d JG |
47 | |
48 | /* Firmware Names */ | |
49 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
50 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
51 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
52 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
53 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
54 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
55 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
56 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
57 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
59 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
60 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
61 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
62 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
63 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
64 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
65 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); | |
66 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
67 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); | |
68 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
d8f60cfc AD |
69 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
70 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); | |
3ce0a23d JG |
71 | |
72 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); | |
771fe6b9 | 73 | |
1a029b76 | 74 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
771fe6b9 JG |
75 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
76 | void r600_gpu_init(struct radeon_device *rdev); | |
3ce0a23d | 77 | void r600_fini(struct radeon_device *rdev); |
771fe6b9 | 78 | |
e0df1ac5 AD |
79 | /* hpd for digital panel detect/disconnect */ |
80 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
81 | { | |
82 | bool connected = false; | |
83 | ||
84 | if (ASIC_IS_DCE3(rdev)) { | |
85 | switch (hpd) { | |
86 | case RADEON_HPD_1: | |
87 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
88 | connected = true; | |
89 | break; | |
90 | case RADEON_HPD_2: | |
91 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
92 | connected = true; | |
93 | break; | |
94 | case RADEON_HPD_3: | |
95 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
96 | connected = true; | |
97 | break; | |
98 | case RADEON_HPD_4: | |
99 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
100 | connected = true; | |
101 | break; | |
102 | /* DCE 3.2 */ | |
103 | case RADEON_HPD_5: | |
104 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
105 | connected = true; | |
106 | break; | |
107 | case RADEON_HPD_6: | |
108 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
109 | connected = true; | |
110 | break; | |
111 | default: | |
112 | break; | |
113 | } | |
114 | } else { | |
115 | switch (hpd) { | |
116 | case RADEON_HPD_1: | |
117 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
118 | connected = true; | |
119 | break; | |
120 | case RADEON_HPD_2: | |
121 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
122 | connected = true; | |
123 | break; | |
124 | case RADEON_HPD_3: | |
125 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
126 | connected = true; | |
127 | break; | |
128 | default: | |
129 | break; | |
130 | } | |
131 | } | |
132 | return connected; | |
133 | } | |
134 | ||
135 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
429770b3 | 136 | enum radeon_hpd_id hpd) |
e0df1ac5 AD |
137 | { |
138 | u32 tmp; | |
139 | bool connected = r600_hpd_sense(rdev, hpd); | |
140 | ||
141 | if (ASIC_IS_DCE3(rdev)) { | |
142 | switch (hpd) { | |
143 | case RADEON_HPD_1: | |
144 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
145 | if (connected) | |
146 | tmp &= ~DC_HPDx_INT_POLARITY; | |
147 | else | |
148 | tmp |= DC_HPDx_INT_POLARITY; | |
149 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
150 | break; | |
151 | case RADEON_HPD_2: | |
152 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
153 | if (connected) | |
154 | tmp &= ~DC_HPDx_INT_POLARITY; | |
155 | else | |
156 | tmp |= DC_HPDx_INT_POLARITY; | |
157 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
158 | break; | |
159 | case RADEON_HPD_3: | |
160 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
161 | if (connected) | |
162 | tmp &= ~DC_HPDx_INT_POLARITY; | |
163 | else | |
164 | tmp |= DC_HPDx_INT_POLARITY; | |
165 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
166 | break; | |
167 | case RADEON_HPD_4: | |
168 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
169 | if (connected) | |
170 | tmp &= ~DC_HPDx_INT_POLARITY; | |
171 | else | |
172 | tmp |= DC_HPDx_INT_POLARITY; | |
173 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
174 | break; | |
175 | case RADEON_HPD_5: | |
176 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
177 | if (connected) | |
178 | tmp &= ~DC_HPDx_INT_POLARITY; | |
179 | else | |
180 | tmp |= DC_HPDx_INT_POLARITY; | |
181 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
182 | break; | |
183 | /* DCE 3.2 */ | |
184 | case RADEON_HPD_6: | |
185 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
186 | if (connected) | |
187 | tmp &= ~DC_HPDx_INT_POLARITY; | |
188 | else | |
189 | tmp |= DC_HPDx_INT_POLARITY; | |
190 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
191 | break; | |
192 | default: | |
193 | break; | |
194 | } | |
195 | } else { | |
196 | switch (hpd) { | |
197 | case RADEON_HPD_1: | |
198 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
199 | if (connected) | |
200 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
201 | else | |
202 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
203 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
204 | break; | |
205 | case RADEON_HPD_2: | |
206 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
207 | if (connected) | |
208 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
209 | else | |
210 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
211 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
212 | break; | |
213 | case RADEON_HPD_3: | |
214 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
215 | if (connected) | |
216 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
217 | else | |
218 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
219 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
220 | break; | |
221 | default: | |
222 | break; | |
223 | } | |
224 | } | |
225 | } | |
226 | ||
227 | void r600_hpd_init(struct radeon_device *rdev) | |
228 | { | |
229 | struct drm_device *dev = rdev->ddev; | |
230 | struct drm_connector *connector; | |
231 | ||
232 | if (ASIC_IS_DCE3(rdev)) { | |
233 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); | |
234 | if (ASIC_IS_DCE32(rdev)) | |
235 | tmp |= DC_HPDx_EN; | |
236 | ||
237 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
238 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
239 | switch (radeon_connector->hpd.hpd) { | |
240 | case RADEON_HPD_1: | |
241 | WREG32(DC_HPD1_CONTROL, tmp); | |
242 | rdev->irq.hpd[0] = true; | |
243 | break; | |
244 | case RADEON_HPD_2: | |
245 | WREG32(DC_HPD2_CONTROL, tmp); | |
246 | rdev->irq.hpd[1] = true; | |
247 | break; | |
248 | case RADEON_HPD_3: | |
249 | WREG32(DC_HPD3_CONTROL, tmp); | |
250 | rdev->irq.hpd[2] = true; | |
251 | break; | |
252 | case RADEON_HPD_4: | |
253 | WREG32(DC_HPD4_CONTROL, tmp); | |
254 | rdev->irq.hpd[3] = true; | |
255 | break; | |
256 | /* DCE 3.2 */ | |
257 | case RADEON_HPD_5: | |
258 | WREG32(DC_HPD5_CONTROL, tmp); | |
259 | rdev->irq.hpd[4] = true; | |
260 | break; | |
261 | case RADEON_HPD_6: | |
262 | WREG32(DC_HPD6_CONTROL, tmp); | |
263 | rdev->irq.hpd[5] = true; | |
264 | break; | |
265 | default: | |
266 | break; | |
267 | } | |
268 | } | |
269 | } else { | |
270 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
271 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
272 | switch (radeon_connector->hpd.hpd) { | |
273 | case RADEON_HPD_1: | |
274 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
275 | rdev->irq.hpd[0] = true; | |
276 | break; | |
277 | case RADEON_HPD_2: | |
278 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
279 | rdev->irq.hpd[1] = true; | |
280 | break; | |
281 | case RADEON_HPD_3: | |
282 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
283 | rdev->irq.hpd[2] = true; | |
284 | break; | |
285 | default: | |
286 | break; | |
287 | } | |
288 | } | |
289 | } | |
003e69f9 JG |
290 | if (rdev->irq.installed) |
291 | r600_irq_set(rdev); | |
e0df1ac5 AD |
292 | } |
293 | ||
294 | void r600_hpd_fini(struct radeon_device *rdev) | |
295 | { | |
296 | struct drm_device *dev = rdev->ddev; | |
297 | struct drm_connector *connector; | |
298 | ||
299 | if (ASIC_IS_DCE3(rdev)) { | |
300 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
301 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
302 | switch (radeon_connector->hpd.hpd) { | |
303 | case RADEON_HPD_1: | |
304 | WREG32(DC_HPD1_CONTROL, 0); | |
305 | rdev->irq.hpd[0] = false; | |
306 | break; | |
307 | case RADEON_HPD_2: | |
308 | WREG32(DC_HPD2_CONTROL, 0); | |
309 | rdev->irq.hpd[1] = false; | |
310 | break; | |
311 | case RADEON_HPD_3: | |
312 | WREG32(DC_HPD3_CONTROL, 0); | |
313 | rdev->irq.hpd[2] = false; | |
314 | break; | |
315 | case RADEON_HPD_4: | |
316 | WREG32(DC_HPD4_CONTROL, 0); | |
317 | rdev->irq.hpd[3] = false; | |
318 | break; | |
319 | /* DCE 3.2 */ | |
320 | case RADEON_HPD_5: | |
321 | WREG32(DC_HPD5_CONTROL, 0); | |
322 | rdev->irq.hpd[4] = false; | |
323 | break; | |
324 | case RADEON_HPD_6: | |
325 | WREG32(DC_HPD6_CONTROL, 0); | |
326 | rdev->irq.hpd[5] = false; | |
327 | break; | |
328 | default: | |
329 | break; | |
330 | } | |
331 | } | |
332 | } else { | |
333 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
334 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
335 | switch (radeon_connector->hpd.hpd) { | |
336 | case RADEON_HPD_1: | |
337 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); | |
338 | rdev->irq.hpd[0] = false; | |
339 | break; | |
340 | case RADEON_HPD_2: | |
341 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); | |
342 | rdev->irq.hpd[1] = false; | |
343 | break; | |
344 | case RADEON_HPD_3: | |
345 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); | |
346 | rdev->irq.hpd[2] = false; | |
347 | break; | |
348 | default: | |
349 | break; | |
350 | } | |
351 | } | |
352 | } | |
353 | } | |
354 | ||
771fe6b9 | 355 | /* |
3ce0a23d | 356 | * R600 PCIE GART |
771fe6b9 | 357 | */ |
3ce0a23d JG |
358 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
359 | { | |
360 | unsigned i; | |
361 | u32 tmp; | |
362 | ||
2e98f10a DA |
363 | /* flush hdp cache so updates hit vram */ |
364 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
365 | ||
3ce0a23d JG |
366 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
367 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); | |
368 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
369 | for (i = 0; i < rdev->usec_timeout; i++) { | |
370 | /* read MC_STATUS */ | |
371 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
372 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
373 | if (tmp == 2) { | |
374 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
375 | return; | |
376 | } | |
377 | if (tmp) { | |
378 | return; | |
379 | } | |
380 | udelay(1); | |
381 | } | |
382 | } | |
383 | ||
4aac0473 | 384 | int r600_pcie_gart_init(struct radeon_device *rdev) |
3ce0a23d | 385 | { |
4aac0473 | 386 | int r; |
3ce0a23d | 387 | |
4aac0473 JG |
388 | if (rdev->gart.table.vram.robj) { |
389 | WARN(1, "R600 PCIE GART already initialized.\n"); | |
390 | return 0; | |
391 | } | |
3ce0a23d JG |
392 | /* Initialize common gart structure */ |
393 | r = radeon_gart_init(rdev); | |
4aac0473 | 394 | if (r) |
3ce0a23d | 395 | return r; |
3ce0a23d | 396 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
4aac0473 JG |
397 | return radeon_gart_table_vram_alloc(rdev); |
398 | } | |
399 | ||
400 | int r600_pcie_gart_enable(struct radeon_device *rdev) | |
401 | { | |
402 | u32 tmp; | |
403 | int r, i; | |
404 | ||
405 | if (rdev->gart.table.vram.robj == NULL) { | |
406 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
407 | return -EINVAL; | |
771fe6b9 | 408 | } |
4aac0473 JG |
409 | r = radeon_gart_table_vram_pin(rdev); |
410 | if (r) | |
411 | return r; | |
82568565 | 412 | radeon_gart_restore(rdev); |
bc1a631e | 413 | |
3ce0a23d JG |
414 | /* Setup L2 cache */ |
415 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
416 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
417 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
418 | WREG32(VM_L2_CNTL2, 0); | |
419 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
420 | /* Setup TLB control */ | |
421 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
422 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
423 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
424 | ENABLE_WAIT_L2_QUERY; | |
425 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
426 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
427 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
428 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
429 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
430 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
431 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
432 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
433 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
434 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
435 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
436 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
437 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
438 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
439 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1a029b76 | 440 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
441 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
442 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
443 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
444 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
445 | (u32)(rdev->dummy_page.addr >> 12)); | |
446 | for (i = 1; i < 7; i++) | |
447 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 448 | |
3ce0a23d JG |
449 | r600_pcie_gart_tlb_flush(rdev); |
450 | rdev->gart.ready = true; | |
771fe6b9 JG |
451 | return 0; |
452 | } | |
453 | ||
3ce0a23d | 454 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 455 | { |
3ce0a23d | 456 | u32 tmp; |
4c788679 | 457 | int i, r; |
771fe6b9 | 458 | |
3ce0a23d JG |
459 | /* Disable all tables */ |
460 | for (i = 0; i < 7; i++) | |
461 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 462 | |
3ce0a23d JG |
463 | /* Disable L2 cache */ |
464 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
465 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
466 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
467 | /* Setup L1 TLB control */ | |
468 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
469 | ENABLE_WAIT_L2_QUERY; | |
470 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
471 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
472 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
473 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
474 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
475 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
476 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
477 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
478 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); | |
479 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); | |
480 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
481 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
482 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); | |
483 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
4aac0473 | 484 | if (rdev->gart.table.vram.robj) { |
4c788679 JG |
485 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
486 | if (likely(r == 0)) { | |
487 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
488 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
489 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
490 | } | |
4aac0473 JG |
491 | } |
492 | } | |
493 | ||
494 | void r600_pcie_gart_fini(struct radeon_device *rdev) | |
495 | { | |
f9274562 | 496 | radeon_gart_fini(rdev); |
4aac0473 JG |
497 | r600_pcie_gart_disable(rdev); |
498 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
499 | } |
500 | ||
1a029b76 JG |
501 | void r600_agp_enable(struct radeon_device *rdev) |
502 | { | |
503 | u32 tmp; | |
504 | int i; | |
505 | ||
506 | /* Setup L2 cache */ | |
507 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
508 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
509 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
510 | WREG32(VM_L2_CNTL2, 0); | |
511 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
512 | /* Setup TLB control */ | |
513 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
514 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
515 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
516 | ENABLE_WAIT_L2_QUERY; | |
517 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
518 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
519 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
520 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
521 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
522 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
523 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
524 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
525 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
526 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
527 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
528 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
529 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
530 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
531 | for (i = 0; i < 7; i++) | |
532 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
533 | } | |
534 | ||
771fe6b9 JG |
535 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
536 | { | |
3ce0a23d JG |
537 | unsigned i; |
538 | u32 tmp; | |
539 | ||
540 | for (i = 0; i < rdev->usec_timeout; i++) { | |
541 | /* read MC_STATUS */ | |
542 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; | |
543 | if (!tmp) | |
544 | return 0; | |
545 | udelay(1); | |
546 | } | |
547 | return -1; | |
771fe6b9 JG |
548 | } |
549 | ||
a3c1945a | 550 | static void r600_mc_program(struct radeon_device *rdev) |
771fe6b9 | 551 | { |
a3c1945a | 552 | struct rv515_mc_save save; |
3ce0a23d JG |
553 | u32 tmp; |
554 | int i, j; | |
771fe6b9 | 555 | |
3ce0a23d JG |
556 | /* Initialize HDP */ |
557 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
558 | WREG32((0x2c14 + j), 0x00000000); | |
559 | WREG32((0x2c18 + j), 0x00000000); | |
560 | WREG32((0x2c1c + j), 0x00000000); | |
561 | WREG32((0x2c20 + j), 0x00000000); | |
562 | WREG32((0x2c24 + j), 0x00000000); | |
563 | } | |
564 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
771fe6b9 | 565 | |
a3c1945a | 566 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 567 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 568 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 569 | } |
a3c1945a | 570 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
3ce0a23d | 571 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
3ce0a23d | 572 | /* Update configuration */ |
1a029b76 JG |
573 | if (rdev->flags & RADEON_IS_AGP) { |
574 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
575 | /* VRAM before AGP */ | |
576 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
577 | rdev->mc.vram_start >> 12); | |
578 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
579 | rdev->mc.gtt_end >> 12); | |
580 | } else { | |
581 | /* VRAM after AGP */ | |
582 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
583 | rdev->mc.gtt_start >> 12); | |
584 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
585 | rdev->mc.vram_end >> 12); | |
586 | } | |
587 | } else { | |
588 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); | |
589 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); | |
590 | } | |
3ce0a23d | 591 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
1a029b76 | 592 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
593 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
594 | WREG32(MC_VM_FB_LOCATION, tmp); | |
595 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
596 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
1a029b76 | 597 | WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF); |
3ce0a23d | 598 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 JG |
599 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
600 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | |
3ce0a23d JG |
601 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
602 | } else { | |
603 | WREG32(MC_VM_AGP_BASE, 0); | |
604 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
605 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
606 | } | |
3ce0a23d | 607 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 608 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 609 | } |
a3c1945a | 610 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
611 | /* we need to own VRAM, so turn off the VGA renderer here |
612 | * to stop it overwriting our objects */ | |
d39c3b89 | 613 | rv515_vga_render_disable(rdev); |
3ce0a23d JG |
614 | } |
615 | ||
d594e46a JG |
616 | /** |
617 | * r600_vram_gtt_location - try to find VRAM & GTT location | |
618 | * @rdev: radeon device structure holding all necessary informations | |
619 | * @mc: memory controller structure holding memory informations | |
620 | * | |
621 | * Function will place try to place VRAM at same place as in CPU (PCI) | |
622 | * address space as some GPU seems to have issue when we reprogram at | |
623 | * different address space. | |
624 | * | |
625 | * If there is not enough space to fit the unvisible VRAM after the | |
626 | * aperture then we limit the VRAM size to the aperture. | |
627 | * | |
628 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need | |
629 | * them to be in one from GPU point of view so that we can program GPU to | |
630 | * catch access outside them (weird GPU policy see ??). | |
631 | * | |
632 | * This function will never fails, worst case are limiting VRAM or GTT. | |
633 | * | |
634 | * Note: GTT start, end, size should be initialized before calling this | |
635 | * function on AGP platform. | |
636 | */ | |
637 | void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
638 | { | |
639 | u64 size_bf, size_af; | |
640 | ||
641 | if (mc->mc_vram_size > 0xE0000000) { | |
642 | /* leave room for at least 512M GTT */ | |
643 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
644 | mc->real_vram_size = 0xE0000000; | |
645 | mc->mc_vram_size = 0xE0000000; | |
646 | } | |
647 | if (rdev->flags & RADEON_IS_AGP) { | |
648 | size_bf = mc->gtt_start; | |
649 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; | |
650 | if (size_bf > size_af) { | |
651 | if (mc->mc_vram_size > size_bf) { | |
652 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
653 | mc->real_vram_size = size_bf; | |
654 | mc->mc_vram_size = size_bf; | |
655 | } | |
656 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; | |
657 | } else { | |
658 | if (mc->mc_vram_size > size_af) { | |
659 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
660 | mc->real_vram_size = size_af; | |
661 | mc->mc_vram_size = size_af; | |
662 | } | |
663 | mc->vram_start = mc->gtt_end; | |
664 | } | |
665 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
666 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
667 | mc->mc_vram_size >> 20, mc->vram_start, | |
668 | mc->vram_end, mc->real_vram_size >> 20); | |
669 | } else { | |
670 | u64 base = 0; | |
671 | if (rdev->flags & RADEON_IS_IGP) | |
672 | base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; | |
673 | radeon_vram_location(rdev, &rdev->mc, base); | |
674 | radeon_gtt_location(rdev, mc); | |
675 | } | |
676 | } | |
677 | ||
3ce0a23d | 678 | int r600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 679 | { |
3ce0a23d | 680 | u32 tmp; |
5885b7a9 | 681 | int chansize, numchan; |
771fe6b9 | 682 | |
3ce0a23d | 683 | /* Get VRAM informations */ |
771fe6b9 | 684 | rdev->mc.vram_is_ddr = true; |
3ce0a23d JG |
685 | tmp = RREG32(RAMCFG); |
686 | if (tmp & CHANSIZE_OVERRIDE) { | |
771fe6b9 | 687 | chansize = 16; |
3ce0a23d | 688 | } else if (tmp & CHANSIZE_MASK) { |
771fe6b9 JG |
689 | chansize = 64; |
690 | } else { | |
691 | chansize = 32; | |
692 | } | |
5885b7a9 AD |
693 | tmp = RREG32(CHMAP); |
694 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
695 | case 0: | |
696 | default: | |
697 | numchan = 1; | |
698 | break; | |
699 | case 1: | |
700 | numchan = 2; | |
701 | break; | |
702 | case 2: | |
703 | numchan = 4; | |
704 | break; | |
705 | case 3: | |
706 | numchan = 8; | |
707 | break; | |
771fe6b9 | 708 | } |
5885b7a9 | 709 | rdev->mc.vram_width = numchan * chansize; |
3ce0a23d JG |
710 | /* Could aper size report 0 ? */ |
711 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | |
712 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
713 | /* Setup GPU memory space */ | |
714 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
715 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
51e5fcd3 | 716 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a JG |
717 | /* FIXME remove this once we support unmappable VRAM */ |
718 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { | |
974b16e3 | 719 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
974b16e3 | 720 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
3ce0a23d | 721 | } |
d594e46a | 722 | r600_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 | 723 | |
06b6476d AD |
724 | if (rdev->flags & RADEON_IS_IGP) |
725 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | |
f47299c5 | 726 | radeon_update_bandwidth_info(rdev); |
3ce0a23d | 727 | return 0; |
771fe6b9 JG |
728 | } |
729 | ||
3ce0a23d JG |
730 | /* We doesn't check that the GPU really needs a reset we simply do the |
731 | * reset, it's up to the caller to determine if the GPU needs one. We | |
732 | * might add an helper function to check that. | |
733 | */ | |
734 | int r600_gpu_soft_reset(struct radeon_device *rdev) | |
771fe6b9 | 735 | { |
a3c1945a | 736 | struct rv515_mc_save save; |
3ce0a23d JG |
737 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
738 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | | |
739 | S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | | |
740 | S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | | |
741 | S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | | |
742 | S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | | |
743 | S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | | |
744 | S_008010_GUI_ACTIVE(1); | |
745 | u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | | |
746 | S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | | |
747 | S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | | |
748 | S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | | |
749 | S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | | |
750 | S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | | |
751 | S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | | |
752 | S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); | |
753 | u32 srbm_reset = 0; | |
a3c1945a | 754 | u32 tmp; |
771fe6b9 | 755 | |
1a029b76 JG |
756 | dev_info(rdev->dev, "GPU softreset \n"); |
757 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", | |
758 | RREG32(R_008010_GRBM_STATUS)); | |
759 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
a3c1945a | 760 | RREG32(R_008014_GRBM_STATUS2)); |
1a029b76 JG |
761 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
762 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a JG |
763 | rv515_mc_stop(rdev, &save); |
764 | if (r600_mc_wait_for_idle(rdev)) { | |
765 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
766 | } | |
3ce0a23d JG |
767 | /* Disable CP parsing/prefetching */ |
768 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff)); | |
769 | /* Check if any of the rendering block is busy and reset it */ | |
770 | if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || | |
771 | (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { | |
a3c1945a | 772 | tmp = S_008020_SOFT_RESET_CR(1) | |
3ce0a23d JG |
773 | S_008020_SOFT_RESET_DB(1) | |
774 | S_008020_SOFT_RESET_CB(1) | | |
775 | S_008020_SOFT_RESET_PA(1) | | |
776 | S_008020_SOFT_RESET_SC(1) | | |
777 | S_008020_SOFT_RESET_SMX(1) | | |
778 | S_008020_SOFT_RESET_SPI(1) | | |
779 | S_008020_SOFT_RESET_SX(1) | | |
780 | S_008020_SOFT_RESET_SH(1) | | |
781 | S_008020_SOFT_RESET_TC(1) | | |
782 | S_008020_SOFT_RESET_TA(1) | | |
783 | S_008020_SOFT_RESET_VC(1) | | |
a3c1945a | 784 | S_008020_SOFT_RESET_VGT(1); |
1a029b76 | 785 | dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
a3c1945a | 786 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
3ce0a23d JG |
787 | (void)RREG32(R_008020_GRBM_SOFT_RESET); |
788 | udelay(50); | |
789 | WREG32(R_008020_GRBM_SOFT_RESET, 0); | |
790 | (void)RREG32(R_008020_GRBM_SOFT_RESET); | |
791 | } | |
792 | /* Reset CP (we always reset CP) */ | |
a3c1945a JG |
793 | tmp = S_008020_SOFT_RESET_CP(1); |
794 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); | |
795 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
3ce0a23d JG |
796 | (void)RREG32(R_008020_GRBM_SOFT_RESET); |
797 | udelay(50); | |
798 | WREG32(R_008020_GRBM_SOFT_RESET, 0); | |
799 | (void)RREG32(R_008020_GRBM_SOFT_RESET); | |
800 | /* Reset others GPU block if necessary */ | |
801 | if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
802 | srbm_reset |= S_000E60_SOFT_RESET_RLC(1); | |
803 | if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) | |
804 | srbm_reset |= S_000E60_SOFT_RESET_GRBM(1); | |
805 | if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) | |
806 | srbm_reset |= S_000E60_SOFT_RESET_IH(1); | |
807 | if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
808 | srbm_reset |= S_000E60_SOFT_RESET_VMC(1); | |
809 | if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
810 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
811 | if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
812 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
813 | if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
814 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
815 | if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
816 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
817 | if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
818 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
819 | if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
820 | srbm_reset |= S_000E60_SOFT_RESET_RLC(1); | |
821 | if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
822 | srbm_reset |= S_000E60_SOFT_RESET_SEM(1); | |
1a029b76 JG |
823 | if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
824 | srbm_reset |= S_000E60_SOFT_RESET_BIF(1); | |
825 | dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset); | |
826 | WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); | |
827 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
828 | udelay(50); | |
829 | WREG32(R_000E60_SRBM_SOFT_RESET, 0); | |
830 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
3ce0a23d JG |
831 | WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); |
832 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
833 | udelay(50); | |
834 | WREG32(R_000E60_SRBM_SOFT_RESET, 0); | |
835 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
836 | /* Wait a little for things to settle down */ | |
837 | udelay(50); | |
1a029b76 JG |
838 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
839 | RREG32(R_008010_GRBM_STATUS)); | |
840 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
841 | RREG32(R_008014_GRBM_STATUS2)); | |
842 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", | |
843 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a JG |
844 | /* After reset we need to reinit the asic as GPU often endup in an |
845 | * incoherent state. | |
846 | */ | |
847 | atom_asic_init(rdev->mode_info.atom_context); | |
848 | rv515_mc_resume(rdev, &save); | |
3ce0a23d JG |
849 | return 0; |
850 | } | |
851 | ||
852 | int r600_gpu_reset(struct radeon_device *rdev) | |
853 | { | |
854 | return r600_gpu_soft_reset(rdev); | |
855 | } | |
856 | ||
857 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
858 | u32 num_backends, | |
859 | u32 backend_disable_mask) | |
860 | { | |
861 | u32 backend_map = 0; | |
862 | u32 enabled_backends_mask; | |
863 | u32 enabled_backends_count; | |
864 | u32 cur_pipe; | |
865 | u32 swizzle_pipe[R6XX_MAX_PIPES]; | |
866 | u32 cur_backend; | |
867 | u32 i; | |
868 | ||
869 | if (num_tile_pipes > R6XX_MAX_PIPES) | |
870 | num_tile_pipes = R6XX_MAX_PIPES; | |
871 | if (num_tile_pipes < 1) | |
872 | num_tile_pipes = 1; | |
873 | if (num_backends > R6XX_MAX_BACKENDS) | |
874 | num_backends = R6XX_MAX_BACKENDS; | |
875 | if (num_backends < 1) | |
876 | num_backends = 1; | |
877 | ||
878 | enabled_backends_mask = 0; | |
879 | enabled_backends_count = 0; | |
880 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { | |
881 | if (((backend_disable_mask >> i) & 1) == 0) { | |
882 | enabled_backends_mask |= (1 << i); | |
883 | ++enabled_backends_count; | |
884 | } | |
885 | if (enabled_backends_count == num_backends) | |
886 | break; | |
887 | } | |
888 | ||
889 | if (enabled_backends_count == 0) { | |
890 | enabled_backends_mask = 1; | |
891 | enabled_backends_count = 1; | |
892 | } | |
893 | ||
894 | if (enabled_backends_count != num_backends) | |
895 | num_backends = enabled_backends_count; | |
896 | ||
897 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); | |
898 | switch (num_tile_pipes) { | |
899 | case 1: | |
900 | swizzle_pipe[0] = 0; | |
901 | break; | |
902 | case 2: | |
903 | swizzle_pipe[0] = 0; | |
904 | swizzle_pipe[1] = 1; | |
905 | break; | |
906 | case 3: | |
907 | swizzle_pipe[0] = 0; | |
908 | swizzle_pipe[1] = 1; | |
909 | swizzle_pipe[2] = 2; | |
910 | break; | |
911 | case 4: | |
912 | swizzle_pipe[0] = 0; | |
913 | swizzle_pipe[1] = 1; | |
914 | swizzle_pipe[2] = 2; | |
915 | swizzle_pipe[3] = 3; | |
916 | break; | |
917 | case 5: | |
918 | swizzle_pipe[0] = 0; | |
919 | swizzle_pipe[1] = 1; | |
920 | swizzle_pipe[2] = 2; | |
921 | swizzle_pipe[3] = 3; | |
922 | swizzle_pipe[4] = 4; | |
923 | break; | |
924 | case 6: | |
925 | swizzle_pipe[0] = 0; | |
926 | swizzle_pipe[1] = 2; | |
927 | swizzle_pipe[2] = 4; | |
928 | swizzle_pipe[3] = 5; | |
929 | swizzle_pipe[4] = 1; | |
930 | swizzle_pipe[5] = 3; | |
931 | break; | |
932 | case 7: | |
933 | swizzle_pipe[0] = 0; | |
934 | swizzle_pipe[1] = 2; | |
935 | swizzle_pipe[2] = 4; | |
936 | swizzle_pipe[3] = 6; | |
937 | swizzle_pipe[4] = 1; | |
938 | swizzle_pipe[5] = 3; | |
939 | swizzle_pipe[6] = 5; | |
940 | break; | |
941 | case 8: | |
942 | swizzle_pipe[0] = 0; | |
943 | swizzle_pipe[1] = 2; | |
944 | swizzle_pipe[2] = 4; | |
945 | swizzle_pipe[3] = 6; | |
946 | swizzle_pipe[4] = 1; | |
947 | swizzle_pipe[5] = 3; | |
948 | swizzle_pipe[6] = 5; | |
949 | swizzle_pipe[7] = 7; | |
950 | break; | |
951 | } | |
952 | ||
953 | cur_backend = 0; | |
954 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
955 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
956 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
957 | ||
958 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
959 | ||
960 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
961 | } | |
962 | ||
963 | return backend_map; | |
964 | } | |
965 | ||
966 | int r600_count_pipe_bits(uint32_t val) | |
967 | { | |
968 | int i, ret = 0; | |
969 | ||
970 | for (i = 0; i < 32; i++) { | |
971 | ret += val & 1; | |
972 | val >>= 1; | |
973 | } | |
974 | return ret; | |
771fe6b9 JG |
975 | } |
976 | ||
3ce0a23d JG |
977 | void r600_gpu_init(struct radeon_device *rdev) |
978 | { | |
979 | u32 tiling_config; | |
980 | u32 ramcfg; | |
d03f5d59 AD |
981 | u32 backend_map; |
982 | u32 cc_rb_backend_disable; | |
983 | u32 cc_gc_shader_pipe_config; | |
3ce0a23d JG |
984 | u32 tmp; |
985 | int i, j; | |
986 | u32 sq_config; | |
987 | u32 sq_gpr_resource_mgmt_1 = 0; | |
988 | u32 sq_gpr_resource_mgmt_2 = 0; | |
989 | u32 sq_thread_resource_mgmt = 0; | |
990 | u32 sq_stack_resource_mgmt_1 = 0; | |
991 | u32 sq_stack_resource_mgmt_2 = 0; | |
992 | ||
993 | /* FIXME: implement */ | |
994 | switch (rdev->family) { | |
995 | case CHIP_R600: | |
996 | rdev->config.r600.max_pipes = 4; | |
997 | rdev->config.r600.max_tile_pipes = 8; | |
998 | rdev->config.r600.max_simds = 4; | |
999 | rdev->config.r600.max_backends = 4; | |
1000 | rdev->config.r600.max_gprs = 256; | |
1001 | rdev->config.r600.max_threads = 192; | |
1002 | rdev->config.r600.max_stack_entries = 256; | |
1003 | rdev->config.r600.max_hw_contexts = 8; | |
1004 | rdev->config.r600.max_gs_threads = 16; | |
1005 | rdev->config.r600.sx_max_export_size = 128; | |
1006 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1007 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1008 | rdev->config.r600.sq_num_cf_insts = 2; | |
1009 | break; | |
1010 | case CHIP_RV630: | |
1011 | case CHIP_RV635: | |
1012 | rdev->config.r600.max_pipes = 2; | |
1013 | rdev->config.r600.max_tile_pipes = 2; | |
1014 | rdev->config.r600.max_simds = 3; | |
1015 | rdev->config.r600.max_backends = 1; | |
1016 | rdev->config.r600.max_gprs = 128; | |
1017 | rdev->config.r600.max_threads = 192; | |
1018 | rdev->config.r600.max_stack_entries = 128; | |
1019 | rdev->config.r600.max_hw_contexts = 8; | |
1020 | rdev->config.r600.max_gs_threads = 4; | |
1021 | rdev->config.r600.sx_max_export_size = 128; | |
1022 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1023 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1024 | rdev->config.r600.sq_num_cf_insts = 2; | |
1025 | break; | |
1026 | case CHIP_RV610: | |
1027 | case CHIP_RV620: | |
1028 | case CHIP_RS780: | |
1029 | case CHIP_RS880: | |
1030 | rdev->config.r600.max_pipes = 1; | |
1031 | rdev->config.r600.max_tile_pipes = 1; | |
1032 | rdev->config.r600.max_simds = 2; | |
1033 | rdev->config.r600.max_backends = 1; | |
1034 | rdev->config.r600.max_gprs = 128; | |
1035 | rdev->config.r600.max_threads = 192; | |
1036 | rdev->config.r600.max_stack_entries = 128; | |
1037 | rdev->config.r600.max_hw_contexts = 4; | |
1038 | rdev->config.r600.max_gs_threads = 4; | |
1039 | rdev->config.r600.sx_max_export_size = 128; | |
1040 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1041 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1042 | rdev->config.r600.sq_num_cf_insts = 1; | |
1043 | break; | |
1044 | case CHIP_RV670: | |
1045 | rdev->config.r600.max_pipes = 4; | |
1046 | rdev->config.r600.max_tile_pipes = 4; | |
1047 | rdev->config.r600.max_simds = 4; | |
1048 | rdev->config.r600.max_backends = 4; | |
1049 | rdev->config.r600.max_gprs = 192; | |
1050 | rdev->config.r600.max_threads = 192; | |
1051 | rdev->config.r600.max_stack_entries = 256; | |
1052 | rdev->config.r600.max_hw_contexts = 8; | |
1053 | rdev->config.r600.max_gs_threads = 16; | |
1054 | rdev->config.r600.sx_max_export_size = 128; | |
1055 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1056 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1057 | rdev->config.r600.sq_num_cf_insts = 2; | |
1058 | break; | |
1059 | default: | |
1060 | break; | |
1061 | } | |
1062 | ||
1063 | /* Initialize HDP */ | |
1064 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1065 | WREG32((0x2c14 + j), 0x00000000); | |
1066 | WREG32((0x2c18 + j), 0x00000000); | |
1067 | WREG32((0x2c1c + j), 0x00000000); | |
1068 | WREG32((0x2c20 + j), 0x00000000); | |
1069 | WREG32((0x2c24 + j), 0x00000000); | |
1070 | } | |
1071 | ||
1072 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1073 | ||
1074 | /* Setup tiling */ | |
1075 | tiling_config = 0; | |
1076 | ramcfg = RREG32(RAMCFG); | |
1077 | switch (rdev->config.r600.max_tile_pipes) { | |
1078 | case 1: | |
1079 | tiling_config |= PIPE_TILING(0); | |
1080 | break; | |
1081 | case 2: | |
1082 | tiling_config |= PIPE_TILING(1); | |
1083 | break; | |
1084 | case 4: | |
1085 | tiling_config |= PIPE_TILING(2); | |
1086 | break; | |
1087 | case 8: | |
1088 | tiling_config |= PIPE_TILING(3); | |
1089 | break; | |
1090 | default: | |
1091 | break; | |
1092 | } | |
d03f5d59 | 1093 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
961fb597 | 1094 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
3ce0a23d JG |
1095 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1096 | tiling_config |= GROUP_SIZE(0); | |
961fb597 | 1097 | rdev->config.r600.tiling_group_size = 256; |
3ce0a23d JG |
1098 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
1099 | if (tmp > 3) { | |
1100 | tiling_config |= ROW_TILING(3); | |
1101 | tiling_config |= SAMPLE_SPLIT(3); | |
1102 | } else { | |
1103 | tiling_config |= ROW_TILING(tmp); | |
1104 | tiling_config |= SAMPLE_SPLIT(tmp); | |
1105 | } | |
1106 | tiling_config |= BANK_SWAPS(1); | |
d03f5d59 AD |
1107 | |
1108 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | |
1109 | cc_rb_backend_disable |= | |
1110 | BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); | |
1111 | ||
1112 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; | |
1113 | cc_gc_shader_pipe_config |= | |
1114 | INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); | |
1115 | cc_gc_shader_pipe_config |= | |
1116 | INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); | |
1117 | ||
1118 | backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, | |
1119 | (R6XX_MAX_BACKENDS - | |
1120 | r600_count_pipe_bits((cc_rb_backend_disable & | |
1121 | R6XX_MAX_BACKENDS_MASK) >> 16)), | |
1122 | (cc_rb_backend_disable >> 16)); | |
1123 | ||
1124 | tiling_config |= BACKEND_MAP(backend_map); | |
3ce0a23d JG |
1125 | WREG32(GB_TILING_CONFIG, tiling_config); |
1126 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); | |
1127 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); | |
1128 | ||
3ce0a23d | 1129 | /* Setup pipes */ |
d03f5d59 AD |
1130 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
1131 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
f867c60d | 1132 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
3ce0a23d | 1133 | |
d03f5d59 | 1134 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
3ce0a23d JG |
1135 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
1136 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
1137 | ||
1138 | /* Setup some CP states */ | |
1139 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); | |
1140 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); | |
1141 | ||
1142 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | | |
1143 | SYNC_WALKER | SYNC_ALIGNER)); | |
1144 | /* Setup various GPU states */ | |
1145 | if (rdev->family == CHIP_RV670) | |
1146 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); | |
1147 | ||
1148 | tmp = RREG32(SX_DEBUG_1); | |
1149 | tmp |= SMX_EVENT_RELEASE; | |
1150 | if ((rdev->family > CHIP_R600)) | |
1151 | tmp |= ENABLE_NEW_SMX_ADDRESS; | |
1152 | WREG32(SX_DEBUG_1, tmp); | |
1153 | ||
1154 | if (((rdev->family) == CHIP_R600) || | |
1155 | ((rdev->family) == CHIP_RV630) || | |
1156 | ((rdev->family) == CHIP_RV610) || | |
1157 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1158 | ((rdev->family) == CHIP_RS780) || |
1159 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1160 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
1161 | } else { | |
1162 | WREG32(DB_DEBUG, 0); | |
1163 | } | |
1164 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | | |
1165 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); | |
1166 | ||
1167 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1168 | WREG32(VGT_NUM_INSTANCES, 0); | |
1169 | ||
1170 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); | |
1171 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); | |
1172 | ||
1173 | tmp = RREG32(SQ_MS_FIFO_SIZES); | |
1174 | if (((rdev->family) == CHIP_RV610) || | |
1175 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1176 | ((rdev->family) == CHIP_RS780) || |
1177 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1178 | tmp = (CACHE_FIFO_SIZE(0xa) | |
1179 | FETCH_FIFO_HIWATER(0xa) | | |
1180 | DONE_FIFO_HIWATER(0xe0) | | |
1181 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
1182 | } else if (((rdev->family) == CHIP_R600) || | |
1183 | ((rdev->family) == CHIP_RV630)) { | |
1184 | tmp &= ~DONE_FIFO_HIWATER(0xff); | |
1185 | tmp |= DONE_FIFO_HIWATER(0x4); | |
1186 | } | |
1187 | WREG32(SQ_MS_FIFO_SIZES, tmp); | |
1188 | ||
1189 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
1190 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
1191 | */ | |
1192 | sq_config = RREG32(SQ_CONFIG); | |
1193 | sq_config &= ~(PS_PRIO(3) | | |
1194 | VS_PRIO(3) | | |
1195 | GS_PRIO(3) | | |
1196 | ES_PRIO(3)); | |
1197 | sq_config |= (DX9_CONSTS | | |
1198 | VC_ENABLE | | |
1199 | PS_PRIO(0) | | |
1200 | VS_PRIO(1) | | |
1201 | GS_PRIO(2) | | |
1202 | ES_PRIO(3)); | |
1203 | ||
1204 | if ((rdev->family) == CHIP_R600) { | |
1205 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | | |
1206 | NUM_VS_GPRS(124) | | |
1207 | NUM_CLAUSE_TEMP_GPRS(4)); | |
1208 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | | |
1209 | NUM_ES_GPRS(0)); | |
1210 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | | |
1211 | NUM_VS_THREADS(48) | | |
1212 | NUM_GS_THREADS(4) | | |
1213 | NUM_ES_THREADS(4)); | |
1214 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | | |
1215 | NUM_VS_STACK_ENTRIES(128)); | |
1216 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | | |
1217 | NUM_ES_STACK_ENTRIES(0)); | |
1218 | } else if (((rdev->family) == CHIP_RV610) || | |
1219 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1220 | ((rdev->family) == CHIP_RS780) || |
1221 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1222 | /* no vertex cache */ |
1223 | sq_config &= ~VC_ENABLE; | |
1224 | ||
1225 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1226 | NUM_VS_GPRS(44) | | |
1227 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1228 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1229 | NUM_ES_GPRS(17)); | |
1230 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1231 | NUM_VS_THREADS(78) | | |
1232 | NUM_GS_THREADS(4) | | |
1233 | NUM_ES_THREADS(31)); | |
1234 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1235 | NUM_VS_STACK_ENTRIES(40)); | |
1236 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1237 | NUM_ES_STACK_ENTRIES(16)); | |
1238 | } else if (((rdev->family) == CHIP_RV630) || | |
1239 | ((rdev->family) == CHIP_RV635)) { | |
1240 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1241 | NUM_VS_GPRS(44) | | |
1242 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1243 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | | |
1244 | NUM_ES_GPRS(18)); | |
1245 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1246 | NUM_VS_THREADS(78) | | |
1247 | NUM_GS_THREADS(4) | | |
1248 | NUM_ES_THREADS(31)); | |
1249 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1250 | NUM_VS_STACK_ENTRIES(40)); | |
1251 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1252 | NUM_ES_STACK_ENTRIES(16)); | |
1253 | } else if ((rdev->family) == CHIP_RV670) { | |
1254 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1255 | NUM_VS_GPRS(44) | | |
1256 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1257 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1258 | NUM_ES_GPRS(17)); | |
1259 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1260 | NUM_VS_THREADS(78) | | |
1261 | NUM_GS_THREADS(4) | | |
1262 | NUM_ES_THREADS(31)); | |
1263 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | | |
1264 | NUM_VS_STACK_ENTRIES(64)); | |
1265 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | | |
1266 | NUM_ES_STACK_ENTRIES(64)); | |
1267 | } | |
1268 | ||
1269 | WREG32(SQ_CONFIG, sq_config); | |
1270 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1271 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1272 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1273 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1274 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1275 | ||
1276 | if (((rdev->family) == CHIP_RV610) || | |
1277 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1278 | ((rdev->family) == CHIP_RS780) || |
1279 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1280 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
1281 | } else { | |
1282 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); | |
1283 | } | |
1284 | ||
1285 | /* More default values. 2D/3D driver should adjust as needed */ | |
1286 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | | |
1287 | S1_X(0x4) | S1_Y(0xc))); | |
1288 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | | |
1289 | S1_X(0x2) | S1_Y(0x2) | | |
1290 | S2_X(0xa) | S2_Y(0x6) | | |
1291 | S3_X(0x6) | S3_Y(0xa))); | |
1292 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | | |
1293 | S1_X(0x4) | S1_Y(0xc) | | |
1294 | S2_X(0x1) | S2_Y(0x6) | | |
1295 | S3_X(0xa) | S3_Y(0xe))); | |
1296 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | | |
1297 | S5_X(0x0) | S5_Y(0x0) | | |
1298 | S6_X(0xb) | S6_Y(0x4) | | |
1299 | S7_X(0x7) | S7_Y(0x8))); | |
1300 | ||
1301 | WREG32(VGT_STRMOUT_EN, 0); | |
1302 | tmp = rdev->config.r600.max_pipes * 16; | |
1303 | switch (rdev->family) { | |
1304 | case CHIP_RV610: | |
3ce0a23d | 1305 | case CHIP_RV620: |
ee59f2b4 AD |
1306 | case CHIP_RS780: |
1307 | case CHIP_RS880: | |
3ce0a23d JG |
1308 | tmp += 32; |
1309 | break; | |
1310 | case CHIP_RV670: | |
1311 | tmp += 128; | |
1312 | break; | |
1313 | default: | |
1314 | break; | |
1315 | } | |
1316 | if (tmp > 256) { | |
1317 | tmp = 256; | |
1318 | } | |
1319 | WREG32(VGT_ES_PER_GS, 128); | |
1320 | WREG32(VGT_GS_PER_ES, tmp); | |
1321 | WREG32(VGT_GS_PER_VS, 2); | |
1322 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
1323 | ||
1324 | /* more default values. 2D/3D driver should adjust as needed */ | |
1325 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
1326 | WREG32(VGT_STRMOUT_EN, 0); | |
1327 | WREG32(SX_MISC, 0); | |
1328 | WREG32(PA_SC_MODE_CNTL, 0); | |
1329 | WREG32(PA_SC_AA_CONFIG, 0); | |
1330 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
1331 | WREG32(SPI_INPUT_Z, 0); | |
1332 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
1333 | WREG32(CB_COLOR7_FRAG, 0); | |
1334 | ||
1335 | /* Clear render buffer base addresses */ | |
1336 | WREG32(CB_COLOR0_BASE, 0); | |
1337 | WREG32(CB_COLOR1_BASE, 0); | |
1338 | WREG32(CB_COLOR2_BASE, 0); | |
1339 | WREG32(CB_COLOR3_BASE, 0); | |
1340 | WREG32(CB_COLOR4_BASE, 0); | |
1341 | WREG32(CB_COLOR5_BASE, 0); | |
1342 | WREG32(CB_COLOR6_BASE, 0); | |
1343 | WREG32(CB_COLOR7_BASE, 0); | |
1344 | WREG32(CB_COLOR7_FRAG, 0); | |
1345 | ||
1346 | switch (rdev->family) { | |
1347 | case CHIP_RV610: | |
3ce0a23d | 1348 | case CHIP_RV620: |
ee59f2b4 AD |
1349 | case CHIP_RS780: |
1350 | case CHIP_RS880: | |
3ce0a23d JG |
1351 | tmp = TC_L2_SIZE(8); |
1352 | break; | |
1353 | case CHIP_RV630: | |
1354 | case CHIP_RV635: | |
1355 | tmp = TC_L2_SIZE(4); | |
1356 | break; | |
1357 | case CHIP_R600: | |
1358 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; | |
1359 | break; | |
1360 | default: | |
1361 | tmp = TC_L2_SIZE(0); | |
1362 | break; | |
1363 | } | |
1364 | WREG32(TC_CNTL, tmp); | |
1365 | ||
1366 | tmp = RREG32(HDP_HOST_PATH_CNTL); | |
1367 | WREG32(HDP_HOST_PATH_CNTL, tmp); | |
1368 | ||
1369 | tmp = RREG32(ARB_POP); | |
1370 | tmp |= ENABLE_TC128; | |
1371 | WREG32(ARB_POP, tmp); | |
1372 | ||
1373 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1374 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
1375 | NUM_CLIP_SEQ(3))); | |
1376 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); | |
1377 | } | |
1378 | ||
1379 | ||
771fe6b9 JG |
1380 | /* |
1381 | * Indirect registers accessor | |
1382 | */ | |
3ce0a23d JG |
1383 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
1384 | { | |
1385 | u32 r; | |
1386 | ||
1387 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1388 | (void)RREG32(PCIE_PORT_INDEX); | |
1389 | r = RREG32(PCIE_PORT_DATA); | |
1390 | return r; | |
1391 | } | |
1392 | ||
1393 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1394 | { | |
1395 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1396 | (void)RREG32(PCIE_PORT_INDEX); | |
1397 | WREG32(PCIE_PORT_DATA, (v)); | |
1398 | (void)RREG32(PCIE_PORT_DATA); | |
1399 | } | |
1400 | ||
3ce0a23d JG |
1401 | /* |
1402 | * CP & Ring | |
1403 | */ | |
1404 | void r600_cp_stop(struct radeon_device *rdev) | |
1405 | { | |
1406 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1407 | } | |
1408 | ||
d8f60cfc | 1409 | int r600_init_microcode(struct radeon_device *rdev) |
3ce0a23d JG |
1410 | { |
1411 | struct platform_device *pdev; | |
1412 | const char *chip_name; | |
d8f60cfc AD |
1413 | const char *rlc_chip_name; |
1414 | size_t pfp_req_size, me_req_size, rlc_req_size; | |
3ce0a23d JG |
1415 | char fw_name[30]; |
1416 | int err; | |
1417 | ||
1418 | DRM_DEBUG("\n"); | |
1419 | ||
1420 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); | |
1421 | err = IS_ERR(pdev); | |
1422 | if (err) { | |
1423 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
1424 | return -EINVAL; | |
1425 | } | |
1426 | ||
1427 | switch (rdev->family) { | |
d8f60cfc AD |
1428 | case CHIP_R600: |
1429 | chip_name = "R600"; | |
1430 | rlc_chip_name = "R600"; | |
1431 | break; | |
1432 | case CHIP_RV610: | |
1433 | chip_name = "RV610"; | |
1434 | rlc_chip_name = "R600"; | |
1435 | break; | |
1436 | case CHIP_RV630: | |
1437 | chip_name = "RV630"; | |
1438 | rlc_chip_name = "R600"; | |
1439 | break; | |
1440 | case CHIP_RV620: | |
1441 | chip_name = "RV620"; | |
1442 | rlc_chip_name = "R600"; | |
1443 | break; | |
1444 | case CHIP_RV635: | |
1445 | chip_name = "RV635"; | |
1446 | rlc_chip_name = "R600"; | |
1447 | break; | |
1448 | case CHIP_RV670: | |
1449 | chip_name = "RV670"; | |
1450 | rlc_chip_name = "R600"; | |
1451 | break; | |
3ce0a23d | 1452 | case CHIP_RS780: |
d8f60cfc AD |
1453 | case CHIP_RS880: |
1454 | chip_name = "RS780"; | |
1455 | rlc_chip_name = "R600"; | |
1456 | break; | |
1457 | case CHIP_RV770: | |
1458 | chip_name = "RV770"; | |
1459 | rlc_chip_name = "R700"; | |
1460 | break; | |
3ce0a23d | 1461 | case CHIP_RV730: |
d8f60cfc AD |
1462 | case CHIP_RV740: |
1463 | chip_name = "RV730"; | |
1464 | rlc_chip_name = "R700"; | |
1465 | break; | |
1466 | case CHIP_RV710: | |
1467 | chip_name = "RV710"; | |
1468 | rlc_chip_name = "R700"; | |
1469 | break; | |
3ce0a23d JG |
1470 | default: BUG(); |
1471 | } | |
1472 | ||
1473 | if (rdev->family >= CHIP_RV770) { | |
1474 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; | |
1475 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
d8f60cfc | 1476 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1477 | } else { |
1478 | pfp_req_size = PFP_UCODE_SIZE * 4; | |
1479 | me_req_size = PM4_UCODE_SIZE * 12; | |
d8f60cfc | 1480 | rlc_req_size = RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1481 | } |
1482 | ||
d8f60cfc | 1483 | DRM_INFO("Loading %s Microcode\n", chip_name); |
3ce0a23d JG |
1484 | |
1485 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
1486 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); | |
1487 | if (err) | |
1488 | goto out; | |
1489 | if (rdev->pfp_fw->size != pfp_req_size) { | |
1490 | printk(KERN_ERR | |
1491 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
1492 | rdev->pfp_fw->size, fw_name); | |
1493 | err = -EINVAL; | |
1494 | goto out; | |
1495 | } | |
1496 | ||
1497 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
1498 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); | |
1499 | if (err) | |
1500 | goto out; | |
1501 | if (rdev->me_fw->size != me_req_size) { | |
1502 | printk(KERN_ERR | |
1503 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
1504 | rdev->me_fw->size, fw_name); | |
1505 | err = -EINVAL; | |
1506 | } | |
d8f60cfc AD |
1507 | |
1508 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
1509 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); | |
1510 | if (err) | |
1511 | goto out; | |
1512 | if (rdev->rlc_fw->size != rlc_req_size) { | |
1513 | printk(KERN_ERR | |
1514 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", | |
1515 | rdev->rlc_fw->size, fw_name); | |
1516 | err = -EINVAL; | |
1517 | } | |
1518 | ||
3ce0a23d JG |
1519 | out: |
1520 | platform_device_unregister(pdev); | |
1521 | ||
1522 | if (err) { | |
1523 | if (err != -EINVAL) | |
1524 | printk(KERN_ERR | |
1525 | "r600_cp: Failed to load firmware \"%s\"\n", | |
1526 | fw_name); | |
1527 | release_firmware(rdev->pfp_fw); | |
1528 | rdev->pfp_fw = NULL; | |
1529 | release_firmware(rdev->me_fw); | |
1530 | rdev->me_fw = NULL; | |
d8f60cfc AD |
1531 | release_firmware(rdev->rlc_fw); |
1532 | rdev->rlc_fw = NULL; | |
3ce0a23d JG |
1533 | } |
1534 | return err; | |
1535 | } | |
1536 | ||
1537 | static int r600_cp_load_microcode(struct radeon_device *rdev) | |
1538 | { | |
1539 | const __be32 *fw_data; | |
1540 | int i; | |
1541 | ||
1542 | if (!rdev->me_fw || !rdev->pfp_fw) | |
1543 | return -EINVAL; | |
1544 | ||
1545 | r600_cp_stop(rdev); | |
1546 | ||
1547 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
1548 | ||
1549 | /* Reset cp */ | |
1550 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
1551 | RREG32(GRBM_SOFT_RESET); | |
1552 | mdelay(15); | |
1553 | WREG32(GRBM_SOFT_RESET, 0); | |
1554 | ||
1555 | WREG32(CP_ME_RAM_WADDR, 0); | |
1556 | ||
1557 | fw_data = (const __be32 *)rdev->me_fw->data; | |
1558 | WREG32(CP_ME_RAM_WADDR, 0); | |
1559 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) | |
1560 | WREG32(CP_ME_RAM_DATA, | |
1561 | be32_to_cpup(fw_data++)); | |
1562 | ||
1563 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
1564 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1565 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
1566 | WREG32(CP_PFP_UCODE_DATA, | |
1567 | be32_to_cpup(fw_data++)); | |
1568 | ||
1569 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1570 | WREG32(CP_ME_RAM_WADDR, 0); | |
1571 | WREG32(CP_ME_RAM_RADDR, 0); | |
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | int r600_cp_start(struct radeon_device *rdev) | |
1576 | { | |
1577 | int r; | |
1578 | uint32_t cp_me; | |
1579 | ||
1580 | r = radeon_ring_lock(rdev, 7); | |
1581 | if (r) { | |
1582 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1583 | return r; | |
1584 | } | |
1585 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | |
1586 | radeon_ring_write(rdev, 0x1); | |
1587 | if (rdev->family < CHIP_RV770) { | |
1588 | radeon_ring_write(rdev, 0x3); | |
1589 | radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); | |
1590 | } else { | |
1591 | radeon_ring_write(rdev, 0x0); | |
1592 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); | |
1593 | } | |
1594 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
1595 | radeon_ring_write(rdev, 0); | |
1596 | radeon_ring_write(rdev, 0); | |
1597 | radeon_ring_unlock_commit(rdev); | |
1598 | ||
1599 | cp_me = 0xff; | |
1600 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | |
1601 | return 0; | |
1602 | } | |
1603 | ||
1604 | int r600_cp_resume(struct radeon_device *rdev) | |
1605 | { | |
1606 | u32 tmp; | |
1607 | u32 rb_bufsz; | |
1608 | int r; | |
1609 | ||
1610 | /* Reset cp */ | |
1611 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
1612 | RREG32(GRBM_SOFT_RESET); | |
1613 | mdelay(15); | |
1614 | WREG32(GRBM_SOFT_RESET, 0); | |
1615 | ||
1616 | /* Set ring buffer size */ | |
1617 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); | |
d6f28938 | 1618 | tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3ce0a23d | 1619 | #ifdef __BIG_ENDIAN |
d6f28938 | 1620 | tmp |= BUF_SWAP_32BIT; |
3ce0a23d | 1621 | #endif |
d6f28938 | 1622 | WREG32(CP_RB_CNTL, tmp); |
3ce0a23d JG |
1623 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
1624 | ||
1625 | /* Set the write pointer delay */ | |
1626 | WREG32(CP_RB_WPTR_DELAY, 0); | |
1627 | ||
1628 | /* Initialize the ring buffer's read and write pointers */ | |
3ce0a23d JG |
1629 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
1630 | WREG32(CP_RB_RPTR_WR, 0); | |
1631 | WREG32(CP_RB_WPTR, 0); | |
1632 | WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); | |
1633 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); | |
1634 | mdelay(1); | |
1635 | WREG32(CP_RB_CNTL, tmp); | |
1636 | ||
1637 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); | |
1638 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | |
1639 | ||
1640 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | |
1641 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | |
1642 | ||
1643 | r600_cp_start(rdev); | |
1644 | rdev->cp.ready = true; | |
1645 | r = radeon_ring_test(rdev); | |
1646 | if (r) { | |
1647 | rdev->cp.ready = false; | |
1648 | return r; | |
1649 | } | |
1650 | return 0; | |
1651 | } | |
1652 | ||
1653 | void r600_cp_commit(struct radeon_device *rdev) | |
1654 | { | |
1655 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | |
1656 | (void)RREG32(CP_RB_WPTR); | |
1657 | } | |
1658 | ||
1659 | void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
1660 | { | |
1661 | u32 rb_bufsz; | |
1662 | ||
1663 | /* Align ring size */ | |
1664 | rb_bufsz = drm_order(ring_size / 8); | |
1665 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
1666 | rdev->cp.ring_size = ring_size; | |
1667 | rdev->cp.align_mask = 16 - 1; | |
1668 | } | |
1669 | ||
655efd3d JG |
1670 | void r600_cp_fini(struct radeon_device *rdev) |
1671 | { | |
1672 | r600_cp_stop(rdev); | |
1673 | radeon_ring_fini(rdev); | |
1674 | } | |
1675 | ||
3ce0a23d JG |
1676 | |
1677 | /* | |
1678 | * GPU scratch registers helpers function. | |
1679 | */ | |
1680 | void r600_scratch_init(struct radeon_device *rdev) | |
1681 | { | |
1682 | int i; | |
1683 | ||
1684 | rdev->scratch.num_reg = 7; | |
1685 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
1686 | rdev->scratch.free[i] = true; | |
1687 | rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); | |
1688 | } | |
1689 | } | |
1690 | ||
1691 | int r600_ring_test(struct radeon_device *rdev) | |
1692 | { | |
1693 | uint32_t scratch; | |
1694 | uint32_t tmp = 0; | |
1695 | unsigned i; | |
1696 | int r; | |
1697 | ||
1698 | r = radeon_scratch_get(rdev, &scratch); | |
1699 | if (r) { | |
1700 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
1701 | return r; | |
1702 | } | |
1703 | WREG32(scratch, 0xCAFEDEAD); | |
1704 | r = radeon_ring_lock(rdev, 3); | |
1705 | if (r) { | |
1706 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1707 | radeon_scratch_free(rdev, scratch); | |
1708 | return r; | |
1709 | } | |
1710 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1711 | radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
1712 | radeon_ring_write(rdev, 0xDEADBEEF); | |
1713 | radeon_ring_unlock_commit(rdev); | |
1714 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1715 | tmp = RREG32(scratch); | |
1716 | if (tmp == 0xDEADBEEF) | |
1717 | break; | |
1718 | DRM_UDELAY(1); | |
1719 | } | |
1720 | if (i < rdev->usec_timeout) { | |
1721 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
1722 | } else { | |
1723 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", | |
1724 | scratch, tmp); | |
1725 | r = -EINVAL; | |
1726 | } | |
1727 | radeon_scratch_free(rdev, scratch); | |
1728 | return r; | |
1729 | } | |
1730 | ||
81cc35bf JG |
1731 | void r600_wb_disable(struct radeon_device *rdev) |
1732 | { | |
4c788679 JG |
1733 | int r; |
1734 | ||
81cc35bf JG |
1735 | WREG32(SCRATCH_UMSK, 0); |
1736 | if (rdev->wb.wb_obj) { | |
4c788679 JG |
1737 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
1738 | if (unlikely(r != 0)) | |
1739 | return; | |
1740 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
1741 | radeon_bo_unpin(rdev->wb.wb_obj); | |
1742 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
81cc35bf JG |
1743 | } |
1744 | } | |
1745 | ||
1746 | void r600_wb_fini(struct radeon_device *rdev) | |
1747 | { | |
1748 | r600_wb_disable(rdev); | |
1749 | if (rdev->wb.wb_obj) { | |
4c788679 | 1750 | radeon_bo_unref(&rdev->wb.wb_obj); |
81cc35bf JG |
1751 | rdev->wb.wb = NULL; |
1752 | rdev->wb.wb_obj = NULL; | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | int r600_wb_enable(struct radeon_device *rdev) | |
3ce0a23d JG |
1757 | { |
1758 | int r; | |
1759 | ||
1760 | if (rdev->wb.wb_obj == NULL) { | |
4c788679 JG |
1761 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
1762 | RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); | |
3ce0a23d | 1763 | if (r) { |
4c788679 | 1764 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
3ce0a23d JG |
1765 | return r; |
1766 | } | |
4c788679 JG |
1767 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
1768 | if (unlikely(r != 0)) { | |
1769 | r600_wb_fini(rdev); | |
3ce0a23d JG |
1770 | return r; |
1771 | } | |
4c788679 | 1772 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
81cc35bf | 1773 | &rdev->wb.gpu_addr); |
3ce0a23d | 1774 | if (r) { |
4c788679 JG |
1775 | radeon_bo_unreserve(rdev->wb.wb_obj); |
1776 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); | |
81cc35bf | 1777 | r600_wb_fini(rdev); |
3ce0a23d JG |
1778 | return r; |
1779 | } | |
4c788679 JG |
1780 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
1781 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
3ce0a23d | 1782 | if (r) { |
4c788679 | 1783 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
81cc35bf | 1784 | r600_wb_fini(rdev); |
3ce0a23d JG |
1785 | return r; |
1786 | } | |
1787 | } | |
1788 | WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); | |
1789 | WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); | |
1790 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); | |
1791 | WREG32(SCRATCH_UMSK, 0xff); | |
1792 | return 0; | |
1793 | } | |
1794 | ||
3ce0a23d JG |
1795 | void r600_fence_ring_emit(struct radeon_device *rdev, |
1796 | struct radeon_fence *fence) | |
1797 | { | |
d8f60cfc | 1798 | /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ |
44224c3f AD |
1799 | |
1800 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); | |
1801 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); | |
1802 | /* wait for 3D idle clean */ | |
1803 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1804 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
1805 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | |
3ce0a23d JG |
1806 | /* Emit fence sequence & fire IRQ */ |
1807 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1808 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
1809 | radeon_ring_write(rdev, fence->seq); | |
d8f60cfc AD |
1810 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
1811 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); | |
1812 | radeon_ring_write(rdev, RB_INT_STAT); | |
3ce0a23d JG |
1813 | } |
1814 | ||
3ce0a23d JG |
1815 | int r600_copy_blit(struct radeon_device *rdev, |
1816 | uint64_t src_offset, uint64_t dst_offset, | |
1817 | unsigned num_pages, struct radeon_fence *fence) | |
1818 | { | |
ff82f052 JG |
1819 | int r; |
1820 | ||
1821 | mutex_lock(&rdev->r600_blit.mutex); | |
1822 | rdev->r600_blit.vb_ib = NULL; | |
1823 | r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); | |
1824 | if (r) { | |
1825 | if (rdev->r600_blit.vb_ib) | |
1826 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); | |
1827 | mutex_unlock(&rdev->r600_blit.mutex); | |
1828 | return r; | |
1829 | } | |
a77f1718 | 1830 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
3ce0a23d | 1831 | r600_blit_done_copy(rdev, fence); |
ff82f052 | 1832 | mutex_unlock(&rdev->r600_blit.mutex); |
3ce0a23d JG |
1833 | return 0; |
1834 | } | |
1835 | ||
3ce0a23d JG |
1836 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
1837 | uint32_t tiling_flags, uint32_t pitch, | |
1838 | uint32_t offset, uint32_t obj_size) | |
1839 | { | |
1840 | /* FIXME: implement */ | |
1841 | return 0; | |
1842 | } | |
1843 | ||
1844 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |
1845 | { | |
1846 | /* FIXME: implement */ | |
1847 | } | |
1848 | ||
1849 | ||
1850 | bool r600_card_posted(struct radeon_device *rdev) | |
1851 | { | |
1852 | uint32_t reg; | |
1853 | ||
1854 | /* first check CRTCs */ | |
1855 | reg = RREG32(D1CRTC_CONTROL) | | |
1856 | RREG32(D2CRTC_CONTROL); | |
1857 | if (reg & CRTC_EN) | |
1858 | return true; | |
1859 | ||
1860 | /* then check MEM_SIZE, in case the crtcs are off */ | |
1861 | if (RREG32(CONFIG_MEMSIZE)) | |
1862 | return true; | |
1863 | ||
1864 | return false; | |
1865 | } | |
1866 | ||
fc30b8ef | 1867 | int r600_startup(struct radeon_device *rdev) |
3ce0a23d JG |
1868 | { |
1869 | int r; | |
1870 | ||
779720a3 AD |
1871 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
1872 | r = r600_init_microcode(rdev); | |
1873 | if (r) { | |
1874 | DRM_ERROR("Failed to load firmware!\n"); | |
1875 | return r; | |
1876 | } | |
1877 | } | |
1878 | ||
a3c1945a | 1879 | r600_mc_program(rdev); |
1a029b76 JG |
1880 | if (rdev->flags & RADEON_IS_AGP) { |
1881 | r600_agp_enable(rdev); | |
1882 | } else { | |
1883 | r = r600_pcie_gart_enable(rdev); | |
1884 | if (r) | |
1885 | return r; | |
1886 | } | |
3ce0a23d | 1887 | r600_gpu_init(rdev); |
c38c7b64 JG |
1888 | r = r600_blit_init(rdev); |
1889 | if (r) { | |
1890 | r600_blit_fini(rdev); | |
1891 | rdev->asic->copy = NULL; | |
1892 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | |
1893 | } | |
ff82f052 JG |
1894 | /* pin copy shader into vram */ |
1895 | if (rdev->r600_blit.shader_obj) { | |
1896 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
1897 | if (unlikely(r != 0)) | |
1898 | return r; | |
1899 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, | |
1900 | &rdev->r600_blit.shader_gpu_addr); | |
1901 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
7923c615 | 1902 | if (r) { |
ff82f052 | 1903 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
7923c615 AD |
1904 | return r; |
1905 | } | |
1906 | } | |
d8f60cfc | 1907 | /* Enable IRQ */ |
d8f60cfc AD |
1908 | r = r600_irq_init(rdev); |
1909 | if (r) { | |
1910 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
1911 | radeon_irq_kms_fini(rdev); | |
1912 | return r; | |
1913 | } | |
1914 | r600_irq_set(rdev); | |
1915 | ||
3ce0a23d JG |
1916 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1917 | if (r) | |
1918 | return r; | |
1919 | r = r600_cp_load_microcode(rdev); | |
1920 | if (r) | |
1921 | return r; | |
1922 | r = r600_cp_resume(rdev); | |
1923 | if (r) | |
1924 | return r; | |
81cc35bf JG |
1925 | /* write back buffer are not vital so don't worry about failure */ |
1926 | r600_wb_enable(rdev); | |
3ce0a23d JG |
1927 | return 0; |
1928 | } | |
1929 | ||
28d52043 DA |
1930 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
1931 | { | |
1932 | uint32_t temp; | |
1933 | ||
1934 | temp = RREG32(CONFIG_CNTL); | |
1935 | if (state == false) { | |
1936 | temp &= ~(1<<0); | |
1937 | temp |= (1<<1); | |
1938 | } else { | |
1939 | temp &= ~(1<<1); | |
1940 | } | |
1941 | WREG32(CONFIG_CNTL, temp); | |
1942 | } | |
1943 | ||
fc30b8ef DA |
1944 | int r600_resume(struct radeon_device *rdev) |
1945 | { | |
1946 | int r; | |
1947 | ||
1a029b76 JG |
1948 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
1949 | * posting will perform necessary task to bring back GPU into good | |
1950 | * shape. | |
1951 | */ | |
fc30b8ef | 1952 | /* post card */ |
e7d40b9a | 1953 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef DA |
1954 | /* Initialize clocks */ |
1955 | r = radeon_clocks_init(rdev); | |
1956 | if (r) { | |
1957 | return r; | |
1958 | } | |
1959 | ||
1960 | r = r600_startup(rdev); | |
1961 | if (r) { | |
1962 | DRM_ERROR("r600 startup failed on resume\n"); | |
1963 | return r; | |
1964 | } | |
1965 | ||
62a8ea3f | 1966 | r = r600_ib_test(rdev); |
fc30b8ef DA |
1967 | if (r) { |
1968 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); | |
1969 | return r; | |
1970 | } | |
38fd2c6f RM |
1971 | |
1972 | r = r600_audio_init(rdev); | |
1973 | if (r) { | |
1974 | DRM_ERROR("radeon: audio resume failed\n"); | |
1975 | return r; | |
1976 | } | |
1977 | ||
fc30b8ef DA |
1978 | return r; |
1979 | } | |
1980 | ||
3ce0a23d JG |
1981 | int r600_suspend(struct radeon_device *rdev) |
1982 | { | |
4c788679 JG |
1983 | int r; |
1984 | ||
38fd2c6f | 1985 | r600_audio_fini(rdev); |
3ce0a23d JG |
1986 | /* FIXME: we should wait for ring to be empty */ |
1987 | r600_cp_stop(rdev); | |
bc1a631e | 1988 | rdev->cp.ready = false; |
0c45249f | 1989 | r600_irq_suspend(rdev); |
81cc35bf | 1990 | r600_wb_disable(rdev); |
4aac0473 | 1991 | r600_pcie_gart_disable(rdev); |
bc1a631e | 1992 | /* unpin shaders bo */ |
30d2d9a5 JG |
1993 | if (rdev->r600_blit.shader_obj) { |
1994 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
1995 | if (!r) { | |
1996 | radeon_bo_unpin(rdev->r600_blit.shader_obj); | |
1997 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
1998 | } | |
1999 | } | |
3ce0a23d JG |
2000 | return 0; |
2001 | } | |
2002 | ||
2003 | /* Plan is to move initialization in that function and use | |
2004 | * helper function so that radeon_device_init pretty much | |
2005 | * do nothing more than calling asic specific function. This | |
2006 | * should also allow to remove a bunch of callback function | |
2007 | * like vram_info. | |
2008 | */ | |
2009 | int r600_init(struct radeon_device *rdev) | |
771fe6b9 | 2010 | { |
3ce0a23d | 2011 | int r; |
771fe6b9 | 2012 | |
3ce0a23d JG |
2013 | r = radeon_dummy_page_init(rdev); |
2014 | if (r) | |
2015 | return r; | |
2016 | if (r600_debugfs_mc_info_init(rdev)) { | |
2017 | DRM_ERROR("Failed to register debugfs file for mc !\n"); | |
2018 | } | |
2019 | /* This don't do much */ | |
2020 | r = radeon_gem_init(rdev); | |
2021 | if (r) | |
2022 | return r; | |
2023 | /* Read BIOS */ | |
2024 | if (!radeon_get_bios(rdev)) { | |
2025 | if (ASIC_IS_AVIVO(rdev)) | |
2026 | return -EINVAL; | |
2027 | } | |
2028 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
2029 | if (!rdev->is_atom_bios) { |
2030 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 2031 | return -EINVAL; |
e7d40b9a | 2032 | } |
3ce0a23d JG |
2033 | r = radeon_atombios_init(rdev); |
2034 | if (r) | |
2035 | return r; | |
2036 | /* Post card if necessary */ | |
72542d77 DA |
2037 | if (!r600_card_posted(rdev)) { |
2038 | if (!rdev->bios) { | |
2039 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
2040 | return -EINVAL; | |
2041 | } | |
3ce0a23d JG |
2042 | DRM_INFO("GPU not posted. posting now...\n"); |
2043 | atom_asic_init(rdev->mode_info.atom_context); | |
2044 | } | |
2045 | /* Initialize scratch registers */ | |
2046 | r600_scratch_init(rdev); | |
2047 | /* Initialize surface registers */ | |
2048 | radeon_surface_init(rdev); | |
7433874e | 2049 | /* Initialize clocks */ |
5e6dde7e | 2050 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d JG |
2051 | r = radeon_clocks_init(rdev); |
2052 | if (r) | |
2053 | return r; | |
7433874e RM |
2054 | /* Initialize power management */ |
2055 | radeon_pm_init(rdev); | |
3ce0a23d JG |
2056 | /* Fence driver */ |
2057 | r = radeon_fence_driver_init(rdev); | |
2058 | if (r) | |
2059 | return r; | |
700a0cc0 JG |
2060 | if (rdev->flags & RADEON_IS_AGP) { |
2061 | r = radeon_agp_init(rdev); | |
2062 | if (r) | |
2063 | radeon_agp_disable(rdev); | |
2064 | } | |
3ce0a23d | 2065 | r = r600_mc_init(rdev); |
b574f251 | 2066 | if (r) |
3ce0a23d | 2067 | return r; |
3ce0a23d | 2068 | /* Memory manager */ |
4c788679 | 2069 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
2070 | if (r) |
2071 | return r; | |
d8f60cfc AD |
2072 | |
2073 | r = radeon_irq_kms_init(rdev); | |
2074 | if (r) | |
2075 | return r; | |
2076 | ||
3ce0a23d JG |
2077 | rdev->cp.ring_obj = NULL; |
2078 | r600_ring_init(rdev, 1024 * 1024); | |
2079 | ||
d8f60cfc AD |
2080 | rdev->ih.ring_obj = NULL; |
2081 | r600_ih_ring_init(rdev, 64 * 1024); | |
3ce0a23d | 2082 | |
4aac0473 JG |
2083 | r = r600_pcie_gart_init(rdev); |
2084 | if (r) | |
2085 | return r; | |
2086 | ||
779720a3 | 2087 | rdev->accel_working = true; |
fc30b8ef | 2088 | r = r600_startup(rdev); |
3ce0a23d | 2089 | if (r) { |
655efd3d JG |
2090 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
2091 | r600_cp_fini(rdev); | |
75c81298 | 2092 | r600_wb_fini(rdev); |
655efd3d JG |
2093 | r600_irq_fini(rdev); |
2094 | radeon_irq_kms_fini(rdev); | |
75c81298 | 2095 | r600_pcie_gart_fini(rdev); |
733289c2 | 2096 | rdev->accel_working = false; |
3ce0a23d | 2097 | } |
733289c2 JG |
2098 | if (rdev->accel_working) { |
2099 | r = radeon_ib_pool_init(rdev); | |
2100 | if (r) { | |
db96380e | 2101 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
733289c2 | 2102 | rdev->accel_working = false; |
db96380e JG |
2103 | } else { |
2104 | r = r600_ib_test(rdev); | |
2105 | if (r) { | |
2106 | dev_err(rdev->dev, "IB test failed (%d).\n", r); | |
2107 | rdev->accel_working = false; | |
2108 | } | |
733289c2 | 2109 | } |
3ce0a23d | 2110 | } |
dafc3bd5 CK |
2111 | |
2112 | r = r600_audio_init(rdev); | |
2113 | if (r) | |
2114 | return r; /* TODO error handling */ | |
3ce0a23d JG |
2115 | return 0; |
2116 | } | |
2117 | ||
2118 | void r600_fini(struct radeon_device *rdev) | |
2119 | { | |
29fb52ca | 2120 | radeon_pm_fini(rdev); |
dafc3bd5 | 2121 | r600_audio_fini(rdev); |
3ce0a23d | 2122 | r600_blit_fini(rdev); |
655efd3d JG |
2123 | r600_cp_fini(rdev); |
2124 | r600_wb_fini(rdev); | |
d8f60cfc AD |
2125 | r600_irq_fini(rdev); |
2126 | radeon_irq_kms_fini(rdev); | |
4aac0473 | 2127 | r600_pcie_gart_fini(rdev); |
655efd3d | 2128 | radeon_agp_fini(rdev); |
3ce0a23d JG |
2129 | radeon_gem_fini(rdev); |
2130 | radeon_fence_driver_fini(rdev); | |
2131 | radeon_clocks_fini(rdev); | |
4c788679 | 2132 | radeon_bo_fini(rdev); |
e7d40b9a | 2133 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
2134 | kfree(rdev->bios); |
2135 | rdev->bios = NULL; | |
2136 | radeon_dummy_page_fini(rdev); | |
2137 | } | |
2138 | ||
2139 | ||
2140 | /* | |
2141 | * CS stuff | |
2142 | */ | |
2143 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
2144 | { | |
2145 | /* FIXME: implement */ | |
2146 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | |
2147 | radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); | |
2148 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | |
2149 | radeon_ring_write(rdev, ib->length_dw); | |
2150 | } | |
2151 | ||
2152 | int r600_ib_test(struct radeon_device *rdev) | |
2153 | { | |
2154 | struct radeon_ib *ib; | |
2155 | uint32_t scratch; | |
2156 | uint32_t tmp = 0; | |
2157 | unsigned i; | |
2158 | int r; | |
2159 | ||
2160 | r = radeon_scratch_get(rdev, &scratch); | |
2161 | if (r) { | |
2162 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
2163 | return r; | |
2164 | } | |
2165 | WREG32(scratch, 0xCAFEDEAD); | |
2166 | r = radeon_ib_get(rdev, &ib); | |
2167 | if (r) { | |
2168 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
2169 | return r; | |
2170 | } | |
2171 | ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); | |
2172 | ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2173 | ib->ptr[2] = 0xDEADBEEF; | |
2174 | ib->ptr[3] = PACKET2(0); | |
2175 | ib->ptr[4] = PACKET2(0); | |
2176 | ib->ptr[5] = PACKET2(0); | |
2177 | ib->ptr[6] = PACKET2(0); | |
2178 | ib->ptr[7] = PACKET2(0); | |
2179 | ib->ptr[8] = PACKET2(0); | |
2180 | ib->ptr[9] = PACKET2(0); | |
2181 | ib->ptr[10] = PACKET2(0); | |
2182 | ib->ptr[11] = PACKET2(0); | |
2183 | ib->ptr[12] = PACKET2(0); | |
2184 | ib->ptr[13] = PACKET2(0); | |
2185 | ib->ptr[14] = PACKET2(0); | |
2186 | ib->ptr[15] = PACKET2(0); | |
2187 | ib->length_dw = 16; | |
2188 | r = radeon_ib_schedule(rdev, ib); | |
2189 | if (r) { | |
2190 | radeon_scratch_free(rdev, scratch); | |
2191 | radeon_ib_free(rdev, &ib); | |
2192 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | |
2193 | return r; | |
2194 | } | |
2195 | r = radeon_fence_wait(ib->fence, false); | |
2196 | if (r) { | |
2197 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
2198 | return r; | |
2199 | } | |
2200 | for (i = 0; i < rdev->usec_timeout; i++) { | |
2201 | tmp = RREG32(scratch); | |
2202 | if (tmp == 0xDEADBEEF) | |
2203 | break; | |
2204 | DRM_UDELAY(1); | |
2205 | } | |
2206 | if (i < rdev->usec_timeout) { | |
2207 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
2208 | } else { | |
2209 | DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", | |
2210 | scratch, tmp); | |
2211 | r = -EINVAL; | |
2212 | } | |
2213 | radeon_scratch_free(rdev, scratch); | |
2214 | radeon_ib_free(rdev, &ib); | |
771fe6b9 JG |
2215 | return r; |
2216 | } | |
2217 | ||
d8f60cfc AD |
2218 | /* |
2219 | * Interrupts | |
2220 | * | |
2221 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty | |
2222 | * the same as the CP ring buffer, but in reverse. Rather than the CPU | |
2223 | * writing to the ring and the GPU consuming, the GPU writes to the ring | |
2224 | * and host consumes. As the host irq handler processes interrupts, it | |
2225 | * increments the rptr. When the rptr catches up with the wptr, all the | |
2226 | * current interrupts have been processed. | |
2227 | */ | |
2228 | ||
2229 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
2230 | { | |
2231 | u32 rb_bufsz; | |
2232 | ||
2233 | /* Align ring size */ | |
2234 | rb_bufsz = drm_order(ring_size / 4); | |
2235 | ring_size = (1 << rb_bufsz) * 4; | |
2236 | rdev->ih.ring_size = ring_size; | |
0c45249f JG |
2237 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
2238 | rdev->ih.rptr = 0; | |
d8f60cfc AD |
2239 | } |
2240 | ||
0c45249f | 2241 | static int r600_ih_ring_alloc(struct radeon_device *rdev) |
d8f60cfc AD |
2242 | { |
2243 | int r; | |
2244 | ||
d8f60cfc AD |
2245 | /* Allocate ring buffer */ |
2246 | if (rdev->ih.ring_obj == NULL) { | |
4c788679 JG |
2247 | r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, |
2248 | true, | |
2249 | RADEON_GEM_DOMAIN_GTT, | |
2250 | &rdev->ih.ring_obj); | |
d8f60cfc AD |
2251 | if (r) { |
2252 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); | |
2253 | return r; | |
2254 | } | |
4c788679 JG |
2255 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2256 | if (unlikely(r != 0)) | |
2257 | return r; | |
2258 | r = radeon_bo_pin(rdev->ih.ring_obj, | |
2259 | RADEON_GEM_DOMAIN_GTT, | |
2260 | &rdev->ih.gpu_addr); | |
d8f60cfc | 2261 | if (r) { |
4c788679 | 2262 | radeon_bo_unreserve(rdev->ih.ring_obj); |
d8f60cfc AD |
2263 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
2264 | return r; | |
2265 | } | |
4c788679 JG |
2266 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
2267 | (void **)&rdev->ih.ring); | |
2268 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
d8f60cfc AD |
2269 | if (r) { |
2270 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); | |
2271 | return r; | |
2272 | } | |
2273 | } | |
d8f60cfc AD |
2274 | return 0; |
2275 | } | |
2276 | ||
2277 | static void r600_ih_ring_fini(struct radeon_device *rdev) | |
2278 | { | |
4c788679 | 2279 | int r; |
d8f60cfc | 2280 | if (rdev->ih.ring_obj) { |
4c788679 JG |
2281 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2282 | if (likely(r == 0)) { | |
2283 | radeon_bo_kunmap(rdev->ih.ring_obj); | |
2284 | radeon_bo_unpin(rdev->ih.ring_obj); | |
2285 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
2286 | } | |
2287 | radeon_bo_unref(&rdev->ih.ring_obj); | |
d8f60cfc AD |
2288 | rdev->ih.ring = NULL; |
2289 | rdev->ih.ring_obj = NULL; | |
2290 | } | |
2291 | } | |
2292 | ||
2293 | static void r600_rlc_stop(struct radeon_device *rdev) | |
2294 | { | |
2295 | ||
2296 | if (rdev->family >= CHIP_RV770) { | |
2297 | /* r7xx asics need to soft reset RLC before halting */ | |
2298 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); | |
2299 | RREG32(SRBM_SOFT_RESET); | |
2300 | udelay(15000); | |
2301 | WREG32(SRBM_SOFT_RESET, 0); | |
2302 | RREG32(SRBM_SOFT_RESET); | |
2303 | } | |
2304 | ||
2305 | WREG32(RLC_CNTL, 0); | |
2306 | } | |
2307 | ||
2308 | static void r600_rlc_start(struct radeon_device *rdev) | |
2309 | { | |
2310 | WREG32(RLC_CNTL, RLC_ENABLE); | |
2311 | } | |
2312 | ||
2313 | static int r600_rlc_init(struct radeon_device *rdev) | |
2314 | { | |
2315 | u32 i; | |
2316 | const __be32 *fw_data; | |
2317 | ||
2318 | if (!rdev->rlc_fw) | |
2319 | return -EINVAL; | |
2320 | ||
2321 | r600_rlc_stop(rdev); | |
2322 | ||
2323 | WREG32(RLC_HB_BASE, 0); | |
2324 | WREG32(RLC_HB_CNTL, 0); | |
2325 | WREG32(RLC_HB_RPTR, 0); | |
2326 | WREG32(RLC_HB_WPTR, 0); | |
2327 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); | |
2328 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); | |
2329 | WREG32(RLC_MC_CNTL, 0); | |
2330 | WREG32(RLC_UCODE_CNTL, 0); | |
2331 | ||
2332 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
2333 | if (rdev->family >= CHIP_RV770) { | |
2334 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { | |
2335 | WREG32(RLC_UCODE_ADDR, i); | |
2336 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2337 | } | |
2338 | } else { | |
2339 | for (i = 0; i < RLC_UCODE_SIZE; i++) { | |
2340 | WREG32(RLC_UCODE_ADDR, i); | |
2341 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2342 | } | |
2343 | } | |
2344 | WREG32(RLC_UCODE_ADDR, 0); | |
2345 | ||
2346 | r600_rlc_start(rdev); | |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
2351 | static void r600_enable_interrupts(struct radeon_device *rdev) | |
2352 | { | |
2353 | u32 ih_cntl = RREG32(IH_CNTL); | |
2354 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2355 | ||
2356 | ih_cntl |= ENABLE_INTR; | |
2357 | ih_rb_cntl |= IH_RB_ENABLE; | |
2358 | WREG32(IH_CNTL, ih_cntl); | |
2359 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2360 | rdev->ih.enabled = true; | |
2361 | } | |
2362 | ||
2363 | static void r600_disable_interrupts(struct radeon_device *rdev) | |
2364 | { | |
2365 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2366 | u32 ih_cntl = RREG32(IH_CNTL); | |
2367 | ||
2368 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
2369 | ih_cntl &= ~ENABLE_INTR; | |
2370 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2371 | WREG32(IH_CNTL, ih_cntl); | |
2372 | /* set rptr, wptr to 0 */ | |
2373 | WREG32(IH_RB_RPTR, 0); | |
2374 | WREG32(IH_RB_WPTR, 0); | |
2375 | rdev->ih.enabled = false; | |
2376 | rdev->ih.wptr = 0; | |
2377 | rdev->ih.rptr = 0; | |
2378 | } | |
2379 | ||
e0df1ac5 AD |
2380 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
2381 | { | |
2382 | u32 tmp; | |
2383 | ||
2384 | WREG32(CP_INT_CNTL, 0); | |
2385 | WREG32(GRBM_INT_CNTL, 0); | |
2386 | WREG32(DxMODE_INT_MASK, 0); | |
2387 | if (ASIC_IS_DCE3(rdev)) { | |
2388 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); | |
2389 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); | |
2390 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2391 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2392 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2393 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2394 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2395 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2396 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2397 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2398 | if (ASIC_IS_DCE32(rdev)) { | |
2399 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
5898b1f3 | 2400 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
e0df1ac5 | 2401 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
5898b1f3 | 2402 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
e0df1ac5 AD |
2403 | } |
2404 | } else { | |
2405 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
2406 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
2407 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
5898b1f3 | 2408 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
e0df1ac5 | 2409 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2410 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
e0df1ac5 | 2411 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2412 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
e0df1ac5 AD |
2413 | } |
2414 | } | |
2415 | ||
d8f60cfc AD |
2416 | int r600_irq_init(struct radeon_device *rdev) |
2417 | { | |
2418 | int ret = 0; | |
2419 | int rb_bufsz; | |
2420 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
2421 | ||
2422 | /* allocate ring */ | |
0c45249f | 2423 | ret = r600_ih_ring_alloc(rdev); |
d8f60cfc AD |
2424 | if (ret) |
2425 | return ret; | |
2426 | ||
2427 | /* disable irqs */ | |
2428 | r600_disable_interrupts(rdev); | |
2429 | ||
2430 | /* init rlc */ | |
2431 | ret = r600_rlc_init(rdev); | |
2432 | if (ret) { | |
2433 | r600_ih_ring_fini(rdev); | |
2434 | return ret; | |
2435 | } | |
2436 | ||
2437 | /* setup interrupt control */ | |
2438 | /* set dummy read address to ring address */ | |
2439 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
2440 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
2441 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
2442 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
2443 | */ | |
2444 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
2445 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
2446 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
2447 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
2448 | ||
2449 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
2450 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); | |
2451 | ||
2452 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
2453 | IH_WPTR_OVERFLOW_CLEAR | | |
2454 | (rb_bufsz << 1)); | |
2455 | /* WPTR writeback, not yet */ | |
2456 | /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/ | |
2457 | WREG32(IH_RB_WPTR_ADDR_LO, 0); | |
2458 | WREG32(IH_RB_WPTR_ADDR_HI, 0); | |
2459 | ||
2460 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2461 | ||
2462 | /* set rptr, wptr to 0 */ | |
2463 | WREG32(IH_RB_RPTR, 0); | |
2464 | WREG32(IH_RB_WPTR, 0); | |
2465 | ||
2466 | /* Default settings for IH_CNTL (disabled at first) */ | |
2467 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); | |
2468 | /* RPTR_REARM only works if msi's are enabled */ | |
2469 | if (rdev->msi_enabled) | |
2470 | ih_cntl |= RPTR_REARM; | |
2471 | ||
2472 | #ifdef __BIG_ENDIAN | |
2473 | ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); | |
2474 | #endif | |
2475 | WREG32(IH_CNTL, ih_cntl); | |
2476 | ||
2477 | /* force the active interrupt state to all disabled */ | |
e0df1ac5 | 2478 | r600_disable_interrupt_state(rdev); |
d8f60cfc AD |
2479 | |
2480 | /* enable irqs */ | |
2481 | r600_enable_interrupts(rdev); | |
2482 | ||
2483 | return ret; | |
2484 | } | |
2485 | ||
0c45249f | 2486 | void r600_irq_suspend(struct radeon_device *rdev) |
d8f60cfc AD |
2487 | { |
2488 | r600_disable_interrupts(rdev); | |
2489 | r600_rlc_stop(rdev); | |
0c45249f JG |
2490 | } |
2491 | ||
2492 | void r600_irq_fini(struct radeon_device *rdev) | |
2493 | { | |
2494 | r600_irq_suspend(rdev); | |
d8f60cfc AD |
2495 | r600_ih_ring_fini(rdev); |
2496 | } | |
2497 | ||
2498 | int r600_irq_set(struct radeon_device *rdev) | |
2499 | { | |
e0df1ac5 AD |
2500 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
2501 | u32 mode_int = 0; | |
2502 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | |
d8f60cfc | 2503 | |
003e69f9 JG |
2504 | if (!rdev->irq.installed) { |
2505 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
2506 | return -EINVAL; | |
2507 | } | |
d8f60cfc | 2508 | /* don't enable anything if the ih is disabled */ |
79c2bbc5 JG |
2509 | if (!rdev->ih.enabled) { |
2510 | r600_disable_interrupts(rdev); | |
2511 | /* force the active interrupt state to all disabled */ | |
2512 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 2513 | return 0; |
79c2bbc5 | 2514 | } |
d8f60cfc | 2515 | |
e0df1ac5 AD |
2516 | if (ASIC_IS_DCE3(rdev)) { |
2517 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2518 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2519 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2520 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2521 | if (ASIC_IS_DCE32(rdev)) { | |
2522 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2523 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2524 | } | |
2525 | } else { | |
2526 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2527 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2528 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2529 | } | |
2530 | ||
d8f60cfc AD |
2531 | if (rdev->irq.sw_int) { |
2532 | DRM_DEBUG("r600_irq_set: sw int\n"); | |
2533 | cp_int_cntl |= RB_INT_ENABLE; | |
2534 | } | |
2535 | if (rdev->irq.crtc_vblank_int[0]) { | |
2536 | DRM_DEBUG("r600_irq_set: vblank 0\n"); | |
2537 | mode_int |= D1MODE_VBLANK_INT_MASK; | |
2538 | } | |
2539 | if (rdev->irq.crtc_vblank_int[1]) { | |
2540 | DRM_DEBUG("r600_irq_set: vblank 1\n"); | |
2541 | mode_int |= D2MODE_VBLANK_INT_MASK; | |
2542 | } | |
e0df1ac5 AD |
2543 | if (rdev->irq.hpd[0]) { |
2544 | DRM_DEBUG("r600_irq_set: hpd 1\n"); | |
2545 | hpd1 |= DC_HPDx_INT_EN; | |
2546 | } | |
2547 | if (rdev->irq.hpd[1]) { | |
2548 | DRM_DEBUG("r600_irq_set: hpd 2\n"); | |
2549 | hpd2 |= DC_HPDx_INT_EN; | |
2550 | } | |
2551 | if (rdev->irq.hpd[2]) { | |
2552 | DRM_DEBUG("r600_irq_set: hpd 3\n"); | |
2553 | hpd3 |= DC_HPDx_INT_EN; | |
2554 | } | |
2555 | if (rdev->irq.hpd[3]) { | |
2556 | DRM_DEBUG("r600_irq_set: hpd 4\n"); | |
2557 | hpd4 |= DC_HPDx_INT_EN; | |
2558 | } | |
2559 | if (rdev->irq.hpd[4]) { | |
2560 | DRM_DEBUG("r600_irq_set: hpd 5\n"); | |
2561 | hpd5 |= DC_HPDx_INT_EN; | |
2562 | } | |
2563 | if (rdev->irq.hpd[5]) { | |
2564 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | |
2565 | hpd6 |= DC_HPDx_INT_EN; | |
2566 | } | |
d8f60cfc AD |
2567 | |
2568 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
2569 | WREG32(DxMODE_INT_MASK, mode_int); | |
e0df1ac5 AD |
2570 | if (ASIC_IS_DCE3(rdev)) { |
2571 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | |
2572 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
2573 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
2574 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
2575 | if (ASIC_IS_DCE32(rdev)) { | |
2576 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
2577 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
2578 | } | |
2579 | } else { | |
2580 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); | |
2581 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
2582 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | |
2583 | } | |
d8f60cfc AD |
2584 | |
2585 | return 0; | |
2586 | } | |
2587 | ||
e0df1ac5 AD |
2588 | static inline void r600_irq_ack(struct radeon_device *rdev, |
2589 | u32 *disp_int, | |
2590 | u32 *disp_int_cont, | |
2591 | u32 *disp_int_cont2) | |
d8f60cfc | 2592 | { |
e0df1ac5 AD |
2593 | u32 tmp; |
2594 | ||
2595 | if (ASIC_IS_DCE3(rdev)) { | |
2596 | *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); | |
2597 | *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | |
2598 | *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | |
2599 | } else { | |
2600 | *disp_int = RREG32(DISP_INTERRUPT_STATUS); | |
2601 | *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
2602 | *disp_int_cont2 = 0; | |
2603 | } | |
d8f60cfc | 2604 | |
e0df1ac5 | 2605 | if (*disp_int & LB_D1_VBLANK_INTERRUPT) |
d8f60cfc | 2606 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 2607 | if (*disp_int & LB_D1_VLINE_INTERRUPT) |
d8f60cfc | 2608 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 | 2609 | if (*disp_int & LB_D2_VBLANK_INTERRUPT) |
d8f60cfc | 2610 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 2611 | if (*disp_int & LB_D2_VLINE_INTERRUPT) |
d8f60cfc | 2612 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 AD |
2613 | if (*disp_int & DC_HPD1_INTERRUPT) { |
2614 | if (ASIC_IS_DCE3(rdev)) { | |
2615 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
2616 | tmp |= DC_HPDx_INT_ACK; | |
2617 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2618 | } else { | |
2619 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
2620 | tmp |= DC_HPDx_INT_ACK; | |
2621 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
2622 | } | |
2623 | } | |
2624 | if (*disp_int & DC_HPD2_INTERRUPT) { | |
2625 | if (ASIC_IS_DCE3(rdev)) { | |
2626 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
2627 | tmp |= DC_HPDx_INT_ACK; | |
2628 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2629 | } else { | |
2630 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
2631 | tmp |= DC_HPDx_INT_ACK; | |
2632 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
2633 | } | |
2634 | } | |
2635 | if (*disp_int_cont & DC_HPD3_INTERRUPT) { | |
2636 | if (ASIC_IS_DCE3(rdev)) { | |
2637 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
2638 | tmp |= DC_HPDx_INT_ACK; | |
2639 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2640 | } else { | |
2641 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
2642 | tmp |= DC_HPDx_INT_ACK; | |
2643 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
2644 | } | |
2645 | } | |
2646 | if (*disp_int_cont & DC_HPD4_INTERRUPT) { | |
2647 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
2648 | tmp |= DC_HPDx_INT_ACK; | |
2649 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2650 | } | |
2651 | if (ASIC_IS_DCE32(rdev)) { | |
2652 | if (*disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
2653 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
2654 | tmp |= DC_HPDx_INT_ACK; | |
2655 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
2656 | } | |
2657 | if (*disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
2658 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
2659 | tmp |= DC_HPDx_INT_ACK; | |
2660 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
2661 | } | |
2662 | } | |
d8f60cfc AD |
2663 | } |
2664 | ||
2665 | void r600_irq_disable(struct radeon_device *rdev) | |
2666 | { | |
e0df1ac5 | 2667 | u32 disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc AD |
2668 | |
2669 | r600_disable_interrupts(rdev); | |
2670 | /* Wait and acknowledge irq */ | |
2671 | mdelay(1); | |
e0df1ac5 AD |
2672 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
2673 | r600_disable_interrupt_state(rdev); | |
d8f60cfc AD |
2674 | } |
2675 | ||
2676 | static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) | |
2677 | { | |
2678 | u32 wptr, tmp; | |
3ce0a23d | 2679 | |
d8f60cfc AD |
2680 | /* XXX use writeback */ |
2681 | wptr = RREG32(IH_RB_WPTR); | |
3ce0a23d | 2682 | |
d8f60cfc | 2683 | if (wptr & RB_OVERFLOW) { |
7924e5eb JG |
2684 | /* When a ring buffer overflow happen start parsing interrupt |
2685 | * from the last not overwritten vector (wptr + 16). Hopefully | |
2686 | * this should allow us to catchup. | |
2687 | */ | |
2688 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
2689 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
2690 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
d8f60cfc AD |
2691 | tmp = RREG32(IH_RB_CNTL); |
2692 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
2693 | WREG32(IH_RB_CNTL, tmp); | |
2694 | } | |
0c45249f | 2695 | return (wptr & rdev->ih.ptr_mask); |
d8f60cfc | 2696 | } |
3ce0a23d | 2697 | |
d8f60cfc AD |
2698 | /* r600 IV Ring |
2699 | * Each IV ring entry is 128 bits: | |
2700 | * [7:0] - interrupt source id | |
2701 | * [31:8] - reserved | |
2702 | * [59:32] - interrupt source data | |
2703 | * [127:60] - reserved | |
2704 | * | |
2705 | * The basic interrupt vector entries | |
2706 | * are decoded as follows: | |
2707 | * src_id src_data description | |
2708 | * 1 0 D1 Vblank | |
2709 | * 1 1 D1 Vline | |
2710 | * 5 0 D2 Vblank | |
2711 | * 5 1 D2 Vline | |
2712 | * 19 0 FP Hot plug detection A | |
2713 | * 19 1 FP Hot plug detection B | |
2714 | * 19 2 DAC A auto-detection | |
2715 | * 19 3 DAC B auto-detection | |
2716 | * 176 - CP_INT RB | |
2717 | * 177 - CP_INT IB1 | |
2718 | * 178 - CP_INT IB2 | |
2719 | * 181 - EOP Interrupt | |
2720 | * 233 - GUI Idle | |
2721 | * | |
2722 | * Note, these are based on r600 and may need to be | |
2723 | * adjusted or added to on newer asics | |
2724 | */ | |
2725 | ||
2726 | int r600_irq_process(struct radeon_device *rdev) | |
2727 | { | |
2728 | u32 wptr = r600_get_ih_wptr(rdev); | |
2729 | u32 rptr = rdev->ih.rptr; | |
2730 | u32 src_id, src_data; | |
e0df1ac5 | 2731 | u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc | 2732 | unsigned long flags; |
d4877cf2 | 2733 | bool queue_hotplug = false; |
d8f60cfc AD |
2734 | |
2735 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
79c2bbc5 JG |
2736 | if (!rdev->ih.enabled) |
2737 | return IRQ_NONE; | |
d8f60cfc AD |
2738 | |
2739 | spin_lock_irqsave(&rdev->ih.lock, flags); | |
2740 | ||
2741 | if (rptr == wptr) { | |
2742 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2743 | return IRQ_NONE; | |
2744 | } | |
2745 | if (rdev->shutdown) { | |
2746 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2747 | return IRQ_NONE; | |
2748 | } | |
2749 | ||
2750 | restart_ih: | |
2751 | /* display interrupts */ | |
e0df1ac5 | 2752 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
d8f60cfc AD |
2753 | |
2754 | rdev->ih.wptr = wptr; | |
2755 | while (rptr != wptr) { | |
2756 | /* wptr/rptr are in bytes! */ | |
2757 | ring_index = rptr / 4; | |
2758 | src_id = rdev->ih.ring[ring_index] & 0xff; | |
2759 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | |
2760 | ||
2761 | switch (src_id) { | |
2762 | case 1: /* D1 vblank/vline */ | |
2763 | switch (src_data) { | |
2764 | case 0: /* D1 vblank */ | |
2765 | if (disp_int & LB_D1_VBLANK_INTERRUPT) { | |
2766 | drm_handle_vblank(rdev->ddev, 0); | |
839461d3 | 2767 | rdev->pm.vblank_sync = true; |
73a6d3fc | 2768 | wake_up(&rdev->irq.vblank_queue); |
d8f60cfc AD |
2769 | disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
2770 | DRM_DEBUG("IH: D1 vblank\n"); | |
2771 | } | |
2772 | break; | |
2773 | case 1: /* D1 vline */ | |
2774 | if (disp_int & LB_D1_VLINE_INTERRUPT) { | |
2775 | disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
2776 | DRM_DEBUG("IH: D1 vline\n"); | |
2777 | } | |
2778 | break; | |
2779 | default: | |
b042589c | 2780 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2781 | break; |
2782 | } | |
2783 | break; | |
2784 | case 5: /* D2 vblank/vline */ | |
2785 | switch (src_data) { | |
2786 | case 0: /* D2 vblank */ | |
2787 | if (disp_int & LB_D2_VBLANK_INTERRUPT) { | |
2788 | drm_handle_vblank(rdev->ddev, 1); | |
839461d3 | 2789 | rdev->pm.vblank_sync = true; |
73a6d3fc | 2790 | wake_up(&rdev->irq.vblank_queue); |
d8f60cfc AD |
2791 | disp_int &= ~LB_D2_VBLANK_INTERRUPT; |
2792 | DRM_DEBUG("IH: D2 vblank\n"); | |
2793 | } | |
2794 | break; | |
2795 | case 1: /* D1 vline */ | |
2796 | if (disp_int & LB_D2_VLINE_INTERRUPT) { | |
2797 | disp_int &= ~LB_D2_VLINE_INTERRUPT; | |
2798 | DRM_DEBUG("IH: D2 vline\n"); | |
2799 | } | |
2800 | break; | |
2801 | default: | |
b042589c | 2802 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2803 | break; |
2804 | } | |
2805 | break; | |
e0df1ac5 AD |
2806 | case 19: /* HPD/DAC hotplug */ |
2807 | switch (src_data) { | |
2808 | case 0: | |
2809 | if (disp_int & DC_HPD1_INTERRUPT) { | |
2810 | disp_int &= ~DC_HPD1_INTERRUPT; | |
d4877cf2 AD |
2811 | queue_hotplug = true; |
2812 | DRM_DEBUG("IH: HPD1\n"); | |
e0df1ac5 AD |
2813 | } |
2814 | break; | |
2815 | case 1: | |
2816 | if (disp_int & DC_HPD2_INTERRUPT) { | |
2817 | disp_int &= ~DC_HPD2_INTERRUPT; | |
d4877cf2 AD |
2818 | queue_hotplug = true; |
2819 | DRM_DEBUG("IH: HPD2\n"); | |
e0df1ac5 AD |
2820 | } |
2821 | break; | |
2822 | case 4: | |
2823 | if (disp_int_cont & DC_HPD3_INTERRUPT) { | |
2824 | disp_int_cont &= ~DC_HPD3_INTERRUPT; | |
d4877cf2 AD |
2825 | queue_hotplug = true; |
2826 | DRM_DEBUG("IH: HPD3\n"); | |
e0df1ac5 AD |
2827 | } |
2828 | break; | |
2829 | case 5: | |
2830 | if (disp_int_cont & DC_HPD4_INTERRUPT) { | |
2831 | disp_int_cont &= ~DC_HPD4_INTERRUPT; | |
d4877cf2 AD |
2832 | queue_hotplug = true; |
2833 | DRM_DEBUG("IH: HPD4\n"); | |
e0df1ac5 AD |
2834 | } |
2835 | break; | |
2836 | case 10: | |
2837 | if (disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
5898b1f3 | 2838 | disp_int_cont2 &= ~DC_HPD5_INTERRUPT; |
d4877cf2 AD |
2839 | queue_hotplug = true; |
2840 | DRM_DEBUG("IH: HPD5\n"); | |
e0df1ac5 AD |
2841 | } |
2842 | break; | |
2843 | case 12: | |
2844 | if (disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
5898b1f3 | 2845 | disp_int_cont2 &= ~DC_HPD6_INTERRUPT; |
d4877cf2 AD |
2846 | queue_hotplug = true; |
2847 | DRM_DEBUG("IH: HPD6\n"); | |
e0df1ac5 AD |
2848 | } |
2849 | break; | |
2850 | default: | |
b042589c | 2851 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
e0df1ac5 AD |
2852 | break; |
2853 | } | |
2854 | break; | |
d8f60cfc AD |
2855 | case 176: /* CP_INT in ring buffer */ |
2856 | case 177: /* CP_INT in IB1 */ | |
2857 | case 178: /* CP_INT in IB2 */ | |
2858 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
2859 | radeon_fence_process(rdev); | |
2860 | break; | |
2861 | case 181: /* CP EOP event */ | |
2862 | DRM_DEBUG("IH: CP EOP\n"); | |
2863 | break; | |
2864 | default: | |
b042589c | 2865 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2866 | break; |
2867 | } | |
2868 | ||
2869 | /* wptr/rptr are in bytes! */ | |
0c45249f JG |
2870 | rptr += 16; |
2871 | rptr &= rdev->ih.ptr_mask; | |
d8f60cfc AD |
2872 | } |
2873 | /* make sure wptr hasn't changed while processing */ | |
2874 | wptr = r600_get_ih_wptr(rdev); | |
2875 | if (wptr != rdev->ih.wptr) | |
2876 | goto restart_ih; | |
d4877cf2 AD |
2877 | if (queue_hotplug) |
2878 | queue_work(rdev->wq, &rdev->hotplug_work); | |
d8f60cfc AD |
2879 | rdev->ih.rptr = rptr; |
2880 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
2881 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2882 | return IRQ_HANDLED; | |
2883 | } | |
3ce0a23d JG |
2884 | |
2885 | /* | |
2886 | * Debugfs info | |
2887 | */ | |
2888 | #if defined(CONFIG_DEBUG_FS) | |
2889 | ||
2890 | static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) | |
771fe6b9 | 2891 | { |
3ce0a23d JG |
2892 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2893 | struct drm_device *dev = node->minor->dev; | |
2894 | struct radeon_device *rdev = dev->dev_private; | |
3ce0a23d JG |
2895 | unsigned count, i, j; |
2896 | ||
2897 | radeon_ring_free_size(rdev); | |
d6840766 | 2898 | count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; |
3ce0a23d | 2899 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
d6840766 RM |
2900 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); |
2901 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); | |
2902 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); | |
2903 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); | |
3ce0a23d JG |
2904 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
2905 | seq_printf(m, "%u dwords in ring\n", count); | |
d6840766 | 2906 | i = rdev->cp.rptr; |
3ce0a23d | 2907 | for (j = 0; j <= count; j++) { |
3ce0a23d | 2908 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
d6840766 | 2909 | i = (i + 1) & rdev->cp.ptr_mask; |
3ce0a23d JG |
2910 | } |
2911 | return 0; | |
2912 | } | |
2913 | ||
2914 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) | |
2915 | { | |
2916 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2917 | struct drm_device *dev = node->minor->dev; | |
2918 | struct radeon_device *rdev = dev->dev_private; | |
2919 | ||
2920 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); | |
2921 | DREG32_SYS(m, rdev, VM_L2_STATUS); | |
2922 | return 0; | |
2923 | } | |
2924 | ||
2925 | static struct drm_info_list r600_mc_info_list[] = { | |
2926 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, | |
2927 | {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, | |
2928 | }; | |
2929 | #endif | |
2930 | ||
2931 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) | |
2932 | { | |
2933 | #if defined(CONFIG_DEBUG_FS) | |
2934 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); | |
2935 | #else | |
2936 | return 0; | |
2937 | #endif | |
771fe6b9 | 2938 | } |
062b389c JG |
2939 | |
2940 | /** | |
2941 | * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl | |
2942 | * rdev: radeon device structure | |
2943 | * bo: buffer object struct which userspace is waiting for idle | |
2944 | * | |
2945 | * Some R6XX/R7XX doesn't seems to take into account HDP flush performed | |
2946 | * through ring buffer, this leads to corruption in rendering, see | |
2947 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we | |
2948 | * directly perform HDP flush by writing register through MMIO. | |
2949 | */ | |
2950 | void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) | |
2951 | { | |
2952 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2953 | } |