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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
3ce0a23d JG |
29 | #include <linux/seq_file.h> |
30 | #include <linux/firmware.h> | |
31 | #include <linux/platform_device.h> | |
e0cd3608 | 32 | #include <linux/module.h> |
771fe6b9 | 33 | #include "drmP.h" |
3ce0a23d | 34 | #include "radeon_drm.h" |
771fe6b9 | 35 | #include "radeon.h" |
e6990375 | 36 | #include "radeon_asic.h" |
3ce0a23d | 37 | #include "radeon_mode.h" |
3ce0a23d | 38 | #include "r600d.h" |
3ce0a23d | 39 | #include "atom.h" |
d39c3b89 | 40 | #include "avivod.h" |
771fe6b9 | 41 | |
3ce0a23d JG |
42 | #define PFP_UCODE_SIZE 576 |
43 | #define PM4_UCODE_SIZE 1792 | |
d8f60cfc | 44 | #define RLC_UCODE_SIZE 768 |
3ce0a23d JG |
45 | #define R700_PFP_UCODE_SIZE 848 |
46 | #define R700_PM4_UCODE_SIZE 1360 | |
d8f60cfc | 47 | #define R700_RLC_UCODE_SIZE 1024 |
fe251e2f AD |
48 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
49 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | |
45f9a39b | 50 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
12727809 | 51 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
c420c745 | 52 | #define ARUBA_RLC_UCODE_SIZE 1536 |
3ce0a23d JG |
53 | |
54 | /* Firmware Names */ | |
55 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
56 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
57 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
59 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
60 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
61 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
62 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
63 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
64 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
65 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
66 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
67 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
68 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
69 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
70 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
71 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); | |
72 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
73 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); | |
74 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
d8f60cfc AD |
75 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
76 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); | |
fe251e2f AD |
77 | MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); |
78 | MODULE_FIRMWARE("radeon/CEDAR_me.bin"); | |
45f9a39b | 79 | MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); |
fe251e2f AD |
80 | MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); |
81 | MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); | |
45f9a39b | 82 | MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); |
fe251e2f AD |
83 | MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); |
84 | MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); | |
45f9a39b | 85 | MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); |
a7433742 | 86 | MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); |
fe251e2f | 87 | MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); |
45f9a39b | 88 | MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); |
439bd6cd AD |
89 | MODULE_FIRMWARE("radeon/PALM_pfp.bin"); |
90 | MODULE_FIRMWARE("radeon/PALM_me.bin"); | |
91 | MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); | |
d5c5a72f AD |
92 | MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); |
93 | MODULE_FIRMWARE("radeon/SUMO_me.bin"); | |
94 | MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); | |
95 | MODULE_FIRMWARE("radeon/SUMO2_me.bin"); | |
3ce0a23d JG |
96 | |
97 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); | |
771fe6b9 | 98 | |
1a029b76 | 99 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
771fe6b9 JG |
100 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
101 | void r600_gpu_init(struct radeon_device *rdev); | |
3ce0a23d | 102 | void r600_fini(struct radeon_device *rdev); |
45f9a39b | 103 | void r600_irq_disable(struct radeon_device *rdev); |
9e46a48d | 104 | static void r600_pcie_gen2_enable(struct radeon_device *rdev); |
771fe6b9 | 105 | |
21a8122a | 106 | /* get temperature in millidegrees */ |
20d391d7 | 107 | int rv6xx_get_temp(struct radeon_device *rdev) |
21a8122a AD |
108 | { |
109 | u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> | |
110 | ASIC_T_SHIFT; | |
20d391d7 | 111 | int actual_temp = temp & 0xff; |
21a8122a | 112 | |
20d391d7 AD |
113 | if (temp & 0x100) |
114 | actual_temp -= 256; | |
115 | ||
116 | return actual_temp * 1000; | |
21a8122a AD |
117 | } |
118 | ||
ce8f5370 | 119 | void r600_pm_get_dynpm_state(struct radeon_device *rdev) |
a48b9b4e AD |
120 | { |
121 | int i; | |
122 | ||
ce8f5370 AD |
123 | rdev->pm.dynpm_can_upclock = true; |
124 | rdev->pm.dynpm_can_downclock = true; | |
a48b9b4e AD |
125 | |
126 | /* power state array is low to high, default is first */ | |
127 | if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { | |
128 | int min_power_state_index = 0; | |
129 | ||
130 | if (rdev->pm.num_power_states > 2) | |
131 | min_power_state_index = 1; | |
132 | ||
ce8f5370 AD |
133 | switch (rdev->pm.dynpm_planned_action) { |
134 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e AD |
135 | rdev->pm.requested_power_state_index = min_power_state_index; |
136 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 137 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 138 | break; |
ce8f5370 | 139 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
140 | if (rdev->pm.current_power_state_index == min_power_state_index) { |
141 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 142 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
143 | } else { |
144 | if (rdev->pm.active_crtc_count > 1) { | |
145 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 146 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
147 | continue; |
148 | else if (i >= rdev->pm.current_power_state_index) { | |
149 | rdev->pm.requested_power_state_index = | |
150 | rdev->pm.current_power_state_index; | |
151 | break; | |
152 | } else { | |
153 | rdev->pm.requested_power_state_index = i; | |
154 | break; | |
155 | } | |
156 | } | |
773c3fa3 AD |
157 | } else { |
158 | if (rdev->pm.current_power_state_index == 0) | |
159 | rdev->pm.requested_power_state_index = | |
160 | rdev->pm.num_power_states - 1; | |
161 | else | |
162 | rdev->pm.requested_power_state_index = | |
163 | rdev->pm.current_power_state_index - 1; | |
164 | } | |
a48b9b4e AD |
165 | } |
166 | rdev->pm.requested_clock_mode_index = 0; | |
d7311171 AD |
167 | /* don't use the power state if crtcs are active and no display flag is set */ |
168 | if ((rdev->pm.active_crtc_count > 0) && | |
169 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
170 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
171 | RADEON_PM_MODE_NO_DISPLAY)) { | |
172 | rdev->pm.requested_power_state_index++; | |
173 | } | |
a48b9b4e | 174 | break; |
ce8f5370 | 175 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
176 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
177 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 178 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
179 | } else { |
180 | if (rdev->pm.active_crtc_count > 1) { | |
181 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { | |
d7311171 | 182 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
183 | continue; |
184 | else if (i <= rdev->pm.current_power_state_index) { | |
185 | rdev->pm.requested_power_state_index = | |
186 | rdev->pm.current_power_state_index; | |
187 | break; | |
188 | } else { | |
189 | rdev->pm.requested_power_state_index = i; | |
190 | break; | |
191 | } | |
192 | } | |
193 | } else | |
194 | rdev->pm.requested_power_state_index = | |
195 | rdev->pm.current_power_state_index + 1; | |
196 | } | |
197 | rdev->pm.requested_clock_mode_index = 0; | |
198 | break; | |
ce8f5370 | 199 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
200 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
201 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 202 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 203 | break; |
ce8f5370 | 204 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
205 | default: |
206 | DRM_ERROR("Requested mode for not defined action\n"); | |
207 | return; | |
208 | } | |
209 | } else { | |
210 | /* XXX select a power state based on AC/DC, single/dualhead, etc. */ | |
211 | /* for now just select the first power state and switch between clock modes */ | |
212 | /* power state array is low to high, default is first (0) */ | |
213 | if (rdev->pm.active_crtc_count > 1) { | |
214 | rdev->pm.requested_power_state_index = -1; | |
215 | /* start at 1 as we don't want the default mode */ | |
216 | for (i = 1; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 217 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
218 | continue; |
219 | else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || | |
220 | (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { | |
221 | rdev->pm.requested_power_state_index = i; | |
222 | break; | |
223 | } | |
224 | } | |
225 | /* if nothing selected, grab the default state. */ | |
226 | if (rdev->pm.requested_power_state_index == -1) | |
227 | rdev->pm.requested_power_state_index = 0; | |
228 | } else | |
229 | rdev->pm.requested_power_state_index = 1; | |
230 | ||
ce8f5370 AD |
231 | switch (rdev->pm.dynpm_planned_action) { |
232 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e | 233 | rdev->pm.requested_clock_mode_index = 0; |
ce8f5370 | 234 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 235 | break; |
ce8f5370 | 236 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
237 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
238 | if (rdev->pm.current_clock_mode_index == 0) { | |
239 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 240 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
241 | } else |
242 | rdev->pm.requested_clock_mode_index = | |
243 | rdev->pm.current_clock_mode_index - 1; | |
244 | } else { | |
245 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 246 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 247 | } |
d7311171 AD |
248 | /* don't use the power state if crtcs are active and no display flag is set */ |
249 | if ((rdev->pm.active_crtc_count > 0) && | |
250 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
251 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
252 | RADEON_PM_MODE_NO_DISPLAY)) { | |
253 | rdev->pm.requested_clock_mode_index++; | |
254 | } | |
a48b9b4e | 255 | break; |
ce8f5370 | 256 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
257 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
258 | if (rdev->pm.current_clock_mode_index == | |
259 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { | |
260 | rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; | |
ce8f5370 | 261 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
262 | } else |
263 | rdev->pm.requested_clock_mode_index = | |
264 | rdev->pm.current_clock_mode_index + 1; | |
265 | } else { | |
266 | rdev->pm.requested_clock_mode_index = | |
267 | rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; | |
ce8f5370 | 268 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
269 | } |
270 | break; | |
ce8f5370 | 271 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
272 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
273 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 274 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 275 | break; |
ce8f5370 | 276 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
277 | default: |
278 | DRM_ERROR("Requested mode for not defined action\n"); | |
279 | return; | |
280 | } | |
281 | } | |
282 | ||
d9fdaafb | 283 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
ce8a3eb2 AD |
284 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
285 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | |
286 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
287 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | |
288 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
289 | pcie_lanes); | |
a48b9b4e AD |
290 | } |
291 | ||
ce8f5370 AD |
292 | void rs780_pm_init_profile(struct radeon_device *rdev) |
293 | { | |
294 | if (rdev->pm.num_power_states == 2) { | |
295 | /* default */ | |
296 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
297 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
298 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
299 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
300 | /* low sh */ | |
301 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; | |
302 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; | |
303 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
304 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
305 | /* mid sh */ |
306 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; | |
307 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; | |
308 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
309 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
310 | /* high sh */ |
311 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; | |
312 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
313 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
314 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
315 | /* low mh */ | |
316 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; | |
317 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
318 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
319 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
320 | /* mid mh */ |
321 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; | |
322 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
323 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
324 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
325 | /* high mh */ |
326 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; | |
327 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; | |
328 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
329 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
330 | } else if (rdev->pm.num_power_states == 3) { | |
331 | /* default */ | |
332 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
333 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
334 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
335 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
336 | /* low sh */ | |
337 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; | |
338 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
339 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
340 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
341 | /* mid sh */ |
342 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
343 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
344 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
345 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
346 | /* high sh */ |
347 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; | |
348 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; | |
349 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
350 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
351 | /* low mh */ | |
352 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; | |
353 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; | |
354 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
355 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
356 | /* mid mh */ |
357 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; | |
358 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; | |
359 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
360 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
361 | /* high mh */ |
362 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; | |
363 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
364 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
365 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
366 | } else { | |
367 | /* default */ | |
368 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
369 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
370 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
371 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
372 | /* low sh */ | |
373 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; | |
374 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; | |
375 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
376 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
377 | /* mid sh */ |
378 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; | |
379 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; | |
380 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
381 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
382 | /* high sh */ |
383 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; | |
384 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; | |
385 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
386 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
387 | /* low mh */ | |
388 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; | |
389 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
390 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
391 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
392 | /* mid mh */ |
393 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
394 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
395 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
396 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
397 | /* high mh */ |
398 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; | |
399 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; | |
400 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
401 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
402 | } | |
403 | } | |
bae6b562 | 404 | |
ce8f5370 AD |
405 | void r600_pm_init_profile(struct radeon_device *rdev) |
406 | { | |
bbe26ffe AD |
407 | int idx; |
408 | ||
ce8f5370 AD |
409 | if (rdev->family == CHIP_R600) { |
410 | /* XXX */ | |
411 | /* default */ | |
412 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
413 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
414 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 415 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
416 | /* low sh */ |
417 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
418 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
419 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 420 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
421 | /* mid sh */ |
422 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
423 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
424 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
425 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
426 | /* high sh */ |
427 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
428 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
429 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 430 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
431 | /* low mh */ |
432 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
433 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
434 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 435 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
436 | /* mid mh */ |
437 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
438 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
439 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
440 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
441 | /* high mh */ |
442 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
443 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
444 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 445 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
446 | } else { |
447 | if (rdev->pm.num_power_states < 4) { | |
448 | /* default */ | |
449 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
450 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
451 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
452 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
453 | /* low sh */ | |
4bff5171 AD |
454 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
455 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 | 456 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
457 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
458 | /* mid sh */ | |
459 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
460 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
461 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
462 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 463 | /* high sh */ |
4bff5171 AD |
464 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
465 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 AD |
466 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
467 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
468 | /* low mh */ | |
4bff5171 AD |
469 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
470 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 | 471 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
472 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
473 | /* low mh */ | |
474 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
475 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; | |
476 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
477 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 478 | /* high mh */ |
4bff5171 AD |
479 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
480 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 AD |
481 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
482 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
483 | } else { | |
484 | /* default */ | |
485 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
486 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
487 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
488 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
489 | /* low sh */ | |
bbe26ffe AD |
490 | if (rdev->flags & RADEON_IS_MOBILITY) |
491 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
492 | else | |
493 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
494 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; | |
495 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; | |
496 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
497 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 | 498 | /* mid sh */ |
bbe26ffe AD |
499 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; |
500 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; | |
501 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
502 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 503 | /* high sh */ |
bbe26ffe AD |
504 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); |
505 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; | |
506 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; | |
ce8f5370 AD |
507 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
508 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
509 | /* low mh */ | |
bbe26ffe AD |
510 | if (rdev->flags & RADEON_IS_MOBILITY) |
511 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); | |
512 | else | |
513 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
514 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; | |
515 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; | |
516 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
517 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 | 518 | /* mid mh */ |
bbe26ffe AD |
519 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; |
520 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; | |
521 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
522 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 523 | /* high mh */ |
bbe26ffe AD |
524 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); |
525 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; | |
526 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; | |
ce8f5370 AD |
527 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
528 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
529 | } | |
530 | } | |
bae6b562 AD |
531 | } |
532 | ||
49e02b73 AD |
533 | void r600_pm_misc(struct radeon_device *rdev) |
534 | { | |
a081a9d6 RM |
535 | int req_ps_idx = rdev->pm.requested_power_state_index; |
536 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
537 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
538 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
7ac9aa5a | 539 | |
4d60173f | 540 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
a377e187 AD |
541 | /* 0xff01 is a flag rather then an actual voltage */ |
542 | if (voltage->voltage == 0xff01) | |
543 | return; | |
4d60173f | 544 | if (voltage->voltage != rdev->pm.current_vddc) { |
8a83ec5e | 545 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
4d60173f | 546 | rdev->pm.current_vddc = voltage->voltage; |
d9fdaafb | 547 | DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); |
4d60173f AD |
548 | } |
549 | } | |
49e02b73 AD |
550 | } |
551 | ||
def9ba9c AD |
552 | bool r600_gui_idle(struct radeon_device *rdev) |
553 | { | |
554 | if (RREG32(GRBM_STATUS) & GUI_ACTIVE) | |
555 | return false; | |
556 | else | |
557 | return true; | |
558 | } | |
559 | ||
e0df1ac5 AD |
560 | /* hpd for digital panel detect/disconnect */ |
561 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
562 | { | |
563 | bool connected = false; | |
564 | ||
565 | if (ASIC_IS_DCE3(rdev)) { | |
566 | switch (hpd) { | |
567 | case RADEON_HPD_1: | |
568 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
569 | connected = true; | |
570 | break; | |
571 | case RADEON_HPD_2: | |
572 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
573 | connected = true; | |
574 | break; | |
575 | case RADEON_HPD_3: | |
576 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
577 | connected = true; | |
578 | break; | |
579 | case RADEON_HPD_4: | |
580 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
581 | connected = true; | |
582 | break; | |
583 | /* DCE 3.2 */ | |
584 | case RADEON_HPD_5: | |
585 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
586 | connected = true; | |
587 | break; | |
588 | case RADEON_HPD_6: | |
589 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
590 | connected = true; | |
591 | break; | |
592 | default: | |
593 | break; | |
594 | } | |
595 | } else { | |
596 | switch (hpd) { | |
597 | case RADEON_HPD_1: | |
598 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
599 | connected = true; | |
600 | break; | |
601 | case RADEON_HPD_2: | |
602 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
603 | connected = true; | |
604 | break; | |
605 | case RADEON_HPD_3: | |
606 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
607 | connected = true; | |
608 | break; | |
609 | default: | |
610 | break; | |
611 | } | |
612 | } | |
613 | return connected; | |
614 | } | |
615 | ||
616 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
429770b3 | 617 | enum radeon_hpd_id hpd) |
e0df1ac5 AD |
618 | { |
619 | u32 tmp; | |
620 | bool connected = r600_hpd_sense(rdev, hpd); | |
621 | ||
622 | if (ASIC_IS_DCE3(rdev)) { | |
623 | switch (hpd) { | |
624 | case RADEON_HPD_1: | |
625 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
626 | if (connected) | |
627 | tmp &= ~DC_HPDx_INT_POLARITY; | |
628 | else | |
629 | tmp |= DC_HPDx_INT_POLARITY; | |
630 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
631 | break; | |
632 | case RADEON_HPD_2: | |
633 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
634 | if (connected) | |
635 | tmp &= ~DC_HPDx_INT_POLARITY; | |
636 | else | |
637 | tmp |= DC_HPDx_INT_POLARITY; | |
638 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
639 | break; | |
640 | case RADEON_HPD_3: | |
641 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
642 | if (connected) | |
643 | tmp &= ~DC_HPDx_INT_POLARITY; | |
644 | else | |
645 | tmp |= DC_HPDx_INT_POLARITY; | |
646 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
647 | break; | |
648 | case RADEON_HPD_4: | |
649 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
650 | if (connected) | |
651 | tmp &= ~DC_HPDx_INT_POLARITY; | |
652 | else | |
653 | tmp |= DC_HPDx_INT_POLARITY; | |
654 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
655 | break; | |
656 | case RADEON_HPD_5: | |
657 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
658 | if (connected) | |
659 | tmp &= ~DC_HPDx_INT_POLARITY; | |
660 | else | |
661 | tmp |= DC_HPDx_INT_POLARITY; | |
662 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
663 | break; | |
664 | /* DCE 3.2 */ | |
665 | case RADEON_HPD_6: | |
666 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
667 | if (connected) | |
668 | tmp &= ~DC_HPDx_INT_POLARITY; | |
669 | else | |
670 | tmp |= DC_HPDx_INT_POLARITY; | |
671 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
672 | break; | |
673 | default: | |
674 | break; | |
675 | } | |
676 | } else { | |
677 | switch (hpd) { | |
678 | case RADEON_HPD_1: | |
679 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
680 | if (connected) | |
681 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
682 | else | |
683 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
684 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
685 | break; | |
686 | case RADEON_HPD_2: | |
687 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
688 | if (connected) | |
689 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
690 | else | |
691 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
692 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
693 | break; | |
694 | case RADEON_HPD_3: | |
695 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
696 | if (connected) | |
697 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
698 | else | |
699 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
700 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
701 | break; | |
702 | default: | |
703 | break; | |
704 | } | |
705 | } | |
706 | } | |
707 | ||
708 | void r600_hpd_init(struct radeon_device *rdev) | |
709 | { | |
710 | struct drm_device *dev = rdev->ddev; | |
711 | struct drm_connector *connector; | |
712 | ||
64912e99 AD |
713 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
714 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
715 | ||
716 | if (ASIC_IS_DCE3(rdev)) { | |
717 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); | |
718 | if (ASIC_IS_DCE32(rdev)) | |
719 | tmp |= DC_HPDx_EN; | |
e0df1ac5 | 720 | |
e0df1ac5 AD |
721 | switch (radeon_connector->hpd.hpd) { |
722 | case RADEON_HPD_1: | |
723 | WREG32(DC_HPD1_CONTROL, tmp); | |
724 | rdev->irq.hpd[0] = true; | |
725 | break; | |
726 | case RADEON_HPD_2: | |
727 | WREG32(DC_HPD2_CONTROL, tmp); | |
728 | rdev->irq.hpd[1] = true; | |
729 | break; | |
730 | case RADEON_HPD_3: | |
731 | WREG32(DC_HPD3_CONTROL, tmp); | |
732 | rdev->irq.hpd[2] = true; | |
733 | break; | |
734 | case RADEON_HPD_4: | |
735 | WREG32(DC_HPD4_CONTROL, tmp); | |
736 | rdev->irq.hpd[3] = true; | |
737 | break; | |
738 | /* DCE 3.2 */ | |
739 | case RADEON_HPD_5: | |
740 | WREG32(DC_HPD5_CONTROL, tmp); | |
741 | rdev->irq.hpd[4] = true; | |
742 | break; | |
743 | case RADEON_HPD_6: | |
744 | WREG32(DC_HPD6_CONTROL, tmp); | |
745 | rdev->irq.hpd[5] = true; | |
746 | break; | |
747 | default: | |
748 | break; | |
749 | } | |
64912e99 | 750 | } else { |
e0df1ac5 AD |
751 | switch (radeon_connector->hpd.hpd) { |
752 | case RADEON_HPD_1: | |
753 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
754 | rdev->irq.hpd[0] = true; | |
755 | break; | |
756 | case RADEON_HPD_2: | |
757 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
758 | rdev->irq.hpd[1] = true; | |
759 | break; | |
760 | case RADEON_HPD_3: | |
761 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
762 | rdev->irq.hpd[2] = true; | |
763 | break; | |
764 | default: | |
765 | break; | |
766 | } | |
767 | } | |
64912e99 | 768 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
e0df1ac5 | 769 | } |
003e69f9 JG |
770 | if (rdev->irq.installed) |
771 | r600_irq_set(rdev); | |
e0df1ac5 AD |
772 | } |
773 | ||
774 | void r600_hpd_fini(struct radeon_device *rdev) | |
775 | { | |
776 | struct drm_device *dev = rdev->ddev; | |
777 | struct drm_connector *connector; | |
778 | ||
779 | if (ASIC_IS_DCE3(rdev)) { | |
780 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
781 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
782 | switch (radeon_connector->hpd.hpd) { | |
783 | case RADEON_HPD_1: | |
784 | WREG32(DC_HPD1_CONTROL, 0); | |
785 | rdev->irq.hpd[0] = false; | |
786 | break; | |
787 | case RADEON_HPD_2: | |
788 | WREG32(DC_HPD2_CONTROL, 0); | |
789 | rdev->irq.hpd[1] = false; | |
790 | break; | |
791 | case RADEON_HPD_3: | |
792 | WREG32(DC_HPD3_CONTROL, 0); | |
793 | rdev->irq.hpd[2] = false; | |
794 | break; | |
795 | case RADEON_HPD_4: | |
796 | WREG32(DC_HPD4_CONTROL, 0); | |
797 | rdev->irq.hpd[3] = false; | |
798 | break; | |
799 | /* DCE 3.2 */ | |
800 | case RADEON_HPD_5: | |
801 | WREG32(DC_HPD5_CONTROL, 0); | |
802 | rdev->irq.hpd[4] = false; | |
803 | break; | |
804 | case RADEON_HPD_6: | |
805 | WREG32(DC_HPD6_CONTROL, 0); | |
806 | rdev->irq.hpd[5] = false; | |
807 | break; | |
808 | default: | |
809 | break; | |
810 | } | |
811 | } | |
812 | } else { | |
813 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
814 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
815 | switch (radeon_connector->hpd.hpd) { | |
816 | case RADEON_HPD_1: | |
817 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); | |
818 | rdev->irq.hpd[0] = false; | |
819 | break; | |
820 | case RADEON_HPD_2: | |
821 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); | |
822 | rdev->irq.hpd[1] = false; | |
823 | break; | |
824 | case RADEON_HPD_3: | |
825 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); | |
826 | rdev->irq.hpd[2] = false; | |
827 | break; | |
828 | default: | |
829 | break; | |
830 | } | |
831 | } | |
832 | } | |
833 | } | |
834 | ||
771fe6b9 | 835 | /* |
3ce0a23d | 836 | * R600 PCIE GART |
771fe6b9 | 837 | */ |
3ce0a23d JG |
838 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
839 | { | |
840 | unsigned i; | |
841 | u32 tmp; | |
842 | ||
2e98f10a | 843 | /* flush hdp cache so updates hit vram */ |
f3886f85 AD |
844 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
845 | !(rdev->flags & RADEON_IS_AGP)) { | |
c9a1be96 | 846 | void __iomem *ptr = (void *)rdev->gart.ptr; |
812d0469 AD |
847 | u32 tmp; |
848 | ||
849 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read | |
850 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL | |
f3886f85 AD |
851 | * This seems to cause problems on some AGP cards. Just use the old |
852 | * method for them. | |
812d0469 AD |
853 | */ |
854 | WREG32(HDP_DEBUG1, 0); | |
855 | tmp = readl((void __iomem *)ptr); | |
856 | } else | |
857 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2e98f10a | 858 | |
3ce0a23d JG |
859 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
860 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); | |
861 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
862 | for (i = 0; i < rdev->usec_timeout; i++) { | |
863 | /* read MC_STATUS */ | |
864 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
865 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
866 | if (tmp == 2) { | |
867 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
868 | return; | |
869 | } | |
870 | if (tmp) { | |
871 | return; | |
872 | } | |
873 | udelay(1); | |
874 | } | |
875 | } | |
876 | ||
4aac0473 | 877 | int r600_pcie_gart_init(struct radeon_device *rdev) |
3ce0a23d | 878 | { |
4aac0473 | 879 | int r; |
3ce0a23d | 880 | |
c9a1be96 | 881 | if (rdev->gart.robj) { |
fce7d61b | 882 | WARN(1, "R600 PCIE GART already initialized\n"); |
4aac0473 JG |
883 | return 0; |
884 | } | |
3ce0a23d JG |
885 | /* Initialize common gart structure */ |
886 | r = radeon_gart_init(rdev); | |
4aac0473 | 887 | if (r) |
3ce0a23d | 888 | return r; |
3ce0a23d | 889 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
4aac0473 JG |
890 | return radeon_gart_table_vram_alloc(rdev); |
891 | } | |
892 | ||
893 | int r600_pcie_gart_enable(struct radeon_device *rdev) | |
894 | { | |
895 | u32 tmp; | |
896 | int r, i; | |
897 | ||
c9a1be96 | 898 | if (rdev->gart.robj == NULL) { |
4aac0473 JG |
899 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
900 | return -EINVAL; | |
771fe6b9 | 901 | } |
4aac0473 JG |
902 | r = radeon_gart_table_vram_pin(rdev); |
903 | if (r) | |
904 | return r; | |
82568565 | 905 | radeon_gart_restore(rdev); |
bc1a631e | 906 | |
3ce0a23d JG |
907 | /* Setup L2 cache */ |
908 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
909 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
910 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
911 | WREG32(VM_L2_CNTL2, 0); | |
912 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
913 | /* Setup TLB control */ | |
914 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
915 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
916 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
917 | ENABLE_WAIT_L2_QUERY; | |
918 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
919 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
920 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
921 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
922 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
923 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
924 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
925 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
926 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
927 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
928 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
929 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
930 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
931 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
932 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1a029b76 | 933 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
934 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
935 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
936 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
937 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
938 | (u32)(rdev->dummy_page.addr >> 12)); | |
939 | for (i = 1; i < 7; i++) | |
940 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 941 | |
3ce0a23d | 942 | r600_pcie_gart_tlb_flush(rdev); |
fcf4de5a TV |
943 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
944 | (unsigned)(rdev->mc.gtt_size >> 20), | |
945 | (unsigned long long)rdev->gart.table_addr); | |
3ce0a23d | 946 | rdev->gart.ready = true; |
771fe6b9 JG |
947 | return 0; |
948 | } | |
949 | ||
3ce0a23d | 950 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 951 | { |
3ce0a23d | 952 | u32 tmp; |
c9a1be96 | 953 | int i; |
771fe6b9 | 954 | |
3ce0a23d JG |
955 | /* Disable all tables */ |
956 | for (i = 0; i < 7; i++) | |
957 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 958 | |
3ce0a23d JG |
959 | /* Disable L2 cache */ |
960 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
961 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
962 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
963 | /* Setup L1 TLB control */ | |
964 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
965 | ENABLE_WAIT_L2_QUERY; | |
966 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
967 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
968 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
969 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
970 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
971 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
972 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
973 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
974 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); | |
975 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); | |
976 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
977 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
978 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); | |
979 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
c9a1be96 | 980 | radeon_gart_table_vram_unpin(rdev); |
4aac0473 JG |
981 | } |
982 | ||
983 | void r600_pcie_gart_fini(struct radeon_device *rdev) | |
984 | { | |
f9274562 | 985 | radeon_gart_fini(rdev); |
4aac0473 JG |
986 | r600_pcie_gart_disable(rdev); |
987 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
988 | } |
989 | ||
1a029b76 JG |
990 | void r600_agp_enable(struct radeon_device *rdev) |
991 | { | |
992 | u32 tmp; | |
993 | int i; | |
994 | ||
995 | /* Setup L2 cache */ | |
996 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
997 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
998 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
999 | WREG32(VM_L2_CNTL2, 0); | |
1000 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
1001 | /* Setup TLB control */ | |
1002 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1003 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1004 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
1005 | ENABLE_WAIT_L2_QUERY; | |
1006 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
1007 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
1008 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
1009 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
1010 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
1011 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
1012 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
1013 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
1014 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
1015 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
1016 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
1017 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
1018 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1019 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1020 | for (i = 0; i < 7; i++) | |
1021 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
1022 | } | |
1023 | ||
771fe6b9 JG |
1024 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
1025 | { | |
3ce0a23d JG |
1026 | unsigned i; |
1027 | u32 tmp; | |
1028 | ||
1029 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1030 | /* read MC_STATUS */ | |
1031 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; | |
1032 | if (!tmp) | |
1033 | return 0; | |
1034 | udelay(1); | |
1035 | } | |
1036 | return -1; | |
771fe6b9 JG |
1037 | } |
1038 | ||
a3c1945a | 1039 | static void r600_mc_program(struct radeon_device *rdev) |
771fe6b9 | 1040 | { |
a3c1945a | 1041 | struct rv515_mc_save save; |
3ce0a23d JG |
1042 | u32 tmp; |
1043 | int i, j; | |
771fe6b9 | 1044 | |
3ce0a23d JG |
1045 | /* Initialize HDP */ |
1046 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1047 | WREG32((0x2c14 + j), 0x00000000); | |
1048 | WREG32((0x2c18 + j), 0x00000000); | |
1049 | WREG32((0x2c1c + j), 0x00000000); | |
1050 | WREG32((0x2c20 + j), 0x00000000); | |
1051 | WREG32((0x2c24 + j), 0x00000000); | |
1052 | } | |
1053 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
771fe6b9 | 1054 | |
a3c1945a | 1055 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 1056 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1057 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1058 | } |
a3c1945a | 1059 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
3ce0a23d | 1060 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
3ce0a23d | 1061 | /* Update configuration */ |
1a029b76 JG |
1062 | if (rdev->flags & RADEON_IS_AGP) { |
1063 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
1064 | /* VRAM before AGP */ | |
1065 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1066 | rdev->mc.vram_start >> 12); | |
1067 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1068 | rdev->mc.gtt_end >> 12); | |
1069 | } else { | |
1070 | /* VRAM after AGP */ | |
1071 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1072 | rdev->mc.gtt_start >> 12); | |
1073 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1074 | rdev->mc.vram_end >> 12); | |
1075 | } | |
1076 | } else { | |
1077 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); | |
1078 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); | |
1079 | } | |
16cdf04d | 1080 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
1a029b76 | 1081 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
1082 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
1083 | WREG32(MC_VM_FB_LOCATION, tmp); | |
1084 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
1085 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
46fcd2b3 | 1086 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
3ce0a23d | 1087 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 JG |
1088 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
1089 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | |
3ce0a23d JG |
1090 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
1091 | } else { | |
1092 | WREG32(MC_VM_AGP_BASE, 0); | |
1093 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
1094 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
1095 | } | |
3ce0a23d | 1096 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1097 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1098 | } |
a3c1945a | 1099 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
1100 | /* we need to own VRAM, so turn off the VGA renderer here |
1101 | * to stop it overwriting our objects */ | |
d39c3b89 | 1102 | rv515_vga_render_disable(rdev); |
3ce0a23d JG |
1103 | } |
1104 | ||
d594e46a JG |
1105 | /** |
1106 | * r600_vram_gtt_location - try to find VRAM & GTT location | |
1107 | * @rdev: radeon device structure holding all necessary informations | |
1108 | * @mc: memory controller structure holding memory informations | |
1109 | * | |
1110 | * Function will place try to place VRAM at same place as in CPU (PCI) | |
1111 | * address space as some GPU seems to have issue when we reprogram at | |
1112 | * different address space. | |
1113 | * | |
1114 | * If there is not enough space to fit the unvisible VRAM after the | |
1115 | * aperture then we limit the VRAM size to the aperture. | |
1116 | * | |
1117 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need | |
1118 | * them to be in one from GPU point of view so that we can program GPU to | |
1119 | * catch access outside them (weird GPU policy see ??). | |
1120 | * | |
1121 | * This function will never fails, worst case are limiting VRAM or GTT. | |
1122 | * | |
1123 | * Note: GTT start, end, size should be initialized before calling this | |
1124 | * function on AGP platform. | |
1125 | */ | |
0ef0c1f7 | 1126 | static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
d594e46a JG |
1127 | { |
1128 | u64 size_bf, size_af; | |
1129 | ||
1130 | if (mc->mc_vram_size > 0xE0000000) { | |
1131 | /* leave room for at least 512M GTT */ | |
1132 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1133 | mc->real_vram_size = 0xE0000000; | |
1134 | mc->mc_vram_size = 0xE0000000; | |
1135 | } | |
1136 | if (rdev->flags & RADEON_IS_AGP) { | |
1137 | size_bf = mc->gtt_start; | |
1138 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; | |
1139 | if (size_bf > size_af) { | |
1140 | if (mc->mc_vram_size > size_bf) { | |
1141 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1142 | mc->real_vram_size = size_bf; | |
1143 | mc->mc_vram_size = size_bf; | |
1144 | } | |
1145 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; | |
1146 | } else { | |
1147 | if (mc->mc_vram_size > size_af) { | |
1148 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1149 | mc->real_vram_size = size_af; | |
1150 | mc->mc_vram_size = size_af; | |
1151 | } | |
1152 | mc->vram_start = mc->gtt_end; | |
1153 | } | |
1154 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
1155 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
1156 | mc->mc_vram_size >> 20, mc->vram_start, | |
1157 | mc->vram_end, mc->real_vram_size >> 20); | |
1158 | } else { | |
1159 | u64 base = 0; | |
8961d52d AD |
1160 | if (rdev->flags & RADEON_IS_IGP) { |
1161 | base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; | |
1162 | base <<= 24; | |
1163 | } | |
d594e46a | 1164 | radeon_vram_location(rdev, &rdev->mc, base); |
8d369bb1 | 1165 | rdev->mc.gtt_base_align = 0; |
d594e46a JG |
1166 | radeon_gtt_location(rdev, mc); |
1167 | } | |
1168 | } | |
1169 | ||
3ce0a23d | 1170 | int r600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 1171 | { |
3ce0a23d | 1172 | u32 tmp; |
5885b7a9 | 1173 | int chansize, numchan; |
771fe6b9 | 1174 | |
3ce0a23d | 1175 | /* Get VRAM informations */ |
771fe6b9 | 1176 | rdev->mc.vram_is_ddr = true; |
3ce0a23d JG |
1177 | tmp = RREG32(RAMCFG); |
1178 | if (tmp & CHANSIZE_OVERRIDE) { | |
771fe6b9 | 1179 | chansize = 16; |
3ce0a23d | 1180 | } else if (tmp & CHANSIZE_MASK) { |
771fe6b9 JG |
1181 | chansize = 64; |
1182 | } else { | |
1183 | chansize = 32; | |
1184 | } | |
5885b7a9 AD |
1185 | tmp = RREG32(CHMAP); |
1186 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
1187 | case 0: | |
1188 | default: | |
1189 | numchan = 1; | |
1190 | break; | |
1191 | case 1: | |
1192 | numchan = 2; | |
1193 | break; | |
1194 | case 2: | |
1195 | numchan = 4; | |
1196 | break; | |
1197 | case 3: | |
1198 | numchan = 8; | |
1199 | break; | |
771fe6b9 | 1200 | } |
5885b7a9 | 1201 | rdev->mc.vram_width = numchan * chansize; |
3ce0a23d | 1202 | /* Could aper size report 0 ? */ |
01d73a69 JC |
1203 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
1204 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
3ce0a23d JG |
1205 | /* Setup GPU memory space */ |
1206 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
1207 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
51e5fcd3 | 1208 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a | 1209 | r600_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 | 1210 | |
f892034a AD |
1211 | if (rdev->flags & RADEON_IS_IGP) { |
1212 | rs690_pm_info(rdev); | |
06b6476d | 1213 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
f892034a | 1214 | } |
f47299c5 | 1215 | radeon_update_bandwidth_info(rdev); |
3ce0a23d | 1216 | return 0; |
771fe6b9 JG |
1217 | } |
1218 | ||
16cdf04d AD |
1219 | int r600_vram_scratch_init(struct radeon_device *rdev) |
1220 | { | |
1221 | int r; | |
1222 | ||
1223 | if (rdev->vram_scratch.robj == NULL) { | |
1224 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, | |
1225 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, | |
1226 | &rdev->vram_scratch.robj); | |
1227 | if (r) { | |
1228 | return r; | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | |
1233 | if (unlikely(r != 0)) | |
1234 | return r; | |
1235 | r = radeon_bo_pin(rdev->vram_scratch.robj, | |
1236 | RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); | |
1237 | if (r) { | |
1238 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1239 | return r; | |
1240 | } | |
1241 | r = radeon_bo_kmap(rdev->vram_scratch.robj, | |
1242 | (void **)&rdev->vram_scratch.ptr); | |
1243 | if (r) | |
1244 | radeon_bo_unpin(rdev->vram_scratch.robj); | |
1245 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1246 | ||
1247 | return r; | |
1248 | } | |
1249 | ||
1250 | void r600_vram_scratch_fini(struct radeon_device *rdev) | |
1251 | { | |
1252 | int r; | |
1253 | ||
1254 | if (rdev->vram_scratch.robj == NULL) { | |
1255 | return; | |
1256 | } | |
1257 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | |
1258 | if (likely(r == 0)) { | |
1259 | radeon_bo_kunmap(rdev->vram_scratch.robj); | |
1260 | radeon_bo_unpin(rdev->vram_scratch.robj); | |
1261 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1262 | } | |
1263 | radeon_bo_unref(&rdev->vram_scratch.robj); | |
1264 | } | |
1265 | ||
3ce0a23d JG |
1266 | /* We doesn't check that the GPU really needs a reset we simply do the |
1267 | * reset, it's up to the caller to determine if the GPU needs one. We | |
1268 | * might add an helper function to check that. | |
1269 | */ | |
1270 | int r600_gpu_soft_reset(struct radeon_device *rdev) | |
771fe6b9 | 1271 | { |
a3c1945a | 1272 | struct rv515_mc_save save; |
3ce0a23d JG |
1273 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
1274 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | | |
1275 | S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | | |
1276 | S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | | |
1277 | S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | | |
1278 | S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | | |
1279 | S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | | |
1280 | S_008010_GUI_ACTIVE(1); | |
1281 | u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | | |
1282 | S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | | |
1283 | S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | | |
1284 | S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | | |
1285 | S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | | |
1286 | S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | | |
1287 | S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | | |
1288 | S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); | |
a3c1945a | 1289 | u32 tmp; |
771fe6b9 | 1290 | |
8d96fe93 AD |
1291 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
1292 | return 0; | |
1293 | ||
1a029b76 JG |
1294 | dev_info(rdev->dev, "GPU softreset \n"); |
1295 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", | |
1296 | RREG32(R_008010_GRBM_STATUS)); | |
1297 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
a3c1945a | 1298 | RREG32(R_008014_GRBM_STATUS2)); |
1a029b76 JG |
1299 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
1300 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a JG |
1301 | rv515_mc_stop(rdev, &save); |
1302 | if (r600_mc_wait_for_idle(rdev)) { | |
1303 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1304 | } | |
3ce0a23d | 1305 | /* Disable CP parsing/prefetching */ |
90aca4d2 | 1306 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
3ce0a23d JG |
1307 | /* Check if any of the rendering block is busy and reset it */ |
1308 | if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || | |
1309 | (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { | |
a3c1945a | 1310 | tmp = S_008020_SOFT_RESET_CR(1) | |
3ce0a23d JG |
1311 | S_008020_SOFT_RESET_DB(1) | |
1312 | S_008020_SOFT_RESET_CB(1) | | |
1313 | S_008020_SOFT_RESET_PA(1) | | |
1314 | S_008020_SOFT_RESET_SC(1) | | |
1315 | S_008020_SOFT_RESET_SMX(1) | | |
1316 | S_008020_SOFT_RESET_SPI(1) | | |
1317 | S_008020_SOFT_RESET_SX(1) | | |
1318 | S_008020_SOFT_RESET_SH(1) | | |
1319 | S_008020_SOFT_RESET_TC(1) | | |
1320 | S_008020_SOFT_RESET_TA(1) | | |
1321 | S_008020_SOFT_RESET_VC(1) | | |
a3c1945a | 1322 | S_008020_SOFT_RESET_VGT(1); |
1a029b76 | 1323 | dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
a3c1945a | 1324 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
90aca4d2 JG |
1325 | RREG32(R_008020_GRBM_SOFT_RESET); |
1326 | mdelay(15); | |
3ce0a23d | 1327 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
3ce0a23d JG |
1328 | } |
1329 | /* Reset CP (we always reset CP) */ | |
a3c1945a JG |
1330 | tmp = S_008020_SOFT_RESET_CP(1); |
1331 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); | |
1332 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
90aca4d2 JG |
1333 | RREG32(R_008020_GRBM_SOFT_RESET); |
1334 | mdelay(15); | |
3ce0a23d | 1335 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
3ce0a23d | 1336 | /* Wait a little for things to settle down */ |
225758d8 | 1337 | mdelay(1); |
1a029b76 JG |
1338 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
1339 | RREG32(R_008010_GRBM_STATUS)); | |
1340 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
1341 | RREG32(R_008014_GRBM_STATUS2)); | |
1342 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", | |
1343 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a | 1344 | rv515_mc_resume(rdev, &save); |
3ce0a23d JG |
1345 | return 0; |
1346 | } | |
1347 | ||
e32eb50d | 1348 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
225758d8 JG |
1349 | { |
1350 | u32 srbm_status; | |
1351 | u32 grbm_status; | |
1352 | u32 grbm_status2; | |
e29ff729 | 1353 | struct r100_gpu_lockup *lockup; |
225758d8 JG |
1354 | int r; |
1355 | ||
e29ff729 AD |
1356 | if (rdev->family >= CHIP_RV770) |
1357 | lockup = &rdev->config.rv770.lockup; | |
1358 | else | |
1359 | lockup = &rdev->config.r600.lockup; | |
1360 | ||
225758d8 JG |
1361 | srbm_status = RREG32(R_000E50_SRBM_STATUS); |
1362 | grbm_status = RREG32(R_008010_GRBM_STATUS); | |
1363 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); | |
1364 | if (!G_008010_GUI_ACTIVE(grbm_status)) { | |
e32eb50d | 1365 | r100_gpu_lockup_update(lockup, ring); |
225758d8 JG |
1366 | return false; |
1367 | } | |
1368 | /* force CP activities */ | |
e32eb50d | 1369 | r = radeon_ring_lock(rdev, ring, 2); |
225758d8 JG |
1370 | if (!r) { |
1371 | /* PACKET2 NOP */ | |
e32eb50d CK |
1372 | radeon_ring_write(ring, 0x80000000); |
1373 | radeon_ring_write(ring, 0x80000000); | |
1374 | radeon_ring_unlock_commit(rdev, ring); | |
225758d8 | 1375 | } |
e32eb50d CK |
1376 | ring->rptr = RREG32(ring->rptr_reg); |
1377 | return r100_gpu_cp_is_lockup(rdev, lockup, ring); | |
225758d8 JG |
1378 | } |
1379 | ||
a2d07b74 | 1380 | int r600_asic_reset(struct radeon_device *rdev) |
3ce0a23d JG |
1381 | { |
1382 | return r600_gpu_soft_reset(rdev); | |
1383 | } | |
1384 | ||
1385 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
1386 | u32 num_backends, | |
1387 | u32 backend_disable_mask) | |
1388 | { | |
1389 | u32 backend_map = 0; | |
1390 | u32 enabled_backends_mask; | |
1391 | u32 enabled_backends_count; | |
1392 | u32 cur_pipe; | |
1393 | u32 swizzle_pipe[R6XX_MAX_PIPES]; | |
1394 | u32 cur_backend; | |
1395 | u32 i; | |
1396 | ||
1397 | if (num_tile_pipes > R6XX_MAX_PIPES) | |
1398 | num_tile_pipes = R6XX_MAX_PIPES; | |
1399 | if (num_tile_pipes < 1) | |
1400 | num_tile_pipes = 1; | |
1401 | if (num_backends > R6XX_MAX_BACKENDS) | |
1402 | num_backends = R6XX_MAX_BACKENDS; | |
1403 | if (num_backends < 1) | |
1404 | num_backends = 1; | |
1405 | ||
1406 | enabled_backends_mask = 0; | |
1407 | enabled_backends_count = 0; | |
1408 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { | |
1409 | if (((backend_disable_mask >> i) & 1) == 0) { | |
1410 | enabled_backends_mask |= (1 << i); | |
1411 | ++enabled_backends_count; | |
1412 | } | |
1413 | if (enabled_backends_count == num_backends) | |
1414 | break; | |
1415 | } | |
1416 | ||
1417 | if (enabled_backends_count == 0) { | |
1418 | enabled_backends_mask = 1; | |
1419 | enabled_backends_count = 1; | |
1420 | } | |
1421 | ||
1422 | if (enabled_backends_count != num_backends) | |
1423 | num_backends = enabled_backends_count; | |
1424 | ||
1425 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); | |
1426 | switch (num_tile_pipes) { | |
1427 | case 1: | |
1428 | swizzle_pipe[0] = 0; | |
1429 | break; | |
1430 | case 2: | |
1431 | swizzle_pipe[0] = 0; | |
1432 | swizzle_pipe[1] = 1; | |
1433 | break; | |
1434 | case 3: | |
1435 | swizzle_pipe[0] = 0; | |
1436 | swizzle_pipe[1] = 1; | |
1437 | swizzle_pipe[2] = 2; | |
1438 | break; | |
1439 | case 4: | |
1440 | swizzle_pipe[0] = 0; | |
1441 | swizzle_pipe[1] = 1; | |
1442 | swizzle_pipe[2] = 2; | |
1443 | swizzle_pipe[3] = 3; | |
1444 | break; | |
1445 | case 5: | |
1446 | swizzle_pipe[0] = 0; | |
1447 | swizzle_pipe[1] = 1; | |
1448 | swizzle_pipe[2] = 2; | |
1449 | swizzle_pipe[3] = 3; | |
1450 | swizzle_pipe[4] = 4; | |
1451 | break; | |
1452 | case 6: | |
1453 | swizzle_pipe[0] = 0; | |
1454 | swizzle_pipe[1] = 2; | |
1455 | swizzle_pipe[2] = 4; | |
1456 | swizzle_pipe[3] = 5; | |
1457 | swizzle_pipe[4] = 1; | |
1458 | swizzle_pipe[5] = 3; | |
1459 | break; | |
1460 | case 7: | |
1461 | swizzle_pipe[0] = 0; | |
1462 | swizzle_pipe[1] = 2; | |
1463 | swizzle_pipe[2] = 4; | |
1464 | swizzle_pipe[3] = 6; | |
1465 | swizzle_pipe[4] = 1; | |
1466 | swizzle_pipe[5] = 3; | |
1467 | swizzle_pipe[6] = 5; | |
1468 | break; | |
1469 | case 8: | |
1470 | swizzle_pipe[0] = 0; | |
1471 | swizzle_pipe[1] = 2; | |
1472 | swizzle_pipe[2] = 4; | |
1473 | swizzle_pipe[3] = 6; | |
1474 | swizzle_pipe[4] = 1; | |
1475 | swizzle_pipe[5] = 3; | |
1476 | swizzle_pipe[6] = 5; | |
1477 | swizzle_pipe[7] = 7; | |
1478 | break; | |
1479 | } | |
1480 | ||
1481 | cur_backend = 0; | |
1482 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
1483 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
1484 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
1485 | ||
1486 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
1487 | ||
1488 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
1489 | } | |
1490 | ||
1491 | return backend_map; | |
1492 | } | |
1493 | ||
1494 | int r600_count_pipe_bits(uint32_t val) | |
1495 | { | |
1496 | int i, ret = 0; | |
1497 | ||
1498 | for (i = 0; i < 32; i++) { | |
1499 | ret += val & 1; | |
1500 | val >>= 1; | |
1501 | } | |
1502 | return ret; | |
771fe6b9 JG |
1503 | } |
1504 | ||
3ce0a23d JG |
1505 | void r600_gpu_init(struct radeon_device *rdev) |
1506 | { | |
1507 | u32 tiling_config; | |
1508 | u32 ramcfg; | |
d03f5d59 AD |
1509 | u32 backend_map; |
1510 | u32 cc_rb_backend_disable; | |
1511 | u32 cc_gc_shader_pipe_config; | |
3ce0a23d JG |
1512 | u32 tmp; |
1513 | int i, j; | |
1514 | u32 sq_config; | |
1515 | u32 sq_gpr_resource_mgmt_1 = 0; | |
1516 | u32 sq_gpr_resource_mgmt_2 = 0; | |
1517 | u32 sq_thread_resource_mgmt = 0; | |
1518 | u32 sq_stack_resource_mgmt_1 = 0; | |
1519 | u32 sq_stack_resource_mgmt_2 = 0; | |
1520 | ||
1521 | /* FIXME: implement */ | |
1522 | switch (rdev->family) { | |
1523 | case CHIP_R600: | |
1524 | rdev->config.r600.max_pipes = 4; | |
1525 | rdev->config.r600.max_tile_pipes = 8; | |
1526 | rdev->config.r600.max_simds = 4; | |
1527 | rdev->config.r600.max_backends = 4; | |
1528 | rdev->config.r600.max_gprs = 256; | |
1529 | rdev->config.r600.max_threads = 192; | |
1530 | rdev->config.r600.max_stack_entries = 256; | |
1531 | rdev->config.r600.max_hw_contexts = 8; | |
1532 | rdev->config.r600.max_gs_threads = 16; | |
1533 | rdev->config.r600.sx_max_export_size = 128; | |
1534 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1535 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1536 | rdev->config.r600.sq_num_cf_insts = 2; | |
1537 | break; | |
1538 | case CHIP_RV630: | |
1539 | case CHIP_RV635: | |
1540 | rdev->config.r600.max_pipes = 2; | |
1541 | rdev->config.r600.max_tile_pipes = 2; | |
1542 | rdev->config.r600.max_simds = 3; | |
1543 | rdev->config.r600.max_backends = 1; | |
1544 | rdev->config.r600.max_gprs = 128; | |
1545 | rdev->config.r600.max_threads = 192; | |
1546 | rdev->config.r600.max_stack_entries = 128; | |
1547 | rdev->config.r600.max_hw_contexts = 8; | |
1548 | rdev->config.r600.max_gs_threads = 4; | |
1549 | rdev->config.r600.sx_max_export_size = 128; | |
1550 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1551 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1552 | rdev->config.r600.sq_num_cf_insts = 2; | |
1553 | break; | |
1554 | case CHIP_RV610: | |
1555 | case CHIP_RV620: | |
1556 | case CHIP_RS780: | |
1557 | case CHIP_RS880: | |
1558 | rdev->config.r600.max_pipes = 1; | |
1559 | rdev->config.r600.max_tile_pipes = 1; | |
1560 | rdev->config.r600.max_simds = 2; | |
1561 | rdev->config.r600.max_backends = 1; | |
1562 | rdev->config.r600.max_gprs = 128; | |
1563 | rdev->config.r600.max_threads = 192; | |
1564 | rdev->config.r600.max_stack_entries = 128; | |
1565 | rdev->config.r600.max_hw_contexts = 4; | |
1566 | rdev->config.r600.max_gs_threads = 4; | |
1567 | rdev->config.r600.sx_max_export_size = 128; | |
1568 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1569 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1570 | rdev->config.r600.sq_num_cf_insts = 1; | |
1571 | break; | |
1572 | case CHIP_RV670: | |
1573 | rdev->config.r600.max_pipes = 4; | |
1574 | rdev->config.r600.max_tile_pipes = 4; | |
1575 | rdev->config.r600.max_simds = 4; | |
1576 | rdev->config.r600.max_backends = 4; | |
1577 | rdev->config.r600.max_gprs = 192; | |
1578 | rdev->config.r600.max_threads = 192; | |
1579 | rdev->config.r600.max_stack_entries = 256; | |
1580 | rdev->config.r600.max_hw_contexts = 8; | |
1581 | rdev->config.r600.max_gs_threads = 16; | |
1582 | rdev->config.r600.sx_max_export_size = 128; | |
1583 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1584 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1585 | rdev->config.r600.sq_num_cf_insts = 2; | |
1586 | break; | |
1587 | default: | |
1588 | break; | |
1589 | } | |
1590 | ||
1591 | /* Initialize HDP */ | |
1592 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1593 | WREG32((0x2c14 + j), 0x00000000); | |
1594 | WREG32((0x2c18 + j), 0x00000000); | |
1595 | WREG32((0x2c1c + j), 0x00000000); | |
1596 | WREG32((0x2c20 + j), 0x00000000); | |
1597 | WREG32((0x2c24 + j), 0x00000000); | |
1598 | } | |
1599 | ||
1600 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1601 | ||
1602 | /* Setup tiling */ | |
1603 | tiling_config = 0; | |
1604 | ramcfg = RREG32(RAMCFG); | |
1605 | switch (rdev->config.r600.max_tile_pipes) { | |
1606 | case 1: | |
1607 | tiling_config |= PIPE_TILING(0); | |
1608 | break; | |
1609 | case 2: | |
1610 | tiling_config |= PIPE_TILING(1); | |
1611 | break; | |
1612 | case 4: | |
1613 | tiling_config |= PIPE_TILING(2); | |
1614 | break; | |
1615 | case 8: | |
1616 | tiling_config |= PIPE_TILING(3); | |
1617 | break; | |
1618 | default: | |
1619 | break; | |
1620 | } | |
d03f5d59 | 1621 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
961fb597 | 1622 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
3ce0a23d | 1623 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
881fe6c1 AD |
1624 | tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
1625 | if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) | |
1626 | rdev->config.r600.tiling_group_size = 512; | |
1627 | else | |
1628 | rdev->config.r600.tiling_group_size = 256; | |
3ce0a23d JG |
1629 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
1630 | if (tmp > 3) { | |
1631 | tiling_config |= ROW_TILING(3); | |
1632 | tiling_config |= SAMPLE_SPLIT(3); | |
1633 | } else { | |
1634 | tiling_config |= ROW_TILING(tmp); | |
1635 | tiling_config |= SAMPLE_SPLIT(tmp); | |
1636 | } | |
1637 | tiling_config |= BANK_SWAPS(1); | |
d03f5d59 AD |
1638 | |
1639 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | |
1640 | cc_rb_backend_disable |= | |
1641 | BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); | |
1642 | ||
1643 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; | |
1644 | cc_gc_shader_pipe_config |= | |
1645 | INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); | |
1646 | cc_gc_shader_pipe_config |= | |
1647 | INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); | |
1648 | ||
1649 | backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, | |
1650 | (R6XX_MAX_BACKENDS - | |
1651 | r600_count_pipe_bits((cc_rb_backend_disable & | |
1652 | R6XX_MAX_BACKENDS_MASK) >> 16)), | |
1653 | (cc_rb_backend_disable >> 16)); | |
e7aeeba6 | 1654 | rdev->config.r600.tile_config = tiling_config; |
e55b9422 | 1655 | rdev->config.r600.backend_map = backend_map; |
d03f5d59 | 1656 | tiling_config |= BACKEND_MAP(backend_map); |
3ce0a23d JG |
1657 | WREG32(GB_TILING_CONFIG, tiling_config); |
1658 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); | |
1659 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); | |
1660 | ||
3ce0a23d | 1661 | /* Setup pipes */ |
d03f5d59 AD |
1662 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
1663 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
f867c60d | 1664 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
3ce0a23d | 1665 | |
d03f5d59 | 1666 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
3ce0a23d JG |
1667 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
1668 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
1669 | ||
1670 | /* Setup some CP states */ | |
1671 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); | |
1672 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); | |
1673 | ||
1674 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | | |
1675 | SYNC_WALKER | SYNC_ALIGNER)); | |
1676 | /* Setup various GPU states */ | |
1677 | if (rdev->family == CHIP_RV670) | |
1678 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); | |
1679 | ||
1680 | tmp = RREG32(SX_DEBUG_1); | |
1681 | tmp |= SMX_EVENT_RELEASE; | |
1682 | if ((rdev->family > CHIP_R600)) | |
1683 | tmp |= ENABLE_NEW_SMX_ADDRESS; | |
1684 | WREG32(SX_DEBUG_1, tmp); | |
1685 | ||
1686 | if (((rdev->family) == CHIP_R600) || | |
1687 | ((rdev->family) == CHIP_RV630) || | |
1688 | ((rdev->family) == CHIP_RV610) || | |
1689 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1690 | ((rdev->family) == CHIP_RS780) || |
1691 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1692 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
1693 | } else { | |
1694 | WREG32(DB_DEBUG, 0); | |
1695 | } | |
1696 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | | |
1697 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); | |
1698 | ||
1699 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1700 | WREG32(VGT_NUM_INSTANCES, 0); | |
1701 | ||
1702 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); | |
1703 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); | |
1704 | ||
1705 | tmp = RREG32(SQ_MS_FIFO_SIZES); | |
1706 | if (((rdev->family) == CHIP_RV610) || | |
1707 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1708 | ((rdev->family) == CHIP_RS780) || |
1709 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1710 | tmp = (CACHE_FIFO_SIZE(0xa) | |
1711 | FETCH_FIFO_HIWATER(0xa) | | |
1712 | DONE_FIFO_HIWATER(0xe0) | | |
1713 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
1714 | } else if (((rdev->family) == CHIP_R600) || | |
1715 | ((rdev->family) == CHIP_RV630)) { | |
1716 | tmp &= ~DONE_FIFO_HIWATER(0xff); | |
1717 | tmp |= DONE_FIFO_HIWATER(0x4); | |
1718 | } | |
1719 | WREG32(SQ_MS_FIFO_SIZES, tmp); | |
1720 | ||
1721 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
1722 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
1723 | */ | |
1724 | sq_config = RREG32(SQ_CONFIG); | |
1725 | sq_config &= ~(PS_PRIO(3) | | |
1726 | VS_PRIO(3) | | |
1727 | GS_PRIO(3) | | |
1728 | ES_PRIO(3)); | |
1729 | sq_config |= (DX9_CONSTS | | |
1730 | VC_ENABLE | | |
1731 | PS_PRIO(0) | | |
1732 | VS_PRIO(1) | | |
1733 | GS_PRIO(2) | | |
1734 | ES_PRIO(3)); | |
1735 | ||
1736 | if ((rdev->family) == CHIP_R600) { | |
1737 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | | |
1738 | NUM_VS_GPRS(124) | | |
1739 | NUM_CLAUSE_TEMP_GPRS(4)); | |
1740 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | | |
1741 | NUM_ES_GPRS(0)); | |
1742 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | | |
1743 | NUM_VS_THREADS(48) | | |
1744 | NUM_GS_THREADS(4) | | |
1745 | NUM_ES_THREADS(4)); | |
1746 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | | |
1747 | NUM_VS_STACK_ENTRIES(128)); | |
1748 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | | |
1749 | NUM_ES_STACK_ENTRIES(0)); | |
1750 | } else if (((rdev->family) == CHIP_RV610) || | |
1751 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1752 | ((rdev->family) == CHIP_RS780) || |
1753 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1754 | /* no vertex cache */ |
1755 | sq_config &= ~VC_ENABLE; | |
1756 | ||
1757 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1758 | NUM_VS_GPRS(44) | | |
1759 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1760 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1761 | NUM_ES_GPRS(17)); | |
1762 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1763 | NUM_VS_THREADS(78) | | |
1764 | NUM_GS_THREADS(4) | | |
1765 | NUM_ES_THREADS(31)); | |
1766 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1767 | NUM_VS_STACK_ENTRIES(40)); | |
1768 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1769 | NUM_ES_STACK_ENTRIES(16)); | |
1770 | } else if (((rdev->family) == CHIP_RV630) || | |
1771 | ((rdev->family) == CHIP_RV635)) { | |
1772 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1773 | NUM_VS_GPRS(44) | | |
1774 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1775 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | | |
1776 | NUM_ES_GPRS(18)); | |
1777 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1778 | NUM_VS_THREADS(78) | | |
1779 | NUM_GS_THREADS(4) | | |
1780 | NUM_ES_THREADS(31)); | |
1781 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1782 | NUM_VS_STACK_ENTRIES(40)); | |
1783 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1784 | NUM_ES_STACK_ENTRIES(16)); | |
1785 | } else if ((rdev->family) == CHIP_RV670) { | |
1786 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1787 | NUM_VS_GPRS(44) | | |
1788 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1789 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1790 | NUM_ES_GPRS(17)); | |
1791 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1792 | NUM_VS_THREADS(78) | | |
1793 | NUM_GS_THREADS(4) | | |
1794 | NUM_ES_THREADS(31)); | |
1795 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | | |
1796 | NUM_VS_STACK_ENTRIES(64)); | |
1797 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | | |
1798 | NUM_ES_STACK_ENTRIES(64)); | |
1799 | } | |
1800 | ||
1801 | WREG32(SQ_CONFIG, sq_config); | |
1802 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1803 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1804 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1805 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1806 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1807 | ||
1808 | if (((rdev->family) == CHIP_RV610) || | |
1809 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1810 | ((rdev->family) == CHIP_RS780) || |
1811 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1812 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
1813 | } else { | |
1814 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); | |
1815 | } | |
1816 | ||
1817 | /* More default values. 2D/3D driver should adjust as needed */ | |
1818 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | | |
1819 | S1_X(0x4) | S1_Y(0xc))); | |
1820 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | | |
1821 | S1_X(0x2) | S1_Y(0x2) | | |
1822 | S2_X(0xa) | S2_Y(0x6) | | |
1823 | S3_X(0x6) | S3_Y(0xa))); | |
1824 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | | |
1825 | S1_X(0x4) | S1_Y(0xc) | | |
1826 | S2_X(0x1) | S2_Y(0x6) | | |
1827 | S3_X(0xa) | S3_Y(0xe))); | |
1828 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | | |
1829 | S5_X(0x0) | S5_Y(0x0) | | |
1830 | S6_X(0xb) | S6_Y(0x4) | | |
1831 | S7_X(0x7) | S7_Y(0x8))); | |
1832 | ||
1833 | WREG32(VGT_STRMOUT_EN, 0); | |
1834 | tmp = rdev->config.r600.max_pipes * 16; | |
1835 | switch (rdev->family) { | |
1836 | case CHIP_RV610: | |
3ce0a23d | 1837 | case CHIP_RV620: |
ee59f2b4 AD |
1838 | case CHIP_RS780: |
1839 | case CHIP_RS880: | |
3ce0a23d JG |
1840 | tmp += 32; |
1841 | break; | |
1842 | case CHIP_RV670: | |
1843 | tmp += 128; | |
1844 | break; | |
1845 | default: | |
1846 | break; | |
1847 | } | |
1848 | if (tmp > 256) { | |
1849 | tmp = 256; | |
1850 | } | |
1851 | WREG32(VGT_ES_PER_GS, 128); | |
1852 | WREG32(VGT_GS_PER_ES, tmp); | |
1853 | WREG32(VGT_GS_PER_VS, 2); | |
1854 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
1855 | ||
1856 | /* more default values. 2D/3D driver should adjust as needed */ | |
1857 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
1858 | WREG32(VGT_STRMOUT_EN, 0); | |
1859 | WREG32(SX_MISC, 0); | |
1860 | WREG32(PA_SC_MODE_CNTL, 0); | |
1861 | WREG32(PA_SC_AA_CONFIG, 0); | |
1862 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
1863 | WREG32(SPI_INPUT_Z, 0); | |
1864 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
1865 | WREG32(CB_COLOR7_FRAG, 0); | |
1866 | ||
1867 | /* Clear render buffer base addresses */ | |
1868 | WREG32(CB_COLOR0_BASE, 0); | |
1869 | WREG32(CB_COLOR1_BASE, 0); | |
1870 | WREG32(CB_COLOR2_BASE, 0); | |
1871 | WREG32(CB_COLOR3_BASE, 0); | |
1872 | WREG32(CB_COLOR4_BASE, 0); | |
1873 | WREG32(CB_COLOR5_BASE, 0); | |
1874 | WREG32(CB_COLOR6_BASE, 0); | |
1875 | WREG32(CB_COLOR7_BASE, 0); | |
1876 | WREG32(CB_COLOR7_FRAG, 0); | |
1877 | ||
1878 | switch (rdev->family) { | |
1879 | case CHIP_RV610: | |
3ce0a23d | 1880 | case CHIP_RV620: |
ee59f2b4 AD |
1881 | case CHIP_RS780: |
1882 | case CHIP_RS880: | |
3ce0a23d JG |
1883 | tmp = TC_L2_SIZE(8); |
1884 | break; | |
1885 | case CHIP_RV630: | |
1886 | case CHIP_RV635: | |
1887 | tmp = TC_L2_SIZE(4); | |
1888 | break; | |
1889 | case CHIP_R600: | |
1890 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; | |
1891 | break; | |
1892 | default: | |
1893 | tmp = TC_L2_SIZE(0); | |
1894 | break; | |
1895 | } | |
1896 | WREG32(TC_CNTL, tmp); | |
1897 | ||
1898 | tmp = RREG32(HDP_HOST_PATH_CNTL); | |
1899 | WREG32(HDP_HOST_PATH_CNTL, tmp); | |
1900 | ||
1901 | tmp = RREG32(ARB_POP); | |
1902 | tmp |= ENABLE_TC128; | |
1903 | WREG32(ARB_POP, tmp); | |
1904 | ||
1905 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1906 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
1907 | NUM_CLIP_SEQ(3))); | |
1908 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); | |
1909 | } | |
1910 | ||
1911 | ||
771fe6b9 JG |
1912 | /* |
1913 | * Indirect registers accessor | |
1914 | */ | |
3ce0a23d JG |
1915 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
1916 | { | |
1917 | u32 r; | |
1918 | ||
1919 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1920 | (void)RREG32(PCIE_PORT_INDEX); | |
1921 | r = RREG32(PCIE_PORT_DATA); | |
1922 | return r; | |
1923 | } | |
1924 | ||
1925 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1926 | { | |
1927 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1928 | (void)RREG32(PCIE_PORT_INDEX); | |
1929 | WREG32(PCIE_PORT_DATA, (v)); | |
1930 | (void)RREG32(PCIE_PORT_DATA); | |
1931 | } | |
1932 | ||
3ce0a23d JG |
1933 | /* |
1934 | * CP & Ring | |
1935 | */ | |
1936 | void r600_cp_stop(struct radeon_device *rdev) | |
1937 | { | |
53595338 | 1938 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
3ce0a23d | 1939 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
724c80e1 | 1940 | WREG32(SCRATCH_UMSK, 0); |
3ce0a23d JG |
1941 | } |
1942 | ||
d8f60cfc | 1943 | int r600_init_microcode(struct radeon_device *rdev) |
3ce0a23d JG |
1944 | { |
1945 | struct platform_device *pdev; | |
1946 | const char *chip_name; | |
d8f60cfc AD |
1947 | const char *rlc_chip_name; |
1948 | size_t pfp_req_size, me_req_size, rlc_req_size; | |
3ce0a23d JG |
1949 | char fw_name[30]; |
1950 | int err; | |
1951 | ||
1952 | DRM_DEBUG("\n"); | |
1953 | ||
1954 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); | |
1955 | err = IS_ERR(pdev); | |
1956 | if (err) { | |
1957 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
1958 | return -EINVAL; | |
1959 | } | |
1960 | ||
1961 | switch (rdev->family) { | |
d8f60cfc AD |
1962 | case CHIP_R600: |
1963 | chip_name = "R600"; | |
1964 | rlc_chip_name = "R600"; | |
1965 | break; | |
1966 | case CHIP_RV610: | |
1967 | chip_name = "RV610"; | |
1968 | rlc_chip_name = "R600"; | |
1969 | break; | |
1970 | case CHIP_RV630: | |
1971 | chip_name = "RV630"; | |
1972 | rlc_chip_name = "R600"; | |
1973 | break; | |
1974 | case CHIP_RV620: | |
1975 | chip_name = "RV620"; | |
1976 | rlc_chip_name = "R600"; | |
1977 | break; | |
1978 | case CHIP_RV635: | |
1979 | chip_name = "RV635"; | |
1980 | rlc_chip_name = "R600"; | |
1981 | break; | |
1982 | case CHIP_RV670: | |
1983 | chip_name = "RV670"; | |
1984 | rlc_chip_name = "R600"; | |
1985 | break; | |
3ce0a23d | 1986 | case CHIP_RS780: |
d8f60cfc AD |
1987 | case CHIP_RS880: |
1988 | chip_name = "RS780"; | |
1989 | rlc_chip_name = "R600"; | |
1990 | break; | |
1991 | case CHIP_RV770: | |
1992 | chip_name = "RV770"; | |
1993 | rlc_chip_name = "R700"; | |
1994 | break; | |
3ce0a23d | 1995 | case CHIP_RV730: |
d8f60cfc AD |
1996 | case CHIP_RV740: |
1997 | chip_name = "RV730"; | |
1998 | rlc_chip_name = "R700"; | |
1999 | break; | |
2000 | case CHIP_RV710: | |
2001 | chip_name = "RV710"; | |
2002 | rlc_chip_name = "R700"; | |
2003 | break; | |
fe251e2f AD |
2004 | case CHIP_CEDAR: |
2005 | chip_name = "CEDAR"; | |
45f9a39b | 2006 | rlc_chip_name = "CEDAR"; |
fe251e2f AD |
2007 | break; |
2008 | case CHIP_REDWOOD: | |
2009 | chip_name = "REDWOOD"; | |
45f9a39b | 2010 | rlc_chip_name = "REDWOOD"; |
fe251e2f AD |
2011 | break; |
2012 | case CHIP_JUNIPER: | |
2013 | chip_name = "JUNIPER"; | |
45f9a39b | 2014 | rlc_chip_name = "JUNIPER"; |
fe251e2f AD |
2015 | break; |
2016 | case CHIP_CYPRESS: | |
2017 | case CHIP_HEMLOCK: | |
2018 | chip_name = "CYPRESS"; | |
45f9a39b | 2019 | rlc_chip_name = "CYPRESS"; |
fe251e2f | 2020 | break; |
439bd6cd AD |
2021 | case CHIP_PALM: |
2022 | chip_name = "PALM"; | |
2023 | rlc_chip_name = "SUMO"; | |
2024 | break; | |
d5c5a72f AD |
2025 | case CHIP_SUMO: |
2026 | chip_name = "SUMO"; | |
2027 | rlc_chip_name = "SUMO"; | |
2028 | break; | |
2029 | case CHIP_SUMO2: | |
2030 | chip_name = "SUMO2"; | |
2031 | rlc_chip_name = "SUMO"; | |
2032 | break; | |
3ce0a23d JG |
2033 | default: BUG(); |
2034 | } | |
2035 | ||
fe251e2f AD |
2036 | if (rdev->family >= CHIP_CEDAR) { |
2037 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; | |
2038 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; | |
45f9a39b | 2039 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
fe251e2f | 2040 | } else if (rdev->family >= CHIP_RV770) { |
3ce0a23d JG |
2041 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
2042 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
d8f60cfc | 2043 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
2044 | } else { |
2045 | pfp_req_size = PFP_UCODE_SIZE * 4; | |
2046 | me_req_size = PM4_UCODE_SIZE * 12; | |
d8f60cfc | 2047 | rlc_req_size = RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
2048 | } |
2049 | ||
d8f60cfc | 2050 | DRM_INFO("Loading %s Microcode\n", chip_name); |
3ce0a23d JG |
2051 | |
2052 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
2053 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); | |
2054 | if (err) | |
2055 | goto out; | |
2056 | if (rdev->pfp_fw->size != pfp_req_size) { | |
2057 | printk(KERN_ERR | |
2058 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2059 | rdev->pfp_fw->size, fw_name); | |
2060 | err = -EINVAL; | |
2061 | goto out; | |
2062 | } | |
2063 | ||
2064 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
2065 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); | |
2066 | if (err) | |
2067 | goto out; | |
2068 | if (rdev->me_fw->size != me_req_size) { | |
2069 | printk(KERN_ERR | |
2070 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2071 | rdev->me_fw->size, fw_name); | |
2072 | err = -EINVAL; | |
2073 | } | |
d8f60cfc AD |
2074 | |
2075 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
2076 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); | |
2077 | if (err) | |
2078 | goto out; | |
2079 | if (rdev->rlc_fw->size != rlc_req_size) { | |
2080 | printk(KERN_ERR | |
2081 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", | |
2082 | rdev->rlc_fw->size, fw_name); | |
2083 | err = -EINVAL; | |
2084 | } | |
2085 | ||
3ce0a23d JG |
2086 | out: |
2087 | platform_device_unregister(pdev); | |
2088 | ||
2089 | if (err) { | |
2090 | if (err != -EINVAL) | |
2091 | printk(KERN_ERR | |
2092 | "r600_cp: Failed to load firmware \"%s\"\n", | |
2093 | fw_name); | |
2094 | release_firmware(rdev->pfp_fw); | |
2095 | rdev->pfp_fw = NULL; | |
2096 | release_firmware(rdev->me_fw); | |
2097 | rdev->me_fw = NULL; | |
d8f60cfc AD |
2098 | release_firmware(rdev->rlc_fw); |
2099 | rdev->rlc_fw = NULL; | |
3ce0a23d JG |
2100 | } |
2101 | return err; | |
2102 | } | |
2103 | ||
2104 | static int r600_cp_load_microcode(struct radeon_device *rdev) | |
2105 | { | |
2106 | const __be32 *fw_data; | |
2107 | int i; | |
2108 | ||
2109 | if (!rdev->me_fw || !rdev->pfp_fw) | |
2110 | return -EINVAL; | |
2111 | ||
2112 | r600_cp_stop(rdev); | |
2113 | ||
4eace7fd CC |
2114 | WREG32(CP_RB_CNTL, |
2115 | #ifdef __BIG_ENDIAN | |
2116 | BUF_SWAP_32BIT | | |
2117 | #endif | |
2118 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
3ce0a23d JG |
2119 | |
2120 | /* Reset cp */ | |
2121 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2122 | RREG32(GRBM_SOFT_RESET); | |
2123 | mdelay(15); | |
2124 | WREG32(GRBM_SOFT_RESET, 0); | |
2125 | ||
2126 | WREG32(CP_ME_RAM_WADDR, 0); | |
2127 | ||
2128 | fw_data = (const __be32 *)rdev->me_fw->data; | |
2129 | WREG32(CP_ME_RAM_WADDR, 0); | |
2130 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) | |
2131 | WREG32(CP_ME_RAM_DATA, | |
2132 | be32_to_cpup(fw_data++)); | |
2133 | ||
2134 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
2135 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
2136 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
2137 | WREG32(CP_PFP_UCODE_DATA, | |
2138 | be32_to_cpup(fw_data++)); | |
2139 | ||
2140 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
2141 | WREG32(CP_ME_RAM_WADDR, 0); | |
2142 | WREG32(CP_ME_RAM_RADDR, 0); | |
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | int r600_cp_start(struct radeon_device *rdev) | |
2147 | { | |
e32eb50d | 2148 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3ce0a23d JG |
2149 | int r; |
2150 | uint32_t cp_me; | |
2151 | ||
e32eb50d | 2152 | r = radeon_ring_lock(rdev, ring, 7); |
3ce0a23d JG |
2153 | if (r) { |
2154 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
2155 | return r; | |
2156 | } | |
e32eb50d CK |
2157 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
2158 | radeon_ring_write(ring, 0x1); | |
7e7b41d2 | 2159 | if (rdev->family >= CHIP_RV770) { |
e32eb50d CK |
2160 | radeon_ring_write(ring, 0x0); |
2161 | radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); | |
fe251e2f | 2162 | } else { |
e32eb50d CK |
2163 | radeon_ring_write(ring, 0x3); |
2164 | radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); | |
3ce0a23d | 2165 | } |
e32eb50d CK |
2166 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
2167 | radeon_ring_write(ring, 0); | |
2168 | radeon_ring_write(ring, 0); | |
2169 | radeon_ring_unlock_commit(rdev, ring); | |
3ce0a23d JG |
2170 | |
2171 | cp_me = 0xff; | |
2172 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | |
2173 | return 0; | |
2174 | } | |
2175 | ||
2176 | int r600_cp_resume(struct radeon_device *rdev) | |
2177 | { | |
e32eb50d | 2178 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3ce0a23d JG |
2179 | u32 tmp; |
2180 | u32 rb_bufsz; | |
2181 | int r; | |
2182 | ||
2183 | /* Reset cp */ | |
2184 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2185 | RREG32(GRBM_SOFT_RESET); | |
2186 | mdelay(15); | |
2187 | WREG32(GRBM_SOFT_RESET, 0); | |
2188 | ||
2189 | /* Set ring buffer size */ | |
e32eb50d | 2190 | rb_bufsz = drm_order(ring->ring_size / 8); |
724c80e1 | 2191 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3ce0a23d | 2192 | #ifdef __BIG_ENDIAN |
d6f28938 | 2193 | tmp |= BUF_SWAP_32BIT; |
3ce0a23d | 2194 | #endif |
d6f28938 | 2195 | WREG32(CP_RB_CNTL, tmp); |
15d3332f | 2196 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
3ce0a23d JG |
2197 | |
2198 | /* Set the write pointer delay */ | |
2199 | WREG32(CP_RB_WPTR_DELAY, 0); | |
2200 | ||
2201 | /* Initialize the ring buffer's read and write pointers */ | |
3ce0a23d JG |
2202 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
2203 | WREG32(CP_RB_RPTR_WR, 0); | |
e32eb50d CK |
2204 | ring->wptr = 0; |
2205 | WREG32(CP_RB_WPTR, ring->wptr); | |
724c80e1 AD |
2206 | |
2207 | /* set the wb address whether it's enabled or not */ | |
4eace7fd | 2208 | WREG32(CP_RB_RPTR_ADDR, |
4eace7fd | 2209 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
724c80e1 AD |
2210 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
2211 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | |
2212 | ||
2213 | if (rdev->wb.enabled) | |
2214 | WREG32(SCRATCH_UMSK, 0xff); | |
2215 | else { | |
2216 | tmp |= RB_NO_UPDATE; | |
2217 | WREG32(SCRATCH_UMSK, 0); | |
2218 | } | |
2219 | ||
3ce0a23d JG |
2220 | mdelay(1); |
2221 | WREG32(CP_RB_CNTL, tmp); | |
2222 | ||
e32eb50d | 2223 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
3ce0a23d JG |
2224 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
2225 | ||
e32eb50d | 2226 | ring->rptr = RREG32(CP_RB_RPTR); |
3ce0a23d JG |
2227 | |
2228 | r600_cp_start(rdev); | |
e32eb50d | 2229 | ring->ready = true; |
f712812e | 2230 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
3ce0a23d | 2231 | if (r) { |
e32eb50d | 2232 | ring->ready = false; |
3ce0a23d JG |
2233 | return r; |
2234 | } | |
2235 | return 0; | |
2236 | } | |
2237 | ||
e32eb50d | 2238 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) |
3ce0a23d JG |
2239 | { |
2240 | u32 rb_bufsz; | |
2241 | ||
2242 | /* Align ring size */ | |
2243 | rb_bufsz = drm_order(ring_size / 8); | |
2244 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
e32eb50d CK |
2245 | ring->ring_size = ring_size; |
2246 | ring->align_mask = 16 - 1; | |
3ce0a23d JG |
2247 | } |
2248 | ||
655efd3d JG |
2249 | void r600_cp_fini(struct radeon_device *rdev) |
2250 | { | |
2251 | r600_cp_stop(rdev); | |
e32eb50d | 2252 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
655efd3d JG |
2253 | } |
2254 | ||
3ce0a23d JG |
2255 | |
2256 | /* | |
2257 | * GPU scratch registers helpers function. | |
2258 | */ | |
2259 | void r600_scratch_init(struct radeon_device *rdev) | |
2260 | { | |
2261 | int i; | |
2262 | ||
2263 | rdev->scratch.num_reg = 7; | |
724c80e1 | 2264 | rdev->scratch.reg_base = SCRATCH_REG0; |
3ce0a23d JG |
2265 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
2266 | rdev->scratch.free[i] = true; | |
724c80e1 | 2267 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
3ce0a23d JG |
2268 | } |
2269 | } | |
2270 | ||
e32eb50d | 2271 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d JG |
2272 | { |
2273 | uint32_t scratch; | |
2274 | uint32_t tmp = 0; | |
e32eb50d | 2275 | unsigned i, ridx = radeon_ring_index(rdev, ring); |
3ce0a23d JG |
2276 | int r; |
2277 | ||
2278 | r = radeon_scratch_get(rdev, &scratch); | |
2279 | if (r) { | |
2280 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
2281 | return r; | |
2282 | } | |
2283 | WREG32(scratch, 0xCAFEDEAD); | |
e32eb50d | 2284 | r = radeon_ring_lock(rdev, ring, 3); |
3ce0a23d | 2285 | if (r) { |
bf852799 | 2286 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r); |
3ce0a23d JG |
2287 | radeon_scratch_free(rdev, scratch); |
2288 | return r; | |
2289 | } | |
e32eb50d CK |
2290 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2291 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2292 | radeon_ring_write(ring, 0xDEADBEEF); | |
2293 | radeon_ring_unlock_commit(rdev, ring); | |
3ce0a23d JG |
2294 | for (i = 0; i < rdev->usec_timeout; i++) { |
2295 | tmp = RREG32(scratch); | |
2296 | if (tmp == 0xDEADBEEF) | |
2297 | break; | |
2298 | DRM_UDELAY(1); | |
2299 | } | |
2300 | if (i < rdev->usec_timeout) { | |
bf852799 | 2301 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i); |
3ce0a23d | 2302 | } else { |
bf852799 CK |
2303 | DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
2304 | ridx, scratch, tmp); | |
3ce0a23d JG |
2305 | r = -EINVAL; |
2306 | } | |
2307 | radeon_scratch_free(rdev, scratch); | |
2308 | return r; | |
2309 | } | |
2310 | ||
3ce0a23d JG |
2311 | void r600_fence_ring_emit(struct radeon_device *rdev, |
2312 | struct radeon_fence *fence) | |
2313 | { | |
e32eb50d | 2314 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
7b1f2485 | 2315 | |
d0f8a854 | 2316 | if (rdev->wb.use_event) { |
30eb77f4 | 2317 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
77b1bad4 | 2318 | /* flush read cache over gart */ |
e32eb50d CK |
2319 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
2320 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | | |
2321 | PACKET3_VC_ACTION_ENA | | |
2322 | PACKET3_SH_ACTION_ENA); | |
2323 | radeon_ring_write(ring, 0xFFFFFFFF); | |
2324 | radeon_ring_write(ring, 0); | |
2325 | radeon_ring_write(ring, 10); /* poll interval */ | |
d0f8a854 | 2326 | /* EVENT_WRITE_EOP - flush caches, send int */ |
e32eb50d CK |
2327 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
2328 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); | |
2329 | radeon_ring_write(ring, addr & 0xffffffff); | |
2330 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); | |
2331 | radeon_ring_write(ring, fence->seq); | |
2332 | radeon_ring_write(ring, 0); | |
d0f8a854 | 2333 | } else { |
77b1bad4 | 2334 | /* flush read cache over gart */ |
e32eb50d CK |
2335 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
2336 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | | |
2337 | PACKET3_VC_ACTION_ENA | | |
2338 | PACKET3_SH_ACTION_ENA); | |
2339 | radeon_ring_write(ring, 0xFFFFFFFF); | |
2340 | radeon_ring_write(ring, 0); | |
2341 | radeon_ring_write(ring, 10); /* poll interval */ | |
2342 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); | |
2343 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); | |
d0f8a854 | 2344 | /* wait for 3D idle clean */ |
e32eb50d CK |
2345 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2346 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2347 | radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | |
d0f8a854 | 2348 | /* Emit fence sequence & fire IRQ */ |
e32eb50d CK |
2349 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2350 | radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2351 | radeon_ring_write(ring, fence->seq); | |
d0f8a854 | 2352 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
e32eb50d CK |
2353 | radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); |
2354 | radeon_ring_write(ring, RB_INT_STAT); | |
d0f8a854 | 2355 | } |
3ce0a23d JG |
2356 | } |
2357 | ||
15d3332f | 2358 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 2359 | struct radeon_ring *ring, |
15d3332f | 2360 | struct radeon_semaphore *semaphore, |
7b1f2485 | 2361 | bool emit_wait) |
15d3332f CK |
2362 | { |
2363 | uint64_t addr = semaphore->gpu_addr; | |
2364 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; | |
2365 | ||
0be70439 CK |
2366 | if (rdev->family < CHIP_CAYMAN) |
2367 | sel |= PACKET3_SEM_WAIT_ON_SIGNAL; | |
2368 | ||
e32eb50d CK |
2369 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); |
2370 | radeon_ring_write(ring, addr & 0xffffffff); | |
2371 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); | |
15d3332f CK |
2372 | } |
2373 | ||
3ce0a23d | 2374 | int r600_copy_blit(struct radeon_device *rdev, |
003cefe0 AD |
2375 | uint64_t src_offset, |
2376 | uint64_t dst_offset, | |
2377 | unsigned num_gpu_pages, | |
2378 | struct radeon_fence *fence) | |
3ce0a23d | 2379 | { |
ff82f052 JG |
2380 | int r; |
2381 | ||
2382 | mutex_lock(&rdev->r600_blit.mutex); | |
2383 | rdev->r600_blit.vb_ib = NULL; | |
017ed801 | 2384 | r = r600_blit_prepare_copy(rdev, num_gpu_pages); |
ff82f052 JG |
2385 | if (r) { |
2386 | if (rdev->r600_blit.vb_ib) | |
2387 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); | |
2388 | mutex_unlock(&rdev->r600_blit.mutex); | |
2389 | return r; | |
2390 | } | |
017ed801 | 2391 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages); |
3ce0a23d | 2392 | r600_blit_done_copy(rdev, fence); |
ff82f052 | 2393 | mutex_unlock(&rdev->r600_blit.mutex); |
3ce0a23d JG |
2394 | return 0; |
2395 | } | |
2396 | ||
6ddddfe7 AD |
2397 | void r600_blit_suspend(struct radeon_device *rdev) |
2398 | { | |
2399 | int r; | |
2400 | ||
2401 | /* unpin shaders bo */ | |
2402 | if (rdev->r600_blit.shader_obj) { | |
2403 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
2404 | if (!r) { | |
2405 | radeon_bo_unpin(rdev->r600_blit.shader_obj); | |
2406 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
2407 | } | |
2408 | } | |
2409 | } | |
2410 | ||
3ce0a23d JG |
2411 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
2412 | uint32_t tiling_flags, uint32_t pitch, | |
2413 | uint32_t offset, uint32_t obj_size) | |
2414 | { | |
2415 | /* FIXME: implement */ | |
2416 | return 0; | |
2417 | } | |
2418 | ||
2419 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |
2420 | { | |
2421 | /* FIXME: implement */ | |
2422 | } | |
2423 | ||
fc30b8ef | 2424 | int r600_startup(struct radeon_device *rdev) |
3ce0a23d | 2425 | { |
e32eb50d | 2426 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3ce0a23d JG |
2427 | int r; |
2428 | ||
9e46a48d AD |
2429 | /* enable pcie gen2 link */ |
2430 | r600_pcie_gen2_enable(rdev); | |
2431 | ||
779720a3 AD |
2432 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
2433 | r = r600_init_microcode(rdev); | |
2434 | if (r) { | |
2435 | DRM_ERROR("Failed to load firmware!\n"); | |
2436 | return r; | |
2437 | } | |
2438 | } | |
2439 | ||
16cdf04d AD |
2440 | r = r600_vram_scratch_init(rdev); |
2441 | if (r) | |
2442 | return r; | |
2443 | ||
a3c1945a | 2444 | r600_mc_program(rdev); |
1a029b76 JG |
2445 | if (rdev->flags & RADEON_IS_AGP) { |
2446 | r600_agp_enable(rdev); | |
2447 | } else { | |
2448 | r = r600_pcie_gart_enable(rdev); | |
2449 | if (r) | |
2450 | return r; | |
2451 | } | |
3ce0a23d | 2452 | r600_gpu_init(rdev); |
c38c7b64 JG |
2453 | r = r600_blit_init(rdev); |
2454 | if (r) { | |
2455 | r600_blit_fini(rdev); | |
27cd7769 | 2456 | rdev->asic->copy.copy = NULL; |
c38c7b64 JG |
2457 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
2458 | } | |
b70d6bb3 | 2459 | |
724c80e1 AD |
2460 | /* allocate wb buffer */ |
2461 | r = radeon_wb_init(rdev); | |
2462 | if (r) | |
2463 | return r; | |
2464 | ||
30eb77f4 JG |
2465 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2466 | if (r) { | |
2467 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
2468 | return r; | |
2469 | } | |
2470 | ||
d8f60cfc | 2471 | /* Enable IRQ */ |
d8f60cfc AD |
2472 | r = r600_irq_init(rdev); |
2473 | if (r) { | |
2474 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
2475 | radeon_irq_kms_fini(rdev); | |
2476 | return r; | |
2477 | } | |
2478 | r600_irq_set(rdev); | |
2479 | ||
e32eb50d | 2480 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
78c5560a AD |
2481 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
2482 | 0, 0xfffff, RADEON_CP_PACKET2); | |
5596a9db | 2483 | |
3ce0a23d JG |
2484 | if (r) |
2485 | return r; | |
2486 | r = r600_cp_load_microcode(rdev); | |
2487 | if (r) | |
2488 | return r; | |
2489 | r = r600_cp_resume(rdev); | |
2490 | if (r) | |
2491 | return r; | |
724c80e1 | 2492 | |
b15ba512 JG |
2493 | r = radeon_ib_pool_start(rdev); |
2494 | if (r) | |
2495 | return r; | |
2496 | ||
f712812e | 2497 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
b15ba512 JG |
2498 | if (r) { |
2499 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); | |
2500 | rdev->accel_working = false; | |
2501 | return r; | |
2502 | } | |
2503 | ||
3ce0a23d JG |
2504 | return 0; |
2505 | } | |
2506 | ||
28d52043 DA |
2507 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
2508 | { | |
2509 | uint32_t temp; | |
2510 | ||
2511 | temp = RREG32(CONFIG_CNTL); | |
2512 | if (state == false) { | |
2513 | temp &= ~(1<<0); | |
2514 | temp |= (1<<1); | |
2515 | } else { | |
2516 | temp &= ~(1<<1); | |
2517 | } | |
2518 | WREG32(CONFIG_CNTL, temp); | |
2519 | } | |
2520 | ||
fc30b8ef DA |
2521 | int r600_resume(struct radeon_device *rdev) |
2522 | { | |
2523 | int r; | |
2524 | ||
1a029b76 JG |
2525 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
2526 | * posting will perform necessary task to bring back GPU into good | |
2527 | * shape. | |
2528 | */ | |
fc30b8ef | 2529 | /* post card */ |
e7d40b9a | 2530 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef | 2531 | |
b15ba512 | 2532 | rdev->accel_working = true; |
fc30b8ef DA |
2533 | r = r600_startup(rdev); |
2534 | if (r) { | |
2535 | DRM_ERROR("r600 startup failed on resume\n"); | |
6b7746e8 | 2536 | rdev->accel_working = false; |
fc30b8ef DA |
2537 | return r; |
2538 | } | |
2539 | ||
38fd2c6f RM |
2540 | r = r600_audio_init(rdev); |
2541 | if (r) { | |
2542 | DRM_ERROR("radeon: audio resume failed\n"); | |
2543 | return r; | |
2544 | } | |
2545 | ||
fc30b8ef DA |
2546 | return r; |
2547 | } | |
2548 | ||
3ce0a23d JG |
2549 | int r600_suspend(struct radeon_device *rdev) |
2550 | { | |
38fd2c6f | 2551 | r600_audio_fini(rdev); |
b15ba512 JG |
2552 | radeon_ib_pool_suspend(rdev); |
2553 | r600_blit_suspend(rdev); | |
3ce0a23d JG |
2554 | /* FIXME: we should wait for ring to be empty */ |
2555 | r600_cp_stop(rdev); | |
e32eb50d | 2556 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
0c45249f | 2557 | r600_irq_suspend(rdev); |
724c80e1 | 2558 | radeon_wb_disable(rdev); |
4aac0473 | 2559 | r600_pcie_gart_disable(rdev); |
6ddddfe7 | 2560 | |
3ce0a23d JG |
2561 | return 0; |
2562 | } | |
2563 | ||
2564 | /* Plan is to move initialization in that function and use | |
2565 | * helper function so that radeon_device_init pretty much | |
2566 | * do nothing more than calling asic specific function. This | |
2567 | * should also allow to remove a bunch of callback function | |
2568 | * like vram_info. | |
2569 | */ | |
2570 | int r600_init(struct radeon_device *rdev) | |
771fe6b9 | 2571 | { |
3ce0a23d | 2572 | int r; |
771fe6b9 | 2573 | |
3ce0a23d JG |
2574 | if (r600_debugfs_mc_info_init(rdev)) { |
2575 | DRM_ERROR("Failed to register debugfs file for mc !\n"); | |
2576 | } | |
2577 | /* This don't do much */ | |
2578 | r = radeon_gem_init(rdev); | |
2579 | if (r) | |
2580 | return r; | |
2581 | /* Read BIOS */ | |
2582 | if (!radeon_get_bios(rdev)) { | |
2583 | if (ASIC_IS_AVIVO(rdev)) | |
2584 | return -EINVAL; | |
2585 | } | |
2586 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
2587 | if (!rdev->is_atom_bios) { |
2588 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 2589 | return -EINVAL; |
e7d40b9a | 2590 | } |
3ce0a23d JG |
2591 | r = radeon_atombios_init(rdev); |
2592 | if (r) | |
2593 | return r; | |
2594 | /* Post card if necessary */ | |
fd909c37 | 2595 | if (!radeon_card_posted(rdev)) { |
72542d77 DA |
2596 | if (!rdev->bios) { |
2597 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
2598 | return -EINVAL; | |
2599 | } | |
3ce0a23d JG |
2600 | DRM_INFO("GPU not posted. posting now...\n"); |
2601 | atom_asic_init(rdev->mode_info.atom_context); | |
2602 | } | |
2603 | /* Initialize scratch registers */ | |
2604 | r600_scratch_init(rdev); | |
2605 | /* Initialize surface registers */ | |
2606 | radeon_surface_init(rdev); | |
7433874e | 2607 | /* Initialize clocks */ |
5e6dde7e | 2608 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d | 2609 | /* Fence driver */ |
30eb77f4 | 2610 | r = radeon_fence_driver_init(rdev); |
3ce0a23d JG |
2611 | if (r) |
2612 | return r; | |
700a0cc0 JG |
2613 | if (rdev->flags & RADEON_IS_AGP) { |
2614 | r = radeon_agp_init(rdev); | |
2615 | if (r) | |
2616 | radeon_agp_disable(rdev); | |
2617 | } | |
3ce0a23d | 2618 | r = r600_mc_init(rdev); |
b574f251 | 2619 | if (r) |
3ce0a23d | 2620 | return r; |
3ce0a23d | 2621 | /* Memory manager */ |
4c788679 | 2622 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
2623 | if (r) |
2624 | return r; | |
d8f60cfc AD |
2625 | |
2626 | r = radeon_irq_kms_init(rdev); | |
2627 | if (r) | |
2628 | return r; | |
2629 | ||
e32eb50d CK |
2630 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
2631 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); | |
3ce0a23d | 2632 | |
d8f60cfc AD |
2633 | rdev->ih.ring_obj = NULL; |
2634 | r600_ih_ring_init(rdev, 64 * 1024); | |
3ce0a23d | 2635 | |
4aac0473 JG |
2636 | r = r600_pcie_gart_init(rdev); |
2637 | if (r) | |
2638 | return r; | |
2639 | ||
b15ba512 | 2640 | r = radeon_ib_pool_init(rdev); |
779720a3 | 2641 | rdev->accel_working = true; |
b15ba512 JG |
2642 | if (r) { |
2643 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
2644 | rdev->accel_working = false; | |
2645 | } | |
2646 | ||
fc30b8ef | 2647 | r = r600_startup(rdev); |
3ce0a23d | 2648 | if (r) { |
655efd3d JG |
2649 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
2650 | r600_cp_fini(rdev); | |
655efd3d | 2651 | r600_irq_fini(rdev); |
724c80e1 | 2652 | radeon_wb_fini(rdev); |
b15ba512 | 2653 | r100_ib_fini(rdev); |
655efd3d | 2654 | radeon_irq_kms_fini(rdev); |
75c81298 | 2655 | r600_pcie_gart_fini(rdev); |
733289c2 | 2656 | rdev->accel_working = false; |
3ce0a23d | 2657 | } |
dafc3bd5 CK |
2658 | |
2659 | r = r600_audio_init(rdev); | |
2660 | if (r) | |
2661 | return r; /* TODO error handling */ | |
3ce0a23d JG |
2662 | return 0; |
2663 | } | |
2664 | ||
2665 | void r600_fini(struct radeon_device *rdev) | |
2666 | { | |
dafc3bd5 | 2667 | r600_audio_fini(rdev); |
3ce0a23d | 2668 | r600_blit_fini(rdev); |
655efd3d | 2669 | r600_cp_fini(rdev); |
d8f60cfc | 2670 | r600_irq_fini(rdev); |
724c80e1 | 2671 | radeon_wb_fini(rdev); |
b15ba512 | 2672 | r100_ib_fini(rdev); |
d8f60cfc | 2673 | radeon_irq_kms_fini(rdev); |
4aac0473 | 2674 | r600_pcie_gart_fini(rdev); |
16cdf04d | 2675 | r600_vram_scratch_fini(rdev); |
655efd3d | 2676 | radeon_agp_fini(rdev); |
3ce0a23d | 2677 | radeon_gem_fini(rdev); |
15d3332f | 2678 | radeon_semaphore_driver_fini(rdev); |
3ce0a23d | 2679 | radeon_fence_driver_fini(rdev); |
4c788679 | 2680 | radeon_bo_fini(rdev); |
e7d40b9a | 2681 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
2682 | kfree(rdev->bios); |
2683 | rdev->bios = NULL; | |
3ce0a23d JG |
2684 | } |
2685 | ||
2686 | ||
2687 | /* | |
2688 | * CS stuff | |
2689 | */ | |
2690 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
2691 | { | |
e32eb50d | 2692 | struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; |
7b1f2485 | 2693 | |
3ce0a23d | 2694 | /* FIXME: implement */ |
e32eb50d CK |
2695 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2696 | radeon_ring_write(ring, | |
4eace7fd CC |
2697 | #ifdef __BIG_ENDIAN |
2698 | (2 << 0) | | |
2699 | #endif | |
2700 | (ib->gpu_addr & 0xFFFFFFFC)); | |
e32eb50d CK |
2701 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
2702 | radeon_ring_write(ring, ib->length_dw); | |
3ce0a23d JG |
2703 | } |
2704 | ||
f712812e | 2705 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d JG |
2706 | { |
2707 | struct radeon_ib *ib; | |
2708 | uint32_t scratch; | |
2709 | uint32_t tmp = 0; | |
2710 | unsigned i; | |
2711 | int r; | |
f712812e | 2712 | int ring_index = radeon_ring_index(rdev, ring); |
3ce0a23d JG |
2713 | |
2714 | r = radeon_scratch_get(rdev, &scratch); | |
2715 | if (r) { | |
2716 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
2717 | return r; | |
2718 | } | |
2719 | WREG32(scratch, 0xCAFEDEAD); | |
f712812e | 2720 | r = radeon_ib_get(rdev, ring_index, &ib, 256); |
3ce0a23d JG |
2721 | if (r) { |
2722 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
2723 | return r; | |
2724 | } | |
2725 | ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); | |
2726 | ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2727 | ib->ptr[2] = 0xDEADBEEF; | |
442f7cfa | 2728 | ib->length_dw = 3; |
3ce0a23d JG |
2729 | r = radeon_ib_schedule(rdev, ib); |
2730 | if (r) { | |
2731 | radeon_scratch_free(rdev, scratch); | |
2732 | radeon_ib_free(rdev, &ib); | |
2733 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | |
2734 | return r; | |
2735 | } | |
2736 | r = radeon_fence_wait(ib->fence, false); | |
2737 | if (r) { | |
2738 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
2739 | return r; | |
2740 | } | |
2741 | for (i = 0; i < rdev->usec_timeout; i++) { | |
2742 | tmp = RREG32(scratch); | |
2743 | if (tmp == 0xDEADBEEF) | |
2744 | break; | |
2745 | DRM_UDELAY(1); | |
2746 | } | |
2747 | if (i < rdev->usec_timeout) { | |
7b1f2485 | 2748 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i); |
3ce0a23d | 2749 | } else { |
4417d7f6 | 2750 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
3ce0a23d JG |
2751 | scratch, tmp); |
2752 | r = -EINVAL; | |
2753 | } | |
2754 | radeon_scratch_free(rdev, scratch); | |
2755 | radeon_ib_free(rdev, &ib); | |
771fe6b9 JG |
2756 | return r; |
2757 | } | |
2758 | ||
d8f60cfc AD |
2759 | /* |
2760 | * Interrupts | |
2761 | * | |
2762 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty | |
2763 | * the same as the CP ring buffer, but in reverse. Rather than the CPU | |
2764 | * writing to the ring and the GPU consuming, the GPU writes to the ring | |
2765 | * and host consumes. As the host irq handler processes interrupts, it | |
2766 | * increments the rptr. When the rptr catches up with the wptr, all the | |
2767 | * current interrupts have been processed. | |
2768 | */ | |
2769 | ||
2770 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
2771 | { | |
2772 | u32 rb_bufsz; | |
2773 | ||
2774 | /* Align ring size */ | |
2775 | rb_bufsz = drm_order(ring_size / 4); | |
2776 | ring_size = (1 << rb_bufsz) * 4; | |
2777 | rdev->ih.ring_size = ring_size; | |
0c45249f JG |
2778 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
2779 | rdev->ih.rptr = 0; | |
d8f60cfc AD |
2780 | } |
2781 | ||
25a857fb | 2782 | int r600_ih_ring_alloc(struct radeon_device *rdev) |
d8f60cfc AD |
2783 | { |
2784 | int r; | |
2785 | ||
d8f60cfc AD |
2786 | /* Allocate ring buffer */ |
2787 | if (rdev->ih.ring_obj == NULL) { | |
441921d5 | 2788 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
268b2510 | 2789 | PAGE_SIZE, true, |
4c788679 JG |
2790 | RADEON_GEM_DOMAIN_GTT, |
2791 | &rdev->ih.ring_obj); | |
d8f60cfc AD |
2792 | if (r) { |
2793 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); | |
2794 | return r; | |
2795 | } | |
4c788679 JG |
2796 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2797 | if (unlikely(r != 0)) | |
2798 | return r; | |
2799 | r = radeon_bo_pin(rdev->ih.ring_obj, | |
2800 | RADEON_GEM_DOMAIN_GTT, | |
2801 | &rdev->ih.gpu_addr); | |
d8f60cfc | 2802 | if (r) { |
4c788679 | 2803 | radeon_bo_unreserve(rdev->ih.ring_obj); |
d8f60cfc AD |
2804 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
2805 | return r; | |
2806 | } | |
4c788679 JG |
2807 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
2808 | (void **)&rdev->ih.ring); | |
2809 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
d8f60cfc AD |
2810 | if (r) { |
2811 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); | |
2812 | return r; | |
2813 | } | |
2814 | } | |
d8f60cfc AD |
2815 | return 0; |
2816 | } | |
2817 | ||
25a857fb | 2818 | void r600_ih_ring_fini(struct radeon_device *rdev) |
d8f60cfc | 2819 | { |
4c788679 | 2820 | int r; |
d8f60cfc | 2821 | if (rdev->ih.ring_obj) { |
4c788679 JG |
2822 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2823 | if (likely(r == 0)) { | |
2824 | radeon_bo_kunmap(rdev->ih.ring_obj); | |
2825 | radeon_bo_unpin(rdev->ih.ring_obj); | |
2826 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
2827 | } | |
2828 | radeon_bo_unref(&rdev->ih.ring_obj); | |
d8f60cfc AD |
2829 | rdev->ih.ring = NULL; |
2830 | rdev->ih.ring_obj = NULL; | |
2831 | } | |
2832 | } | |
2833 | ||
45f9a39b | 2834 | void r600_rlc_stop(struct radeon_device *rdev) |
d8f60cfc AD |
2835 | { |
2836 | ||
45f9a39b AD |
2837 | if ((rdev->family >= CHIP_RV770) && |
2838 | (rdev->family <= CHIP_RV740)) { | |
d8f60cfc AD |
2839 | /* r7xx asics need to soft reset RLC before halting */ |
2840 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); | |
2841 | RREG32(SRBM_SOFT_RESET); | |
2842 | udelay(15000); | |
2843 | WREG32(SRBM_SOFT_RESET, 0); | |
2844 | RREG32(SRBM_SOFT_RESET); | |
2845 | } | |
2846 | ||
2847 | WREG32(RLC_CNTL, 0); | |
2848 | } | |
2849 | ||
2850 | static void r600_rlc_start(struct radeon_device *rdev) | |
2851 | { | |
2852 | WREG32(RLC_CNTL, RLC_ENABLE); | |
2853 | } | |
2854 | ||
2855 | static int r600_rlc_init(struct radeon_device *rdev) | |
2856 | { | |
2857 | u32 i; | |
2858 | const __be32 *fw_data; | |
2859 | ||
2860 | if (!rdev->rlc_fw) | |
2861 | return -EINVAL; | |
2862 | ||
2863 | r600_rlc_stop(rdev); | |
2864 | ||
d8f60cfc | 2865 | WREG32(RLC_HB_CNTL, 0); |
c420c745 AD |
2866 | |
2867 | if (rdev->family == CHIP_ARUBA) { | |
2868 | WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); | |
2869 | WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); | |
2870 | } | |
2871 | if (rdev->family <= CHIP_CAYMAN) { | |
2872 | WREG32(RLC_HB_BASE, 0); | |
2873 | WREG32(RLC_HB_RPTR, 0); | |
2874 | WREG32(RLC_HB_WPTR, 0); | |
2875 | } | |
12727809 AD |
2876 | if (rdev->family <= CHIP_CAICOS) { |
2877 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); | |
2878 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); | |
2879 | } | |
d8f60cfc AD |
2880 | WREG32(RLC_MC_CNTL, 0); |
2881 | WREG32(RLC_UCODE_CNTL, 0); | |
2882 | ||
2883 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
c420c745 AD |
2884 | if (rdev->family >= CHIP_ARUBA) { |
2885 | for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { | |
2886 | WREG32(RLC_UCODE_ADDR, i); | |
2887 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2888 | } | |
2889 | } else if (rdev->family >= CHIP_CAYMAN) { | |
12727809 AD |
2890 | for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { |
2891 | WREG32(RLC_UCODE_ADDR, i); | |
2892 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2893 | } | |
2894 | } else if (rdev->family >= CHIP_CEDAR) { | |
45f9a39b AD |
2895 | for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { |
2896 | WREG32(RLC_UCODE_ADDR, i); | |
2897 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2898 | } | |
2899 | } else if (rdev->family >= CHIP_RV770) { | |
d8f60cfc AD |
2900 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { |
2901 | WREG32(RLC_UCODE_ADDR, i); | |
2902 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2903 | } | |
2904 | } else { | |
2905 | for (i = 0; i < RLC_UCODE_SIZE; i++) { | |
2906 | WREG32(RLC_UCODE_ADDR, i); | |
2907 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2908 | } | |
2909 | } | |
2910 | WREG32(RLC_UCODE_ADDR, 0); | |
2911 | ||
2912 | r600_rlc_start(rdev); | |
2913 | ||
2914 | return 0; | |
2915 | } | |
2916 | ||
2917 | static void r600_enable_interrupts(struct radeon_device *rdev) | |
2918 | { | |
2919 | u32 ih_cntl = RREG32(IH_CNTL); | |
2920 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2921 | ||
2922 | ih_cntl |= ENABLE_INTR; | |
2923 | ih_rb_cntl |= IH_RB_ENABLE; | |
2924 | WREG32(IH_CNTL, ih_cntl); | |
2925 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2926 | rdev->ih.enabled = true; | |
2927 | } | |
2928 | ||
45f9a39b | 2929 | void r600_disable_interrupts(struct radeon_device *rdev) |
d8f60cfc AD |
2930 | { |
2931 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2932 | u32 ih_cntl = RREG32(IH_CNTL); | |
2933 | ||
2934 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
2935 | ih_cntl &= ~ENABLE_INTR; | |
2936 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2937 | WREG32(IH_CNTL, ih_cntl); | |
2938 | /* set rptr, wptr to 0 */ | |
2939 | WREG32(IH_RB_RPTR, 0); | |
2940 | WREG32(IH_RB_WPTR, 0); | |
2941 | rdev->ih.enabled = false; | |
2942 | rdev->ih.wptr = 0; | |
2943 | rdev->ih.rptr = 0; | |
2944 | } | |
2945 | ||
e0df1ac5 AD |
2946 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
2947 | { | |
2948 | u32 tmp; | |
2949 | ||
3555e53b | 2950 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
e0df1ac5 AD |
2951 | WREG32(GRBM_INT_CNTL, 0); |
2952 | WREG32(DxMODE_INT_MASK, 0); | |
6f34be50 AD |
2953 | WREG32(D1GRPH_INTERRUPT_CONTROL, 0); |
2954 | WREG32(D2GRPH_INTERRUPT_CONTROL, 0); | |
e0df1ac5 AD |
2955 | if (ASIC_IS_DCE3(rdev)) { |
2956 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); | |
2957 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); | |
2958 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2959 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2960 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2961 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2962 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2963 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2964 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2965 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2966 | if (ASIC_IS_DCE32(rdev)) { | |
2967 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
5898b1f3 | 2968 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
e0df1ac5 | 2969 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
5898b1f3 | 2970 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
e0df1ac5 AD |
2971 | } |
2972 | } else { | |
2973 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
2974 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
2975 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
5898b1f3 | 2976 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
e0df1ac5 | 2977 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2978 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
e0df1ac5 | 2979 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2980 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
e0df1ac5 AD |
2981 | } |
2982 | } | |
2983 | ||
d8f60cfc AD |
2984 | int r600_irq_init(struct radeon_device *rdev) |
2985 | { | |
2986 | int ret = 0; | |
2987 | int rb_bufsz; | |
2988 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
2989 | ||
2990 | /* allocate ring */ | |
0c45249f | 2991 | ret = r600_ih_ring_alloc(rdev); |
d8f60cfc AD |
2992 | if (ret) |
2993 | return ret; | |
2994 | ||
2995 | /* disable irqs */ | |
2996 | r600_disable_interrupts(rdev); | |
2997 | ||
2998 | /* init rlc */ | |
2999 | ret = r600_rlc_init(rdev); | |
3000 | if (ret) { | |
3001 | r600_ih_ring_fini(rdev); | |
3002 | return ret; | |
3003 | } | |
3004 | ||
3005 | /* setup interrupt control */ | |
3006 | /* set dummy read address to ring address */ | |
3007 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
3008 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
3009 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
3010 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
3011 | */ | |
3012 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
3013 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
3014 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
3015 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
3016 | ||
3017 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
3018 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); | |
3019 | ||
3020 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
3021 | IH_WPTR_OVERFLOW_CLEAR | | |
3022 | (rb_bufsz << 1)); | |
724c80e1 AD |
3023 | |
3024 | if (rdev->wb.enabled) | |
3025 | ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; | |
3026 | ||
3027 | /* set the writeback address whether it's enabled or not */ | |
3028 | WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); | |
3029 | WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); | |
d8f60cfc AD |
3030 | |
3031 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3032 | ||
3033 | /* set rptr, wptr to 0 */ | |
3034 | WREG32(IH_RB_RPTR, 0); | |
3035 | WREG32(IH_RB_WPTR, 0); | |
3036 | ||
3037 | /* Default settings for IH_CNTL (disabled at first) */ | |
3038 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); | |
3039 | /* RPTR_REARM only works if msi's are enabled */ | |
3040 | if (rdev->msi_enabled) | |
3041 | ih_cntl |= RPTR_REARM; | |
d8f60cfc AD |
3042 | WREG32(IH_CNTL, ih_cntl); |
3043 | ||
3044 | /* force the active interrupt state to all disabled */ | |
45f9a39b AD |
3045 | if (rdev->family >= CHIP_CEDAR) |
3046 | evergreen_disable_interrupt_state(rdev); | |
3047 | else | |
3048 | r600_disable_interrupt_state(rdev); | |
d8f60cfc AD |
3049 | |
3050 | /* enable irqs */ | |
3051 | r600_enable_interrupts(rdev); | |
3052 | ||
3053 | return ret; | |
3054 | } | |
3055 | ||
0c45249f | 3056 | void r600_irq_suspend(struct radeon_device *rdev) |
d8f60cfc | 3057 | { |
45f9a39b | 3058 | r600_irq_disable(rdev); |
d8f60cfc | 3059 | r600_rlc_stop(rdev); |
0c45249f JG |
3060 | } |
3061 | ||
3062 | void r600_irq_fini(struct radeon_device *rdev) | |
3063 | { | |
3064 | r600_irq_suspend(rdev); | |
d8f60cfc AD |
3065 | r600_ih_ring_fini(rdev); |
3066 | } | |
3067 | ||
3068 | int r600_irq_set(struct radeon_device *rdev) | |
3069 | { | |
e0df1ac5 AD |
3070 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
3071 | u32 mode_int = 0; | |
3072 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | |
2031f77c | 3073 | u32 grbm_int_cntl = 0; |
f2594933 | 3074 | u32 hdmi1, hdmi2; |
6f34be50 | 3075 | u32 d1grph = 0, d2grph = 0; |
d8f60cfc | 3076 | |
003e69f9 | 3077 | if (!rdev->irq.installed) { |
fce7d61b | 3078 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
003e69f9 JG |
3079 | return -EINVAL; |
3080 | } | |
d8f60cfc | 3081 | /* don't enable anything if the ih is disabled */ |
79c2bbc5 JG |
3082 | if (!rdev->ih.enabled) { |
3083 | r600_disable_interrupts(rdev); | |
3084 | /* force the active interrupt state to all disabled */ | |
3085 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 3086 | return 0; |
79c2bbc5 | 3087 | } |
d8f60cfc | 3088 | |
f2594933 | 3089 | hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 | 3090 | if (ASIC_IS_DCE3(rdev)) { |
f2594933 | 3091 | hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 AD |
3092 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3093 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3094 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3095 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3096 | if (ASIC_IS_DCE32(rdev)) { | |
3097 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3098 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3099 | } | |
3100 | } else { | |
f2594933 | 3101 | hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 AD |
3102 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3103 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3104 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3105 | } | |
3106 | ||
1b37078b | 3107 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { |
d8f60cfc AD |
3108 | DRM_DEBUG("r600_irq_set: sw int\n"); |
3109 | cp_int_cntl |= RB_INT_ENABLE; | |
d0f8a854 | 3110 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
d8f60cfc | 3111 | } |
6f34be50 AD |
3112 | if (rdev->irq.crtc_vblank_int[0] || |
3113 | rdev->irq.pflip[0]) { | |
d8f60cfc AD |
3114 | DRM_DEBUG("r600_irq_set: vblank 0\n"); |
3115 | mode_int |= D1MODE_VBLANK_INT_MASK; | |
3116 | } | |
6f34be50 AD |
3117 | if (rdev->irq.crtc_vblank_int[1] || |
3118 | rdev->irq.pflip[1]) { | |
d8f60cfc AD |
3119 | DRM_DEBUG("r600_irq_set: vblank 1\n"); |
3120 | mode_int |= D2MODE_VBLANK_INT_MASK; | |
3121 | } | |
e0df1ac5 AD |
3122 | if (rdev->irq.hpd[0]) { |
3123 | DRM_DEBUG("r600_irq_set: hpd 1\n"); | |
3124 | hpd1 |= DC_HPDx_INT_EN; | |
3125 | } | |
3126 | if (rdev->irq.hpd[1]) { | |
3127 | DRM_DEBUG("r600_irq_set: hpd 2\n"); | |
3128 | hpd2 |= DC_HPDx_INT_EN; | |
3129 | } | |
3130 | if (rdev->irq.hpd[2]) { | |
3131 | DRM_DEBUG("r600_irq_set: hpd 3\n"); | |
3132 | hpd3 |= DC_HPDx_INT_EN; | |
3133 | } | |
3134 | if (rdev->irq.hpd[3]) { | |
3135 | DRM_DEBUG("r600_irq_set: hpd 4\n"); | |
3136 | hpd4 |= DC_HPDx_INT_EN; | |
3137 | } | |
3138 | if (rdev->irq.hpd[4]) { | |
3139 | DRM_DEBUG("r600_irq_set: hpd 5\n"); | |
3140 | hpd5 |= DC_HPDx_INT_EN; | |
3141 | } | |
3142 | if (rdev->irq.hpd[5]) { | |
3143 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | |
3144 | hpd6 |= DC_HPDx_INT_EN; | |
3145 | } | |
f2594933 CK |
3146 | if (rdev->irq.hdmi[0]) { |
3147 | DRM_DEBUG("r600_irq_set: hdmi 1\n"); | |
3148 | hdmi1 |= R600_HDMI_INT_EN; | |
3149 | } | |
3150 | if (rdev->irq.hdmi[1]) { | |
3151 | DRM_DEBUG("r600_irq_set: hdmi 2\n"); | |
3152 | hdmi2 |= R600_HDMI_INT_EN; | |
3153 | } | |
2031f77c AD |
3154 | if (rdev->irq.gui_idle) { |
3155 | DRM_DEBUG("gui idle\n"); | |
3156 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; | |
3157 | } | |
d8f60cfc AD |
3158 | |
3159 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
3160 | WREG32(DxMODE_INT_MASK, mode_int); | |
6f34be50 AD |
3161 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); |
3162 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); | |
2031f77c | 3163 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
f2594933 | 3164 | WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); |
e0df1ac5 | 3165 | if (ASIC_IS_DCE3(rdev)) { |
f2594933 | 3166 | WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); |
e0df1ac5 AD |
3167 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
3168 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
3169 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
3170 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
3171 | if (ASIC_IS_DCE32(rdev)) { | |
3172 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
3173 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
3174 | } | |
3175 | } else { | |
f2594933 | 3176 | WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2); |
e0df1ac5 AD |
3177 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
3178 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
3179 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | |
3180 | } | |
d8f60cfc AD |
3181 | |
3182 | return 0; | |
3183 | } | |
3184 | ||
ce580fab | 3185 | static void r600_irq_ack(struct radeon_device *rdev) |
d8f60cfc | 3186 | { |
e0df1ac5 AD |
3187 | u32 tmp; |
3188 | ||
3189 | if (ASIC_IS_DCE3(rdev)) { | |
6f34be50 AD |
3190 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
3191 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | |
3192 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | |
e0df1ac5 | 3193 | } else { |
6f34be50 AD |
3194 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
3195 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
3196 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; | |
3197 | } | |
3198 | rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); | |
3199 | rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); | |
3200 | ||
3201 | if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) | |
3202 | WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); | |
3203 | if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) | |
3204 | WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); | |
3205 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) | |
d8f60cfc | 3206 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
6f34be50 | 3207 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) |
d8f60cfc | 3208 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
6f34be50 | 3209 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) |
d8f60cfc | 3210 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
6f34be50 | 3211 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) |
d8f60cfc | 3212 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
6f34be50 | 3213 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
e0df1ac5 AD |
3214 | if (ASIC_IS_DCE3(rdev)) { |
3215 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
3216 | tmp |= DC_HPDx_INT_ACK; | |
3217 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3218 | } else { | |
3219 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
3220 | tmp |= DC_HPDx_INT_ACK; | |
3221 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
3222 | } | |
3223 | } | |
6f34be50 | 3224 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
e0df1ac5 AD |
3225 | if (ASIC_IS_DCE3(rdev)) { |
3226 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
3227 | tmp |= DC_HPDx_INT_ACK; | |
3228 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3229 | } else { | |
3230 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
3231 | tmp |= DC_HPDx_INT_ACK; | |
3232 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
3233 | } | |
3234 | } | |
6f34be50 | 3235 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
e0df1ac5 AD |
3236 | if (ASIC_IS_DCE3(rdev)) { |
3237 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
3238 | tmp |= DC_HPDx_INT_ACK; | |
3239 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3240 | } else { | |
3241 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
3242 | tmp |= DC_HPDx_INT_ACK; | |
3243 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
3244 | } | |
3245 | } | |
6f34be50 | 3246 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
e0df1ac5 AD |
3247 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
3248 | tmp |= DC_HPDx_INT_ACK; | |
3249 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3250 | } | |
3251 | if (ASIC_IS_DCE32(rdev)) { | |
6f34be50 | 3252 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
e0df1ac5 AD |
3253 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
3254 | tmp |= DC_HPDx_INT_ACK; | |
3255 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
3256 | } | |
6f34be50 | 3257 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
e0df1ac5 AD |
3258 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
3259 | tmp |= DC_HPDx_INT_ACK; | |
3260 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
3261 | } | |
3262 | } | |
f2594933 CK |
3263 | if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
3264 | WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
3265 | } | |
3266 | if (ASIC_IS_DCE3(rdev)) { | |
3267 | if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | |
3268 | WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
3269 | } | |
3270 | } else { | |
3271 | if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | |
3272 | WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
3273 | } | |
3274 | } | |
d8f60cfc AD |
3275 | } |
3276 | ||
3277 | void r600_irq_disable(struct radeon_device *rdev) | |
3278 | { | |
d8f60cfc AD |
3279 | r600_disable_interrupts(rdev); |
3280 | /* Wait and acknowledge irq */ | |
3281 | mdelay(1); | |
6f34be50 | 3282 | r600_irq_ack(rdev); |
e0df1ac5 | 3283 | r600_disable_interrupt_state(rdev); |
d8f60cfc AD |
3284 | } |
3285 | ||
ce580fab | 3286 | static u32 r600_get_ih_wptr(struct radeon_device *rdev) |
d8f60cfc AD |
3287 | { |
3288 | u32 wptr, tmp; | |
3ce0a23d | 3289 | |
724c80e1 | 3290 | if (rdev->wb.enabled) |
204ae24d | 3291 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
724c80e1 AD |
3292 | else |
3293 | wptr = RREG32(IH_RB_WPTR); | |
3ce0a23d | 3294 | |
d8f60cfc | 3295 | if (wptr & RB_OVERFLOW) { |
7924e5eb JG |
3296 | /* When a ring buffer overflow happen start parsing interrupt |
3297 | * from the last not overwritten vector (wptr + 16). Hopefully | |
3298 | * this should allow us to catchup. | |
3299 | */ | |
3300 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
3301 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
3302 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
d8f60cfc AD |
3303 | tmp = RREG32(IH_RB_CNTL); |
3304 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
3305 | WREG32(IH_RB_CNTL, tmp); | |
3306 | } | |
0c45249f | 3307 | return (wptr & rdev->ih.ptr_mask); |
d8f60cfc | 3308 | } |
3ce0a23d | 3309 | |
d8f60cfc AD |
3310 | /* r600 IV Ring |
3311 | * Each IV ring entry is 128 bits: | |
3312 | * [7:0] - interrupt source id | |
3313 | * [31:8] - reserved | |
3314 | * [59:32] - interrupt source data | |
3315 | * [127:60] - reserved | |
3316 | * | |
3317 | * The basic interrupt vector entries | |
3318 | * are decoded as follows: | |
3319 | * src_id src_data description | |
3320 | * 1 0 D1 Vblank | |
3321 | * 1 1 D1 Vline | |
3322 | * 5 0 D2 Vblank | |
3323 | * 5 1 D2 Vline | |
3324 | * 19 0 FP Hot plug detection A | |
3325 | * 19 1 FP Hot plug detection B | |
3326 | * 19 2 DAC A auto-detection | |
3327 | * 19 3 DAC B auto-detection | |
f2594933 CK |
3328 | * 21 4 HDMI block A |
3329 | * 21 5 HDMI block B | |
d8f60cfc AD |
3330 | * 176 - CP_INT RB |
3331 | * 177 - CP_INT IB1 | |
3332 | * 178 - CP_INT IB2 | |
3333 | * 181 - EOP Interrupt | |
3334 | * 233 - GUI Idle | |
3335 | * | |
3336 | * Note, these are based on r600 and may need to be | |
3337 | * adjusted or added to on newer asics | |
3338 | */ | |
3339 | ||
3340 | int r600_irq_process(struct radeon_device *rdev) | |
3341 | { | |
682f1a54 DA |
3342 | u32 wptr; |
3343 | u32 rptr; | |
d8f60cfc | 3344 | u32 src_id, src_data; |
6f34be50 | 3345 | u32 ring_index; |
d8f60cfc | 3346 | unsigned long flags; |
d4877cf2 | 3347 | bool queue_hotplug = false; |
d8f60cfc | 3348 | |
682f1a54 | 3349 | if (!rdev->ih.enabled || rdev->shutdown) |
79c2bbc5 | 3350 | return IRQ_NONE; |
d8f60cfc | 3351 | |
f6a56939 BH |
3352 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
3353 | if (!rdev->msi_enabled) | |
3354 | RREG32(IH_RB_WPTR); | |
3355 | ||
682f1a54 DA |
3356 | wptr = r600_get_ih_wptr(rdev); |
3357 | rptr = rdev->ih.rptr; | |
3358 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
3359 | ||
d8f60cfc AD |
3360 | spin_lock_irqsave(&rdev->ih.lock, flags); |
3361 | ||
3362 | if (rptr == wptr) { | |
3363 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3364 | return IRQ_NONE; | |
3365 | } | |
d8f60cfc AD |
3366 | |
3367 | restart_ih: | |
964f6645 BH |
3368 | /* Order reading of wptr vs. reading of IH ring data */ |
3369 | rmb(); | |
3370 | ||
d8f60cfc | 3371 | /* display interrupts */ |
6f34be50 | 3372 | r600_irq_ack(rdev); |
d8f60cfc AD |
3373 | |
3374 | rdev->ih.wptr = wptr; | |
3375 | while (rptr != wptr) { | |
3376 | /* wptr/rptr are in bytes! */ | |
3377 | ring_index = rptr / 4; | |
4eace7fd CC |
3378 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
3379 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; | |
d8f60cfc AD |
3380 | |
3381 | switch (src_id) { | |
3382 | case 1: /* D1 vblank/vline */ | |
3383 | switch (src_data) { | |
3384 | case 0: /* D1 vblank */ | |
6f34be50 | 3385 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { |
6f34be50 AD |
3386 | if (rdev->irq.crtc_vblank_int[0]) { |
3387 | drm_handle_vblank(rdev->ddev, 0); | |
3388 | rdev->pm.vblank_sync = true; | |
3389 | wake_up(&rdev->irq.vblank_queue); | |
3390 | } | |
3e4ea742 MK |
3391 | if (rdev->irq.pflip[0]) |
3392 | radeon_crtc_handle_flip(rdev, 0); | |
6f34be50 | 3393 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
d8f60cfc AD |
3394 | DRM_DEBUG("IH: D1 vblank\n"); |
3395 | } | |
3396 | break; | |
3397 | case 1: /* D1 vline */ | |
6f34be50 AD |
3398 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { |
3399 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
d8f60cfc AD |
3400 | DRM_DEBUG("IH: D1 vline\n"); |
3401 | } | |
3402 | break; | |
3403 | default: | |
b042589c | 3404 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3405 | break; |
3406 | } | |
3407 | break; | |
3408 | case 5: /* D2 vblank/vline */ | |
3409 | switch (src_data) { | |
3410 | case 0: /* D2 vblank */ | |
6f34be50 | 3411 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { |
6f34be50 AD |
3412 | if (rdev->irq.crtc_vblank_int[1]) { |
3413 | drm_handle_vblank(rdev->ddev, 1); | |
3414 | rdev->pm.vblank_sync = true; | |
3415 | wake_up(&rdev->irq.vblank_queue); | |
3416 | } | |
3e4ea742 MK |
3417 | if (rdev->irq.pflip[1]) |
3418 | radeon_crtc_handle_flip(rdev, 1); | |
6f34be50 | 3419 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; |
d8f60cfc AD |
3420 | DRM_DEBUG("IH: D2 vblank\n"); |
3421 | } | |
3422 | break; | |
3423 | case 1: /* D1 vline */ | |
6f34be50 AD |
3424 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { |
3425 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; | |
d8f60cfc AD |
3426 | DRM_DEBUG("IH: D2 vline\n"); |
3427 | } | |
3428 | break; | |
3429 | default: | |
b042589c | 3430 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3431 | break; |
3432 | } | |
3433 | break; | |
e0df1ac5 AD |
3434 | case 19: /* HPD/DAC hotplug */ |
3435 | switch (src_data) { | |
3436 | case 0: | |
6f34be50 AD |
3437 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
3438 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; | |
d4877cf2 AD |
3439 | queue_hotplug = true; |
3440 | DRM_DEBUG("IH: HPD1\n"); | |
e0df1ac5 AD |
3441 | } |
3442 | break; | |
3443 | case 1: | |
6f34be50 AD |
3444 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
3445 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; | |
d4877cf2 AD |
3446 | queue_hotplug = true; |
3447 | DRM_DEBUG("IH: HPD2\n"); | |
e0df1ac5 AD |
3448 | } |
3449 | break; | |
3450 | case 4: | |
6f34be50 AD |
3451 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
3452 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; | |
d4877cf2 AD |
3453 | queue_hotplug = true; |
3454 | DRM_DEBUG("IH: HPD3\n"); | |
e0df1ac5 AD |
3455 | } |
3456 | break; | |
3457 | case 5: | |
6f34be50 AD |
3458 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
3459 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; | |
d4877cf2 AD |
3460 | queue_hotplug = true; |
3461 | DRM_DEBUG("IH: HPD4\n"); | |
e0df1ac5 AD |
3462 | } |
3463 | break; | |
3464 | case 10: | |
6f34be50 AD |
3465 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
3466 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; | |
d4877cf2 AD |
3467 | queue_hotplug = true; |
3468 | DRM_DEBUG("IH: HPD5\n"); | |
e0df1ac5 AD |
3469 | } |
3470 | break; | |
3471 | case 12: | |
6f34be50 AD |
3472 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
3473 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; | |
d4877cf2 AD |
3474 | queue_hotplug = true; |
3475 | DRM_DEBUG("IH: HPD6\n"); | |
e0df1ac5 AD |
3476 | } |
3477 | break; | |
3478 | default: | |
b042589c | 3479 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
e0df1ac5 AD |
3480 | break; |
3481 | } | |
3482 | break; | |
f2594933 CK |
3483 | case 21: /* HDMI */ |
3484 | DRM_DEBUG("IH: HDMI: 0x%x\n", src_data); | |
3485 | r600_audio_schedule_polling(rdev); | |
3486 | break; | |
d8f60cfc AD |
3487 | case 176: /* CP_INT in ring buffer */ |
3488 | case 177: /* CP_INT in IB1 */ | |
3489 | case 178: /* CP_INT in IB2 */ | |
3490 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
7465280c | 3491 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
d8f60cfc AD |
3492 | break; |
3493 | case 181: /* CP EOP event */ | |
3494 | DRM_DEBUG("IH: CP EOP\n"); | |
7465280c | 3495 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
d8f60cfc | 3496 | break; |
2031f77c | 3497 | case 233: /* GUI IDLE */ |
303c805c | 3498 | DRM_DEBUG("IH: GUI idle\n"); |
2031f77c AD |
3499 | rdev->pm.gui_idle = true; |
3500 | wake_up(&rdev->irq.idle_queue); | |
3501 | break; | |
d8f60cfc | 3502 | default: |
b042589c | 3503 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3504 | break; |
3505 | } | |
3506 | ||
3507 | /* wptr/rptr are in bytes! */ | |
0c45249f JG |
3508 | rptr += 16; |
3509 | rptr &= rdev->ih.ptr_mask; | |
d8f60cfc AD |
3510 | } |
3511 | /* make sure wptr hasn't changed while processing */ | |
3512 | wptr = r600_get_ih_wptr(rdev); | |
3513 | if (wptr != rdev->ih.wptr) | |
3514 | goto restart_ih; | |
d4877cf2 | 3515 | if (queue_hotplug) |
32c87fca | 3516 | schedule_work(&rdev->hotplug_work); |
d8f60cfc AD |
3517 | rdev->ih.rptr = rptr; |
3518 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
3519 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3520 | return IRQ_HANDLED; | |
3521 | } | |
3ce0a23d JG |
3522 | |
3523 | /* | |
3524 | * Debugfs info | |
3525 | */ | |
3526 | #if defined(CONFIG_DEBUG_FS) | |
3527 | ||
3ce0a23d JG |
3528 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
3529 | { | |
3530 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3531 | struct drm_device *dev = node->minor->dev; | |
3532 | struct radeon_device *rdev = dev->dev_private; | |
3533 | ||
3534 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); | |
3535 | DREG32_SYS(m, rdev, VM_L2_STATUS); | |
3536 | return 0; | |
3537 | } | |
3538 | ||
3539 | static struct drm_info_list r600_mc_info_list[] = { | |
3540 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, | |
3ce0a23d JG |
3541 | }; |
3542 | #endif | |
3543 | ||
3544 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) | |
3545 | { | |
3546 | #if defined(CONFIG_DEBUG_FS) | |
3547 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); | |
3548 | #else | |
3549 | return 0; | |
3550 | #endif | |
771fe6b9 | 3551 | } |
062b389c JG |
3552 | |
3553 | /** | |
3554 | * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl | |
3555 | * rdev: radeon device structure | |
3556 | * bo: buffer object struct which userspace is waiting for idle | |
3557 | * | |
3558 | * Some R6XX/R7XX doesn't seems to take into account HDP flush performed | |
3559 | * through ring buffer, this leads to corruption in rendering, see | |
3560 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we | |
3561 | * directly perform HDP flush by writing register through MMIO. | |
3562 | */ | |
3563 | void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) | |
3564 | { | |
812d0469 | 3565 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
f3886f85 AD |
3566 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. |
3567 | * This seems to cause problems on some AGP cards. Just use the old | |
3568 | * method for them. | |
812d0469 | 3569 | */ |
e488459a | 3570 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
f3886f85 | 3571 | rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { |
87cbf8f2 | 3572 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
812d0469 AD |
3573 | u32 tmp; |
3574 | ||
3575 | WREG32(HDP_DEBUG1, 0); | |
3576 | tmp = readl((void __iomem *)ptr); | |
3577 | } else | |
3578 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
062b389c | 3579 | } |
3313e3d4 AD |
3580 | |
3581 | void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) | |
3582 | { | |
3583 | u32 link_width_cntl, mask, target_reg; | |
3584 | ||
3585 | if (rdev->flags & RADEON_IS_IGP) | |
3586 | return; | |
3587 | ||
3588 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
3589 | return; | |
3590 | ||
3591 | /* x2 cards have a special sequence */ | |
3592 | if (ASIC_IS_X2(rdev)) | |
3593 | return; | |
3594 | ||
3595 | /* FIXME wait for idle */ | |
3596 | ||
3597 | switch (lanes) { | |
3598 | case 0: | |
3599 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; | |
3600 | break; | |
3601 | case 1: | |
3602 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; | |
3603 | break; | |
3604 | case 2: | |
3605 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; | |
3606 | break; | |
3607 | case 4: | |
3608 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; | |
3609 | break; | |
3610 | case 8: | |
3611 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; | |
3612 | break; | |
3613 | case 12: | |
3614 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; | |
3615 | break; | |
3616 | case 16: | |
3617 | default: | |
3618 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; | |
3619 | break; | |
3620 | } | |
3621 | ||
3622 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
3623 | ||
3624 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == | |
3625 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) | |
3626 | return; | |
3627 | ||
3628 | if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) | |
3629 | return; | |
3630 | ||
3631 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | | |
3632 | RADEON_PCIE_LC_RECONFIG_NOW | | |
3633 | R600_PCIE_LC_RENEGOTIATE_EN | | |
3634 | R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); | |
3635 | link_width_cntl |= mask; | |
3636 | ||
3637 | WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3638 | ||
3639 | /* some northbridges can renegotiate the link rather than requiring | |
3640 | * a complete re-config. | |
3641 | * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) | |
3642 | */ | |
3643 | if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) | |
3644 | link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; | |
3645 | else | |
3646 | link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; | |
3647 | ||
3648 | WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | | |
3649 | RADEON_PCIE_LC_RECONFIG_NOW)); | |
3650 | ||
3651 | if (rdev->family >= CHIP_RV770) | |
3652 | target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; | |
3653 | else | |
3654 | target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; | |
3655 | ||
3656 | /* wait for lane set to complete */ | |
3657 | link_width_cntl = RREG32(target_reg); | |
3658 | while (link_width_cntl == 0xffffffff) | |
3659 | link_width_cntl = RREG32(target_reg); | |
3660 | ||
3661 | } | |
3662 | ||
3663 | int r600_get_pcie_lanes(struct radeon_device *rdev) | |
3664 | { | |
3665 | u32 link_width_cntl; | |
3666 | ||
3667 | if (rdev->flags & RADEON_IS_IGP) | |
3668 | return 0; | |
3669 | ||
3670 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
3671 | return 0; | |
3672 | ||
3673 | /* x2 cards have a special sequence */ | |
3674 | if (ASIC_IS_X2(rdev)) | |
3675 | return 0; | |
3676 | ||
3677 | /* FIXME wait for idle */ | |
3678 | ||
3679 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
3680 | ||
3681 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { | |
3682 | case RADEON_PCIE_LC_LINK_WIDTH_X0: | |
3683 | return 0; | |
3684 | case RADEON_PCIE_LC_LINK_WIDTH_X1: | |
3685 | return 1; | |
3686 | case RADEON_PCIE_LC_LINK_WIDTH_X2: | |
3687 | return 2; | |
3688 | case RADEON_PCIE_LC_LINK_WIDTH_X4: | |
3689 | return 4; | |
3690 | case RADEON_PCIE_LC_LINK_WIDTH_X8: | |
3691 | return 8; | |
3692 | case RADEON_PCIE_LC_LINK_WIDTH_X16: | |
3693 | default: | |
3694 | return 16; | |
3695 | } | |
3696 | } | |
3697 | ||
9e46a48d AD |
3698 | static void r600_pcie_gen2_enable(struct radeon_device *rdev) |
3699 | { | |
3700 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; | |
3701 | u16 link_cntl2; | |
3702 | ||
d42dd579 AD |
3703 | if (radeon_pcie_gen2 == 0) |
3704 | return; | |
3705 | ||
9e46a48d AD |
3706 | if (rdev->flags & RADEON_IS_IGP) |
3707 | return; | |
3708 | ||
3709 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
3710 | return; | |
3711 | ||
3712 | /* x2 cards have a special sequence */ | |
3713 | if (ASIC_IS_X2(rdev)) | |
3714 | return; | |
3715 | ||
3716 | /* only RV6xx+ chips are supported */ | |
3717 | if (rdev->family <= CHIP_R600) | |
3718 | return; | |
3719 | ||
3720 | /* 55 nm r6xx asics */ | |
3721 | if ((rdev->family == CHIP_RV670) || | |
3722 | (rdev->family == CHIP_RV620) || | |
3723 | (rdev->family == CHIP_RV635)) { | |
3724 | /* advertise upconfig capability */ | |
3725 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
3726 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
3727 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3728 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
3729 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { | |
3730 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; | |
3731 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | | |
3732 | LC_RECONFIG_ARC_MISSING_ESCAPE); | |
3733 | link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; | |
3734 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3735 | } else { | |
3736 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
3737 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3738 | } | |
3739 | } | |
3740 | ||
3741 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3742 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && | |
3743 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | |
3744 | ||
3745 | /* 55 nm r6xx asics */ | |
3746 | if ((rdev->family == CHIP_RV670) || | |
3747 | (rdev->family == CHIP_RV620) || | |
3748 | (rdev->family == CHIP_RV635)) { | |
3749 | WREG32(MM_CFGREGS_CNTL, 0x8); | |
3750 | link_cntl2 = RREG32(0x4088); | |
3751 | WREG32(MM_CFGREGS_CNTL, 0); | |
3752 | /* not supported yet */ | |
3753 | if (link_cntl2 & SELECTABLE_DEEMPHASIS) | |
3754 | return; | |
3755 | } | |
3756 | ||
3757 | speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; | |
3758 | speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); | |
3759 | speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; | |
3760 | speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; | |
3761 | speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; | |
3762 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3763 | ||
3764 | tmp = RREG32(0x541c); | |
3765 | WREG32(0x541c, tmp | 0x8); | |
3766 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); | |
3767 | link_cntl2 = RREG16(0x4088); | |
3768 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; | |
3769 | link_cntl2 |= 0x2; | |
3770 | WREG16(0x4088, link_cntl2); | |
3771 | WREG32(MM_CFGREGS_CNTL, 0); | |
3772 | ||
3773 | if ((rdev->family == CHIP_RV670) || | |
3774 | (rdev->family == CHIP_RV620) || | |
3775 | (rdev->family == CHIP_RV635)) { | |
3776 | training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); | |
3777 | training_cntl &= ~LC_POINT_7_PLUS_EN; | |
3778 | WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); | |
3779 | } else { | |
3780 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3781 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; | |
3782 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3783 | } | |
3784 | ||
3785 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3786 | speed_cntl |= LC_GEN2_EN_STRAP; | |
3787 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3788 | ||
3789 | } else { | |
3790 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
3791 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ | |
3792 | if (1) | |
3793 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
3794 | else | |
3795 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
3796 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3797 | } | |
3798 | } |