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drm/radeon: fix surface sync in fence on cayman (v2)
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
e0cd3608 31#include <linux/module.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
138e4e16 40#include "radeon_ucode.h"
3ce0a23d
JG		 41
42/* Firmware Names */
43MODULE_FIRMWARE("radeon/R600_pfp.bin");
44MODULE_FIRMWARE("radeon/R600_me.bin");
45MODULE_FIRMWARE("radeon/RV610_pfp.bin");
46MODULE_FIRMWARE("radeon/RV610_me.bin");
47MODULE_FIRMWARE("radeon/RV630_pfp.bin");
48MODULE_FIRMWARE("radeon/RV630_me.bin");
49MODULE_FIRMWARE("radeon/RV620_pfp.bin");
50MODULE_FIRMWARE("radeon/RV620_me.bin");
51MODULE_FIRMWARE("radeon/RV635_pfp.bin");
52MODULE_FIRMWARE("radeon/RV635_me.bin");
53MODULE_FIRMWARE("radeon/RV670_pfp.bin");
54MODULE_FIRMWARE("radeon/RV670_me.bin");
55MODULE_FIRMWARE("radeon/RS780_pfp.bin");
56MODULE_FIRMWARE("radeon/RS780_me.bin");
57MODULE_FIRMWARE("radeon/RV770_pfp.bin");
58MODULE_FIRMWARE("radeon/RV770_me.bin");
66229b20 59MODULE_FIRMWARE("radeon/RV770_smc.bin");
3ce0a23d
JG		 60MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61MODULE_FIRMWARE("radeon/RV730_me.bin");
66229b20
AD		 62MODULE_FIRMWARE("radeon/RV730_smc.bin");
63MODULE_FIRMWARE("radeon/RV740_smc.bin");
3ce0a23d
JG		 64MODULE_FIRMWARE("radeon/RV710_pfp.bin");
65MODULE_FIRMWARE("radeon/RV710_me.bin");
66229b20 66MODULE_FIRMWARE("radeon/RV710_smc.bin");
d8f60cfc
AD		 67MODULE_FIRMWARE("radeon/R600_rlc.bin");
68MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 69MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
70MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 71MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
dc50ba7f 72MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
fe251e2f
AD		 73MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
74MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 75MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
dc50ba7f 76MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
78MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
dc50ba7f 80MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
a7433742 81MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 82MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 83MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
dc50ba7f 84MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
439bd6cd
AD		 85MODULE_FIRMWARE("radeon/PALM_pfp.bin");
86MODULE_FIRMWARE("radeon/PALM_me.bin");
87MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 88MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
89MODULE_FIRMWARE("radeon/SUMO_me.bin");
90MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
91MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d 92
f13f7731
AD		 93static const u32 crtc_offsets[2] =
94{
95 0,
96 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
97};
98
3ce0a23d 99int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 100
1a029b76 101/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9 102int r600_mc_wait_for_idle(struct radeon_device *rdev);
1109ca09 103static void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 104void r600_fini(struct radeon_device *rdev);
45f9a39b 105void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 106static void r600_pcie_gen2_enable(struct radeon_device *rdev);
2948f5e6 107extern int evergreen_rlc_resume(struct radeon_device *rdev);
de9ae744 108extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
771fe6b9 109
454d2e2a
AD		 110/**
111 * r600_get_xclk - get the xclk
112 *
113 * @rdev: radeon_device pointer
114 *
115 * Returns the reference clock used by the gfx engine
116 * (r6xx, IGPs, APUs).
117 */
118u32 r600_get_xclk(struct radeon_device *rdev)
119{
120 return rdev->clock.spll.reference_freq;
121}
122
1b9ba70a
AD		 123int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
124{
125 return 0;
126}
127
134b480f
AD		 128void dce3_program_fmt(struct drm_encoder *encoder)
129{
130 struct drm_device *dev = encoder->dev;
131 struct radeon_device *rdev = dev->dev_private;
132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
133 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
134 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
135 int bpc = 0;
136 u32 tmp = 0;
6214bb74 137 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
134b480f 138
6214bb74
AD		 139 if (connector) {
140 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
134b480f 141 bpc = radeon_get_monitor_bpc(connector);
6214bb74
AD		 142 dither = radeon_connector->dither;
143 }
134b480f
AD		 144
145 /* LVDS FMT is set up by atom */
146 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
147 return;
148
149 /* not needed for analog */
150 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
151 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
152 return;
153
154 if (bpc == 0)
155 return;
156
157 switch (bpc) {
158 case 6:
6214bb74 159 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 160 /* XXX sort out optimal dither settings */
161 tmp |= FMT_SPATIAL_DITHER_EN;
162 else
163 tmp |= FMT_TRUNCATE_EN;
164 break;
165 case 8:
6214bb74 166 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 167 /* XXX sort out optimal dither settings */
168 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
169 else
170 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
171 break;
172 case 10:
173 default:
174 /* not needed */
175 break;
176 }
177
178 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
179}
180
21a8122a 181/* get temperature in millidegrees */
20d391d7 182int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 183{
184 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
185 ASIC_T_SHIFT;
20d391d7 186 int actual_temp = temp & 0xff;
21a8122a 187
20d391d7
AD		 188 if (temp & 0x100)
189 actual_temp -= 256;
190
191 return actual_temp * 1000;
21a8122a
AD		 192}
193
ce8f5370 194void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 195{
196 int i;
197
ce8f5370
AD		 198 rdev->pm.dynpm_can_upclock = true;
199 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 200
201 /* power state array is low to high, default is first */
202 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
203 int min_power_state_index = 0;
204
205 if (rdev->pm.num_power_states > 2)
206 min_power_state_index = 1;
207
ce8f5370
AD		 208 switch (rdev->pm.dynpm_planned_action) {
209 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 210 rdev->pm.requested_power_state_index = min_power_state_index;
211 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 212 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 213 break;
ce8f5370 214 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 215 if (rdev->pm.current_power_state_index == min_power_state_index) {
216 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 217 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 218 } else {
219 if (rdev->pm.active_crtc_count > 1) {
220 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 221 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 222 continue;
223 else if (i >= rdev->pm.current_power_state_index) {
224 rdev->pm.requested_power_state_index =
225 rdev->pm.current_power_state_index;
226 break;
227 } else {
228 rdev->pm.requested_power_state_index = i;
229 break;
230 }
231 }
773c3fa3
AD		 232 } else {
233 if (rdev->pm.current_power_state_index == 0)
234 rdev->pm.requested_power_state_index =
235 rdev->pm.num_power_states - 1;
236 else
237 rdev->pm.requested_power_state_index =
238 rdev->pm.current_power_state_index - 1;
239 }
a48b9b4e
AD		 240 }
241 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 242 /* don't use the power state if crtcs are active and no display flag is set */
243 if ((rdev->pm.active_crtc_count > 0) &&
244 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
245 clock_info[rdev->pm.requested_clock_mode_index].flags &
246 RADEON_PM_MODE_NO_DISPLAY)) {
247 rdev->pm.requested_power_state_index++;
248 }
a48b9b4e 249 break;
ce8f5370 250 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 251 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
252 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 253 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 254 } else {
255 if (rdev->pm.active_crtc_count > 1) {
256 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 257 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 258 continue;
259 else if (i <= rdev->pm.current_power_state_index) {
260 rdev->pm.requested_power_state_index =
261 rdev->pm.current_power_state_index;
262 break;
263 } else {
264 rdev->pm.requested_power_state_index = i;
265 break;
266 }
267 }
268 } else
269 rdev->pm.requested_power_state_index =
270 rdev->pm.current_power_state_index + 1;
271 }
272 rdev->pm.requested_clock_mode_index = 0;
273 break;
ce8f5370 274 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 275 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
276 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 277 rdev->pm.dynpm_can_upclock = false;
58e21dff 278 break;
ce8f5370 279 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 280 default:
281 DRM_ERROR("Requested mode for not defined action\n");
282 return;
283 }
284 } else {
285 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
286 /* for now just select the first power state and switch between clock modes */
287 /* power state array is low to high, default is first (0) */
288 if (rdev->pm.active_crtc_count > 1) {
289 rdev->pm.requested_power_state_index = -1;
290 /* start at 1 as we don't want the default mode */
291 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 292 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 293 continue;
294 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
295 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
296 rdev->pm.requested_power_state_index = i;
297 break;
298 }
299 }
300 /* if nothing selected, grab the default state. */
301 if (rdev->pm.requested_power_state_index == -1)
302 rdev->pm.requested_power_state_index = 0;
303 } else
304 rdev->pm.requested_power_state_index = 1;
305
ce8f5370
AD		 306 switch (rdev->pm.dynpm_planned_action) {
307 case DYNPM_ACTION_MINIMUM:
a48b9b4e 308 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 309 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 310 break;
ce8f5370 311 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 312 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
313 if (rdev->pm.current_clock_mode_index == 0) {
314 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 315 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 316 } else
317 rdev->pm.requested_clock_mode_index =
318 rdev->pm.current_clock_mode_index - 1;
319 } else {
320 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 321 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 322 }
d7311171
AD		 323 /* don't use the power state if crtcs are active and no display flag is set */
324 if ((rdev->pm.active_crtc_count > 0) &&
325 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
326 clock_info[rdev->pm.requested_clock_mode_index].flags &
327 RADEON_PM_MODE_NO_DISPLAY)) {
328 rdev->pm.requested_clock_mode_index++;
329 }
a48b9b4e 330 break;
ce8f5370 331 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 332 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
333 if (rdev->pm.current_clock_mode_index ==
334 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
335 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 336 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 337 } else
338 rdev->pm.requested_clock_mode_index =
339 rdev->pm.current_clock_mode_index + 1;
340 } else {
341 rdev->pm.requested_clock_mode_index =
342 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 343 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 344 }
345 break;
ce8f5370 346 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 347 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
348 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 349 rdev->pm.dynpm_can_upclock = false;
58e21dff 350 break;
ce8f5370 351 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 352 default:
353 DRM_ERROR("Requested mode for not defined action\n");
354 return;
355 }
356 }
357
d9fdaafb 358 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 359 rdev->pm.power_state[rdev->pm.requested_power_state_index].
360 clock_info[rdev->pm.requested_clock_mode_index].sclk,
361 rdev->pm.power_state[rdev->pm.requested_power_state_index].
362 clock_info[rdev->pm.requested_clock_mode_index].mclk,
363 rdev->pm.power_state[rdev->pm.requested_power_state_index].
364 pcie_lanes);
a48b9b4e
AD		 365}
366
ce8f5370
AD		 367void rs780_pm_init_profile(struct radeon_device *rdev)
368{
369 if (rdev->pm.num_power_states == 2) {
370 /* default */
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
372 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
373 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
375 /* low sh */
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
377 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
378 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 380 /* mid sh */
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
382 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
383 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 385 /* high sh */
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
388 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
389 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
390 /* low mh */
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
393 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
394 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 395 /* mid mh */
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
399 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 400 /* high mh */
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
403 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
405 } else if (rdev->pm.num_power_states == 3) {
406 /* default */
407 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
408 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
409 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
410 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
411 /* low sh */
412 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
413 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
414 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
415 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 416 /* mid sh */
417 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
418 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
419 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
420 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 421 /* high sh */
422 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
423 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
424 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
426 /* low mh */
427 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
428 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
429 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
430 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 431 /* mid mh */
432 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
433 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
434 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
435 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 436 /* high mh */
437 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
438 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
439 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
441 } else {
442 /* default */
443 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
445 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
446 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
447 /* low sh */
448 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
449 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
450 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
451 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 452 /* mid sh */
453 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
454 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
455 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
456 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 457 /* high sh */
458 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
459 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
460 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
461 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
462 /* low mh */
463 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
464 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
465 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
466 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 467 /* mid mh */
468 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
469 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
470 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
471 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 472 /* high mh */
473 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
474 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
475 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
477 }
478}
bae6b562 479
ce8f5370
AD		 480void r600_pm_init_profile(struct radeon_device *rdev)
481{
bbe26ffe
AD		 482 int idx;
483
ce8f5370
AD		 484 if (rdev->family == CHIP_R600) {
485 /* XXX */
486 /* default */
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
489 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 490 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 491 /* low sh */
492 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 496 /* mid sh */
497 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 501 /* high sh */
502 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
503 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 506 /* low mh */
507 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
508 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
509 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 510 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 511 /* mid mh */
512 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
513 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
514 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
515 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 516 /* high mh */
517 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
518 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
519 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 520 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 521 } else {
522 if (rdev->pm.num_power_states < 4) {
523 /* default */
524 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
525 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
526 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
527 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
528 /* low sh */
4bff5171
AD		 529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 531 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 532 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
533 /* mid sh */
534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
536 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
537 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 538 /* high sh */
4bff5171
AD		 539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
542 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
543 /* low mh */
4bff5171
AD		 544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 547 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
548 /* low mh */
549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
552 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 553 /* high mh */
4bff5171
AD		 554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 556 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
557 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
558 } else {
559 /* default */
560 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
561 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
562 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
563 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
564 /* low sh */
bbe26ffe
AD		 565 if (rdev->flags & RADEON_IS_MOBILITY)
566 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
567 else
568 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
569 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
570 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
571 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 573 /* mid sh */
bbe26ffe
AD		 574 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
575 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
576 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
577 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 578 /* high sh */
bbe26ffe
AD		 579 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
580 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
581 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 582 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
583 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
584 /* low mh */
bbe26ffe
AD		 585 if (rdev->flags & RADEON_IS_MOBILITY)
586 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
587 else
588 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
589 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
590 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
591 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
592 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 593 /* mid mh */
bbe26ffe
AD		 594 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
595 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
596 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
597 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 598 /* high mh */
bbe26ffe
AD		 599 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
600 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
601 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 602 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
603 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
604 }
605 }
bae6b562
AD		 606}
607
49e02b73
AD		 608void r600_pm_misc(struct radeon_device *rdev)
609{
a081a9d6
RM		 610 int req_ps_idx = rdev->pm.requested_power_state_index;
611 int req_cm_idx = rdev->pm.requested_clock_mode_index;
612 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
613 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 614
4d60173f 615 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 616 /* 0xff01 is a flag rather then an actual voltage */
617 if (voltage->voltage == 0xff01)
618 return;
4d60173f 619 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 620 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 621 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 622 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 623 }
624 }
49e02b73
AD		 625}
626
def9ba9c
AD		 627bool r600_gui_idle(struct radeon_device *rdev)
628{
629 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
630 return false;
631 else
632 return true;
633}
634
e0df1ac5
AD		 635/* hpd for digital panel detect/disconnect */
636bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
637{
638 bool connected = false;
639
640 if (ASIC_IS_DCE3(rdev)) {
641 switch (hpd) {
642 case RADEON_HPD_1:
643 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
644 connected = true;
645 break;
646 case RADEON_HPD_2:
647 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
648 connected = true;
649 break;
650 case RADEON_HPD_3:
651 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
652 connected = true;
653 break;
654 case RADEON_HPD_4:
655 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
656 connected = true;
657 break;
658 /* DCE 3.2 */
659 case RADEON_HPD_5:
660 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
661 connected = true;
662 break;
663 case RADEON_HPD_6:
664 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
665 connected = true;
666 break;
667 default:
668 break;
669 }
670 } else {
671 switch (hpd) {
672 case RADEON_HPD_1:
673 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
674 connected = true;
675 break;
676 case RADEON_HPD_2:
677 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
678 connected = true;
679 break;
680 case RADEON_HPD_3:
681 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
682 connected = true;
683 break;
684 default:
685 break;
686 }
687 }
688 return connected;
689}
690
691void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 692 enum radeon_hpd_id hpd)
e0df1ac5
AD		 693{
694 u32 tmp;
695 bool connected = r600_hpd_sense(rdev, hpd);
696
697 if (ASIC_IS_DCE3(rdev)) {
698 switch (hpd) {
699 case RADEON_HPD_1:
700 tmp = RREG32(DC_HPD1_INT_CONTROL);
701 if (connected)
702 tmp &= ~DC_HPDx_INT_POLARITY;
703 else
704 tmp |= DC_HPDx_INT_POLARITY;
705 WREG32(DC_HPD1_INT_CONTROL, tmp);
706 break;
707 case RADEON_HPD_2:
708 tmp = RREG32(DC_HPD2_INT_CONTROL);
709 if (connected)
710 tmp &= ~DC_HPDx_INT_POLARITY;
711 else
712 tmp |= DC_HPDx_INT_POLARITY;
713 WREG32(DC_HPD2_INT_CONTROL, tmp);
714 break;
715 case RADEON_HPD_3:
716 tmp = RREG32(DC_HPD3_INT_CONTROL);
717 if (connected)
718 tmp &= ~DC_HPDx_INT_POLARITY;
719 else
720 tmp |= DC_HPDx_INT_POLARITY;
721 WREG32(DC_HPD3_INT_CONTROL, tmp);
722 break;
723 case RADEON_HPD_4:
724 tmp = RREG32(DC_HPD4_INT_CONTROL);
725 if (connected)
726 tmp &= ~DC_HPDx_INT_POLARITY;
727 else
728 tmp |= DC_HPDx_INT_POLARITY;
729 WREG32(DC_HPD4_INT_CONTROL, tmp);
730 break;
731 case RADEON_HPD_5:
732 tmp = RREG32(DC_HPD5_INT_CONTROL);
733 if (connected)
734 tmp &= ~DC_HPDx_INT_POLARITY;
735 else
736 tmp |= DC_HPDx_INT_POLARITY;
737 WREG32(DC_HPD5_INT_CONTROL, tmp);
738 break;
739 /* DCE 3.2 */
740 case RADEON_HPD_6:
741 tmp = RREG32(DC_HPD6_INT_CONTROL);
742 if (connected)
743 tmp &= ~DC_HPDx_INT_POLARITY;
744 else
745 tmp |= DC_HPDx_INT_POLARITY;
746 WREG32(DC_HPD6_INT_CONTROL, tmp);
747 break;
748 default:
749 break;
750 }
751 } else {
752 switch (hpd) {
753 case RADEON_HPD_1:
754 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
755 if (connected)
756 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
757 else
758 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
759 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
760 break;
761 case RADEON_HPD_2:
762 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
763 if (connected)
764 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
765 else
766 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
767 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
768 break;
769 case RADEON_HPD_3:
770 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
771 if (connected)
772 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
773 else
774 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
775 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
776 break;
777 default:
778 break;
779 }
780 }
781}
782
783void r600_hpd_init(struct radeon_device *rdev)
784{
785 struct drm_device *dev = rdev->ddev;
786 struct drm_connector *connector;
fb98257a 787 unsigned enable = 0;
e0df1ac5 788
64912e99
AD		 789 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
790 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
791
455c89b9
JG		 792 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
793 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
794 /* don't try to enable hpd on eDP or LVDS avoid breaking the
795 * aux dp channel on imac and help (but not completely fix)
796 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
797 */
798 continue;
799 }
64912e99
AD		 800 if (ASIC_IS_DCE3(rdev)) {
801 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
802 if (ASIC_IS_DCE32(rdev))
803 tmp |= DC_HPDx_EN;
e0df1ac5 804
e0df1ac5
AD		 805 switch (radeon_connector->hpd.hpd) {
806 case RADEON_HPD_1:
807 WREG32(DC_HPD1_CONTROL, tmp);
e0df1ac5
AD		 808 break;
809 case RADEON_HPD_2:
810 WREG32(DC_HPD2_CONTROL, tmp);
e0df1ac5
AD		 811 break;
812 case RADEON_HPD_3:
813 WREG32(DC_HPD3_CONTROL, tmp);
e0df1ac5
AD		 814 break;
815 case RADEON_HPD_4:
816 WREG32(DC_HPD4_CONTROL, tmp);
e0df1ac5
AD		 817 break;
818 /* DCE 3.2 */
819 case RADEON_HPD_5:
820 WREG32(DC_HPD5_CONTROL, tmp);
e0df1ac5
AD		 821 break;
822 case RADEON_HPD_6:
823 WREG32(DC_HPD6_CONTROL, tmp);
e0df1ac5
AD		 824 break;
825 default:
826 break;
827 }
64912e99 828 } else {
e0df1ac5
AD		 829 switch (radeon_connector->hpd.hpd) {
830 case RADEON_HPD_1:
831 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 832 break;
833 case RADEON_HPD_2:
834 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 835 break;
836 case RADEON_HPD_3:
837 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 838 break;
839 default:
840 break;
841 }
842 }
fb98257a 843 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 844 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 845 }
fb98257a 846 radeon_irq_kms_enable_hpd(rdev, enable);
e0df1ac5
AD		 847}
848
849void r600_hpd_fini(struct radeon_device *rdev)
850{
851 struct drm_device *dev = rdev->ddev;
852 struct drm_connector *connector;
fb98257a 853 unsigned disable = 0;
e0df1ac5 854
fb98257a
CK		 855 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
856 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
857 if (ASIC_IS_DCE3(rdev)) {
e0df1ac5
AD		 858 switch (radeon_connector->hpd.hpd) {
859 case RADEON_HPD_1:
860 WREG32(DC_HPD1_CONTROL, 0);
e0df1ac5
AD		 861 break;
862 case RADEON_HPD_2:
863 WREG32(DC_HPD2_CONTROL, 0);
e0df1ac5
AD		 864 break;
865 case RADEON_HPD_3:
866 WREG32(DC_HPD3_CONTROL, 0);
e0df1ac5
AD		 867 break;
868 case RADEON_HPD_4:
869 WREG32(DC_HPD4_CONTROL, 0);
e0df1ac5
AD		 870 break;
871 /* DCE 3.2 */
872 case RADEON_HPD_5:
873 WREG32(DC_HPD5_CONTROL, 0);
e0df1ac5
AD		 874 break;
875 case RADEON_HPD_6:
876 WREG32(DC_HPD6_CONTROL, 0);
e0df1ac5
AD		 877 break;
878 default:
879 break;
880 }
fb98257a 881 } else {
e0df1ac5
AD		 882 switch (radeon_connector->hpd.hpd) {
883 case RADEON_HPD_1:
884 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
e0df1ac5
AD		 885 break;
886 case RADEON_HPD_2:
887 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
e0df1ac5
AD		 888 break;
889 case RADEON_HPD_3:
890 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
e0df1ac5
AD		 891 break;
892 default:
893 break;
894 }
895 }
fb98257a 896 disable |= 1 << radeon_connector->hpd.hpd;
e0df1ac5 897 }
fb98257a 898 radeon_irq_kms_disable_hpd(rdev, disable);
e0df1ac5
AD		 899}
900
771fe6b9 901/*
3ce0a23d 902 * R600 PCIE GART
771fe6b9 903 */
3ce0a23d
JG		 904void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
905{
906 unsigned i;
907 u32 tmp;
908
2e98f10a 909 /* flush hdp cache so updates hit vram */
f3886f85
AD		 910 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
911 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 912 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 913 u32 tmp;
914
915 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
916 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 917 * This seems to cause problems on some AGP cards. Just use the old
918 * method for them.
812d0469
AD		 919 */
920 WREG32(HDP_DEBUG1, 0);
921 tmp = readl((void __iomem *)ptr);
922 } else
923 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 924
3ce0a23d
JG		 925 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
926 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
927 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
928 for (i = 0; i < rdev->usec_timeout; i++) {
929 /* read MC_STATUS */
930 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
931 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
932 if (tmp == 2) {
933 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
934 return;
935 }
936 if (tmp) {
937 return;
938 }
939 udelay(1);
940 }
941}
942
4aac0473 943int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 944{
4aac0473 945 int r;
3ce0a23d 946
c9a1be96 947 if (rdev->gart.robj) {
fce7d61b 948 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 949 return 0;
950 }
3ce0a23d
JG		 951 /* Initialize common gart structure */
952 r = radeon_gart_init(rdev);
4aac0473 953 if (r)
3ce0a23d 954 return r;
3ce0a23d 955 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 956 return radeon_gart_table_vram_alloc(rdev);
957}
958
1109ca09 959static int r600_pcie_gart_enable(struct radeon_device *rdev)
4aac0473
JG		 960{
961 u32 tmp;
962 int r, i;
963
c9a1be96 964 if (rdev->gart.robj == NULL) {
4aac0473
JG		 965 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
966 return -EINVAL;
771fe6b9 967 }
4aac0473
JG		 968 r = radeon_gart_table_vram_pin(rdev);
969 if (r)
970 return r;
82568565 971 radeon_gart_restore(rdev);
bc1a631e 972
3ce0a23d
JG		 973 /* Setup L2 cache */
974 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
975 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
976 EFFECTIVE_L2_QUEUE_SIZE(7));
977 WREG32(VM_L2_CNTL2, 0);
978 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
979 /* Setup TLB control */
980 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
981 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
982 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
983 ENABLE_WAIT_L2_QUERY;
984 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
985 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
986 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
987 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
988 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
989 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
990 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
991 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
992 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
993 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
994 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
995 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
996 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
997 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
998 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 999 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 1000 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1001 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1002 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1003 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1004 (u32)(rdev->dummy_page.addr >> 12));
1005 for (i = 1; i < 7; i++)
1006 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 1007
3ce0a23d 1008 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1009 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1010 (unsigned)(rdev->mc.gtt_size >> 20),
1011 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 1012 rdev->gart.ready = true;
771fe6b9
JG		 1013 return 0;
1014}
1015
1109ca09 1016static void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 1017{
3ce0a23d 1018 u32 tmp;
c9a1be96 1019 int i;
771fe6b9 1020
3ce0a23d
JG		 1021 /* Disable all tables */
1022 for (i = 0; i < 7; i++)
1023 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 1024
3ce0a23d
JG		 1025 /* Disable L2 cache */
1026 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1027 EFFECTIVE_L2_QUEUE_SIZE(7));
1028 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1029 /* Setup L1 TLB control */
1030 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1031 ENABLE_WAIT_L2_QUERY;
1032 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1033 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1034 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1035 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1036 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1037 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1038 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1039 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1040 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1041 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1042 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1043 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1044 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1045 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
c9a1be96 1046 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 1047}
1048
1109ca09 1049static void r600_pcie_gart_fini(struct radeon_device *rdev)
4aac0473 1050{
f9274562 1051 radeon_gart_fini(rdev);
4aac0473
JG		 1052 r600_pcie_gart_disable(rdev);
1053 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1054}
1055
1109ca09 1056static void r600_agp_enable(struct radeon_device *rdev)
1a029b76
JG		 1057{
1058 u32 tmp;
1059 int i;
1060
1061 /* Setup L2 cache */
1062 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1063 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1064 EFFECTIVE_L2_QUEUE_SIZE(7));
1065 WREG32(VM_L2_CNTL2, 0);
1066 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1067 /* Setup TLB control */
1068 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1069 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1070 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1071 ENABLE_WAIT_L2_QUERY;
1072 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1073 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1074 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1075 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1076 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1077 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1078 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1079 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1080 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1081 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1082 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1083 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1084 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1085 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1086 for (i = 0; i < 7; i++)
1087 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1088}
1089
771fe6b9
JG		 1090int r600_mc_wait_for_idle(struct radeon_device *rdev)
1091{
3ce0a23d
JG		 1092 unsigned i;
1093 u32 tmp;
1094
1095 for (i = 0; i < rdev->usec_timeout; i++) {
1096 /* read MC_STATUS */
1097 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1098 if (!tmp)
1099 return 0;
1100 udelay(1);
1101 }
1102 return -1;
771fe6b9
JG		 1103}
1104
65337e60
SL		 1105uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1106{
0a5b7b0b 1107 unsigned long flags;
65337e60
SL		 1108 uint32_t r;
1109
0a5b7b0b 1110 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1111 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1112 r = RREG32(R_0028FC_MC_DATA);
1113 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
0a5b7b0b 1114 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1115 return r;
1116}
1117
1118void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1119{
0a5b7b0b
AD		 1120 unsigned long flags;
1121
1122 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1123 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1124 S_0028F8_MC_IND_WR_EN(1));
1125 WREG32(R_0028FC_MC_DATA, v);
1126 WREG32(R_0028F8_MC_INDEX, 0x7F);
0a5b7b0b 1127 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1128}
1129
a3c1945a 1130static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1131{
a3c1945a 1132 struct rv515_mc_save save;
3ce0a23d
JG		 1133 u32 tmp;
1134 int i, j;
771fe6b9 1135
3ce0a23d
JG		 1136 /* Initialize HDP */
1137 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1138 WREG32((0x2c14 + j), 0x00000000);
1139 WREG32((0x2c18 + j), 0x00000000);
1140 WREG32((0x2c1c + j), 0x00000000);
1141 WREG32((0x2c20 + j), 0x00000000);
1142 WREG32((0x2c24 + j), 0x00000000);
1143 }
1144 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1145
a3c1945a 1146 rv515_mc_stop(rdev, &save);
3ce0a23d 1147 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1148 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1149 }
a3c1945a 1150 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1151 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1152 /* Update configuration */
1a029b76
JG		 1153 if (rdev->flags & RADEON_IS_AGP) {
1154 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1155 /* VRAM before AGP */
1156 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1157 rdev->mc.vram_start >> 12);
1158 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1159 rdev->mc.gtt_end >> 12);
1160 } else {
1161 /* VRAM after AGP */
1162 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1163 rdev->mc.gtt_start >> 12);
1164 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1165 rdev->mc.vram_end >> 12);
1166 }
1167 } else {
1168 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1169 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1170 }
16cdf04d 1171 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1172 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1173 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1174 WREG32(MC_VM_FB_LOCATION, tmp);
1175 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1176 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1177 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1178 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1179 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1180 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1181 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1182 } else {
1183 WREG32(MC_VM_AGP_BASE, 0);
1184 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1185 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1186 }
3ce0a23d 1187 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1188 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1189 }
a3c1945a 1190 rv515_mc_resume(rdev, &save);
698443d9
DA		 1191 /* we need to own VRAM, so turn off the VGA renderer here
1192 * to stop it overwriting our objects */
d39c3b89 1193 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1194}
1195
d594e46a
JG		 1196/**
1197 * r600_vram_gtt_location - try to find VRAM & GTT location
1198 * @rdev: radeon device structure holding all necessary informations
1199 * @mc: memory controller structure holding memory informations
1200 *
1201 * Function will place try to place VRAM at same place as in CPU (PCI)
1202 * address space as some GPU seems to have issue when we reprogram at
1203 * different address space.
1204 *
1205 * If there is not enough space to fit the unvisible VRAM after the
1206 * aperture then we limit the VRAM size to the aperture.
1207 *
1208 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1209 * them to be in one from GPU point of view so that we can program GPU to
1210 * catch access outside them (weird GPU policy see ??).
1211 *
1212 * This function will never fails, worst case are limiting VRAM or GTT.
1213 *
1214 * Note: GTT start, end, size should be initialized before calling this
1215 * function on AGP platform.
1216 */
0ef0c1f7 1217static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1218{
1219 u64 size_bf, size_af;
1220
1221 if (mc->mc_vram_size > 0xE0000000) {
1222 /* leave room for at least 512M GTT */
1223 dev_warn(rdev->dev, "limiting VRAM\n");
1224 mc->real_vram_size = 0xE0000000;
1225 mc->mc_vram_size = 0xE0000000;
1226 }
1227 if (rdev->flags & RADEON_IS_AGP) {
1228 size_bf = mc->gtt_start;
9ed8b1f9 1229 size_af = mc->mc_mask - mc->gtt_end;
d594e46a
JG		 1230 if (size_bf > size_af) {
1231 if (mc->mc_vram_size > size_bf) {
1232 dev_warn(rdev->dev, "limiting VRAM\n");
1233 mc->real_vram_size = size_bf;
1234 mc->mc_vram_size = size_bf;
1235 }
1236 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1237 } else {
1238 if (mc->mc_vram_size > size_af) {
1239 dev_warn(rdev->dev, "limiting VRAM\n");
1240 mc->real_vram_size = size_af;
1241 mc->mc_vram_size = size_af;
1242 }
dfc6ae5b 1243 mc->vram_start = mc->gtt_end + 1;
d594e46a
JG		 1244 }
1245 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1246 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1247 mc->mc_vram_size >> 20, mc->vram_start,
1248 mc->vram_end, mc->real_vram_size >> 20);
1249 } else {
1250 u64 base = 0;
8961d52d
AD		 1251 if (rdev->flags & RADEON_IS_IGP) {
1252 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1253 base <<= 24;
1254 }
d594e46a 1255 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1256 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1257 radeon_gtt_location(rdev, mc);
1258 }
1259}
1260
1109ca09 1261static int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1262{
3ce0a23d 1263 u32 tmp;
5885b7a9 1264 int chansize, numchan;
65337e60
SL		 1265 uint32_t h_addr, l_addr;
1266 unsigned long long k8_addr;
771fe6b9 1267
3ce0a23d 1268 /* Get VRAM informations */
771fe6b9 1269 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1270 tmp = RREG32(RAMCFG);
1271 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1272 chansize = 16;
3ce0a23d 1273 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1274 chansize = 64;
1275 } else {
1276 chansize = 32;
1277 }
5885b7a9
AD		 1278 tmp = RREG32(CHMAP);
1279 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1280 case 0:
1281 default:
1282 numchan = 1;
1283 break;
1284 case 1:
1285 numchan = 2;
1286 break;
1287 case 2:
1288 numchan = 4;
1289 break;
1290 case 3:
1291 numchan = 8;
1292 break;
771fe6b9 1293 }
5885b7a9 1294 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1295 /* Could aper size report 0 ? */
01d73a69
JC		 1296 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1297 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1298 /* Setup GPU memory space */
1299 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1300 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1301 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1302 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1303
f892034a
AD		 1304 if (rdev->flags & RADEON_IS_IGP) {
1305 rs690_pm_info(rdev);
06b6476d 1306 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
65337e60
SL		 1307
1308 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1309 /* Use K8 direct mapping for fast fb access. */
1310 rdev->fastfb_working = false;
1311 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1312 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1313 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1314#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1315 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1316#endif
1317 {
1318 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1319 * memory is present.
1320 */
1321 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1322 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1323 (unsigned long long)rdev->mc.aper_base, k8_addr);
1324 rdev->mc.aper_base = (resource_size_t)k8_addr;
1325 rdev->fastfb_working = true;
1326 }
1327 }
1328 }
f892034a 1329 }
65337e60 1330
f47299c5 1331 radeon_update_bandwidth_info(rdev);
3ce0a23d 1332 return 0;
771fe6b9
JG		 1333}
1334
16cdf04d
AD		 1335int r600_vram_scratch_init(struct radeon_device *rdev)
1336{
1337 int r;
1338
1339 if (rdev->vram_scratch.robj == NULL) {
1340 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1341 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
40f5cf99 1342 NULL, &rdev->vram_scratch.robj);
16cdf04d
AD		 1343 if (r) {
1344 return r;
1345 }
1346 }
1347
1348 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1349 if (unlikely(r != 0))
1350 return r;
1351 r = radeon_bo_pin(rdev->vram_scratch.robj,
1352 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1353 if (r) {
1354 radeon_bo_unreserve(rdev->vram_scratch.robj);
1355 return r;
1356 }
1357 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1358 (void **)&rdev->vram_scratch.ptr);
1359 if (r)
1360 radeon_bo_unpin(rdev->vram_scratch.robj);
1361 radeon_bo_unreserve(rdev->vram_scratch.robj);
1362
1363 return r;
1364}
1365
1366void r600_vram_scratch_fini(struct radeon_device *rdev)
1367{
1368 int r;
1369
1370 if (rdev->vram_scratch.robj == NULL) {
1371 return;
1372 }
1373 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1374 if (likely(r == 0)) {
1375 radeon_bo_kunmap(rdev->vram_scratch.robj);
1376 radeon_bo_unpin(rdev->vram_scratch.robj);
1377 radeon_bo_unreserve(rdev->vram_scratch.robj);
1378 }
1379 radeon_bo_unref(&rdev->vram_scratch.robj);
1380}
1381
410a3418
AD		 1382void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1383{
1384 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1385
1386 if (hung)
1387 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1388 else
1389 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1390
1391 WREG32(R600_BIOS_3_SCRATCH, tmp);
1392}
1393
d3cb781e 1394static void r600_print_gpu_status_regs(struct radeon_device *rdev)
771fe6b9 1395{
64c56e8c 1396 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
d3cb781e 1397 RREG32(R_008010_GRBM_STATUS));
64c56e8c 1398 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
d3cb781e 1399 RREG32(R_008014_GRBM_STATUS2));
64c56e8c 1400 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
d3cb781e 1401 RREG32(R_000E50_SRBM_STATUS));
440a7cd8 1402 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
d3cb781e 1403 RREG32(CP_STALLED_STAT1));
440a7cd8 1404 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
d3cb781e 1405 RREG32(CP_STALLED_STAT2));
440a7cd8 1406 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
d3cb781e 1407 RREG32(CP_BUSY_STAT));
440a7cd8 1408 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
d3cb781e 1409 RREG32(CP_STAT));
71e3d157
AD		 1410 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1411 RREG32(DMA_STATUS_REG));
1412}
1413
f13f7731 1414static bool r600_is_display_hung(struct radeon_device *rdev)
71e3d157 1415{
f13f7731
AD		 1416 u32 crtc_hung = 0;
1417 u32 crtc_status[2];
1418 u32 i, j, tmp;
1419
1420 for (i = 0; i < rdev->num_crtc; i++) {
1421 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1422 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1423 crtc_hung |= (1 << i);
1424 }
1425 }
1426
1427 for (j = 0; j < 10; j++) {
1428 for (i = 0; i < rdev->num_crtc; i++) {
1429 if (crtc_hung & (1 << i)) {
1430 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1431 if (tmp != crtc_status[i])
1432 crtc_hung &= ~(1 << i);
1433 }
1434 }
1435 if (crtc_hung == 0)
1436 return false;
1437 udelay(100);
1438 }
1439
1440 return true;
1441}
1442
2483b4ea 1443u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
f13f7731
AD		 1444{
1445 u32 reset_mask = 0;
d3cb781e 1446 u32 tmp;
71e3d157 1447
f13f7731
AD		 1448 /* GRBM_STATUS */
1449 tmp = RREG32(R_008010_GRBM_STATUS);
1450 if (rdev->family >= CHIP_RV770) {
1451 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1452 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1453 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1454 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1455 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1456 reset_mask |= RADEON_RESET_GFX;
1457 } else {
1458 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1459 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1460 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1461 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1462 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1463 reset_mask |= RADEON_RESET_GFX;
1464 }
1465
1466 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1467 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1468 reset_mask |= RADEON_RESET_CP;
1469
1470 if (G_008010_GRBM_EE_BUSY(tmp))
1471 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1472
1473 /* DMA_STATUS_REG */
1474 tmp = RREG32(DMA_STATUS_REG);
1475 if (!(tmp & DMA_IDLE))
1476 reset_mask |= RADEON_RESET_DMA;
1477
1478 /* SRBM_STATUS */
1479 tmp = RREG32(R_000E50_SRBM_STATUS);
1480 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1481 reset_mask |= RADEON_RESET_RLC;
1482
1483 if (G_000E50_IH_BUSY(tmp))
1484 reset_mask |= RADEON_RESET_IH;
1485
1486 if (G_000E50_SEM_BUSY(tmp))
1487 reset_mask |= RADEON_RESET_SEM;
19fc42ed 1488
f13f7731
AD		 1489 if (G_000E50_GRBM_RQ_PENDING(tmp))
1490 reset_mask |= RADEON_RESET_GRBM;
1491
1492 if (G_000E50_VMC_BUSY(tmp))
1493 reset_mask |= RADEON_RESET_VMC;
1494
1495 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1496 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1497 G_000E50_MCDW_BUSY(tmp))
1498 reset_mask |= RADEON_RESET_MC;
1499
1500 if (r600_is_display_hung(rdev))
1501 reset_mask |= RADEON_RESET_DISPLAY;
1502
d808fc88
AD		 1503 /* Skip MC reset as it's mostly likely not hung, just busy */
1504 if (reset_mask & RADEON_RESET_MC) {
1505 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1506 reset_mask &= ~RADEON_RESET_MC;
1507 }
1508
f13f7731
AD		 1509 return reset_mask;
1510}
1511
1512static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1513{
1514 struct rv515_mc_save save;
1515 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1516 u32 tmp;
19fc42ed 1517
71e3d157 1518 if (reset_mask == 0)
f13f7731 1519 return;
71e3d157
AD		 1520
1521 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1522
d3cb781e
AD		 1523 r600_print_gpu_status_regs(rdev);
1524
d3cb781e
AD		 1525 /* Disable CP parsing/prefetching */
1526 if (rdev->family >= CHIP_RV770)
1527 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1528 else
1529 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1530
1531 /* disable the RLC */
1532 WREG32(RLC_CNTL, 0);
1533
1534 if (reset_mask & RADEON_RESET_DMA) {
1535 /* Disable DMA */
1536 tmp = RREG32(DMA_RB_CNTL);
1537 tmp &= ~DMA_RB_ENABLE;
1538 WREG32(DMA_RB_CNTL, tmp);
1539 }
1540
1541 mdelay(50);
1542
ca57802e
AD		 1543 rv515_mc_stop(rdev, &save);
1544 if (r600_mc_wait_for_idle(rdev)) {
1545 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1546 }
1547
d3cb781e
AD		 1548 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1549 if (rdev->family >= CHIP_RV770)
1550 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1551 S_008020_SOFT_RESET_CB(1) |
1552 S_008020_SOFT_RESET_PA(1) |
1553 S_008020_SOFT_RESET_SC(1) |
1554 S_008020_SOFT_RESET_SPI(1) |
1555 S_008020_SOFT_RESET_SX(1) |
1556 S_008020_SOFT_RESET_SH(1) |
1557 S_008020_SOFT_RESET_TC(1) |
1558 S_008020_SOFT_RESET_TA(1) |
1559 S_008020_SOFT_RESET_VC(1) |
1560 S_008020_SOFT_RESET_VGT(1);
1561 else
1562 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1563 S_008020_SOFT_RESET_DB(1) |
1564 S_008020_SOFT_RESET_CB(1) |
1565 S_008020_SOFT_RESET_PA(1) |
1566 S_008020_SOFT_RESET_SC(1) |
1567 S_008020_SOFT_RESET_SMX(1) |
1568 S_008020_SOFT_RESET_SPI(1) |
1569 S_008020_SOFT_RESET_SX(1) |
1570 S_008020_SOFT_RESET_SH(1) |
1571 S_008020_SOFT_RESET_TC(1) |
1572 S_008020_SOFT_RESET_TA(1) |
1573 S_008020_SOFT_RESET_VC(1) |
1574 S_008020_SOFT_RESET_VGT(1);
1575 }
1576
1577 if (reset_mask & RADEON_RESET_CP) {
1578 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1579 S_008020_SOFT_RESET_VGT(1);
1580
1581 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1582 }
1583
1584 if (reset_mask & RADEON_RESET_DMA) {
1585 if (rdev->family >= CHIP_RV770)
1586 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1587 else
1588 srbm_soft_reset |= SOFT_RESET_DMA;
1589 }
1590
f13f7731
AD		 1591 if (reset_mask & RADEON_RESET_RLC)
1592 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1593
1594 if (reset_mask & RADEON_RESET_SEM)
1595 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1596
1597 if (reset_mask & RADEON_RESET_IH)
1598 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1599
1600 if (reset_mask & RADEON_RESET_GRBM)
1601 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1602
24178ec4
AD		 1603 if (!(rdev->flags & RADEON_IS_IGP)) {
1604 if (reset_mask & RADEON_RESET_MC)
1605 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1606 }
f13f7731
AD		 1607
1608 if (reset_mask & RADEON_RESET_VMC)
1609 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1610
d3cb781e
AD		 1611 if (grbm_soft_reset) {
1612 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1613 tmp |= grbm_soft_reset;
1614 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1615 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1616 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1617
1618 udelay(50);
1619
1620 tmp &= ~grbm_soft_reset;
1621 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1622 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1623 }
1624
1625 if (srbm_soft_reset) {
1626 tmp = RREG32(SRBM_SOFT_RESET);
1627 tmp |= srbm_soft_reset;
1628 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1629 WREG32(SRBM_SOFT_RESET, tmp);
1630 tmp = RREG32(SRBM_SOFT_RESET);
1631
1632 udelay(50);
71e3d157 1633
d3cb781e
AD		 1634 tmp &= ~srbm_soft_reset;
1635 WREG32(SRBM_SOFT_RESET, tmp);
1636 tmp = RREG32(SRBM_SOFT_RESET);
1637 }
71e3d157
AD		 1638
1639 /* Wait a little for things to settle down */
1640 mdelay(1);
1641
a3c1945a 1642 rv515_mc_resume(rdev, &save);
d3cb781e 1643 udelay(50);
410a3418 1644
d3cb781e 1645 r600_print_gpu_status_regs(rdev);
d3cb781e
AD		 1646}
1647
de9ae744
AD		 1648static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1649{
1650 struct rv515_mc_save save;
1651 u32 tmp, i;
1652
1653 dev_info(rdev->dev, "GPU pci config reset\n");
1654
1655 /* disable dpm? */
1656
1657 /* Disable CP parsing/prefetching */
1658 if (rdev->family >= CHIP_RV770)
1659 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1660 else
1661 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1662
1663 /* disable the RLC */
1664 WREG32(RLC_CNTL, 0);
1665
1666 /* Disable DMA */
1667 tmp = RREG32(DMA_RB_CNTL);
1668 tmp &= ~DMA_RB_ENABLE;
1669 WREG32(DMA_RB_CNTL, tmp);
1670
1671 mdelay(50);
1672
1673 /* set mclk/sclk to bypass */
1674 if (rdev->family >= CHIP_RV770)
1675 rv770_set_clk_bypass_mode(rdev);
1676 /* disable BM */
1677 pci_clear_master(rdev->pdev);
1678 /* disable mem access */
1679 rv515_mc_stop(rdev, &save);
1680 if (r600_mc_wait_for_idle(rdev)) {
1681 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1682 }
1683
1684 /* BIF reset workaround. Not sure if this is needed on 6xx */
1685 tmp = RREG32(BUS_CNTL);
1686 tmp |= VGA_COHE_SPEC_TIMER_DIS;
1687 WREG32(BUS_CNTL, tmp);
1688
1689 tmp = RREG32(BIF_SCRATCH0);
1690
1691 /* reset */
1692 radeon_pci_config_reset(rdev);
1693 mdelay(1);
1694
1695 /* BIF reset workaround. Not sure if this is needed on 6xx */
1696 tmp = SOFT_RESET_BIF;
1697 WREG32(SRBM_SOFT_RESET, tmp);
1698 mdelay(1);
1699 WREG32(SRBM_SOFT_RESET, 0);
1700
1701 /* wait for asic to come out of reset */
1702 for (i = 0; i < rdev->usec_timeout; i++) {
1703 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1704 break;
1705 udelay(1);
1706 }
1707}
1708
d3cb781e
AD		 1709int r600_asic_reset(struct radeon_device *rdev)
1710{
f13f7731
AD		 1711 u32 reset_mask;
1712
1713 reset_mask = r600_gpu_check_soft_reset(rdev);
1714
1715 if (reset_mask)
1716 r600_set_bios_scratch_engine_hung(rdev, true);
1717
de9ae744 1718 /* try soft reset */
f13f7731
AD		 1719 r600_gpu_soft_reset(rdev, reset_mask);
1720
1721 reset_mask = r600_gpu_check_soft_reset(rdev);
1722
de9ae744
AD		 1723 /* try pci config reset */
1724 if (reset_mask && radeon_hard_reset)
1725 r600_gpu_pci_config_reset(rdev);
1726
1727 reset_mask = r600_gpu_check_soft_reset(rdev);
1728
f13f7731
AD		 1729 if (!reset_mask)
1730 r600_set_bios_scratch_engine_hung(rdev, false);
1731
1732 return 0;
3ce0a23d
JG		 1733}
1734
123bc183
AD		 1735/**
1736 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1737 *
1738 * @rdev: radeon_device pointer
1739 * @ring: radeon_ring structure holding ring information
1740 *
1741 * Check if the GFX engine is locked up.
1742 * Returns true if the engine appears to be locked up, false if not.
1743 */
1744bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 1745{
123bc183
AD		 1746 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1747
1748 if (!(reset_mask & (RADEON_RESET_GFX |
1749 RADEON_RESET_COMPUTE |
1750 RADEON_RESET_CP))) {
069211e5 1751 radeon_ring_lockup_update(ring);
225758d8
JG		 1752 return false;
1753 }
1754 /* force CP activities */
7b9ef16b 1755 radeon_ring_force_activity(rdev, ring);
069211e5 1756 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 1757}
1758
416a2bd2
AD		 1759u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1760 u32 tiling_pipe_num,
1761 u32 max_rb_num,
1762 u32 total_max_rb_num,
1763 u32 disabled_rb_mask)
3ce0a23d 1764{
416a2bd2 1765 u32 rendering_pipe_num, rb_num_width, req_rb_num;
f689e3ac 1766 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
416a2bd2
AD		 1767 u32 data = 0, mask = 1 << (max_rb_num - 1);
1768 unsigned i, j;
3ce0a23d 1769
416a2bd2 1770 /* mask out the RBs that don't exist on that asic */
f689e3ac
MT		 1771 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1772 /* make sure at least one RB is available */
1773 if ((tmp & 0xff) != 0xff)
1774 disabled_rb_mask = tmp;
3ce0a23d 1775
416a2bd2
AD		 1776 rendering_pipe_num = 1 << tiling_pipe_num;
1777 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1778 BUG_ON(rendering_pipe_num < req_rb_num);
3ce0a23d 1779
416a2bd2
AD		 1780 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1781 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
3ce0a23d 1782
416a2bd2
AD		 1783 if (rdev->family <= CHIP_RV740) {
1784 /* r6xx/r7xx */
1785 rb_num_width = 2;
1786 } else {
1787 /* eg+ */
1788 rb_num_width = 4;
1789 }
3ce0a23d 1790
416a2bd2
AD		 1791 for (i = 0; i < max_rb_num; i++) {
1792 if (!(mask & disabled_rb_mask)) {
1793 for (j = 0; j < pipe_rb_ratio; j++) {
1794 data <<= rb_num_width;
1795 data |= max_rb_num - i - 1;
1796 }
1797 if (pipe_rb_remain) {
1798 data <<= rb_num_width;
1799 data |= max_rb_num - i - 1;
1800 pipe_rb_remain--;
1801 }
1802 }
1803 mask >>= 1;
3ce0a23d
JG		 1804 }
1805
416a2bd2 1806 return data;
3ce0a23d
JG		 1807}
1808
1809int r600_count_pipe_bits(uint32_t val)
1810{
ef8cf3a1 1811 return hweight32(val);
771fe6b9
JG		 1812}
1813
1109ca09 1814static void r600_gpu_init(struct radeon_device *rdev)
3ce0a23d
JG		 1815{
1816 u32 tiling_config;
1817 u32 ramcfg;
d03f5d59
AD		 1818 u32 cc_rb_backend_disable;
1819 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1820 u32 tmp;
1821 int i, j;
1822 u32 sq_config;
1823 u32 sq_gpr_resource_mgmt_1 = 0;
1824 u32 sq_gpr_resource_mgmt_2 = 0;
1825 u32 sq_thread_resource_mgmt = 0;
1826 u32 sq_stack_resource_mgmt_1 = 0;
1827 u32 sq_stack_resource_mgmt_2 = 0;
416a2bd2 1828 u32 disabled_rb_mask;
3ce0a23d 1829
416a2bd2 1830 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1831 switch (rdev->family) {
1832 case CHIP_R600:
1833 rdev->config.r600.max_pipes = 4;
1834 rdev->config.r600.max_tile_pipes = 8;
1835 rdev->config.r600.max_simds = 4;
1836 rdev->config.r600.max_backends = 4;
1837 rdev->config.r600.max_gprs = 256;
1838 rdev->config.r600.max_threads = 192;
1839 rdev->config.r600.max_stack_entries = 256;
1840 rdev->config.r600.max_hw_contexts = 8;
1841 rdev->config.r600.max_gs_threads = 16;
1842 rdev->config.r600.sx_max_export_size = 128;
1843 rdev->config.r600.sx_max_export_pos_size = 16;
1844 rdev->config.r600.sx_max_export_smx_size = 128;
1845 rdev->config.r600.sq_num_cf_insts = 2;
1846 break;
1847 case CHIP_RV630:
1848 case CHIP_RV635:
1849 rdev->config.r600.max_pipes = 2;
1850 rdev->config.r600.max_tile_pipes = 2;
1851 rdev->config.r600.max_simds = 3;
1852 rdev->config.r600.max_backends = 1;
1853 rdev->config.r600.max_gprs = 128;
1854 rdev->config.r600.max_threads = 192;
1855 rdev->config.r600.max_stack_entries = 128;
1856 rdev->config.r600.max_hw_contexts = 8;
1857 rdev->config.r600.max_gs_threads = 4;
1858 rdev->config.r600.sx_max_export_size = 128;
1859 rdev->config.r600.sx_max_export_pos_size = 16;
1860 rdev->config.r600.sx_max_export_smx_size = 128;
1861 rdev->config.r600.sq_num_cf_insts = 2;
1862 break;
1863 case CHIP_RV610:
1864 case CHIP_RV620:
1865 case CHIP_RS780:
1866 case CHIP_RS880:
1867 rdev->config.r600.max_pipes = 1;
1868 rdev->config.r600.max_tile_pipes = 1;
1869 rdev->config.r600.max_simds = 2;
1870 rdev->config.r600.max_backends = 1;
1871 rdev->config.r600.max_gprs = 128;
1872 rdev->config.r600.max_threads = 192;
1873 rdev->config.r600.max_stack_entries = 128;
1874 rdev->config.r600.max_hw_contexts = 4;
1875 rdev->config.r600.max_gs_threads = 4;
1876 rdev->config.r600.sx_max_export_size = 128;
1877 rdev->config.r600.sx_max_export_pos_size = 16;
1878 rdev->config.r600.sx_max_export_smx_size = 128;
1879 rdev->config.r600.sq_num_cf_insts = 1;
1880 break;
1881 case CHIP_RV670:
1882 rdev->config.r600.max_pipes = 4;
1883 rdev->config.r600.max_tile_pipes = 4;
1884 rdev->config.r600.max_simds = 4;
1885 rdev->config.r600.max_backends = 4;
1886 rdev->config.r600.max_gprs = 192;
1887 rdev->config.r600.max_threads = 192;
1888 rdev->config.r600.max_stack_entries = 256;
1889 rdev->config.r600.max_hw_contexts = 8;
1890 rdev->config.r600.max_gs_threads = 16;
1891 rdev->config.r600.sx_max_export_size = 128;
1892 rdev->config.r600.sx_max_export_pos_size = 16;
1893 rdev->config.r600.sx_max_export_smx_size = 128;
1894 rdev->config.r600.sq_num_cf_insts = 2;
1895 break;
1896 default:
1897 break;
1898 }
1899
1900 /* Initialize HDP */
1901 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1902 WREG32((0x2c14 + j), 0x00000000);
1903 WREG32((0x2c18 + j), 0x00000000);
1904 WREG32((0x2c1c + j), 0x00000000);
1905 WREG32((0x2c20 + j), 0x00000000);
1906 WREG32((0x2c24 + j), 0x00000000);
1907 }
1908
1909 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1910
1911 /* Setup tiling */
1912 tiling_config = 0;
1913 ramcfg = RREG32(RAMCFG);
1914 switch (rdev->config.r600.max_tile_pipes) {
1915 case 1:
1916 tiling_config |= PIPE_TILING(0);
1917 break;
1918 case 2:
1919 tiling_config |= PIPE_TILING(1);
1920 break;
1921 case 4:
1922 tiling_config |= PIPE_TILING(2);
1923 break;
1924 case 8:
1925 tiling_config |= PIPE_TILING(3);
1926 break;
1927 default:
1928 break;
1929 }
d03f5d59 1930 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1931 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1932 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1 1933 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
416a2bd2 1934
3ce0a23d
JG		 1935 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1936 if (tmp > 3) {
1937 tiling_config |= ROW_TILING(3);
1938 tiling_config |= SAMPLE_SPLIT(3);
1939 } else {
1940 tiling_config |= ROW_TILING(tmp);
1941 tiling_config |= SAMPLE_SPLIT(tmp);
1942 }
1943 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1944
1945 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
416a2bd2
AD		 1946 tmp = R6XX_MAX_BACKENDS -
1947 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1948 if (tmp < rdev->config.r600.max_backends) {
1949 rdev->config.r600.max_backends = tmp;
1950 }
1951
1952 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1953 tmp = R6XX_MAX_PIPES -
1954 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1955 if (tmp < rdev->config.r600.max_pipes) {
1956 rdev->config.r600.max_pipes = tmp;
1957 }
1958 tmp = R6XX_MAX_SIMDS -
1959 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1960 if (tmp < rdev->config.r600.max_simds) {
1961 rdev->config.r600.max_simds = tmp;
1962 }
1963
1964 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1965 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1966 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1967 R6XX_MAX_BACKENDS, disabled_rb_mask);
1968 tiling_config |= tmp << 16;
1969 rdev->config.r600.backend_map = tmp;
1970
e7aeeba6 1971 rdev->config.r600.tile_config = tiling_config;
3ce0a23d
JG		 1972 WREG32(GB_TILING_CONFIG, tiling_config);
1973 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1974 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
4d75658b 1975 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
3ce0a23d 1976
d03f5d59 1977 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1978 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1979 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1980
1981 /* Setup some CP states */
1982 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1983 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1984
1985 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1986 SYNC_WALKER | SYNC_ALIGNER));
1987 /* Setup various GPU states */
1988 if (rdev->family == CHIP_RV670)
1989 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1990
1991 tmp = RREG32(SX_DEBUG_1);
1992 tmp |= SMX_EVENT_RELEASE;
1993 if ((rdev->family > CHIP_R600))
1994 tmp |= ENABLE_NEW_SMX_ADDRESS;
1995 WREG32(SX_DEBUG_1, tmp);
1996
1997 if (((rdev->family) == CHIP_R600) ||
1998 ((rdev->family) == CHIP_RV630) ||
1999 ((rdev->family) == CHIP_RV610) ||
2000 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2001 ((rdev->family) == CHIP_RS780) ||
2002 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2003 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2004 } else {
2005 WREG32(DB_DEBUG, 0);
2006 }
2007 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2008 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2009
2010 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2011 WREG32(VGT_NUM_INSTANCES, 0);
2012
2013 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2014 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2015
2016 tmp = RREG32(SQ_MS_FIFO_SIZES);
2017 if (((rdev->family) == CHIP_RV610) ||
2018 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2019 ((rdev->family) == CHIP_RS780) ||
2020 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2021 tmp = (CACHE_FIFO_SIZE(0xa) |
2022 FETCH_FIFO_HIWATER(0xa) |
2023 DONE_FIFO_HIWATER(0xe0) |
2024 ALU_UPDATE_FIFO_HIWATER(0x8));
2025 } else if (((rdev->family) == CHIP_R600) ||
2026 ((rdev->family) == CHIP_RV630)) {
2027 tmp &= ~DONE_FIFO_HIWATER(0xff);
2028 tmp |= DONE_FIFO_HIWATER(0x4);
2029 }
2030 WREG32(SQ_MS_FIFO_SIZES, tmp);
2031
2032 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2033 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
2034 */
2035 sq_config = RREG32(SQ_CONFIG);
2036 sq_config &= ~(PS_PRIO(3) |
2037 VS_PRIO(3) |
2038 GS_PRIO(3) |
2039 ES_PRIO(3));
2040 sq_config |= (DX9_CONSTS |
2041 VC_ENABLE |
2042 PS_PRIO(0) |
2043 VS_PRIO(1) |
2044 GS_PRIO(2) |
2045 ES_PRIO(3));
2046
2047 if ((rdev->family) == CHIP_R600) {
2048 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2049 NUM_VS_GPRS(124) |
2050 NUM_CLAUSE_TEMP_GPRS(4));
2051 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2052 NUM_ES_GPRS(0));
2053 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2054 NUM_VS_THREADS(48) |
2055 NUM_GS_THREADS(4) |
2056 NUM_ES_THREADS(4));
2057 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2058 NUM_VS_STACK_ENTRIES(128));
2059 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2060 NUM_ES_STACK_ENTRIES(0));
2061 } else if (((rdev->family) == CHIP_RV610) ||
2062 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2063 ((rdev->family) == CHIP_RS780) ||
2064 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2065 /* no vertex cache */
2066 sq_config &= ~VC_ENABLE;
2067
2068 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2069 NUM_VS_GPRS(44) |
2070 NUM_CLAUSE_TEMP_GPRS(2));
2071 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2072 NUM_ES_GPRS(17));
2073 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2074 NUM_VS_THREADS(78) |
2075 NUM_GS_THREADS(4) |
2076 NUM_ES_THREADS(31));
2077 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2078 NUM_VS_STACK_ENTRIES(40));
2079 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2080 NUM_ES_STACK_ENTRIES(16));
2081 } else if (((rdev->family) == CHIP_RV630) ||
2082 ((rdev->family) == CHIP_RV635)) {
2083 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2084 NUM_VS_GPRS(44) |
2085 NUM_CLAUSE_TEMP_GPRS(2));
2086 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2087 NUM_ES_GPRS(18));
2088 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2089 NUM_VS_THREADS(78) |
2090 NUM_GS_THREADS(4) |
2091 NUM_ES_THREADS(31));
2092 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2093 NUM_VS_STACK_ENTRIES(40));
2094 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2095 NUM_ES_STACK_ENTRIES(16));
2096 } else if ((rdev->family) == CHIP_RV670) {
2097 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2098 NUM_VS_GPRS(44) |
2099 NUM_CLAUSE_TEMP_GPRS(2));
2100 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2101 NUM_ES_GPRS(17));
2102 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2103 NUM_VS_THREADS(78) |
2104 NUM_GS_THREADS(4) |
2105 NUM_ES_THREADS(31));
2106 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2107 NUM_VS_STACK_ENTRIES(64));
2108 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2109 NUM_ES_STACK_ENTRIES(64));
2110 }
2111
2112 WREG32(SQ_CONFIG, sq_config);
2113 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2114 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2115 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2116 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2117 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2118
2119 if (((rdev->family) == CHIP_RV610) ||
2120 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2121 ((rdev->family) == CHIP_RS780) ||
2122 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2123 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2124 } else {
2125 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2126 }
2127
2128 /* More default values. 2D/3D driver should adjust as needed */
2129 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2130 S1_X(0x4) | S1_Y(0xc)));
2131 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2132 S1_X(0x2) | S1_Y(0x2) |
2133 S2_X(0xa) | S2_Y(0x6) |
2134 S3_X(0x6) | S3_Y(0xa)));
2135 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2136 S1_X(0x4) | S1_Y(0xc) |
2137 S2_X(0x1) | S2_Y(0x6) |
2138 S3_X(0xa) | S3_Y(0xe)));
2139 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2140 S5_X(0x0) | S5_Y(0x0) |
2141 S6_X(0xb) | S6_Y(0x4) |
2142 S7_X(0x7) | S7_Y(0x8)));
2143
2144 WREG32(VGT_STRMOUT_EN, 0);
2145 tmp = rdev->config.r600.max_pipes * 16;
2146 switch (rdev->family) {
2147 case CHIP_RV610:
3ce0a23d 2148 case CHIP_RV620:
ee59f2b4
AD		 2149 case CHIP_RS780:
2150 case CHIP_RS880:
3ce0a23d
JG		 2151 tmp += 32;
2152 break;
2153 case CHIP_RV670:
2154 tmp += 128;
2155 break;
2156 default:
2157 break;
2158 }
2159 if (tmp > 256) {
2160 tmp = 256;
2161 }
2162 WREG32(VGT_ES_PER_GS, 128);
2163 WREG32(VGT_GS_PER_ES, tmp);
2164 WREG32(VGT_GS_PER_VS, 2);
2165 WREG32(VGT_GS_VERTEX_REUSE, 16);
2166
2167 /* more default values. 2D/3D driver should adjust as needed */
2168 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2169 WREG32(VGT_STRMOUT_EN, 0);
2170 WREG32(SX_MISC, 0);
2171 WREG32(PA_SC_MODE_CNTL, 0);
2172 WREG32(PA_SC_AA_CONFIG, 0);
2173 WREG32(PA_SC_LINE_STIPPLE, 0);
2174 WREG32(SPI_INPUT_Z, 0);
2175 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2176 WREG32(CB_COLOR7_FRAG, 0);
2177
2178 /* Clear render buffer base addresses */
2179 WREG32(CB_COLOR0_BASE, 0);
2180 WREG32(CB_COLOR1_BASE, 0);
2181 WREG32(CB_COLOR2_BASE, 0);
2182 WREG32(CB_COLOR3_BASE, 0);
2183 WREG32(CB_COLOR4_BASE, 0);
2184 WREG32(CB_COLOR5_BASE, 0);
2185 WREG32(CB_COLOR6_BASE, 0);
2186 WREG32(CB_COLOR7_BASE, 0);
2187 WREG32(CB_COLOR7_FRAG, 0);
2188
2189 switch (rdev->family) {
2190 case CHIP_RV610:
3ce0a23d 2191 case CHIP_RV620:
ee59f2b4
AD		 2192 case CHIP_RS780:
2193 case CHIP_RS880:
3ce0a23d
JG		 2194 tmp = TC_L2_SIZE(8);
2195 break;
2196 case CHIP_RV630:
2197 case CHIP_RV635:
2198 tmp = TC_L2_SIZE(4);
2199 break;
2200 case CHIP_R600:
2201 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2202 break;
2203 default:
2204 tmp = TC_L2_SIZE(0);
2205 break;
2206 }
2207 WREG32(TC_CNTL, tmp);
2208
2209 tmp = RREG32(HDP_HOST_PATH_CNTL);
2210 WREG32(HDP_HOST_PATH_CNTL, tmp);
2211
2212 tmp = RREG32(ARB_POP);
2213 tmp |= ENABLE_TC128;
2214 WREG32(ARB_POP, tmp);
2215
2216 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2217 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2218 NUM_CLIP_SEQ(3)));
2219 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
b866d133 2220 WREG32(VC_ENHANCE, 0);
3ce0a23d
JG		 2221}
2222
2223
771fe6b9
JG		 2224/*
2225 * Indirect registers accessor
2226 */
3ce0a23d
JG		 2227u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2228{
0a5b7b0b 2229 unsigned long flags;
3ce0a23d
JG		 2230 u32 r;
2231
0a5b7b0b 2232 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2233 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2234 (void)RREG32(PCIE_PORT_INDEX);
2235 r = RREG32(PCIE_PORT_DATA);
0a5b7b0b 2236 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2237 return r;
2238}
2239
2240void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2241{
0a5b7b0b
AD		 2242 unsigned long flags;
2243
2244 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2245 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2246 (void)RREG32(PCIE_PORT_INDEX);
2247 WREG32(PCIE_PORT_DATA, (v));
2248 (void)RREG32(PCIE_PORT_DATA);
0a5b7b0b 2249 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2250}
2251
3ce0a23d
JG		 2252/*
2253 * CP & Ring
2254 */
2255void r600_cp_stop(struct radeon_device *rdev)
2256{
53595338 2257 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 2258 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 2259 WREG32(SCRATCH_UMSK, 0);
4d75658b 2260 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3ce0a23d
JG		 2261}
2262
d8f60cfc 2263int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d 2264{
3ce0a23d 2265 const char *chip_name;
d8f60cfc 2266 const char *rlc_chip_name;
66229b20
AD		 2267 const char *smc_chip_name = "RV770";
2268 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
3ce0a23d
JG		 2269 char fw_name[30];
2270 int err;
2271
2272 DRM_DEBUG("\n");
2273
3ce0a23d 2274 switch (rdev->family) {
d8f60cfc
AD		 2275 case CHIP_R600:
2276 chip_name = "R600";
2277 rlc_chip_name = "R600";
2278 break;
2279 case CHIP_RV610:
2280 chip_name = "RV610";
2281 rlc_chip_name = "R600";
2282 break;
2283 case CHIP_RV630:
2284 chip_name = "RV630";
2285 rlc_chip_name = "R600";
2286 break;
2287 case CHIP_RV620:
2288 chip_name = "RV620";
2289 rlc_chip_name = "R600";
2290 break;
2291 case CHIP_RV635:
2292 chip_name = "RV635";
2293 rlc_chip_name = "R600";
2294 break;
2295 case CHIP_RV670:
2296 chip_name = "RV670";
2297 rlc_chip_name = "R600";
2298 break;
3ce0a23d 2299 case CHIP_RS780:
d8f60cfc
AD		 2300 case CHIP_RS880:
2301 chip_name = "RS780";
2302 rlc_chip_name = "R600";
2303 break;
2304 case CHIP_RV770:
2305 chip_name = "RV770";
2306 rlc_chip_name = "R700";
66229b20
AD		 2307 smc_chip_name = "RV770";
2308 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
d8f60cfc 2309 break;
3ce0a23d 2310 case CHIP_RV730:
d8f60cfc
AD		 2311 chip_name = "RV730";
2312 rlc_chip_name = "R700";
66229b20
AD		 2313 smc_chip_name = "RV730";
2314 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
d8f60cfc
AD		 2315 break;
2316 case CHIP_RV710:
2317 chip_name = "RV710";
2318 rlc_chip_name = "R700";
66229b20
AD		 2319 smc_chip_name = "RV710";
2320 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2321 break;
2322 case CHIP_RV740:
2323 chip_name = "RV730";
2324 rlc_chip_name = "R700";
2325 smc_chip_name = "RV740";
2326 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
d8f60cfc 2327 break;
fe251e2f
AD		 2328 case CHIP_CEDAR:
2329 chip_name = "CEDAR";
45f9a39b 2330 rlc_chip_name = "CEDAR";
dc50ba7f
AD		 2331 smc_chip_name = "CEDAR";
2332 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2333 break;
2334 case CHIP_REDWOOD:
2335 chip_name = "REDWOOD";
45f9a39b 2336 rlc_chip_name = "REDWOOD";
dc50ba7f
AD		 2337 smc_chip_name = "REDWOOD";
2338 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2339 break;
2340 case CHIP_JUNIPER:
2341 chip_name = "JUNIPER";
45f9a39b 2342 rlc_chip_name = "JUNIPER";
dc50ba7f
AD		 2343 smc_chip_name = "JUNIPER";
2344 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2345 break;
2346 case CHIP_CYPRESS:
2347 case CHIP_HEMLOCK:
2348 chip_name = "CYPRESS";
45f9a39b 2349 rlc_chip_name = "CYPRESS";
dc50ba7f
AD		 2350 smc_chip_name = "CYPRESS";
2351 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
fe251e2f 2352 break;
439bd6cd
AD		 2353 case CHIP_PALM:
2354 chip_name = "PALM";
2355 rlc_chip_name = "SUMO";
2356 break;
d5c5a72f
AD		 2357 case CHIP_SUMO:
2358 chip_name = "SUMO";
2359 rlc_chip_name = "SUMO";
2360 break;
2361 case CHIP_SUMO2:
2362 chip_name = "SUMO2";
2363 rlc_chip_name = "SUMO";
2364 break;
3ce0a23d
JG		 2365 default: BUG();
2366 }
2367
fe251e2f
AD		 2368 if (rdev->family >= CHIP_CEDAR) {
2369 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2370 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2371 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2372 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2373 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2374 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2375 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d 2376 } else {
138e4e16
AD		 2377 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2378 me_req_size = R600_PM4_UCODE_SIZE * 12;
2379 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2380 }
2381
d8f60cfc 2382 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2383
2384 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
0a168933 2385 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2386 if (err)
2387 goto out;
2388 if (rdev->pfp_fw->size != pfp_req_size) {
2389 printk(KERN_ERR
2390 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2391 rdev->pfp_fw->size, fw_name);
2392 err = -EINVAL;
2393 goto out;
2394 }
2395
2396 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
0a168933 2397 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2398 if (err)
2399 goto out;
2400 if (rdev->me_fw->size != me_req_size) {
2401 printk(KERN_ERR
2402 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2403 rdev->me_fw->size, fw_name);
2404 err = -EINVAL;
2405 }
d8f60cfc
AD		 2406
2407 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
0a168933 2408 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
d8f60cfc
AD		 2409 if (err)
2410 goto out;
2411 if (rdev->rlc_fw->size != rlc_req_size) {
2412 printk(KERN_ERR
2413 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2414 rdev->rlc_fw->size, fw_name);
2415 err = -EINVAL;
2416 }
2417
dc50ba7f 2418 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
66229b20 2419 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
0a168933 2420 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
8a53fa23
AD		 2421 if (err) {
2422 printk(KERN_ERR
2423 "smc: error loading firmware \"%s\"\n",
2424 fw_name);
2425 release_firmware(rdev->smc_fw);
2426 rdev->smc_fw = NULL;
d8367112 2427 err = 0;
8a53fa23 2428 } else if (rdev->smc_fw->size != smc_req_size) {
66229b20
AD		 2429 printk(KERN_ERR
2430 "smc: Bogus length %zu in firmware \"%s\"\n",
2431 rdev->smc_fw->size, fw_name);
2432 err = -EINVAL;
2433 }
2434 }
2435
3ce0a23d 2436out:
3ce0a23d
JG		 2437 if (err) {
2438 if (err != -EINVAL)
2439 printk(KERN_ERR
2440 "r600_cp: Failed to load firmware \"%s\"\n",
2441 fw_name);
2442 release_firmware(rdev->pfp_fw);
2443 rdev->pfp_fw = NULL;
2444 release_firmware(rdev->me_fw);
2445 rdev->me_fw = NULL;
d8f60cfc
AD		 2446 release_firmware(rdev->rlc_fw);
2447 rdev->rlc_fw = NULL;
66229b20
AD		 2448 release_firmware(rdev->smc_fw);
2449 rdev->smc_fw = NULL;
3ce0a23d
JG		 2450 }
2451 return err;
2452}
2453
ea31bf69
AD		 2454u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2455 struct radeon_ring *ring)
2456{
2457 u32 rptr;
2458
2459 if (rdev->wb.enabled)
2460 rptr = rdev->wb.wb[ring->rptr_offs/4];
2461 else
2462 rptr = RREG32(R600_CP_RB_RPTR);
2463
2464 return rptr;
2465}
2466
2467u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2468 struct radeon_ring *ring)
2469{
2470 u32 wptr;
2471
2472 wptr = RREG32(R600_CP_RB_WPTR);
2473
2474 return wptr;
2475}
2476
2477void r600_gfx_set_wptr(struct radeon_device *rdev,
2478 struct radeon_ring *ring)
2479{
2480 WREG32(R600_CP_RB_WPTR, ring->wptr);
2481 (void)RREG32(R600_CP_RB_WPTR);
2482}
2483
3ce0a23d
JG		 2484static int r600_cp_load_microcode(struct radeon_device *rdev)
2485{
2486 const __be32 *fw_data;
2487 int i;
2488
2489 if (!rdev->me_fw || !rdev->pfp_fw)
2490 return -EINVAL;
2491
2492 r600_cp_stop(rdev);
2493
4eace7fd
CC		 2494 WREG32(CP_RB_CNTL,
2495#ifdef __BIG_ENDIAN
2496 BUF_SWAP_32BIT |
2497#endif
2498 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2499
2500 /* Reset cp */
2501 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2502 RREG32(GRBM_SOFT_RESET);
2503 mdelay(15);
2504 WREG32(GRBM_SOFT_RESET, 0);
2505
2506 WREG32(CP_ME_RAM_WADDR, 0);
2507
2508 fw_data = (const __be32 *)rdev->me_fw->data;
2509 WREG32(CP_ME_RAM_WADDR, 0);
138e4e16 2510 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
3ce0a23d
JG		 2511 WREG32(CP_ME_RAM_DATA,
2512 be32_to_cpup(fw_data++));
2513
2514 fw_data = (const __be32 *)rdev->pfp_fw->data;
2515 WREG32(CP_PFP_UCODE_ADDR, 0);
138e4e16 2516 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
3ce0a23d
JG		 2517 WREG32(CP_PFP_UCODE_DATA,
2518 be32_to_cpup(fw_data++));
2519
2520 WREG32(CP_PFP_UCODE_ADDR, 0);
2521 WREG32(CP_ME_RAM_WADDR, 0);
2522 WREG32(CP_ME_RAM_RADDR, 0);
2523 return 0;
2524}
2525
2526int r600_cp_start(struct radeon_device *rdev)
2527{
e32eb50d 2528 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2529 int r;
2530 uint32_t cp_me;
2531
e32eb50d 2532 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2533 if (r) {
2534 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2535 return r;
2536 }
e32eb50d
CK		 2537 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2538 radeon_ring_write(ring, 0x1);
7e7b41d2 2539 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2540 radeon_ring_write(ring, 0x0);
2541 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2542 } else {
e32eb50d
CK		 2543 radeon_ring_write(ring, 0x3);
2544 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2545 }
e32eb50d
CK		 2546 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2547 radeon_ring_write(ring, 0);
2548 radeon_ring_write(ring, 0);
2549 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2550
2551 cp_me = 0xff;
2552 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2553 return 0;
2554}
2555
2556int r600_cp_resume(struct radeon_device *rdev)
2557{
e32eb50d 2558 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2559 u32 tmp;
2560 u32 rb_bufsz;
2561 int r;
2562
2563 /* Reset cp */
2564 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2565 RREG32(GRBM_SOFT_RESET);
2566 mdelay(15);
2567 WREG32(GRBM_SOFT_RESET, 0);
2568
2569 /* Set ring buffer size */
b72a8925
DV		 2570 rb_bufsz = order_base_2(ring->ring_size / 8);
2571 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2572#ifdef __BIG_ENDIAN
d6f28938 2573 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2574#endif
d6f28938 2575 WREG32(CP_RB_CNTL, tmp);
15d3332f 2576 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2577
2578 /* Set the write pointer delay */
2579 WREG32(CP_RB_WPTR_DELAY, 0);
2580
2581 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2582 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2583 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2584 ring->wptr = 0;
2585 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2586
2587 /* set the wb address whether it's enabled or not */
4eace7fd 2588 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2589 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2590 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2591 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2592
2593 if (rdev->wb.enabled)
2594 WREG32(SCRATCH_UMSK, 0xff);
2595 else {
2596 tmp |= RB_NO_UPDATE;
2597 WREG32(SCRATCH_UMSK, 0);
2598 }
2599
3ce0a23d
JG		 2600 mdelay(1);
2601 WREG32(CP_RB_CNTL, tmp);
2602
e32eb50d 2603 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2604 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2605
e32eb50d 2606 ring->rptr = RREG32(CP_RB_RPTR);
3ce0a23d
JG		 2607
2608 r600_cp_start(rdev);
e32eb50d 2609 ring->ready = true;
f712812e 2610 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3ce0a23d 2611 if (r) {
e32eb50d 2612 ring->ready = false;
3ce0a23d
JG		 2613 return r;
2614 }
2615 return 0;
2616}
2617
e32eb50d 2618void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2619{
2620 u32 rb_bufsz;
45df6803 2621 int r;
3ce0a23d
JG		 2622
2623 /* Align ring size */
b72a8925 2624 rb_bufsz = order_base_2(ring_size / 8);
3ce0a23d 2625 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2626 ring->ring_size = ring_size;
2627 ring->align_mask = 16 - 1;
45df6803 2628
89d35807
AD		 2629 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2630 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2631 if (r) {
2632 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2633 ring->rptr_save_reg = 0;
2634 }
45df6803 2635 }
3ce0a23d
JG		 2636}
2637
655efd3d
JG		 2638void r600_cp_fini(struct radeon_device *rdev)
2639{
45df6803 2640 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
655efd3d 2641 r600_cp_stop(rdev);
45df6803
CK		 2642 radeon_ring_fini(rdev, ring);
2643 radeon_scratch_free(rdev, ring->rptr_save_reg);
655efd3d
JG		 2644}
2645
3ce0a23d
JG		 2646/*
2647 * GPU scratch registers helpers function.
2648 */
2649void r600_scratch_init(struct radeon_device *rdev)
2650{
2651 int i;
2652
2653 rdev->scratch.num_reg = 7;
724c80e1 2654 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2655 for (i = 0; i < rdev->scratch.num_reg; i++) {
2656 rdev->scratch.free[i] = true;
724c80e1 2657 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2658 }
2659}
2660
e32eb50d 2661int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2662{
2663 uint32_t scratch;
2664 uint32_t tmp = 0;
8b25ed34 2665 unsigned i;
3ce0a23d
JG		 2666 int r;
2667
2668 r = radeon_scratch_get(rdev, &scratch);
2669 if (r) {
2670 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2671 return r;
2672 }
2673 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2674 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2675 if (r) {
8b25ed34 2676 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3ce0a23d
JG		 2677 radeon_scratch_free(rdev, scratch);
2678 return r;
2679 }
e32eb50d
CK		 2680 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2681 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2682 radeon_ring_write(ring, 0xDEADBEEF);
2683 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2684 for (i = 0; i < rdev->usec_timeout; i++) {
2685 tmp = RREG32(scratch);
2686 if (tmp == 0xDEADBEEF)
2687 break;
2688 DRM_UDELAY(1);
2689 }
2690 if (i < rdev->usec_timeout) {
8b25ed34 2691 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3ce0a23d 2692 } else {
bf852799 2693 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
8b25ed34 2694 ring->idx, scratch, tmp);
3ce0a23d
JG		 2695 r = -EINVAL;
2696 }
2697 radeon_scratch_free(rdev, scratch);
2698 return r;
2699}
2700
4d75658b
AD		 2701/*
2702 * CP fences/semaphores
2703 */
2704
3ce0a23d
JG		 2705void r600_fence_ring_emit(struct radeon_device *rdev,
2706 struct radeon_fence *fence)
2707{
e32eb50d 2708 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 2709
d0f8a854 2710 if (rdev->wb.use_event) {
30eb77f4 2711 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
77b1bad4 2712 /* flush read cache over gart */
e32eb50d
CK		 2713 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2714 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2715 PACKET3_VC_ACTION_ENA |
2716 PACKET3_SH_ACTION_ENA);
2717 radeon_ring_write(ring, 0xFFFFFFFF);
2718 radeon_ring_write(ring, 0);
2719 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2720 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2721 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2722 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2723 radeon_ring_write(ring, addr & 0xffffffff);
2724 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2725 radeon_ring_write(ring, fence->seq);
2726 radeon_ring_write(ring, 0);
d0f8a854 2727 } else {
77b1bad4 2728 /* flush read cache over gart */
e32eb50d
CK		 2729 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2730 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2731 PACKET3_VC_ACTION_ENA |
2732 PACKET3_SH_ACTION_ENA);
2733 radeon_ring_write(ring, 0xFFFFFFFF);
2734 radeon_ring_write(ring, 0);
2735 radeon_ring_write(ring, 10); /* poll interval */
2736 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2737 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2738 /* wait for 3D idle clean */
e32eb50d
CK		 2739 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2740 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2741 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2742 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2743 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2744 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2745 radeon_ring_write(ring, fence->seq);
d0f8a854 2746 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2747 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2748 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2749 }
3ce0a23d
JG		 2750}
2751
1654b817 2752bool r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2753 struct radeon_ring *ring,
15d3332f 2754 struct radeon_semaphore *semaphore,
7b1f2485 2755 bool emit_wait)
15d3332f
CK		 2756{
2757 uint64_t addr = semaphore->gpu_addr;
2758 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2759
0be70439
CK		 2760 if (rdev->family < CHIP_CAYMAN)
2761 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2762
e32eb50d
CK		 2763 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2764 radeon_ring_write(ring, addr & 0xffffffff);
2765 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
1654b817
CK		 2766
2767 return true;
15d3332f
CK		 2768}
2769
072b5acc
AD		 2770/**
2771 * r600_copy_cpdma - copy pages using the CP DMA engine
2772 *
2773 * @rdev: radeon_device pointer
2774 * @src_offset: src GPU address
2775 * @dst_offset: dst GPU address
2776 * @num_gpu_pages: number of GPU pages to xfer
2777 * @fence: radeon fence object
2778 *
2779 * Copy GPU paging using the CP DMA engine (r6xx+).
2780 * Used by the radeon ttm implementation to move pages if
2781 * registered as the asic copy callback.
2782 */
2783int r600_copy_cpdma(struct radeon_device *rdev,
2784 uint64_t src_offset, uint64_t dst_offset,
2785 unsigned num_gpu_pages,
2786 struct radeon_fence **fence)
2787{
2788 struct radeon_semaphore *sem = NULL;
2789 int ring_index = rdev->asic->copy.blit_ring_index;
2790 struct radeon_ring *ring = &rdev->ring[ring_index];
2791 u32 size_in_bytes, cur_size_in_bytes, tmp;
2792 int i, num_loops;
2793 int r = 0;
2794
2795 r = radeon_semaphore_create(rdev, &sem);
2796 if (r) {
2797 DRM_ERROR("radeon: moving bo (%d).\n", r);
2798 return r;
2799 }
2800
2801 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2802 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
745a39a9 2803 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
072b5acc
AD		 2804 if (r) {
2805 DRM_ERROR("radeon: moving bo (%d).\n", r);
2806 radeon_semaphore_free(rdev, &sem, NULL);
2807 return r;
2808 }
2809
1654b817
CK		 2810 radeon_semaphore_sync_to(sem, *fence);
2811 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
072b5acc 2812
745a39a9
AD		 2813 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2814 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2815 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
072b5acc
AD		 2816 for (i = 0; i < num_loops; i++) {
2817 cur_size_in_bytes = size_in_bytes;
2818 if (cur_size_in_bytes > 0x1fffff)
2819 cur_size_in_bytes = 0x1fffff;
2820 size_in_bytes -= cur_size_in_bytes;
2821 tmp = upper_32_bits(src_offset) & 0xff;
2822 if (size_in_bytes == 0)
2823 tmp |= PACKET3_CP_DMA_CP_SYNC;
2824 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2825 radeon_ring_write(ring, src_offset & 0xffffffff);
2826 radeon_ring_write(ring, tmp);
2827 radeon_ring_write(ring, dst_offset & 0xffffffff);
2828 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2829 radeon_ring_write(ring, cur_size_in_bytes);
2830 src_offset += cur_size_in_bytes;
2831 dst_offset += cur_size_in_bytes;
2832 }
2833 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2834 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2835 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2836
2837 r = radeon_fence_emit(rdev, fence, ring->idx);
2838 if (r) {
2839 radeon_ring_unlock_undo(rdev, ring);
2840 return r;
2841 }
2842
2843 radeon_ring_unlock_commit(rdev, ring);
2844 radeon_semaphore_free(rdev, &sem, *fence);
2845
2846 return r;
2847}
2848
3ce0a23d
JG		 2849int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2850 uint32_t tiling_flags, uint32_t pitch,
2851 uint32_t offset, uint32_t obj_size)
2852{
2853 /* FIXME: implement */
2854 return 0;
2855}
2856
2857void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2858{
2859 /* FIXME: implement */
2860}
2861
1109ca09 2862static int r600_startup(struct radeon_device *rdev)
3ce0a23d 2863{
4d75658b 2864 struct radeon_ring *ring;
3ce0a23d
JG		 2865 int r;
2866
9e46a48d
AD		 2867 /* enable pcie gen2 link */
2868 r600_pcie_gen2_enable(rdev);
2869
e5903d39
AD		 2870 /* scratch needs to be initialized before MC */
2871 r = r600_vram_scratch_init(rdev);
2872 if (r)
2873 return r;
2874
6fab3feb
AD		 2875 r600_mc_program(rdev);
2876
1a029b76
JG		 2877 if (rdev->flags & RADEON_IS_AGP) {
2878 r600_agp_enable(rdev);
2879 } else {
2880 r = r600_pcie_gart_enable(rdev);
2881 if (r)
2882 return r;
2883 }
3ce0a23d 2884 r600_gpu_init(rdev);
b70d6bb3 2885
724c80e1
AD		 2886 /* allocate wb buffer */
2887 r = radeon_wb_init(rdev);
2888 if (r)
2889 return r;
2890
30eb77f4
JG		 2891 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2892 if (r) {
2893 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2894 return r;
2895 }
2896
4d75658b
AD		 2897 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2898 if (r) {
2899 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2900 return r;
2901 }
2902
d8f60cfc 2903 /* Enable IRQ */
e49f3959
AH		 2904 if (!rdev->irq.installed) {
2905 r = radeon_irq_kms_init(rdev);
2906 if (r)
2907 return r;
2908 }
2909
d8f60cfc
AD		 2910 r = r600_irq_init(rdev);
2911 if (r) {
2912 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2913 radeon_irq_kms_fini(rdev);
2914 return r;
2915 }
2916 r600_irq_set(rdev);
2917
4d75658b 2918 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 2919 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2e1e6dad 2920 RADEON_CP_PACKET2);
4d75658b
AD		 2921 if (r)
2922 return r;
5596a9db 2923
4d75658b
AD		 2924 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2925 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2e1e6dad 2926 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3ce0a23d
JG		 2927 if (r)
2928 return r;
4d75658b 2929
3ce0a23d
JG		 2930 r = r600_cp_load_microcode(rdev);
2931 if (r)
2932 return r;
2933 r = r600_cp_resume(rdev);
2934 if (r)
2935 return r;
724c80e1 2936
4d75658b
AD		 2937 r = r600_dma_resume(rdev);
2938 if (r)
2939 return r;
2940
2898c348
CK		 2941 r = radeon_ib_pool_init(rdev);
2942 if (r) {
2943 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 2944 return r;
2898c348 2945 }
b15ba512 2946
d4e30ef0
AD		 2947 r = r600_audio_init(rdev);
2948 if (r) {
2949 DRM_ERROR("radeon: audio init failed\n");
2950 return r;
2951 }
2952
3ce0a23d
JG		 2953 return 0;
2954}
2955
28d52043
DA		 2956void r600_vga_set_state(struct radeon_device *rdev, bool state)
2957{
2958 uint32_t temp;
2959
2960 temp = RREG32(CONFIG_CNTL);
2961 if (state == false) {
2962 temp &= ~(1<<0);
2963 temp |= (1<<1);
2964 } else {
2965 temp &= ~(1<<1);
2966 }
2967 WREG32(CONFIG_CNTL, temp);
2968}
2969
fc30b8ef
DA		 2970int r600_resume(struct radeon_device *rdev)
2971{
2972 int r;
2973
1a029b76
JG		 2974 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2975 * posting will perform necessary task to bring back GPU into good
2976 * shape.
2977 */
fc30b8ef 2978 /* post card */
e7d40b9a 2979 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 2980
6c7bccea
AD		 2981 radeon_pm_resume(rdev);
2982
b15ba512 2983 rdev->accel_working = true;
fc30b8ef
DA		 2984 r = r600_startup(rdev);
2985 if (r) {
2986 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 2987 rdev->accel_working = false;
fc30b8ef
DA		 2988 return r;
2989 }
2990
fc30b8ef
DA		 2991 return r;
2992}
2993
3ce0a23d
JG		 2994int r600_suspend(struct radeon_device *rdev)
2995{
6c7bccea 2996 radeon_pm_suspend(rdev);
38fd2c6f 2997 r600_audio_fini(rdev);
3ce0a23d 2998 r600_cp_stop(rdev);
4d75658b 2999 r600_dma_stop(rdev);
0c45249f 3000 r600_irq_suspend(rdev);
724c80e1 3001 radeon_wb_disable(rdev);
4aac0473 3002 r600_pcie_gart_disable(rdev);
6ddddfe7 3003
3ce0a23d
JG		 3004 return 0;
3005}
3006
3007/* Plan is to move initialization in that function and use
3008 * helper function so that radeon_device_init pretty much
3009 * do nothing more than calling asic specific function. This
3010 * should also allow to remove a bunch of callback function
3011 * like vram_info.
3012 */
3013int r600_init(struct radeon_device *rdev)
771fe6b9 3014{
3ce0a23d 3015 int r;
771fe6b9 3016
3ce0a23d
JG		 3017 if (r600_debugfs_mc_info_init(rdev)) {
3018 DRM_ERROR("Failed to register debugfs file for mc !\n");
3019 }
3ce0a23d
JG		 3020 /* Read BIOS */
3021 if (!radeon_get_bios(rdev)) {
3022 if (ASIC_IS_AVIVO(rdev))
3023 return -EINVAL;
3024 }
3025 /* Must be an ATOMBIOS */
e7d40b9a
JG		 3026 if (!rdev->is_atom_bios) {
3027 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 3028 return -EINVAL;
e7d40b9a 3029 }
3ce0a23d
JG		 3030 r = radeon_atombios_init(rdev);
3031 if (r)
3032 return r;
3033 /* Post card if necessary */
fd909c37 3034 if (!radeon_card_posted(rdev)) {
72542d77
DA		 3035 if (!rdev->bios) {
3036 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3037 return -EINVAL;
3038 }
3ce0a23d
JG		 3039 DRM_INFO("GPU not posted. posting now...\n");
3040 atom_asic_init(rdev->mode_info.atom_context);
3041 }
3042 /* Initialize scratch registers */
3043 r600_scratch_init(rdev);
3044 /* Initialize surface registers */
3045 radeon_surface_init(rdev);
7433874e 3046 /* Initialize clocks */
5e6dde7e 3047 radeon_get_clock_info(rdev->ddev);
3ce0a23d 3048 /* Fence driver */
30eb77f4 3049 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 3050 if (r)
3051 return r;
700a0cc0
JG		 3052 if (rdev->flags & RADEON_IS_AGP) {
3053 r = radeon_agp_init(rdev);
3054 if (r)
3055 radeon_agp_disable(rdev);
3056 }
3ce0a23d 3057 r = r600_mc_init(rdev);
b574f251 3058 if (r)
3ce0a23d 3059 return r;
3ce0a23d 3060 /* Memory manager */
4c788679 3061 r = radeon_bo_init(rdev);
3ce0a23d
JG		 3062 if (r)
3063 return r;
d8f60cfc 3064
01ac8794
AD		 3065 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3066 r = r600_init_microcode(rdev);
3067 if (r) {
3068 DRM_ERROR("Failed to load firmware!\n");
3069 return r;
3070 }
3071 }
3072
6c7bccea
AD		 3073 /* Initialize power management */
3074 radeon_pm_init(rdev);
3075
e32eb50d
CK		 3076 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3077 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 3078
4d75658b
AD		 3079 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3080 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3081
d8f60cfc
AD		 3082 rdev->ih.ring_obj = NULL;
3083 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 3084
4aac0473
JG		 3085 r = r600_pcie_gart_init(rdev);
3086 if (r)
3087 return r;
3088
779720a3 3089 rdev->accel_working = true;
fc30b8ef 3090 r = r600_startup(rdev);
3ce0a23d 3091 if (r) {
655efd3d
JG		 3092 dev_err(rdev->dev, "disabling GPU acceleration\n");
3093 r600_cp_fini(rdev);
4d75658b 3094 r600_dma_fini(rdev);
655efd3d 3095 r600_irq_fini(rdev);
724c80e1 3096 radeon_wb_fini(rdev);
2898c348 3097 radeon_ib_pool_fini(rdev);
655efd3d 3098 radeon_irq_kms_fini(rdev);
75c81298 3099 r600_pcie_gart_fini(rdev);
733289c2 3100 rdev->accel_working = false;
3ce0a23d 3101 }
dafc3bd5 3102
3ce0a23d
JG		 3103 return 0;
3104}
3105
3106void r600_fini(struct radeon_device *rdev)
3107{
6c7bccea 3108 radeon_pm_fini(rdev);
dafc3bd5 3109 r600_audio_fini(rdev);
655efd3d 3110 r600_cp_fini(rdev);
4d75658b 3111 r600_dma_fini(rdev);
d8f60cfc 3112 r600_irq_fini(rdev);
724c80e1 3113 radeon_wb_fini(rdev);
2898c348 3114 radeon_ib_pool_fini(rdev);
d8f60cfc 3115 radeon_irq_kms_fini(rdev);
4aac0473 3116 r600_pcie_gart_fini(rdev);
16cdf04d 3117 r600_vram_scratch_fini(rdev);
655efd3d 3118 radeon_agp_fini(rdev);
3ce0a23d
JG		 3119 radeon_gem_fini(rdev);
3120 radeon_fence_driver_fini(rdev);
4c788679 3121 radeon_bo_fini(rdev);
e7d40b9a 3122 radeon_atombios_fini(rdev);
3ce0a23d
JG		 3123 kfree(rdev->bios);
3124 rdev->bios = NULL;
3ce0a23d
JG		 3125}
3126
3127
3128/*
3129 * CS stuff
3130 */
3131void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3132{
876dc9f3 3133 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 3134 u32 next_rptr;
7b1f2485 3135
45df6803 3136 if (ring->rptr_save_reg) {
89d35807 3137 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 3138 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3139 radeon_ring_write(ring, ((ring->rptr_save_reg -
3140 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3141 radeon_ring_write(ring, next_rptr);
89d35807
AD		 3142 } else if (rdev->wb.enabled) {
3143 next_rptr = ring->wptr + 5 + 4;
3144 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3145 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3146 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3147 radeon_ring_write(ring, next_rptr);
3148 radeon_ring_write(ring, 0);
45df6803
CK		 3149 }
3150
e32eb50d
CK		 3151 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3152 radeon_ring_write(ring,
4eace7fd
CC		 3153#ifdef __BIG_ENDIAN
3154 (2 << 0) |
3155#endif
3156 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 3157 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3158 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3159}
3160
f712812e 3161int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3162{
f2e39221 3163 struct radeon_ib ib;
3ce0a23d
JG		 3164 uint32_t scratch;
3165 uint32_t tmp = 0;
3166 unsigned i;
3167 int r;
3168
3169 r = radeon_scratch_get(rdev, &scratch);
3170 if (r) {
3171 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3172 return r;
3173 }
3174 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3175 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3ce0a23d
JG		 3176 if (r) {
3177 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
af026c5b 3178 goto free_scratch;
3ce0a23d 3179 }
f2e39221
JG		 3180 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3181 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3182 ib.ptr[2] = 0xDEADBEEF;
3183 ib.length_dw = 3;
4ef72566 3184 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d 3185 if (r) {
3ce0a23d 3186 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
af026c5b 3187 goto free_ib;
3ce0a23d 3188 }
f2e39221 3189 r = radeon_fence_wait(ib.fence, false);
3ce0a23d
JG		 3190 if (r) {
3191 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
af026c5b 3192 goto free_ib;
3ce0a23d
JG		 3193 }
3194 for (i = 0; i < rdev->usec_timeout; i++) {
3195 tmp = RREG32(scratch);
3196 if (tmp == 0xDEADBEEF)
3197 break;
3198 DRM_UDELAY(1);
3199 }
3200 if (i < rdev->usec_timeout) {
f2e39221 3201 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3ce0a23d 3202 } else {
4417d7f6 3203 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3204 scratch, tmp);
3205 r = -EINVAL;
3206 }
af026c5b 3207free_ib:
3ce0a23d 3208 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3209free_scratch:
3210 radeon_scratch_free(rdev, scratch);
771fe6b9
JG		 3211 return r;
3212}
3213
d8f60cfc
AD		 3214/*
3215 * Interrupts
3216 *
3217 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3218 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3219 * writing to the ring and the GPU consuming, the GPU writes to the ring
3220 * and host consumes. As the host irq handler processes interrupts, it
3221 * increments the rptr. When the rptr catches up with the wptr, all the
3222 * current interrupts have been processed.
3223 */
3224
3225void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3226{
3227 u32 rb_bufsz;
3228
3229 /* Align ring size */
b72a8925 3230 rb_bufsz = order_base_2(ring_size / 4);
d8f60cfc
AD		 3231 ring_size = (1 << rb_bufsz) * 4;
3232 rdev->ih.ring_size = ring_size;
0c45249f
JG		 3233 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3234 rdev->ih.rptr = 0;
d8f60cfc
AD		 3235}
3236
25a857fb 3237int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 3238{
3239 int r;
3240
d8f60cfc
AD		 3241 /* Allocate ring buffer */
3242 if (rdev->ih.ring_obj == NULL) {
441921d5 3243 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 3244 PAGE_SIZE, true,
4c788679 3245 RADEON_GEM_DOMAIN_GTT,
40f5cf99 3246 NULL, &rdev->ih.ring_obj);
d8f60cfc
AD		 3247 if (r) {
3248 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3249 return r;
3250 }
4c788679
JG		 3251 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3252 if (unlikely(r != 0))
3253 return r;
3254 r = radeon_bo_pin(rdev->ih.ring_obj,
3255 RADEON_GEM_DOMAIN_GTT,
3256 &rdev->ih.gpu_addr);
d8f60cfc 3257 if (r) {
4c788679 3258 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3259 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3260 return r;
3261 }
4c788679
JG		 3262 r = radeon_bo_kmap(rdev->ih.ring_obj,
3263 (void **)&rdev->ih.ring);
3264 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3265 if (r) {
3266 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3267 return r;
3268 }
3269 }
d8f60cfc
AD		 3270 return 0;
3271}
3272
25a857fb 3273void r600_ih_ring_fini(struct radeon_device *rdev)
d8f60cfc 3274{
4c788679 3275 int r;
d8f60cfc 3276 if (rdev->ih.ring_obj) {
4c788679
JG		 3277 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3278 if (likely(r == 0)) {
3279 radeon_bo_kunmap(rdev->ih.ring_obj);
3280 radeon_bo_unpin(rdev->ih.ring_obj);
3281 radeon_bo_unreserve(rdev->ih.ring_obj);
3282 }
3283 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 3284 rdev->ih.ring = NULL;
3285 rdev->ih.ring_obj = NULL;
3286 }
3287}
3288
45f9a39b 3289void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 3290{
3291
45f9a39b
AD		 3292 if ((rdev->family >= CHIP_RV770) &&
3293 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 3294 /* r7xx asics need to soft reset RLC before halting */
3295 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3296 RREG32(SRBM_SOFT_RESET);
4de833c3 3297 mdelay(15);
d8f60cfc
AD		 3298 WREG32(SRBM_SOFT_RESET, 0);
3299 RREG32(SRBM_SOFT_RESET);
3300 }
3301
3302 WREG32(RLC_CNTL, 0);
3303}
3304
3305static void r600_rlc_start(struct radeon_device *rdev)
3306{
3307 WREG32(RLC_CNTL, RLC_ENABLE);
3308}
3309
2948f5e6 3310static int r600_rlc_resume(struct radeon_device *rdev)
d8f60cfc
AD		 3311{
3312 u32 i;
3313 const __be32 *fw_data;
3314
3315 if (!rdev->rlc_fw)
3316 return -EINVAL;
3317
3318 r600_rlc_stop(rdev);
3319
d8f60cfc 3320 WREG32(RLC_HB_CNTL, 0);
c420c745 3321
2948f5e6
AD		 3322 WREG32(RLC_HB_BASE, 0);
3323 WREG32(RLC_HB_RPTR, 0);
3324 WREG32(RLC_HB_WPTR, 0);
3325 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3326 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
d8f60cfc
AD		 3327 WREG32(RLC_MC_CNTL, 0);
3328 WREG32(RLC_UCODE_CNTL, 0);
3329
3330 fw_data = (const __be32 *)rdev->rlc_fw->data;
2948f5e6 3331 if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 3332 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3333 WREG32(RLC_UCODE_ADDR, i);
3334 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3335 }
3336 } else {
138e4e16 3337 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
d8f60cfc
AD		 3338 WREG32(RLC_UCODE_ADDR, i);
3339 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3340 }
3341 }
3342 WREG32(RLC_UCODE_ADDR, 0);
3343
3344 r600_rlc_start(rdev);
3345
3346 return 0;
3347}
3348
3349static void r600_enable_interrupts(struct radeon_device *rdev)
3350{
3351 u32 ih_cntl = RREG32(IH_CNTL);
3352 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3353
3354 ih_cntl |= ENABLE_INTR;
3355 ih_rb_cntl |= IH_RB_ENABLE;
3356 WREG32(IH_CNTL, ih_cntl);
3357 WREG32(IH_RB_CNTL, ih_rb_cntl);
3358 rdev->ih.enabled = true;
3359}
3360
45f9a39b 3361void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 3362{
3363 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3364 u32 ih_cntl = RREG32(IH_CNTL);
3365
3366 ih_rb_cntl &= ~IH_RB_ENABLE;
3367 ih_cntl &= ~ENABLE_INTR;
3368 WREG32(IH_RB_CNTL, ih_rb_cntl);
3369 WREG32(IH_CNTL, ih_cntl);
3370 /* set rptr, wptr to 0 */
3371 WREG32(IH_RB_RPTR, 0);
3372 WREG32(IH_RB_WPTR, 0);
3373 rdev->ih.enabled = false;
d8f60cfc
AD		 3374 rdev->ih.rptr = 0;
3375}
3376
e0df1ac5
AD		 3377static void r600_disable_interrupt_state(struct radeon_device *rdev)
3378{
3379 u32 tmp;
3380
3555e53b 3381 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4d75658b
AD		 3382 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3383 WREG32(DMA_CNTL, tmp);
e0df1ac5
AD		 3384 WREG32(GRBM_INT_CNTL, 0);
3385 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 3386 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3387 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 3388 if (ASIC_IS_DCE3(rdev)) {
3389 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3390 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3391 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3392 WREG32(DC_HPD1_INT_CONTROL, tmp);
3393 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3394 WREG32(DC_HPD2_INT_CONTROL, tmp);
3395 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3396 WREG32(DC_HPD3_INT_CONTROL, tmp);
3397 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3398 WREG32(DC_HPD4_INT_CONTROL, tmp);
3399 if (ASIC_IS_DCE32(rdev)) {
3400 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3401 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 3402 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3403 WREG32(DC_HPD6_INT_CONTROL, tmp);
c6543a6e
RM		 3404 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3405 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3406 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3407 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f122c610
AD		 3408 } else {
3409 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3410 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3411 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3412 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3413 }
3414 } else {
3415 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3416 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3417 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3418 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 3419 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3420 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 3421 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3422 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
f122c610
AD		 3423 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3424 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3425 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3426 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3427 }
3428}
3429
d8f60cfc
AD		 3430int r600_irq_init(struct radeon_device *rdev)
3431{
3432 int ret = 0;
3433 int rb_bufsz;
3434 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3435
3436 /* allocate ring */
0c45249f 3437 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 3438 if (ret)
3439 return ret;
3440
3441 /* disable irqs */
3442 r600_disable_interrupts(rdev);
3443
3444 /* init rlc */
2948f5e6
AD		 3445 if (rdev->family >= CHIP_CEDAR)
3446 ret = evergreen_rlc_resume(rdev);
3447 else
3448 ret = r600_rlc_resume(rdev);
d8f60cfc
AD		 3449 if (ret) {
3450 r600_ih_ring_fini(rdev);
3451 return ret;
3452 }
3453
3454 /* setup interrupt control */
3455 /* set dummy read address to ring address */
3456 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3457 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3458 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3459 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3460 */
3461 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3462 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3463 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3464 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3465
3466 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
b72a8925 3467 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
d8f60cfc
AD		 3468
3469 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3470 IH_WPTR_OVERFLOW_CLEAR |
3471 (rb_bufsz << 1));
724c80e1
AD		 3472
3473 if (rdev->wb.enabled)
3474 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3475
3476 /* set the writeback address whether it's enabled or not */
3477 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3478 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3479
3480 WREG32(IH_RB_CNTL, ih_rb_cntl);
3481
3482 /* set rptr, wptr to 0 */
3483 WREG32(IH_RB_RPTR, 0);
3484 WREG32(IH_RB_WPTR, 0);
3485
3486 /* Default settings for IH_CNTL (disabled at first) */
3487 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3488 /* RPTR_REARM only works if msi's are enabled */
3489 if (rdev->msi_enabled)
3490 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3491 WREG32(IH_CNTL, ih_cntl);
3492
3493 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3494 if (rdev->family >= CHIP_CEDAR)
3495 evergreen_disable_interrupt_state(rdev);
3496 else
3497 r600_disable_interrupt_state(rdev);
d8f60cfc 3498
2099810f
DA		 3499 /* at this point everything should be setup correctly to enable master */
3500 pci_set_master(rdev->pdev);
3501
d8f60cfc
AD		 3502 /* enable irqs */
3503 r600_enable_interrupts(rdev);
3504
3505 return ret;
3506}
3507
0c45249f 3508void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3509{
45f9a39b 3510 r600_irq_disable(rdev);
d8f60cfc 3511 r600_rlc_stop(rdev);
0c45249f
JG		 3512}
3513
3514void r600_irq_fini(struct radeon_device *rdev)
3515{
3516 r600_irq_suspend(rdev);
d8f60cfc
AD		 3517 r600_ih_ring_fini(rdev);
3518}
3519
3520int r600_irq_set(struct radeon_device *rdev)
3521{
e0df1ac5
AD		 3522 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3523 u32 mode_int = 0;
3524 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3525 u32 grbm_int_cntl = 0;
f122c610 3526 u32 hdmi0, hdmi1;
6f34be50 3527 u32 d1grph = 0, d2grph = 0;
4d75658b 3528 u32 dma_cntl;
4a6369e9 3529 u32 thermal_int = 0;
d8f60cfc 3530
003e69f9 3531 if (!rdev->irq.installed) {
fce7d61b 3532 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3533 return -EINVAL;
3534 }
d8f60cfc 3535 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3536 if (!rdev->ih.enabled) {
3537 r600_disable_interrupts(rdev);
3538 /* force the active interrupt state to all disabled */
3539 r600_disable_interrupt_state(rdev);
d8f60cfc 3540 return 0;
79c2bbc5 3541 }
d8f60cfc 3542
e0df1ac5
AD		 3543 if (ASIC_IS_DCE3(rdev)) {
3544 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3545 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3546 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3547 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3548 if (ASIC_IS_DCE32(rdev)) {
3549 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3550 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
c6543a6e
RM		 3551 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3552 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
f122c610
AD		 3553 } else {
3554 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3555 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3556 }
3557 } else {
3558 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3559 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3560 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
f122c610
AD		 3561 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3562 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5 3563 }
4a6369e9 3564
4d75658b 3565 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
e0df1ac5 3566
4a6369e9
AD		 3567 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3568 thermal_int = RREG32(CG_THERMAL_INT) &
3569 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
66229b20
AD		 3570 } else if (rdev->family >= CHIP_RV770) {
3571 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3572 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3573 }
3574 if (rdev->irq.dpm_thermal) {
3575 DRM_DEBUG("dpm thermal\n");
3576 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
4a6369e9
AD		 3577 }
3578
736fc37f 3579 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
d8f60cfc
AD		 3580 DRM_DEBUG("r600_irq_set: sw int\n");
3581 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3582 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3583 }
4d75658b
AD		 3584
3585 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3586 DRM_DEBUG("r600_irq_set: sw int dma\n");
3587 dma_cntl |= TRAP_ENABLE;
3588 }
3589
6f34be50 3590 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3591 atomic_read(&rdev->irq.pflip[0])) {
d8f60cfc
AD		 3592 DRM_DEBUG("r600_irq_set: vblank 0\n");
3593 mode_int |= D1MODE_VBLANK_INT_MASK;
3594 }
6f34be50 3595 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3596 atomic_read(&rdev->irq.pflip[1])) {
d8f60cfc
AD		 3597 DRM_DEBUG("r600_irq_set: vblank 1\n");
3598 mode_int |= D2MODE_VBLANK_INT_MASK;
3599 }
e0df1ac5
AD		 3600 if (rdev->irq.hpd[0]) {
3601 DRM_DEBUG("r600_irq_set: hpd 1\n");
3602 hpd1 |= DC_HPDx_INT_EN;
3603 }
3604 if (rdev->irq.hpd[1]) {
3605 DRM_DEBUG("r600_irq_set: hpd 2\n");
3606 hpd2 |= DC_HPDx_INT_EN;
3607 }
3608 if (rdev->irq.hpd[2]) {
3609 DRM_DEBUG("r600_irq_set: hpd 3\n");
3610 hpd3 |= DC_HPDx_INT_EN;
3611 }
3612 if (rdev->irq.hpd[3]) {
3613 DRM_DEBUG("r600_irq_set: hpd 4\n");
3614 hpd4 |= DC_HPDx_INT_EN;
3615 }
3616 if (rdev->irq.hpd[4]) {
3617 DRM_DEBUG("r600_irq_set: hpd 5\n");
3618 hpd5 |= DC_HPDx_INT_EN;
3619 }
3620 if (rdev->irq.hpd[5]) {
3621 DRM_DEBUG("r600_irq_set: hpd 6\n");
3622 hpd6 |= DC_HPDx_INT_EN;
3623 }
f122c610
AD		 3624 if (rdev->irq.afmt[0]) {
3625 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3626 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3627 }
f122c610
AD		 3628 if (rdev->irq.afmt[1]) {
3629 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3630 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3631 }
d8f60cfc
AD		 3632
3633 WREG32(CP_INT_CNTL, cp_int_cntl);
4d75658b 3634 WREG32(DMA_CNTL, dma_cntl);
d8f60cfc 3635 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3636 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3637 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3638 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
e0df1ac5
AD		 3639 if (ASIC_IS_DCE3(rdev)) {
3640 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3641 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3642 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3643 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3644 if (ASIC_IS_DCE32(rdev)) {
3645 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3646 WREG32(DC_HPD6_INT_CONTROL, hpd6);
c6543a6e
RM		 3647 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3648 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
f122c610
AD		 3649 } else {
3650 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3651 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5
AD		 3652 }
3653 } else {
3654 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3655 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3656 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
f122c610
AD		 3657 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3658 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5 3659 }
4a6369e9
AD		 3660 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3661 WREG32(CG_THERMAL_INT, thermal_int);
66229b20
AD		 3662 } else if (rdev->family >= CHIP_RV770) {
3663 WREG32(RV770_CG_THERMAL_INT, thermal_int);
4a6369e9 3664 }
d8f60cfc
AD		 3665
3666 return 0;
3667}
3668
ce580fab 3669static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3670{
e0df1ac5
AD		 3671 u32 tmp;
3672
3673 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3674 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3675 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3676 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
f122c610 3677 if (ASIC_IS_DCE32(rdev)) {
c6543a6e
RM		 3678 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3679 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
f122c610
AD		 3680 } else {
3681 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3682 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3683 }
e0df1ac5 3684 } else {
6f34be50
AD		 3685 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3686 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3687 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
f122c610
AD		 3688 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3689 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
6f34be50
AD		 3690 }
3691 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3692 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3693
3694 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3695 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3696 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3697 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3698 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3699 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3700 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3701 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3702 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3703 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3704 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3705 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3706 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3707 if (ASIC_IS_DCE3(rdev)) {
3708 tmp = RREG32(DC_HPD1_INT_CONTROL);
3709 tmp |= DC_HPDx_INT_ACK;
3710 WREG32(DC_HPD1_INT_CONTROL, tmp);
3711 } else {
3712 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3713 tmp |= DC_HPDx_INT_ACK;
3714 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3715 }
3716 }
6f34be50 3717 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3718 if (ASIC_IS_DCE3(rdev)) {
3719 tmp = RREG32(DC_HPD2_INT_CONTROL);
3720 tmp |= DC_HPDx_INT_ACK;
3721 WREG32(DC_HPD2_INT_CONTROL, tmp);
3722 } else {
3723 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3724 tmp |= DC_HPDx_INT_ACK;
3725 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3726 }
3727 }
6f34be50 3728 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3729 if (ASIC_IS_DCE3(rdev)) {
3730 tmp = RREG32(DC_HPD3_INT_CONTROL);
3731 tmp |= DC_HPDx_INT_ACK;
3732 WREG32(DC_HPD3_INT_CONTROL, tmp);
3733 } else {
3734 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3735 tmp |= DC_HPDx_INT_ACK;
3736 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3737 }
3738 }
6f34be50 3739 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3740 tmp = RREG32(DC_HPD4_INT_CONTROL);
3741 tmp |= DC_HPDx_INT_ACK;
3742 WREG32(DC_HPD4_INT_CONTROL, tmp);
3743 }
3744 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3745 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3746 tmp = RREG32(DC_HPD5_INT_CONTROL);
3747 tmp |= DC_HPDx_INT_ACK;
3748 WREG32(DC_HPD5_INT_CONTROL, tmp);
3749 }
6f34be50 3750 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3751 tmp = RREG32(DC_HPD5_INT_CONTROL);
3752 tmp |= DC_HPDx_INT_ACK;
3753 WREG32(DC_HPD6_INT_CONTROL, tmp);
3754 }
f122c610 3755 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3756 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
f122c610 3757 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3758 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
f122c610
AD		 3759 }
3760 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3761 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
f122c610 3762 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3763 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f2594933
CK		 3764 }
3765 } else {
f122c610
AD		 3766 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3767 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3768 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3769 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3770 }
3771 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3772 if (ASIC_IS_DCE3(rdev)) {
3773 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3774 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3775 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3776 } else {
3777 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3778 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3779 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3780 }
f2594933
CK		 3781 }
3782 }
d8f60cfc
AD		 3783}
3784
3785void r600_irq_disable(struct radeon_device *rdev)
3786{
d8f60cfc
AD		 3787 r600_disable_interrupts(rdev);
3788 /* Wait and acknowledge irq */
3789 mdelay(1);
6f34be50 3790 r600_irq_ack(rdev);
e0df1ac5 3791 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3792}
3793
ce580fab 3794static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 3795{
3796 u32 wptr, tmp;
3ce0a23d 3797
724c80e1 3798 if (rdev->wb.enabled)
204ae24d 3799 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3800 else
3801 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3802
d8f60cfc 3803 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3804 /* When a ring buffer overflow happen start parsing interrupt
3805 * from the last not overwritten vector (wptr + 16). Hopefully
3806 * this should allow us to catchup.
3807 */
3808 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3809 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3810 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3811 tmp = RREG32(IH_RB_CNTL);
3812 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3813 WREG32(IH_RB_CNTL, tmp);
3814 }
0c45249f 3815 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3816}
3ce0a23d 3817
d8f60cfc
AD		 3818/* r600 IV Ring
3819 * Each IV ring entry is 128 bits:
3820 * [7:0] - interrupt source id
3821 * [31:8] - reserved
3822 * [59:32] - interrupt source data
3823 * [127:60] - reserved
3824 *
3825 * The basic interrupt vector entries
3826 * are decoded as follows:
3827 * src_id src_data description
3828 * 1 0 D1 Vblank
3829 * 1 1 D1 Vline
3830 * 5 0 D2 Vblank
3831 * 5 1 D2 Vline
3832 * 19 0 FP Hot plug detection A
3833 * 19 1 FP Hot plug detection B
3834 * 19 2 DAC A auto-detection
3835 * 19 3 DAC B auto-detection
f2594933
CK		 3836 * 21 4 HDMI block A
3837 * 21 5 HDMI block B
d8f60cfc
AD		 3838 * 176 - CP_INT RB
3839 * 177 - CP_INT IB1
3840 * 178 - CP_INT IB2
3841 * 181 - EOP Interrupt
3842 * 233 - GUI Idle
3843 *
3844 * Note, these are based on r600 and may need to be
3845 * adjusted or added to on newer asics
3846 */
3847
3848int r600_irq_process(struct radeon_device *rdev)
3849{
682f1a54
DA		 3850 u32 wptr;
3851 u32 rptr;
d8f60cfc 3852 u32 src_id, src_data;
6f34be50 3853 u32 ring_index;
d4877cf2 3854 bool queue_hotplug = false;
f122c610 3855 bool queue_hdmi = false;
4a6369e9 3856 bool queue_thermal = false;
d8f60cfc 3857
682f1a54 3858 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3859 return IRQ_NONE;
d8f60cfc 3860
f6a56939
BH		 3861 /* No MSIs, need a dummy read to flush PCI DMAs */
3862 if (!rdev->msi_enabled)
3863 RREG32(IH_RB_WPTR);
3864
682f1a54 3865 wptr = r600_get_ih_wptr(rdev);
d8f60cfc 3866
c20dc369
CK		 3867restart_ih:
3868 /* is somebody else already processing irqs? */
3869 if (atomic_xchg(&rdev->ih.lock, 1))
d8f60cfc 3870 return IRQ_NONE;
d8f60cfc 3871
c20dc369
CK		 3872 rptr = rdev->ih.rptr;
3873 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3874
964f6645
BH		 3875 /* Order reading of wptr vs. reading of IH ring data */
3876 rmb();
3877
d8f60cfc 3878 /* display interrupts */
6f34be50 3879 r600_irq_ack(rdev);
d8f60cfc 3880
d8f60cfc
AD		 3881 while (rptr != wptr) {
3882 /* wptr/rptr are in bytes! */
3883 ring_index = rptr / 4;
4eace7fd
CC		 3884 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3885 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 3886
3887 switch (src_id) {
3888 case 1: /* D1 vblank/vline */
3889 switch (src_data) {
3890 case 0: /* D1 vblank */
6f34be50 3891 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3892 if (rdev->irq.crtc_vblank_int[0]) {
3893 drm_handle_vblank(rdev->ddev, 0);
3894 rdev->pm.vblank_sync = true;
3895 wake_up(&rdev->irq.vblank_queue);
3896 }
736fc37f 3897 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 3898 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3899 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3900 DRM_DEBUG("IH: D1 vblank\n");
3901 }
3902 break;
3903 case 1: /* D1 vline */
6f34be50
AD		 3904 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3905 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3906 DRM_DEBUG("IH: D1 vline\n");
3907 }
3908 break;
3909 default:
b042589c 3910 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3911 break;
3912 }
3913 break;
3914 case 5: /* D2 vblank/vline */
3915 switch (src_data) {
3916 case 0: /* D2 vblank */
6f34be50 3917 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3918 if (rdev->irq.crtc_vblank_int[1]) {
3919 drm_handle_vblank(rdev->ddev, 1);
3920 rdev->pm.vblank_sync = true;
3921 wake_up(&rdev->irq.vblank_queue);
3922 }
736fc37f 3923 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 3924 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3925 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3926 DRM_DEBUG("IH: D2 vblank\n");
3927 }
3928 break;
3929 case 1: /* D1 vline */
6f34be50
AD		 3930 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3931 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3932 DRM_DEBUG("IH: D2 vline\n");
3933 }
3934 break;
3935 default:
b042589c 3936 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3937 break;
3938 }
3939 break;
e0df1ac5
AD		 3940 case 19: /* HPD/DAC hotplug */
3941 switch (src_data) {
3942 case 0:
6f34be50
AD		 3943 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3944 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3945 queue_hotplug = true;
3946 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3947 }
3948 break;
3949 case 1:
6f34be50
AD		 3950 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3951 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3952 queue_hotplug = true;
3953 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3954 }
3955 break;
3956 case 4:
6f34be50
AD		 3957 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3958 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3959 queue_hotplug = true;
3960 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3961 }
3962 break;
3963 case 5:
6f34be50
AD		 3964 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3965 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3966 queue_hotplug = true;
3967 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3968 }
3969 break;
3970 case 10:
6f34be50
AD		 3971 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3972 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3973 queue_hotplug = true;
3974 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3975 }
3976 break;
3977 case 12:
6f34be50
AD		 3978 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3979 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3980 queue_hotplug = true;
3981 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3982 }
3983 break;
3984 default:
b042589c 3985 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3986 break;
3987 }
3988 break;
f122c610
AD		 3989 case 21: /* hdmi */
3990 switch (src_data) {
3991 case 4:
3992 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3993 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3994 queue_hdmi = true;
3995 DRM_DEBUG("IH: HDMI0\n");
3996 }
3997 break;
3998 case 5:
3999 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4000 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4001 queue_hdmi = true;
4002 DRM_DEBUG("IH: HDMI1\n");
4003 }
4004 break;
4005 default:
4006 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4007 break;
4008 }
f2594933 4009 break;
d8f60cfc
AD		 4010 case 176: /* CP_INT in ring buffer */
4011 case 177: /* CP_INT in IB1 */
4012 case 178: /* CP_INT in IB2 */
4013 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 4014 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 4015 break;
4016 case 181: /* CP EOP event */
4017 DRM_DEBUG("IH: CP EOP\n");
7465280c 4018 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 4019 break;
4d75658b
AD		 4020 case 224: /* DMA trap event */
4021 DRM_DEBUG("IH: DMA trap\n");
4022 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4023 break;
4a6369e9
AD		 4024 case 230: /* thermal low to high */
4025 DRM_DEBUG("IH: thermal low to high\n");
4026 rdev->pm.dpm.thermal.high_to_low = false;
4027 queue_thermal = true;
4028 break;
4029 case 231: /* thermal high to low */
4030 DRM_DEBUG("IH: thermal high to low\n");
4031 rdev->pm.dpm.thermal.high_to_low = true;
4032 queue_thermal = true;
4033 break;
2031f77c 4034 case 233: /* GUI IDLE */
303c805c 4035 DRM_DEBUG("IH: GUI idle\n");
2031f77c 4036 break;
d8f60cfc 4037 default:
b042589c 4038 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4039 break;
4040 }
4041
4042 /* wptr/rptr are in bytes! */
0c45249f
JG		 4043 rptr += 16;
4044 rptr &= rdev->ih.ptr_mask;
d8f60cfc 4045 }
d4877cf2 4046 if (queue_hotplug)
32c87fca 4047 schedule_work(&rdev->hotplug_work);
f122c610
AD		 4048 if (queue_hdmi)
4049 schedule_work(&rdev->audio_work);
4a6369e9
AD		 4050 if (queue_thermal && rdev->pm.dpm_enabled)
4051 schedule_work(&rdev->pm.dpm.thermal.work);
d8f60cfc
AD		 4052 rdev->ih.rptr = rptr;
4053 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4054 atomic_set(&rdev->ih.lock, 0);
4055
4056 /* make sure wptr hasn't changed while processing */
4057 wptr = r600_get_ih_wptr(rdev);
4058 if (wptr != rptr)
4059 goto restart_ih;
4060
d8f60cfc
AD		 4061 return IRQ_HANDLED;
4062}
3ce0a23d
JG		 4063
4064/*
4065 * Debugfs info
4066 */
4067#if defined(CONFIG_DEBUG_FS)
4068
3ce0a23d
JG		 4069static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4070{
4071 struct drm_info_node *node = (struct drm_info_node *) m->private;
4072 struct drm_device *dev = node->minor->dev;
4073 struct radeon_device *rdev = dev->dev_private;
4074
4075 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4076 DREG32_SYS(m, rdev, VM_L2_STATUS);
4077 return 0;
4078}
4079
4080static struct drm_info_list r600_mc_info_list[] = {
4081 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 4082};
4083#endif
4084
4085int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4086{
4087#if defined(CONFIG_DEBUG_FS)
4088 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4089#else
4090 return 0;
4091#endif
771fe6b9 4092}
062b389c
JG		 4093
4094/**
4095 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4096 * rdev: radeon device structure
4097 * bo: buffer object struct which userspace is waiting for idle
4098 *
4099 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4100 * through ring buffer, this leads to corruption in rendering, see
4101 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4102 * directly perform HDP flush by writing register through MMIO.
4103 */
4104void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4105{
812d0469 4106 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 4107 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4108 * This seems to cause problems on some AGP cards. Just use the old
4109 * method for them.
812d0469 4110 */
e488459a 4111 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 4112 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 4113 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 4114 u32 tmp;
4115
4116 WREG32(HDP_DEBUG1, 0);
4117 tmp = readl((void __iomem *)ptr);
4118 } else
4119 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 4120}
3313e3d4
AD		 4121
4122void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4123{
d5445a17 4124 u32 link_width_cntl, mask;
3313e3d4
AD		 4125
4126 if (rdev->flags & RADEON_IS_IGP)
4127 return;
4128
4129 if (!(rdev->flags & RADEON_IS_PCIE))
4130 return;
4131
4132 /* x2 cards have a special sequence */
4133 if (ASIC_IS_X2(rdev))
4134 return;
4135
d5445a17 4136 radeon_gui_idle(rdev);
3313e3d4
AD		 4137
4138 switch (lanes) {
4139 case 0:
4140 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4141 break;
4142 case 1:
4143 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4144 break;
4145 case 2:
4146 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4147 break;
4148 case 4:
4149 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4150 break;
4151 case 8:
4152 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4153 break;
4154 case 12:
d5445a17 4155 /* not actually supported */
3313e3d4
AD		 4156 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4157 break;
4158 case 16:
3313e3d4
AD		 4159 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4160 break;
d5445a17
AD		 4161 default:
4162 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4163 return;
3313e3d4
AD		 4164 }
4165
492d2b61 4166 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
d5445a17
AD		 4167 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4168 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4169 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4170 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3313e3d4 4171
492d2b61 4172 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3313e3d4
AD		 4173}
4174
4175int r600_get_pcie_lanes(struct radeon_device *rdev)
4176{
4177 u32 link_width_cntl;
4178
4179 if (rdev->flags & RADEON_IS_IGP)
4180 return 0;
4181
4182 if (!(rdev->flags & RADEON_IS_PCIE))
4183 return 0;
4184
4185 /* x2 cards have a special sequence */
4186 if (ASIC_IS_X2(rdev))
4187 return 0;
4188
d5445a17 4189 radeon_gui_idle(rdev);
3313e3d4 4190
492d2b61 4191 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3313e3d4
AD		 4192
4193 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3313e3d4
AD		 4194 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4195 return 1;
4196 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4197 return 2;
4198 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4199 return 4;
4200 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4201 return 8;
d5445a17
AD		 4202 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4203 /* not actually supported */
4204 return 12;
4205 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3313e3d4
AD		 4206 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4207 default:
4208 return 16;
4209 }
4210}
4211
9e46a48d
AD		 4212static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4213{
4214 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4215 u16 link_cntl2;
4216
d42dd579
AD		 4217 if (radeon_pcie_gen2 == 0)
4218 return;
4219
9e46a48d
AD		 4220 if (rdev->flags & RADEON_IS_IGP)
4221 return;
4222
4223 if (!(rdev->flags & RADEON_IS_PCIE))
4224 return;
4225
4226 /* x2 cards have a special sequence */
4227 if (ASIC_IS_X2(rdev))
4228 return;
4229
4230 /* only RV6xx+ chips are supported */
4231 if (rdev->family <= CHIP_R600)
4232 return;
4233
7e0e4196
KSS		 4234 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4235 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
197bbb3d
DA		 4236 return;
4237
492d2b61 4238 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3691feea
AD		 4239 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4240 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4241 return;
4242 }
4243
197bbb3d
DA		 4244 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4245
9e46a48d
AD		 4246 /* 55 nm r6xx asics */
4247 if ((rdev->family == CHIP_RV670) ||
4248 (rdev->family == CHIP_RV620) ||
4249 (rdev->family == CHIP_RV635)) {
4250 /* advertise upconfig capability */
492d2b61 4251 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d 4252 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61
AD		 4253 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4254 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4255 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4256 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4257 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4258 LC_RECONFIG_ARC_MISSING_ESCAPE);
4259 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
492d2b61 4260 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4261 } else {
4262 link_width_cntl |= LC_UPCONFIGURE_DIS;
492d2b61 4263 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4264 }
4265 }
4266
492d2b61 4267 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d
AD		 4268 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4269 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4270
4271 /* 55 nm r6xx asics */
4272 if ((rdev->family == CHIP_RV670) ||
4273 (rdev->family == CHIP_RV620) ||
4274 (rdev->family == CHIP_RV635)) {
4275 WREG32(MM_CFGREGS_CNTL, 0x8);
4276 link_cntl2 = RREG32(0x4088);
4277 WREG32(MM_CFGREGS_CNTL, 0);
4278 /* not supported yet */
4279 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4280 return;
4281 }
4282
4283 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4284 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4285 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4286 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4287 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
492d2b61 4288 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4289
4290 tmp = RREG32(0x541c);
4291 WREG32(0x541c, tmp | 0x8);
4292 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4293 link_cntl2 = RREG16(0x4088);
4294 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4295 link_cntl2 |= 0x2;
4296 WREG16(0x4088, link_cntl2);
4297 WREG32(MM_CFGREGS_CNTL, 0);
4298
4299 if ((rdev->family == CHIP_RV670) ||
4300 (rdev->family == CHIP_RV620) ||
4301 (rdev->family == CHIP_RV635)) {
492d2b61 4302 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
9e46a48d 4303 training_cntl &= ~LC_POINT_7_PLUS_EN;
492d2b61 4304 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
9e46a48d 4305 } else {
492d2b61 4306 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4307 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
492d2b61 4308 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4309 }
4310
492d2b61 4311 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4312 speed_cntl |= LC_GEN2_EN_STRAP;
492d2b61 4313 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4314
4315 } else {
492d2b61 4316 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4317 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4318 if (1)
4319 link_width_cntl |= LC_UPCONFIGURE_DIS;
4320 else
4321 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 4322 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4323 }
4324}
6759a0a7
MO		 4325
4326/**
d0418894 4327 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
6759a0a7
MO		 4328 *
4329 * @rdev: radeon_device pointer
4330 *
4331 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4332 * Returns the 64 bit clock counter snapshot.
4333 */
d0418894 4334uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
6759a0a7
MO		 4335{
4336 uint64_t clock;
4337
4338 mutex_lock(&rdev->gpu_clock_mutex);
4339 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4340 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4341 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4342 mutex_unlock(&rdev->gpu_clock_mutex);
4343 return clock;
4344}
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