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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
3ce0a23d JG |
29 | #include <linux/seq_file.h> |
30 | #include <linux/firmware.h> | |
e0cd3608 | 31 | #include <linux/module.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/radeon_drm.h> | |
771fe6b9 | 34 | #include "radeon.h" |
e6990375 | 35 | #include "radeon_asic.h" |
3ce0a23d | 36 | #include "radeon_mode.h" |
3ce0a23d | 37 | #include "r600d.h" |
3ce0a23d | 38 | #include "atom.h" |
d39c3b89 | 39 | #include "avivod.h" |
138e4e16 | 40 | #include "radeon_ucode.h" |
3ce0a23d JG |
41 | |
42 | /* Firmware Names */ | |
43 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
44 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
45 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
46 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
47 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
48 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
49 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
50 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
51 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
52 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
53 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
54 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
55 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
56 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
57 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
66229b20 | 59 | MODULE_FIRMWARE("radeon/RV770_smc.bin"); |
3ce0a23d JG |
60 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); |
61 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
66229b20 AD |
62 | MODULE_FIRMWARE("radeon/RV730_smc.bin"); |
63 | MODULE_FIRMWARE("radeon/RV740_smc.bin"); | |
3ce0a23d JG |
64 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); |
65 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
66229b20 | 66 | MODULE_FIRMWARE("radeon/RV710_smc.bin"); |
d8f60cfc AD |
67 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
68 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); | |
fe251e2f AD |
69 | MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); |
70 | MODULE_FIRMWARE("radeon/CEDAR_me.bin"); | |
45f9a39b | 71 | MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); |
dc50ba7f | 72 | MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); |
fe251e2f AD |
73 | MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); |
74 | MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); | |
45f9a39b | 75 | MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); |
dc50ba7f | 76 | MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); |
fe251e2f AD |
77 | MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); |
78 | MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); | |
45f9a39b | 79 | MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); |
dc50ba7f | 80 | MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); |
a7433742 | 81 | MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); |
fe251e2f | 82 | MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); |
45f9a39b | 83 | MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); |
dc50ba7f | 84 | MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); |
439bd6cd AD |
85 | MODULE_FIRMWARE("radeon/PALM_pfp.bin"); |
86 | MODULE_FIRMWARE("radeon/PALM_me.bin"); | |
87 | MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); | |
d5c5a72f AD |
88 | MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); |
89 | MODULE_FIRMWARE("radeon/SUMO_me.bin"); | |
90 | MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); | |
91 | MODULE_FIRMWARE("radeon/SUMO2_me.bin"); | |
3ce0a23d | 92 | |
f13f7731 AD |
93 | static const u32 crtc_offsets[2] = |
94 | { | |
95 | 0, | |
96 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL | |
97 | }; | |
98 | ||
3ce0a23d | 99 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
771fe6b9 | 100 | |
1a029b76 | 101 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
771fe6b9 | 102 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1109ca09 | 103 | static void r600_gpu_init(struct radeon_device *rdev); |
3ce0a23d | 104 | void r600_fini(struct radeon_device *rdev); |
45f9a39b | 105 | void r600_irq_disable(struct radeon_device *rdev); |
9e46a48d | 106 | static void r600_pcie_gen2_enable(struct radeon_device *rdev); |
2948f5e6 | 107 | extern int evergreen_rlc_resume(struct radeon_device *rdev); |
de9ae744 | 108 | extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); |
771fe6b9 | 109 | |
454d2e2a AD |
110 | /** |
111 | * r600_get_xclk - get the xclk | |
112 | * | |
113 | * @rdev: radeon_device pointer | |
114 | * | |
115 | * Returns the reference clock used by the gfx engine | |
116 | * (r6xx, IGPs, APUs). | |
117 | */ | |
118 | u32 r600_get_xclk(struct radeon_device *rdev) | |
119 | { | |
120 | return rdev->clock.spll.reference_freq; | |
121 | } | |
122 | ||
1b9ba70a AD |
123 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) |
124 | { | |
125 | return 0; | |
126 | } | |
127 | ||
134b480f AD |
128 | void dce3_program_fmt(struct drm_encoder *encoder) |
129 | { | |
130 | struct drm_device *dev = encoder->dev; | |
131 | struct radeon_device *rdev = dev->dev_private; | |
132 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
133 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
134 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
135 | int bpc = 0; | |
136 | u32 tmp = 0; | |
6214bb74 | 137 | enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; |
134b480f | 138 | |
6214bb74 AD |
139 | if (connector) { |
140 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
134b480f | 141 | bpc = radeon_get_monitor_bpc(connector); |
6214bb74 AD |
142 | dither = radeon_connector->dither; |
143 | } | |
134b480f AD |
144 | |
145 | /* LVDS FMT is set up by atom */ | |
146 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
147 | return; | |
148 | ||
149 | /* not needed for analog */ | |
150 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || | |
151 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) | |
152 | return; | |
153 | ||
154 | if (bpc == 0) | |
155 | return; | |
156 | ||
157 | switch (bpc) { | |
158 | case 6: | |
6214bb74 | 159 | if (dither == RADEON_FMT_DITHER_ENABLE) |
134b480f AD |
160 | /* XXX sort out optimal dither settings */ |
161 | tmp |= FMT_SPATIAL_DITHER_EN; | |
162 | else | |
163 | tmp |= FMT_TRUNCATE_EN; | |
164 | break; | |
165 | case 8: | |
6214bb74 | 166 | if (dither == RADEON_FMT_DITHER_ENABLE) |
134b480f AD |
167 | /* XXX sort out optimal dither settings */ |
168 | tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); | |
169 | else | |
170 | tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); | |
171 | break; | |
172 | case 10: | |
173 | default: | |
174 | /* not needed */ | |
175 | break; | |
176 | } | |
177 | ||
178 | WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); | |
179 | } | |
180 | ||
21a8122a | 181 | /* get temperature in millidegrees */ |
20d391d7 | 182 | int rv6xx_get_temp(struct radeon_device *rdev) |
21a8122a AD |
183 | { |
184 | u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> | |
185 | ASIC_T_SHIFT; | |
20d391d7 | 186 | int actual_temp = temp & 0xff; |
21a8122a | 187 | |
20d391d7 AD |
188 | if (temp & 0x100) |
189 | actual_temp -= 256; | |
190 | ||
191 | return actual_temp * 1000; | |
21a8122a AD |
192 | } |
193 | ||
ce8f5370 | 194 | void r600_pm_get_dynpm_state(struct radeon_device *rdev) |
a48b9b4e AD |
195 | { |
196 | int i; | |
197 | ||
ce8f5370 AD |
198 | rdev->pm.dynpm_can_upclock = true; |
199 | rdev->pm.dynpm_can_downclock = true; | |
a48b9b4e AD |
200 | |
201 | /* power state array is low to high, default is first */ | |
202 | if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { | |
203 | int min_power_state_index = 0; | |
204 | ||
205 | if (rdev->pm.num_power_states > 2) | |
206 | min_power_state_index = 1; | |
207 | ||
ce8f5370 AD |
208 | switch (rdev->pm.dynpm_planned_action) { |
209 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e AD |
210 | rdev->pm.requested_power_state_index = min_power_state_index; |
211 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 212 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 213 | break; |
ce8f5370 | 214 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
215 | if (rdev->pm.current_power_state_index == min_power_state_index) { |
216 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 217 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
218 | } else { |
219 | if (rdev->pm.active_crtc_count > 1) { | |
220 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 221 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
222 | continue; |
223 | else if (i >= rdev->pm.current_power_state_index) { | |
224 | rdev->pm.requested_power_state_index = | |
225 | rdev->pm.current_power_state_index; | |
226 | break; | |
227 | } else { | |
228 | rdev->pm.requested_power_state_index = i; | |
229 | break; | |
230 | } | |
231 | } | |
773c3fa3 AD |
232 | } else { |
233 | if (rdev->pm.current_power_state_index == 0) | |
234 | rdev->pm.requested_power_state_index = | |
235 | rdev->pm.num_power_states - 1; | |
236 | else | |
237 | rdev->pm.requested_power_state_index = | |
238 | rdev->pm.current_power_state_index - 1; | |
239 | } | |
a48b9b4e AD |
240 | } |
241 | rdev->pm.requested_clock_mode_index = 0; | |
d7311171 AD |
242 | /* don't use the power state if crtcs are active and no display flag is set */ |
243 | if ((rdev->pm.active_crtc_count > 0) && | |
244 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
245 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
246 | RADEON_PM_MODE_NO_DISPLAY)) { | |
247 | rdev->pm.requested_power_state_index++; | |
248 | } | |
a48b9b4e | 249 | break; |
ce8f5370 | 250 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
251 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
252 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 253 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
254 | } else { |
255 | if (rdev->pm.active_crtc_count > 1) { | |
256 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { | |
d7311171 | 257 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
258 | continue; |
259 | else if (i <= rdev->pm.current_power_state_index) { | |
260 | rdev->pm.requested_power_state_index = | |
261 | rdev->pm.current_power_state_index; | |
262 | break; | |
263 | } else { | |
264 | rdev->pm.requested_power_state_index = i; | |
265 | break; | |
266 | } | |
267 | } | |
268 | } else | |
269 | rdev->pm.requested_power_state_index = | |
270 | rdev->pm.current_power_state_index + 1; | |
271 | } | |
272 | rdev->pm.requested_clock_mode_index = 0; | |
273 | break; | |
ce8f5370 | 274 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
275 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
276 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 277 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 278 | break; |
ce8f5370 | 279 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
280 | default: |
281 | DRM_ERROR("Requested mode for not defined action\n"); | |
282 | return; | |
283 | } | |
284 | } else { | |
285 | /* XXX select a power state based on AC/DC, single/dualhead, etc. */ | |
286 | /* for now just select the first power state and switch between clock modes */ | |
287 | /* power state array is low to high, default is first (0) */ | |
288 | if (rdev->pm.active_crtc_count > 1) { | |
289 | rdev->pm.requested_power_state_index = -1; | |
290 | /* start at 1 as we don't want the default mode */ | |
291 | for (i = 1; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 292 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
293 | continue; |
294 | else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || | |
295 | (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { | |
296 | rdev->pm.requested_power_state_index = i; | |
297 | break; | |
298 | } | |
299 | } | |
300 | /* if nothing selected, grab the default state. */ | |
301 | if (rdev->pm.requested_power_state_index == -1) | |
302 | rdev->pm.requested_power_state_index = 0; | |
303 | } else | |
304 | rdev->pm.requested_power_state_index = 1; | |
305 | ||
ce8f5370 AD |
306 | switch (rdev->pm.dynpm_planned_action) { |
307 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e | 308 | rdev->pm.requested_clock_mode_index = 0; |
ce8f5370 | 309 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 310 | break; |
ce8f5370 | 311 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
312 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
313 | if (rdev->pm.current_clock_mode_index == 0) { | |
314 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 315 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
316 | } else |
317 | rdev->pm.requested_clock_mode_index = | |
318 | rdev->pm.current_clock_mode_index - 1; | |
319 | } else { | |
320 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 321 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 322 | } |
d7311171 AD |
323 | /* don't use the power state if crtcs are active and no display flag is set */ |
324 | if ((rdev->pm.active_crtc_count > 0) && | |
325 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
326 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
327 | RADEON_PM_MODE_NO_DISPLAY)) { | |
328 | rdev->pm.requested_clock_mode_index++; | |
329 | } | |
a48b9b4e | 330 | break; |
ce8f5370 | 331 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
332 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
333 | if (rdev->pm.current_clock_mode_index == | |
334 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { | |
335 | rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; | |
ce8f5370 | 336 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
337 | } else |
338 | rdev->pm.requested_clock_mode_index = | |
339 | rdev->pm.current_clock_mode_index + 1; | |
340 | } else { | |
341 | rdev->pm.requested_clock_mode_index = | |
342 | rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; | |
ce8f5370 | 343 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
344 | } |
345 | break; | |
ce8f5370 | 346 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
347 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
348 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 349 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 350 | break; |
ce8f5370 | 351 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
352 | default: |
353 | DRM_ERROR("Requested mode for not defined action\n"); | |
354 | return; | |
355 | } | |
356 | } | |
357 | ||
d9fdaafb | 358 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
ce8a3eb2 AD |
359 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
360 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | |
361 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
362 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | |
363 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
364 | pcie_lanes); | |
a48b9b4e AD |
365 | } |
366 | ||
ce8f5370 AD |
367 | void rs780_pm_init_profile(struct radeon_device *rdev) |
368 | { | |
369 | if (rdev->pm.num_power_states == 2) { | |
370 | /* default */ | |
371 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
372 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
373 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
374 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
375 | /* low sh */ | |
376 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; | |
377 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; | |
378 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
379 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
380 | /* mid sh */ |
381 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; | |
382 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; | |
383 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
384 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
385 | /* high sh */ |
386 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; | |
387 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
388 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
389 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
390 | /* low mh */ | |
391 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; | |
392 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
393 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
394 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
395 | /* mid mh */ |
396 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; | |
397 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
398 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
399 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
400 | /* high mh */ |
401 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; | |
402 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; | |
403 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
404 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
405 | } else if (rdev->pm.num_power_states == 3) { | |
406 | /* default */ | |
407 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
408 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
409 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
410 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
411 | /* low sh */ | |
412 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; | |
413 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
414 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
415 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
416 | /* mid sh */ |
417 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
418 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
419 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
420 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
421 | /* high sh */ |
422 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; | |
423 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; | |
424 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
425 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
426 | /* low mh */ | |
427 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; | |
428 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; | |
429 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
430 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
431 | /* mid mh */ |
432 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; | |
433 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; | |
434 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
435 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
436 | /* high mh */ |
437 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; | |
438 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
439 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
440 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
441 | } else { | |
442 | /* default */ | |
443 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
444 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
445 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
446 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
447 | /* low sh */ | |
448 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; | |
449 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; | |
450 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
451 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
452 | /* mid sh */ |
453 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; | |
454 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; | |
455 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
456 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
457 | /* high sh */ |
458 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; | |
459 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; | |
460 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
461 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
462 | /* low mh */ | |
463 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; | |
464 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
465 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
466 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
467 | /* mid mh */ |
468 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
469 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
470 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
471 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
472 | /* high mh */ |
473 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; | |
474 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; | |
475 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
476 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
477 | } | |
478 | } | |
bae6b562 | 479 | |
ce8f5370 AD |
480 | void r600_pm_init_profile(struct radeon_device *rdev) |
481 | { | |
bbe26ffe AD |
482 | int idx; |
483 | ||
ce8f5370 AD |
484 | if (rdev->family == CHIP_R600) { |
485 | /* XXX */ | |
486 | /* default */ | |
487 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
488 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
489 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 490 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
491 | /* low sh */ |
492 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
493 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
494 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 495 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
496 | /* mid sh */ |
497 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
498 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
499 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
500 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
501 | /* high sh */ |
502 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
503 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
504 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 505 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
506 | /* low mh */ |
507 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
508 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
509 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 510 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
511 | /* mid mh */ |
512 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
513 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
514 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
515 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
516 | /* high mh */ |
517 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
518 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
519 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 520 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
521 | } else { |
522 | if (rdev->pm.num_power_states < 4) { | |
523 | /* default */ | |
524 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
525 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
526 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
527 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
528 | /* low sh */ | |
4bff5171 AD |
529 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
530 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 | 531 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
532 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
533 | /* mid sh */ | |
534 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
535 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
536 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
537 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 538 | /* high sh */ |
4bff5171 AD |
539 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
540 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 AD |
541 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
542 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
543 | /* low mh */ | |
4bff5171 AD |
544 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
545 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 | 546 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
547 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
548 | /* low mh */ | |
549 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
550 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; | |
551 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
552 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 553 | /* high mh */ |
4bff5171 AD |
554 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
555 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 AD |
556 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
557 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
558 | } else { | |
559 | /* default */ | |
560 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
561 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
562 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
563 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
564 | /* low sh */ | |
bbe26ffe AD |
565 | if (rdev->flags & RADEON_IS_MOBILITY) |
566 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
567 | else | |
568 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
569 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; | |
570 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; | |
571 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
572 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 | 573 | /* mid sh */ |
bbe26ffe AD |
574 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; |
575 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; | |
576 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
577 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 578 | /* high sh */ |
bbe26ffe AD |
579 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); |
580 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; | |
581 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; | |
ce8f5370 AD |
582 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
583 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
584 | /* low mh */ | |
bbe26ffe AD |
585 | if (rdev->flags & RADEON_IS_MOBILITY) |
586 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); | |
587 | else | |
588 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
589 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; | |
590 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; | |
591 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
592 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 | 593 | /* mid mh */ |
bbe26ffe AD |
594 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; |
595 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; | |
596 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
597 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 598 | /* high mh */ |
bbe26ffe AD |
599 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); |
600 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; | |
601 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; | |
ce8f5370 AD |
602 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
603 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
604 | } | |
605 | } | |
bae6b562 AD |
606 | } |
607 | ||
49e02b73 AD |
608 | void r600_pm_misc(struct radeon_device *rdev) |
609 | { | |
a081a9d6 RM |
610 | int req_ps_idx = rdev->pm.requested_power_state_index; |
611 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
612 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
613 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
7ac9aa5a | 614 | |
4d60173f | 615 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
a377e187 AD |
616 | /* 0xff01 is a flag rather then an actual voltage */ |
617 | if (voltage->voltage == 0xff01) | |
618 | return; | |
4d60173f | 619 | if (voltage->voltage != rdev->pm.current_vddc) { |
8a83ec5e | 620 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
4d60173f | 621 | rdev->pm.current_vddc = voltage->voltage; |
d9fdaafb | 622 | DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); |
4d60173f AD |
623 | } |
624 | } | |
49e02b73 AD |
625 | } |
626 | ||
def9ba9c AD |
627 | bool r600_gui_idle(struct radeon_device *rdev) |
628 | { | |
629 | if (RREG32(GRBM_STATUS) & GUI_ACTIVE) | |
630 | return false; | |
631 | else | |
632 | return true; | |
633 | } | |
634 | ||
e0df1ac5 AD |
635 | /* hpd for digital panel detect/disconnect */ |
636 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
637 | { | |
638 | bool connected = false; | |
639 | ||
640 | if (ASIC_IS_DCE3(rdev)) { | |
641 | switch (hpd) { | |
642 | case RADEON_HPD_1: | |
643 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
644 | connected = true; | |
645 | break; | |
646 | case RADEON_HPD_2: | |
647 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
648 | connected = true; | |
649 | break; | |
650 | case RADEON_HPD_3: | |
651 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
652 | connected = true; | |
653 | break; | |
654 | case RADEON_HPD_4: | |
655 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
656 | connected = true; | |
657 | break; | |
658 | /* DCE 3.2 */ | |
659 | case RADEON_HPD_5: | |
660 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
661 | connected = true; | |
662 | break; | |
663 | case RADEON_HPD_6: | |
664 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
665 | connected = true; | |
666 | break; | |
667 | default: | |
668 | break; | |
669 | } | |
670 | } else { | |
671 | switch (hpd) { | |
672 | case RADEON_HPD_1: | |
673 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
674 | connected = true; | |
675 | break; | |
676 | case RADEON_HPD_2: | |
677 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
678 | connected = true; | |
679 | break; | |
680 | case RADEON_HPD_3: | |
681 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
682 | connected = true; | |
683 | break; | |
684 | default: | |
685 | break; | |
686 | } | |
687 | } | |
688 | return connected; | |
689 | } | |
690 | ||
691 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
429770b3 | 692 | enum radeon_hpd_id hpd) |
e0df1ac5 AD |
693 | { |
694 | u32 tmp; | |
695 | bool connected = r600_hpd_sense(rdev, hpd); | |
696 | ||
697 | if (ASIC_IS_DCE3(rdev)) { | |
698 | switch (hpd) { | |
699 | case RADEON_HPD_1: | |
700 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
701 | if (connected) | |
702 | tmp &= ~DC_HPDx_INT_POLARITY; | |
703 | else | |
704 | tmp |= DC_HPDx_INT_POLARITY; | |
705 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
706 | break; | |
707 | case RADEON_HPD_2: | |
708 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
709 | if (connected) | |
710 | tmp &= ~DC_HPDx_INT_POLARITY; | |
711 | else | |
712 | tmp |= DC_HPDx_INT_POLARITY; | |
713 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
714 | break; | |
715 | case RADEON_HPD_3: | |
716 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
717 | if (connected) | |
718 | tmp &= ~DC_HPDx_INT_POLARITY; | |
719 | else | |
720 | tmp |= DC_HPDx_INT_POLARITY; | |
721 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
722 | break; | |
723 | case RADEON_HPD_4: | |
724 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
725 | if (connected) | |
726 | tmp &= ~DC_HPDx_INT_POLARITY; | |
727 | else | |
728 | tmp |= DC_HPDx_INT_POLARITY; | |
729 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
730 | break; | |
731 | case RADEON_HPD_5: | |
732 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
733 | if (connected) | |
734 | tmp &= ~DC_HPDx_INT_POLARITY; | |
735 | else | |
736 | tmp |= DC_HPDx_INT_POLARITY; | |
737 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
738 | break; | |
739 | /* DCE 3.2 */ | |
740 | case RADEON_HPD_6: | |
741 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
742 | if (connected) | |
743 | tmp &= ~DC_HPDx_INT_POLARITY; | |
744 | else | |
745 | tmp |= DC_HPDx_INT_POLARITY; | |
746 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
747 | break; | |
748 | default: | |
749 | break; | |
750 | } | |
751 | } else { | |
752 | switch (hpd) { | |
753 | case RADEON_HPD_1: | |
754 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
755 | if (connected) | |
756 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
757 | else | |
758 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
759 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
760 | break; | |
761 | case RADEON_HPD_2: | |
762 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
763 | if (connected) | |
764 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
765 | else | |
766 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
767 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
768 | break; | |
769 | case RADEON_HPD_3: | |
770 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
771 | if (connected) | |
772 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
773 | else | |
774 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
775 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
776 | break; | |
777 | default: | |
778 | break; | |
779 | } | |
780 | } | |
781 | } | |
782 | ||
783 | void r600_hpd_init(struct radeon_device *rdev) | |
784 | { | |
785 | struct drm_device *dev = rdev->ddev; | |
786 | struct drm_connector *connector; | |
fb98257a | 787 | unsigned enable = 0; |
e0df1ac5 | 788 | |
64912e99 AD |
789 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
790 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
791 | ||
455c89b9 JG |
792 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || |
793 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { | |
794 | /* don't try to enable hpd on eDP or LVDS avoid breaking the | |
795 | * aux dp channel on imac and help (but not completely fix) | |
796 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 | |
797 | */ | |
798 | continue; | |
799 | } | |
64912e99 AD |
800 | if (ASIC_IS_DCE3(rdev)) { |
801 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); | |
802 | if (ASIC_IS_DCE32(rdev)) | |
803 | tmp |= DC_HPDx_EN; | |
e0df1ac5 | 804 | |
e0df1ac5 AD |
805 | switch (radeon_connector->hpd.hpd) { |
806 | case RADEON_HPD_1: | |
807 | WREG32(DC_HPD1_CONTROL, tmp); | |
e0df1ac5 AD |
808 | break; |
809 | case RADEON_HPD_2: | |
810 | WREG32(DC_HPD2_CONTROL, tmp); | |
e0df1ac5 AD |
811 | break; |
812 | case RADEON_HPD_3: | |
813 | WREG32(DC_HPD3_CONTROL, tmp); | |
e0df1ac5 AD |
814 | break; |
815 | case RADEON_HPD_4: | |
816 | WREG32(DC_HPD4_CONTROL, tmp); | |
e0df1ac5 AD |
817 | break; |
818 | /* DCE 3.2 */ | |
819 | case RADEON_HPD_5: | |
820 | WREG32(DC_HPD5_CONTROL, tmp); | |
e0df1ac5 AD |
821 | break; |
822 | case RADEON_HPD_6: | |
823 | WREG32(DC_HPD6_CONTROL, tmp); | |
e0df1ac5 AD |
824 | break; |
825 | default: | |
826 | break; | |
827 | } | |
64912e99 | 828 | } else { |
e0df1ac5 AD |
829 | switch (radeon_connector->hpd.hpd) { |
830 | case RADEON_HPD_1: | |
831 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
e0df1ac5 AD |
832 | break; |
833 | case RADEON_HPD_2: | |
834 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
e0df1ac5 AD |
835 | break; |
836 | case RADEON_HPD_3: | |
837 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
e0df1ac5 AD |
838 | break; |
839 | default: | |
840 | break; | |
841 | } | |
842 | } | |
fb98257a | 843 | enable |= 1 << radeon_connector->hpd.hpd; |
64912e99 | 844 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
e0df1ac5 | 845 | } |
fb98257a | 846 | radeon_irq_kms_enable_hpd(rdev, enable); |
e0df1ac5 AD |
847 | } |
848 | ||
849 | void r600_hpd_fini(struct radeon_device *rdev) | |
850 | { | |
851 | struct drm_device *dev = rdev->ddev; | |
852 | struct drm_connector *connector; | |
fb98257a | 853 | unsigned disable = 0; |
e0df1ac5 | 854 | |
fb98257a CK |
855 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
856 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
857 | if (ASIC_IS_DCE3(rdev)) { | |
e0df1ac5 AD |
858 | switch (radeon_connector->hpd.hpd) { |
859 | case RADEON_HPD_1: | |
860 | WREG32(DC_HPD1_CONTROL, 0); | |
e0df1ac5 AD |
861 | break; |
862 | case RADEON_HPD_2: | |
863 | WREG32(DC_HPD2_CONTROL, 0); | |
e0df1ac5 AD |
864 | break; |
865 | case RADEON_HPD_3: | |
866 | WREG32(DC_HPD3_CONTROL, 0); | |
e0df1ac5 AD |
867 | break; |
868 | case RADEON_HPD_4: | |
869 | WREG32(DC_HPD4_CONTROL, 0); | |
e0df1ac5 AD |
870 | break; |
871 | /* DCE 3.2 */ | |
872 | case RADEON_HPD_5: | |
873 | WREG32(DC_HPD5_CONTROL, 0); | |
e0df1ac5 AD |
874 | break; |
875 | case RADEON_HPD_6: | |
876 | WREG32(DC_HPD6_CONTROL, 0); | |
e0df1ac5 AD |
877 | break; |
878 | default: | |
879 | break; | |
880 | } | |
fb98257a | 881 | } else { |
e0df1ac5 AD |
882 | switch (radeon_connector->hpd.hpd) { |
883 | case RADEON_HPD_1: | |
884 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); | |
e0df1ac5 AD |
885 | break; |
886 | case RADEON_HPD_2: | |
887 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); | |
e0df1ac5 AD |
888 | break; |
889 | case RADEON_HPD_3: | |
890 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); | |
e0df1ac5 AD |
891 | break; |
892 | default: | |
893 | break; | |
894 | } | |
895 | } | |
fb98257a | 896 | disable |= 1 << radeon_connector->hpd.hpd; |
e0df1ac5 | 897 | } |
fb98257a | 898 | radeon_irq_kms_disable_hpd(rdev, disable); |
e0df1ac5 AD |
899 | } |
900 | ||
771fe6b9 | 901 | /* |
3ce0a23d | 902 | * R600 PCIE GART |
771fe6b9 | 903 | */ |
3ce0a23d JG |
904 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
905 | { | |
906 | unsigned i; | |
907 | u32 tmp; | |
908 | ||
2e98f10a | 909 | /* flush hdp cache so updates hit vram */ |
f3886f85 AD |
910 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
911 | !(rdev->flags & RADEON_IS_AGP)) { | |
c9a1be96 | 912 | void __iomem *ptr = (void *)rdev->gart.ptr; |
812d0469 AD |
913 | u32 tmp; |
914 | ||
915 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read | |
916 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL | |
f3886f85 AD |
917 | * This seems to cause problems on some AGP cards. Just use the old |
918 | * method for them. | |
812d0469 AD |
919 | */ |
920 | WREG32(HDP_DEBUG1, 0); | |
921 | tmp = readl((void __iomem *)ptr); | |
922 | } else | |
923 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2e98f10a | 924 | |
3ce0a23d JG |
925 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
926 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); | |
927 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
928 | for (i = 0; i < rdev->usec_timeout; i++) { | |
929 | /* read MC_STATUS */ | |
930 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
931 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
932 | if (tmp == 2) { | |
933 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
934 | return; | |
935 | } | |
936 | if (tmp) { | |
937 | return; | |
938 | } | |
939 | udelay(1); | |
940 | } | |
941 | } | |
942 | ||
4aac0473 | 943 | int r600_pcie_gart_init(struct radeon_device *rdev) |
3ce0a23d | 944 | { |
4aac0473 | 945 | int r; |
3ce0a23d | 946 | |
c9a1be96 | 947 | if (rdev->gart.robj) { |
fce7d61b | 948 | WARN(1, "R600 PCIE GART already initialized\n"); |
4aac0473 JG |
949 | return 0; |
950 | } | |
3ce0a23d JG |
951 | /* Initialize common gart structure */ |
952 | r = radeon_gart_init(rdev); | |
4aac0473 | 953 | if (r) |
3ce0a23d | 954 | return r; |
3ce0a23d | 955 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
4aac0473 JG |
956 | return radeon_gart_table_vram_alloc(rdev); |
957 | } | |
958 | ||
1109ca09 | 959 | static int r600_pcie_gart_enable(struct radeon_device *rdev) |
4aac0473 JG |
960 | { |
961 | u32 tmp; | |
962 | int r, i; | |
963 | ||
c9a1be96 | 964 | if (rdev->gart.robj == NULL) { |
4aac0473 JG |
965 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
966 | return -EINVAL; | |
771fe6b9 | 967 | } |
4aac0473 JG |
968 | r = radeon_gart_table_vram_pin(rdev); |
969 | if (r) | |
970 | return r; | |
82568565 | 971 | radeon_gart_restore(rdev); |
bc1a631e | 972 | |
3ce0a23d JG |
973 | /* Setup L2 cache */ |
974 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
975 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
976 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
977 | WREG32(VM_L2_CNTL2, 0); | |
978 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
979 | /* Setup TLB control */ | |
980 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
981 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
982 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
983 | ENABLE_WAIT_L2_QUERY; | |
984 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
985 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
986 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
987 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
988 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
989 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
990 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
991 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
992 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
993 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
994 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
995 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
996 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
997 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
998 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1a029b76 | 999 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
1000 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
1001 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
1002 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
1003 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
1004 | (u32)(rdev->dummy_page.addr >> 12)); | |
1005 | for (i = 1; i < 7; i++) | |
1006 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 1007 | |
3ce0a23d | 1008 | r600_pcie_gart_tlb_flush(rdev); |
fcf4de5a TV |
1009 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
1010 | (unsigned)(rdev->mc.gtt_size >> 20), | |
1011 | (unsigned long long)rdev->gart.table_addr); | |
3ce0a23d | 1012 | rdev->gart.ready = true; |
771fe6b9 JG |
1013 | return 0; |
1014 | } | |
1015 | ||
1109ca09 | 1016 | static void r600_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 1017 | { |
3ce0a23d | 1018 | u32 tmp; |
c9a1be96 | 1019 | int i; |
771fe6b9 | 1020 | |
3ce0a23d JG |
1021 | /* Disable all tables */ |
1022 | for (i = 0; i < 7; i++) | |
1023 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 1024 | |
3ce0a23d JG |
1025 | /* Disable L2 cache */ |
1026 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
1027 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1028 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
1029 | /* Setup L1 TLB control */ | |
1030 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
1031 | ENABLE_WAIT_L2_QUERY; | |
1032 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
1033 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
1034 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
1035 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
1036 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
1037 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
1038 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
1039 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
1040 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); | |
1041 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); | |
1042 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
1043 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
1044 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); | |
1045 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
c9a1be96 | 1046 | radeon_gart_table_vram_unpin(rdev); |
4aac0473 JG |
1047 | } |
1048 | ||
1109ca09 | 1049 | static void r600_pcie_gart_fini(struct radeon_device *rdev) |
4aac0473 | 1050 | { |
f9274562 | 1051 | radeon_gart_fini(rdev); |
4aac0473 JG |
1052 | r600_pcie_gart_disable(rdev); |
1053 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
1054 | } |
1055 | ||
1109ca09 | 1056 | static void r600_agp_enable(struct radeon_device *rdev) |
1a029b76 JG |
1057 | { |
1058 | u32 tmp; | |
1059 | int i; | |
1060 | ||
1061 | /* Setup L2 cache */ | |
1062 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
1063 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
1064 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1065 | WREG32(VM_L2_CNTL2, 0); | |
1066 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
1067 | /* Setup TLB control */ | |
1068 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1069 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1070 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
1071 | ENABLE_WAIT_L2_QUERY; | |
1072 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
1073 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
1074 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
1075 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
1076 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
1077 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
1078 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
1079 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
1080 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
1081 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
1082 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
1083 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
1084 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1085 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1086 | for (i = 0; i < 7; i++) | |
1087 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
1088 | } | |
1089 | ||
771fe6b9 JG |
1090 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
1091 | { | |
3ce0a23d JG |
1092 | unsigned i; |
1093 | u32 tmp; | |
1094 | ||
1095 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1096 | /* read MC_STATUS */ | |
1097 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; | |
1098 | if (!tmp) | |
1099 | return 0; | |
1100 | udelay(1); | |
1101 | } | |
1102 | return -1; | |
771fe6b9 JG |
1103 | } |
1104 | ||
65337e60 SL |
1105 | uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
1106 | { | |
0a5b7b0b | 1107 | unsigned long flags; |
65337e60 SL |
1108 | uint32_t r; |
1109 | ||
0a5b7b0b | 1110 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
65337e60 SL |
1111 | WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); |
1112 | r = RREG32(R_0028FC_MC_DATA); | |
1113 | WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); | |
0a5b7b0b | 1114 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
65337e60 SL |
1115 | return r; |
1116 | } | |
1117 | ||
1118 | void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1119 | { | |
0a5b7b0b AD |
1120 | unsigned long flags; |
1121 | ||
1122 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); | |
65337e60 SL |
1123 | WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | |
1124 | S_0028F8_MC_IND_WR_EN(1)); | |
1125 | WREG32(R_0028FC_MC_DATA, v); | |
1126 | WREG32(R_0028F8_MC_INDEX, 0x7F); | |
0a5b7b0b | 1127 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
65337e60 SL |
1128 | } |
1129 | ||
a3c1945a | 1130 | static void r600_mc_program(struct radeon_device *rdev) |
771fe6b9 | 1131 | { |
a3c1945a | 1132 | struct rv515_mc_save save; |
3ce0a23d JG |
1133 | u32 tmp; |
1134 | int i, j; | |
771fe6b9 | 1135 | |
3ce0a23d JG |
1136 | /* Initialize HDP */ |
1137 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1138 | WREG32((0x2c14 + j), 0x00000000); | |
1139 | WREG32((0x2c18 + j), 0x00000000); | |
1140 | WREG32((0x2c1c + j), 0x00000000); | |
1141 | WREG32((0x2c20 + j), 0x00000000); | |
1142 | WREG32((0x2c24 + j), 0x00000000); | |
1143 | } | |
1144 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
771fe6b9 | 1145 | |
a3c1945a | 1146 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 1147 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1148 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1149 | } |
a3c1945a | 1150 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
3ce0a23d | 1151 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
3ce0a23d | 1152 | /* Update configuration */ |
1a029b76 JG |
1153 | if (rdev->flags & RADEON_IS_AGP) { |
1154 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
1155 | /* VRAM before AGP */ | |
1156 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1157 | rdev->mc.vram_start >> 12); | |
1158 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1159 | rdev->mc.gtt_end >> 12); | |
1160 | } else { | |
1161 | /* VRAM after AGP */ | |
1162 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1163 | rdev->mc.gtt_start >> 12); | |
1164 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1165 | rdev->mc.vram_end >> 12); | |
1166 | } | |
1167 | } else { | |
1168 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); | |
1169 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); | |
1170 | } | |
16cdf04d | 1171 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
1a029b76 | 1172 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
1173 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
1174 | WREG32(MC_VM_FB_LOCATION, tmp); | |
1175 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
1176 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
46fcd2b3 | 1177 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
3ce0a23d | 1178 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 JG |
1179 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
1180 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | |
3ce0a23d JG |
1181 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
1182 | } else { | |
1183 | WREG32(MC_VM_AGP_BASE, 0); | |
1184 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
1185 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
1186 | } | |
3ce0a23d | 1187 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1188 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1189 | } |
a3c1945a | 1190 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
1191 | /* we need to own VRAM, so turn off the VGA renderer here |
1192 | * to stop it overwriting our objects */ | |
d39c3b89 | 1193 | rv515_vga_render_disable(rdev); |
3ce0a23d JG |
1194 | } |
1195 | ||
d594e46a JG |
1196 | /** |
1197 | * r600_vram_gtt_location - try to find VRAM & GTT location | |
1198 | * @rdev: radeon device structure holding all necessary informations | |
1199 | * @mc: memory controller structure holding memory informations | |
1200 | * | |
1201 | * Function will place try to place VRAM at same place as in CPU (PCI) | |
1202 | * address space as some GPU seems to have issue when we reprogram at | |
1203 | * different address space. | |
1204 | * | |
1205 | * If there is not enough space to fit the unvisible VRAM after the | |
1206 | * aperture then we limit the VRAM size to the aperture. | |
1207 | * | |
1208 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need | |
1209 | * them to be in one from GPU point of view so that we can program GPU to | |
1210 | * catch access outside them (weird GPU policy see ??). | |
1211 | * | |
1212 | * This function will never fails, worst case are limiting VRAM or GTT. | |
1213 | * | |
1214 | * Note: GTT start, end, size should be initialized before calling this | |
1215 | * function on AGP platform. | |
1216 | */ | |
0ef0c1f7 | 1217 | static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
d594e46a JG |
1218 | { |
1219 | u64 size_bf, size_af; | |
1220 | ||
1221 | if (mc->mc_vram_size > 0xE0000000) { | |
1222 | /* leave room for at least 512M GTT */ | |
1223 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1224 | mc->real_vram_size = 0xE0000000; | |
1225 | mc->mc_vram_size = 0xE0000000; | |
1226 | } | |
1227 | if (rdev->flags & RADEON_IS_AGP) { | |
1228 | size_bf = mc->gtt_start; | |
9ed8b1f9 | 1229 | size_af = mc->mc_mask - mc->gtt_end; |
d594e46a JG |
1230 | if (size_bf > size_af) { |
1231 | if (mc->mc_vram_size > size_bf) { | |
1232 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1233 | mc->real_vram_size = size_bf; | |
1234 | mc->mc_vram_size = size_bf; | |
1235 | } | |
1236 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; | |
1237 | } else { | |
1238 | if (mc->mc_vram_size > size_af) { | |
1239 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1240 | mc->real_vram_size = size_af; | |
1241 | mc->mc_vram_size = size_af; | |
1242 | } | |
dfc6ae5b | 1243 | mc->vram_start = mc->gtt_end + 1; |
d594e46a JG |
1244 | } |
1245 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
1246 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
1247 | mc->mc_vram_size >> 20, mc->vram_start, | |
1248 | mc->vram_end, mc->real_vram_size >> 20); | |
1249 | } else { | |
1250 | u64 base = 0; | |
8961d52d AD |
1251 | if (rdev->flags & RADEON_IS_IGP) { |
1252 | base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; | |
1253 | base <<= 24; | |
1254 | } | |
d594e46a | 1255 | radeon_vram_location(rdev, &rdev->mc, base); |
8d369bb1 | 1256 | rdev->mc.gtt_base_align = 0; |
d594e46a JG |
1257 | radeon_gtt_location(rdev, mc); |
1258 | } | |
1259 | } | |
1260 | ||
1109ca09 | 1261 | static int r600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 1262 | { |
3ce0a23d | 1263 | u32 tmp; |
5885b7a9 | 1264 | int chansize, numchan; |
65337e60 SL |
1265 | uint32_t h_addr, l_addr; |
1266 | unsigned long long k8_addr; | |
771fe6b9 | 1267 | |
3ce0a23d | 1268 | /* Get VRAM informations */ |
771fe6b9 | 1269 | rdev->mc.vram_is_ddr = true; |
3ce0a23d JG |
1270 | tmp = RREG32(RAMCFG); |
1271 | if (tmp & CHANSIZE_OVERRIDE) { | |
771fe6b9 | 1272 | chansize = 16; |
3ce0a23d | 1273 | } else if (tmp & CHANSIZE_MASK) { |
771fe6b9 JG |
1274 | chansize = 64; |
1275 | } else { | |
1276 | chansize = 32; | |
1277 | } | |
5885b7a9 AD |
1278 | tmp = RREG32(CHMAP); |
1279 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
1280 | case 0: | |
1281 | default: | |
1282 | numchan = 1; | |
1283 | break; | |
1284 | case 1: | |
1285 | numchan = 2; | |
1286 | break; | |
1287 | case 2: | |
1288 | numchan = 4; | |
1289 | break; | |
1290 | case 3: | |
1291 | numchan = 8; | |
1292 | break; | |
771fe6b9 | 1293 | } |
5885b7a9 | 1294 | rdev->mc.vram_width = numchan * chansize; |
3ce0a23d | 1295 | /* Could aper size report 0 ? */ |
01d73a69 JC |
1296 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
1297 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
3ce0a23d JG |
1298 | /* Setup GPU memory space */ |
1299 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
1300 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
51e5fcd3 | 1301 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a | 1302 | r600_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 | 1303 | |
f892034a AD |
1304 | if (rdev->flags & RADEON_IS_IGP) { |
1305 | rs690_pm_info(rdev); | |
06b6476d | 1306 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
65337e60 SL |
1307 | |
1308 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { | |
1309 | /* Use K8 direct mapping for fast fb access. */ | |
1310 | rdev->fastfb_working = false; | |
1311 | h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); | |
1312 | l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); | |
1313 | k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; | |
1314 | #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) | |
1315 | if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) | |
1316 | #endif | |
1317 | { | |
1318 | /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport | |
1319 | * memory is present. | |
1320 | */ | |
1321 | if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { | |
1322 | DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", | |
1323 | (unsigned long long)rdev->mc.aper_base, k8_addr); | |
1324 | rdev->mc.aper_base = (resource_size_t)k8_addr; | |
1325 | rdev->fastfb_working = true; | |
1326 | } | |
1327 | } | |
1328 | } | |
f892034a | 1329 | } |
65337e60 | 1330 | |
f47299c5 | 1331 | radeon_update_bandwidth_info(rdev); |
3ce0a23d | 1332 | return 0; |
771fe6b9 JG |
1333 | } |
1334 | ||
16cdf04d AD |
1335 | int r600_vram_scratch_init(struct radeon_device *rdev) |
1336 | { | |
1337 | int r; | |
1338 | ||
1339 | if (rdev->vram_scratch.robj == NULL) { | |
1340 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, | |
1341 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, | |
40f5cf99 | 1342 | NULL, &rdev->vram_scratch.robj); |
16cdf04d AD |
1343 | if (r) { |
1344 | return r; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | |
1349 | if (unlikely(r != 0)) | |
1350 | return r; | |
1351 | r = radeon_bo_pin(rdev->vram_scratch.robj, | |
1352 | RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); | |
1353 | if (r) { | |
1354 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1355 | return r; | |
1356 | } | |
1357 | r = radeon_bo_kmap(rdev->vram_scratch.robj, | |
1358 | (void **)&rdev->vram_scratch.ptr); | |
1359 | if (r) | |
1360 | radeon_bo_unpin(rdev->vram_scratch.robj); | |
1361 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1362 | ||
1363 | return r; | |
1364 | } | |
1365 | ||
1366 | void r600_vram_scratch_fini(struct radeon_device *rdev) | |
1367 | { | |
1368 | int r; | |
1369 | ||
1370 | if (rdev->vram_scratch.robj == NULL) { | |
1371 | return; | |
1372 | } | |
1373 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | |
1374 | if (likely(r == 0)) { | |
1375 | radeon_bo_kunmap(rdev->vram_scratch.robj); | |
1376 | radeon_bo_unpin(rdev->vram_scratch.robj); | |
1377 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1378 | } | |
1379 | radeon_bo_unref(&rdev->vram_scratch.robj); | |
1380 | } | |
1381 | ||
410a3418 AD |
1382 | void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) |
1383 | { | |
1384 | u32 tmp = RREG32(R600_BIOS_3_SCRATCH); | |
1385 | ||
1386 | if (hung) | |
1387 | tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
1388 | else | |
1389 | tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
1390 | ||
1391 | WREG32(R600_BIOS_3_SCRATCH, tmp); | |
1392 | } | |
1393 | ||
d3cb781e | 1394 | static void r600_print_gpu_status_regs(struct radeon_device *rdev) |
771fe6b9 | 1395 | { |
64c56e8c | 1396 | dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", |
d3cb781e | 1397 | RREG32(R_008010_GRBM_STATUS)); |
64c56e8c | 1398 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", |
d3cb781e | 1399 | RREG32(R_008014_GRBM_STATUS2)); |
64c56e8c | 1400 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", |
d3cb781e | 1401 | RREG32(R_000E50_SRBM_STATUS)); |
440a7cd8 | 1402 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
d3cb781e | 1403 | RREG32(CP_STALLED_STAT1)); |
440a7cd8 | 1404 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
d3cb781e | 1405 | RREG32(CP_STALLED_STAT2)); |
440a7cd8 | 1406 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
d3cb781e | 1407 | RREG32(CP_BUSY_STAT)); |
440a7cd8 | 1408 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
d3cb781e | 1409 | RREG32(CP_STAT)); |
71e3d157 AD |
1410 | dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", |
1411 | RREG32(DMA_STATUS_REG)); | |
1412 | } | |
1413 | ||
f13f7731 | 1414 | static bool r600_is_display_hung(struct radeon_device *rdev) |
71e3d157 | 1415 | { |
f13f7731 AD |
1416 | u32 crtc_hung = 0; |
1417 | u32 crtc_status[2]; | |
1418 | u32 i, j, tmp; | |
1419 | ||
1420 | for (i = 0; i < rdev->num_crtc; i++) { | |
1421 | if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { | |
1422 | crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
1423 | crtc_hung |= (1 << i); | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | for (j = 0; j < 10; j++) { | |
1428 | for (i = 0; i < rdev->num_crtc; i++) { | |
1429 | if (crtc_hung & (1 << i)) { | |
1430 | tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
1431 | if (tmp != crtc_status[i]) | |
1432 | crtc_hung &= ~(1 << i); | |
1433 | } | |
1434 | } | |
1435 | if (crtc_hung == 0) | |
1436 | return false; | |
1437 | udelay(100); | |
1438 | } | |
1439 | ||
1440 | return true; | |
1441 | } | |
1442 | ||
2483b4ea | 1443 | u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) |
f13f7731 AD |
1444 | { |
1445 | u32 reset_mask = 0; | |
d3cb781e | 1446 | u32 tmp; |
71e3d157 | 1447 | |
f13f7731 AD |
1448 | /* GRBM_STATUS */ |
1449 | tmp = RREG32(R_008010_GRBM_STATUS); | |
1450 | if (rdev->family >= CHIP_RV770) { | |
1451 | if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | | |
1452 | G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | | |
1453 | G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | | |
1454 | G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | | |
1455 | G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) | |
1456 | reset_mask |= RADEON_RESET_GFX; | |
1457 | } else { | |
1458 | if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | | |
1459 | G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | | |
1460 | G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | | |
1461 | G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | | |
1462 | G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) | |
1463 | reset_mask |= RADEON_RESET_GFX; | |
1464 | } | |
1465 | ||
1466 | if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | | |
1467 | G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) | |
1468 | reset_mask |= RADEON_RESET_CP; | |
1469 | ||
1470 | if (G_008010_GRBM_EE_BUSY(tmp)) | |
1471 | reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; | |
1472 | ||
1473 | /* DMA_STATUS_REG */ | |
1474 | tmp = RREG32(DMA_STATUS_REG); | |
1475 | if (!(tmp & DMA_IDLE)) | |
1476 | reset_mask |= RADEON_RESET_DMA; | |
1477 | ||
1478 | /* SRBM_STATUS */ | |
1479 | tmp = RREG32(R_000E50_SRBM_STATUS); | |
1480 | if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) | |
1481 | reset_mask |= RADEON_RESET_RLC; | |
1482 | ||
1483 | if (G_000E50_IH_BUSY(tmp)) | |
1484 | reset_mask |= RADEON_RESET_IH; | |
1485 | ||
1486 | if (G_000E50_SEM_BUSY(tmp)) | |
1487 | reset_mask |= RADEON_RESET_SEM; | |
19fc42ed | 1488 | |
f13f7731 AD |
1489 | if (G_000E50_GRBM_RQ_PENDING(tmp)) |
1490 | reset_mask |= RADEON_RESET_GRBM; | |
1491 | ||
1492 | if (G_000E50_VMC_BUSY(tmp)) | |
1493 | reset_mask |= RADEON_RESET_VMC; | |
1494 | ||
1495 | if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | | |
1496 | G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | | |
1497 | G_000E50_MCDW_BUSY(tmp)) | |
1498 | reset_mask |= RADEON_RESET_MC; | |
1499 | ||
1500 | if (r600_is_display_hung(rdev)) | |
1501 | reset_mask |= RADEON_RESET_DISPLAY; | |
1502 | ||
d808fc88 AD |
1503 | /* Skip MC reset as it's mostly likely not hung, just busy */ |
1504 | if (reset_mask & RADEON_RESET_MC) { | |
1505 | DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); | |
1506 | reset_mask &= ~RADEON_RESET_MC; | |
1507 | } | |
1508 | ||
f13f7731 AD |
1509 | return reset_mask; |
1510 | } | |
1511 | ||
1512 | static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) | |
1513 | { | |
1514 | struct rv515_mc_save save; | |
1515 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; | |
1516 | u32 tmp; | |
19fc42ed | 1517 | |
71e3d157 | 1518 | if (reset_mask == 0) |
f13f7731 | 1519 | return; |
71e3d157 AD |
1520 | |
1521 | dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); | |
1522 | ||
d3cb781e AD |
1523 | r600_print_gpu_status_regs(rdev); |
1524 | ||
d3cb781e AD |
1525 | /* Disable CP parsing/prefetching */ |
1526 | if (rdev->family >= CHIP_RV770) | |
1527 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); | |
1528 | else | |
1529 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1530 | ||
1531 | /* disable the RLC */ | |
1532 | WREG32(RLC_CNTL, 0); | |
1533 | ||
1534 | if (reset_mask & RADEON_RESET_DMA) { | |
1535 | /* Disable DMA */ | |
1536 | tmp = RREG32(DMA_RB_CNTL); | |
1537 | tmp &= ~DMA_RB_ENABLE; | |
1538 | WREG32(DMA_RB_CNTL, tmp); | |
1539 | } | |
1540 | ||
1541 | mdelay(50); | |
1542 | ||
ca57802e AD |
1543 | rv515_mc_stop(rdev, &save); |
1544 | if (r600_mc_wait_for_idle(rdev)) { | |
1545 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1546 | } | |
1547 | ||
d3cb781e AD |
1548 | if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { |
1549 | if (rdev->family >= CHIP_RV770) | |
1550 | grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | | |
1551 | S_008020_SOFT_RESET_CB(1) | | |
1552 | S_008020_SOFT_RESET_PA(1) | | |
1553 | S_008020_SOFT_RESET_SC(1) | | |
1554 | S_008020_SOFT_RESET_SPI(1) | | |
1555 | S_008020_SOFT_RESET_SX(1) | | |
1556 | S_008020_SOFT_RESET_SH(1) | | |
1557 | S_008020_SOFT_RESET_TC(1) | | |
1558 | S_008020_SOFT_RESET_TA(1) | | |
1559 | S_008020_SOFT_RESET_VC(1) | | |
1560 | S_008020_SOFT_RESET_VGT(1); | |
1561 | else | |
1562 | grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | | |
1563 | S_008020_SOFT_RESET_DB(1) | | |
1564 | S_008020_SOFT_RESET_CB(1) | | |
1565 | S_008020_SOFT_RESET_PA(1) | | |
1566 | S_008020_SOFT_RESET_SC(1) | | |
1567 | S_008020_SOFT_RESET_SMX(1) | | |
1568 | S_008020_SOFT_RESET_SPI(1) | | |
1569 | S_008020_SOFT_RESET_SX(1) | | |
1570 | S_008020_SOFT_RESET_SH(1) | | |
1571 | S_008020_SOFT_RESET_TC(1) | | |
1572 | S_008020_SOFT_RESET_TA(1) | | |
1573 | S_008020_SOFT_RESET_VC(1) | | |
1574 | S_008020_SOFT_RESET_VGT(1); | |
1575 | } | |
1576 | ||
1577 | if (reset_mask & RADEON_RESET_CP) { | |
1578 | grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | | |
1579 | S_008020_SOFT_RESET_VGT(1); | |
1580 | ||
1581 | srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); | |
1582 | } | |
1583 | ||
1584 | if (reset_mask & RADEON_RESET_DMA) { | |
1585 | if (rdev->family >= CHIP_RV770) | |
1586 | srbm_soft_reset |= RV770_SOFT_RESET_DMA; | |
1587 | else | |
1588 | srbm_soft_reset |= SOFT_RESET_DMA; | |
1589 | } | |
1590 | ||
f13f7731 AD |
1591 | if (reset_mask & RADEON_RESET_RLC) |
1592 | srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); | |
1593 | ||
1594 | if (reset_mask & RADEON_RESET_SEM) | |
1595 | srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); | |
1596 | ||
1597 | if (reset_mask & RADEON_RESET_IH) | |
1598 | srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); | |
1599 | ||
1600 | if (reset_mask & RADEON_RESET_GRBM) | |
1601 | srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); | |
1602 | ||
24178ec4 AD |
1603 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1604 | if (reset_mask & RADEON_RESET_MC) | |
1605 | srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); | |
1606 | } | |
f13f7731 AD |
1607 | |
1608 | if (reset_mask & RADEON_RESET_VMC) | |
1609 | srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); | |
1610 | ||
d3cb781e AD |
1611 | if (grbm_soft_reset) { |
1612 | tmp = RREG32(R_008020_GRBM_SOFT_RESET); | |
1613 | tmp |= grbm_soft_reset; | |
1614 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); | |
1615 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
1616 | tmp = RREG32(R_008020_GRBM_SOFT_RESET); | |
1617 | ||
1618 | udelay(50); | |
1619 | ||
1620 | tmp &= ~grbm_soft_reset; | |
1621 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
1622 | tmp = RREG32(R_008020_GRBM_SOFT_RESET); | |
1623 | } | |
1624 | ||
1625 | if (srbm_soft_reset) { | |
1626 | tmp = RREG32(SRBM_SOFT_RESET); | |
1627 | tmp |= srbm_soft_reset; | |
1628 | dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1629 | WREG32(SRBM_SOFT_RESET, tmp); | |
1630 | tmp = RREG32(SRBM_SOFT_RESET); | |
1631 | ||
1632 | udelay(50); | |
71e3d157 | 1633 | |
d3cb781e AD |
1634 | tmp &= ~srbm_soft_reset; |
1635 | WREG32(SRBM_SOFT_RESET, tmp); | |
1636 | tmp = RREG32(SRBM_SOFT_RESET); | |
1637 | } | |
71e3d157 AD |
1638 | |
1639 | /* Wait a little for things to settle down */ | |
1640 | mdelay(1); | |
1641 | ||
a3c1945a | 1642 | rv515_mc_resume(rdev, &save); |
d3cb781e | 1643 | udelay(50); |
410a3418 | 1644 | |
d3cb781e | 1645 | r600_print_gpu_status_regs(rdev); |
d3cb781e AD |
1646 | } |
1647 | ||
de9ae744 AD |
1648 | static void r600_gpu_pci_config_reset(struct radeon_device *rdev) |
1649 | { | |
1650 | struct rv515_mc_save save; | |
1651 | u32 tmp, i; | |
1652 | ||
1653 | dev_info(rdev->dev, "GPU pci config reset\n"); | |
1654 | ||
1655 | /* disable dpm? */ | |
1656 | ||
1657 | /* Disable CP parsing/prefetching */ | |
1658 | if (rdev->family >= CHIP_RV770) | |
1659 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); | |
1660 | else | |
1661 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1662 | ||
1663 | /* disable the RLC */ | |
1664 | WREG32(RLC_CNTL, 0); | |
1665 | ||
1666 | /* Disable DMA */ | |
1667 | tmp = RREG32(DMA_RB_CNTL); | |
1668 | tmp &= ~DMA_RB_ENABLE; | |
1669 | WREG32(DMA_RB_CNTL, tmp); | |
1670 | ||
1671 | mdelay(50); | |
1672 | ||
1673 | /* set mclk/sclk to bypass */ | |
1674 | if (rdev->family >= CHIP_RV770) | |
1675 | rv770_set_clk_bypass_mode(rdev); | |
1676 | /* disable BM */ | |
1677 | pci_clear_master(rdev->pdev); | |
1678 | /* disable mem access */ | |
1679 | rv515_mc_stop(rdev, &save); | |
1680 | if (r600_mc_wait_for_idle(rdev)) { | |
1681 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1682 | } | |
1683 | ||
1684 | /* BIF reset workaround. Not sure if this is needed on 6xx */ | |
1685 | tmp = RREG32(BUS_CNTL); | |
1686 | tmp |= VGA_COHE_SPEC_TIMER_DIS; | |
1687 | WREG32(BUS_CNTL, tmp); | |
1688 | ||
1689 | tmp = RREG32(BIF_SCRATCH0); | |
1690 | ||
1691 | /* reset */ | |
1692 | radeon_pci_config_reset(rdev); | |
1693 | mdelay(1); | |
1694 | ||
1695 | /* BIF reset workaround. Not sure if this is needed on 6xx */ | |
1696 | tmp = SOFT_RESET_BIF; | |
1697 | WREG32(SRBM_SOFT_RESET, tmp); | |
1698 | mdelay(1); | |
1699 | WREG32(SRBM_SOFT_RESET, 0); | |
1700 | ||
1701 | /* wait for asic to come out of reset */ | |
1702 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1703 | if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) | |
1704 | break; | |
1705 | udelay(1); | |
1706 | } | |
1707 | } | |
1708 | ||
d3cb781e AD |
1709 | int r600_asic_reset(struct radeon_device *rdev) |
1710 | { | |
f13f7731 AD |
1711 | u32 reset_mask; |
1712 | ||
1713 | reset_mask = r600_gpu_check_soft_reset(rdev); | |
1714 | ||
1715 | if (reset_mask) | |
1716 | r600_set_bios_scratch_engine_hung(rdev, true); | |
1717 | ||
de9ae744 | 1718 | /* try soft reset */ |
f13f7731 AD |
1719 | r600_gpu_soft_reset(rdev, reset_mask); |
1720 | ||
1721 | reset_mask = r600_gpu_check_soft_reset(rdev); | |
1722 | ||
de9ae744 AD |
1723 | /* try pci config reset */ |
1724 | if (reset_mask && radeon_hard_reset) | |
1725 | r600_gpu_pci_config_reset(rdev); | |
1726 | ||
1727 | reset_mask = r600_gpu_check_soft_reset(rdev); | |
1728 | ||
f13f7731 AD |
1729 | if (!reset_mask) |
1730 | r600_set_bios_scratch_engine_hung(rdev, false); | |
1731 | ||
1732 | return 0; | |
3ce0a23d JG |
1733 | } |
1734 | ||
123bc183 AD |
1735 | /** |
1736 | * r600_gfx_is_lockup - Check if the GFX engine is locked up | |
1737 | * | |
1738 | * @rdev: radeon_device pointer | |
1739 | * @ring: radeon_ring structure holding ring information | |
1740 | * | |
1741 | * Check if the GFX engine is locked up. | |
1742 | * Returns true if the engine appears to be locked up, false if not. | |
1743 | */ | |
1744 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
225758d8 | 1745 | { |
123bc183 AD |
1746 | u32 reset_mask = r600_gpu_check_soft_reset(rdev); |
1747 | ||
1748 | if (!(reset_mask & (RADEON_RESET_GFX | | |
1749 | RADEON_RESET_COMPUTE | | |
1750 | RADEON_RESET_CP))) { | |
069211e5 | 1751 | radeon_ring_lockup_update(ring); |
225758d8 JG |
1752 | return false; |
1753 | } | |
1754 | /* force CP activities */ | |
7b9ef16b | 1755 | radeon_ring_force_activity(rdev, ring); |
069211e5 | 1756 | return radeon_ring_test_lockup(rdev, ring); |
225758d8 JG |
1757 | } |
1758 | ||
416a2bd2 AD |
1759 | u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
1760 | u32 tiling_pipe_num, | |
1761 | u32 max_rb_num, | |
1762 | u32 total_max_rb_num, | |
1763 | u32 disabled_rb_mask) | |
3ce0a23d | 1764 | { |
416a2bd2 | 1765 | u32 rendering_pipe_num, rb_num_width, req_rb_num; |
f689e3ac | 1766 | u32 pipe_rb_ratio, pipe_rb_remain, tmp; |
416a2bd2 AD |
1767 | u32 data = 0, mask = 1 << (max_rb_num - 1); |
1768 | unsigned i, j; | |
3ce0a23d | 1769 | |
416a2bd2 | 1770 | /* mask out the RBs that don't exist on that asic */ |
f689e3ac MT |
1771 | tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); |
1772 | /* make sure at least one RB is available */ | |
1773 | if ((tmp & 0xff) != 0xff) | |
1774 | disabled_rb_mask = tmp; | |
3ce0a23d | 1775 | |
416a2bd2 AD |
1776 | rendering_pipe_num = 1 << tiling_pipe_num; |
1777 | req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); | |
1778 | BUG_ON(rendering_pipe_num < req_rb_num); | |
3ce0a23d | 1779 | |
416a2bd2 AD |
1780 | pipe_rb_ratio = rendering_pipe_num / req_rb_num; |
1781 | pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; | |
3ce0a23d | 1782 | |
416a2bd2 AD |
1783 | if (rdev->family <= CHIP_RV740) { |
1784 | /* r6xx/r7xx */ | |
1785 | rb_num_width = 2; | |
1786 | } else { | |
1787 | /* eg+ */ | |
1788 | rb_num_width = 4; | |
1789 | } | |
3ce0a23d | 1790 | |
416a2bd2 AD |
1791 | for (i = 0; i < max_rb_num; i++) { |
1792 | if (!(mask & disabled_rb_mask)) { | |
1793 | for (j = 0; j < pipe_rb_ratio; j++) { | |
1794 | data <<= rb_num_width; | |
1795 | data |= max_rb_num - i - 1; | |
1796 | } | |
1797 | if (pipe_rb_remain) { | |
1798 | data <<= rb_num_width; | |
1799 | data |= max_rb_num - i - 1; | |
1800 | pipe_rb_remain--; | |
1801 | } | |
1802 | } | |
1803 | mask >>= 1; | |
3ce0a23d JG |
1804 | } |
1805 | ||
416a2bd2 | 1806 | return data; |
3ce0a23d JG |
1807 | } |
1808 | ||
1809 | int r600_count_pipe_bits(uint32_t val) | |
1810 | { | |
ef8cf3a1 | 1811 | return hweight32(val); |
771fe6b9 JG |
1812 | } |
1813 | ||
1109ca09 | 1814 | static void r600_gpu_init(struct radeon_device *rdev) |
3ce0a23d JG |
1815 | { |
1816 | u32 tiling_config; | |
1817 | u32 ramcfg; | |
d03f5d59 AD |
1818 | u32 cc_rb_backend_disable; |
1819 | u32 cc_gc_shader_pipe_config; | |
3ce0a23d JG |
1820 | u32 tmp; |
1821 | int i, j; | |
1822 | u32 sq_config; | |
1823 | u32 sq_gpr_resource_mgmt_1 = 0; | |
1824 | u32 sq_gpr_resource_mgmt_2 = 0; | |
1825 | u32 sq_thread_resource_mgmt = 0; | |
1826 | u32 sq_stack_resource_mgmt_1 = 0; | |
1827 | u32 sq_stack_resource_mgmt_2 = 0; | |
416a2bd2 | 1828 | u32 disabled_rb_mask; |
3ce0a23d | 1829 | |
416a2bd2 | 1830 | rdev->config.r600.tiling_group_size = 256; |
3ce0a23d JG |
1831 | switch (rdev->family) { |
1832 | case CHIP_R600: | |
1833 | rdev->config.r600.max_pipes = 4; | |
1834 | rdev->config.r600.max_tile_pipes = 8; | |
1835 | rdev->config.r600.max_simds = 4; | |
1836 | rdev->config.r600.max_backends = 4; | |
1837 | rdev->config.r600.max_gprs = 256; | |
1838 | rdev->config.r600.max_threads = 192; | |
1839 | rdev->config.r600.max_stack_entries = 256; | |
1840 | rdev->config.r600.max_hw_contexts = 8; | |
1841 | rdev->config.r600.max_gs_threads = 16; | |
1842 | rdev->config.r600.sx_max_export_size = 128; | |
1843 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1844 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1845 | rdev->config.r600.sq_num_cf_insts = 2; | |
1846 | break; | |
1847 | case CHIP_RV630: | |
1848 | case CHIP_RV635: | |
1849 | rdev->config.r600.max_pipes = 2; | |
1850 | rdev->config.r600.max_tile_pipes = 2; | |
1851 | rdev->config.r600.max_simds = 3; | |
1852 | rdev->config.r600.max_backends = 1; | |
1853 | rdev->config.r600.max_gprs = 128; | |
1854 | rdev->config.r600.max_threads = 192; | |
1855 | rdev->config.r600.max_stack_entries = 128; | |
1856 | rdev->config.r600.max_hw_contexts = 8; | |
1857 | rdev->config.r600.max_gs_threads = 4; | |
1858 | rdev->config.r600.sx_max_export_size = 128; | |
1859 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1860 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1861 | rdev->config.r600.sq_num_cf_insts = 2; | |
1862 | break; | |
1863 | case CHIP_RV610: | |
1864 | case CHIP_RV620: | |
1865 | case CHIP_RS780: | |
1866 | case CHIP_RS880: | |
1867 | rdev->config.r600.max_pipes = 1; | |
1868 | rdev->config.r600.max_tile_pipes = 1; | |
1869 | rdev->config.r600.max_simds = 2; | |
1870 | rdev->config.r600.max_backends = 1; | |
1871 | rdev->config.r600.max_gprs = 128; | |
1872 | rdev->config.r600.max_threads = 192; | |
1873 | rdev->config.r600.max_stack_entries = 128; | |
1874 | rdev->config.r600.max_hw_contexts = 4; | |
1875 | rdev->config.r600.max_gs_threads = 4; | |
1876 | rdev->config.r600.sx_max_export_size = 128; | |
1877 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1878 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1879 | rdev->config.r600.sq_num_cf_insts = 1; | |
1880 | break; | |
1881 | case CHIP_RV670: | |
1882 | rdev->config.r600.max_pipes = 4; | |
1883 | rdev->config.r600.max_tile_pipes = 4; | |
1884 | rdev->config.r600.max_simds = 4; | |
1885 | rdev->config.r600.max_backends = 4; | |
1886 | rdev->config.r600.max_gprs = 192; | |
1887 | rdev->config.r600.max_threads = 192; | |
1888 | rdev->config.r600.max_stack_entries = 256; | |
1889 | rdev->config.r600.max_hw_contexts = 8; | |
1890 | rdev->config.r600.max_gs_threads = 16; | |
1891 | rdev->config.r600.sx_max_export_size = 128; | |
1892 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1893 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1894 | rdev->config.r600.sq_num_cf_insts = 2; | |
1895 | break; | |
1896 | default: | |
1897 | break; | |
1898 | } | |
1899 | ||
1900 | /* Initialize HDP */ | |
1901 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1902 | WREG32((0x2c14 + j), 0x00000000); | |
1903 | WREG32((0x2c18 + j), 0x00000000); | |
1904 | WREG32((0x2c1c + j), 0x00000000); | |
1905 | WREG32((0x2c20 + j), 0x00000000); | |
1906 | WREG32((0x2c24 + j), 0x00000000); | |
1907 | } | |
1908 | ||
1909 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1910 | ||
1911 | /* Setup tiling */ | |
1912 | tiling_config = 0; | |
1913 | ramcfg = RREG32(RAMCFG); | |
1914 | switch (rdev->config.r600.max_tile_pipes) { | |
1915 | case 1: | |
1916 | tiling_config |= PIPE_TILING(0); | |
1917 | break; | |
1918 | case 2: | |
1919 | tiling_config |= PIPE_TILING(1); | |
1920 | break; | |
1921 | case 4: | |
1922 | tiling_config |= PIPE_TILING(2); | |
1923 | break; | |
1924 | case 8: | |
1925 | tiling_config |= PIPE_TILING(3); | |
1926 | break; | |
1927 | default: | |
1928 | break; | |
1929 | } | |
d03f5d59 | 1930 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
961fb597 | 1931 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
3ce0a23d | 1932 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
881fe6c1 | 1933 | tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
416a2bd2 | 1934 | |
3ce0a23d JG |
1935 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
1936 | if (tmp > 3) { | |
1937 | tiling_config |= ROW_TILING(3); | |
1938 | tiling_config |= SAMPLE_SPLIT(3); | |
1939 | } else { | |
1940 | tiling_config |= ROW_TILING(tmp); | |
1941 | tiling_config |= SAMPLE_SPLIT(tmp); | |
1942 | } | |
1943 | tiling_config |= BANK_SWAPS(1); | |
d03f5d59 AD |
1944 | |
1945 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | |
416a2bd2 AD |
1946 | tmp = R6XX_MAX_BACKENDS - |
1947 | r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); | |
1948 | if (tmp < rdev->config.r600.max_backends) { | |
1949 | rdev->config.r600.max_backends = tmp; | |
1950 | } | |
1951 | ||
1952 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; | |
1953 | tmp = R6XX_MAX_PIPES - | |
1954 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); | |
1955 | if (tmp < rdev->config.r600.max_pipes) { | |
1956 | rdev->config.r600.max_pipes = tmp; | |
1957 | } | |
1958 | tmp = R6XX_MAX_SIMDS - | |
1959 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); | |
1960 | if (tmp < rdev->config.r600.max_simds) { | |
1961 | rdev->config.r600.max_simds = tmp; | |
1962 | } | |
1963 | ||
1964 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; | |
1965 | tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; | |
1966 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, | |
1967 | R6XX_MAX_BACKENDS, disabled_rb_mask); | |
1968 | tiling_config |= tmp << 16; | |
1969 | rdev->config.r600.backend_map = tmp; | |
1970 | ||
e7aeeba6 | 1971 | rdev->config.r600.tile_config = tiling_config; |
3ce0a23d JG |
1972 | WREG32(GB_TILING_CONFIG, tiling_config); |
1973 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); | |
1974 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); | |
4d75658b | 1975 | WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); |
3ce0a23d | 1976 | |
d03f5d59 | 1977 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
3ce0a23d JG |
1978 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
1979 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
1980 | ||
1981 | /* Setup some CP states */ | |
1982 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); | |
1983 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); | |
1984 | ||
1985 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | | |
1986 | SYNC_WALKER | SYNC_ALIGNER)); | |
1987 | /* Setup various GPU states */ | |
1988 | if (rdev->family == CHIP_RV670) | |
1989 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); | |
1990 | ||
1991 | tmp = RREG32(SX_DEBUG_1); | |
1992 | tmp |= SMX_EVENT_RELEASE; | |
1993 | if ((rdev->family > CHIP_R600)) | |
1994 | tmp |= ENABLE_NEW_SMX_ADDRESS; | |
1995 | WREG32(SX_DEBUG_1, tmp); | |
1996 | ||
1997 | if (((rdev->family) == CHIP_R600) || | |
1998 | ((rdev->family) == CHIP_RV630) || | |
1999 | ((rdev->family) == CHIP_RV610) || | |
2000 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2001 | ((rdev->family) == CHIP_RS780) || |
2002 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2003 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
2004 | } else { | |
2005 | WREG32(DB_DEBUG, 0); | |
2006 | } | |
2007 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | | |
2008 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); | |
2009 | ||
2010 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
2011 | WREG32(VGT_NUM_INSTANCES, 0); | |
2012 | ||
2013 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); | |
2014 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); | |
2015 | ||
2016 | tmp = RREG32(SQ_MS_FIFO_SIZES); | |
2017 | if (((rdev->family) == CHIP_RV610) || | |
2018 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2019 | ((rdev->family) == CHIP_RS780) || |
2020 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2021 | tmp = (CACHE_FIFO_SIZE(0xa) | |
2022 | FETCH_FIFO_HIWATER(0xa) | | |
2023 | DONE_FIFO_HIWATER(0xe0) | | |
2024 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
2025 | } else if (((rdev->family) == CHIP_R600) || | |
2026 | ((rdev->family) == CHIP_RV630)) { | |
2027 | tmp &= ~DONE_FIFO_HIWATER(0xff); | |
2028 | tmp |= DONE_FIFO_HIWATER(0x4); | |
2029 | } | |
2030 | WREG32(SQ_MS_FIFO_SIZES, tmp); | |
2031 | ||
2032 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
2033 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
2034 | */ | |
2035 | sq_config = RREG32(SQ_CONFIG); | |
2036 | sq_config &= ~(PS_PRIO(3) | | |
2037 | VS_PRIO(3) | | |
2038 | GS_PRIO(3) | | |
2039 | ES_PRIO(3)); | |
2040 | sq_config |= (DX9_CONSTS | | |
2041 | VC_ENABLE | | |
2042 | PS_PRIO(0) | | |
2043 | VS_PRIO(1) | | |
2044 | GS_PRIO(2) | | |
2045 | ES_PRIO(3)); | |
2046 | ||
2047 | if ((rdev->family) == CHIP_R600) { | |
2048 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | | |
2049 | NUM_VS_GPRS(124) | | |
2050 | NUM_CLAUSE_TEMP_GPRS(4)); | |
2051 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | | |
2052 | NUM_ES_GPRS(0)); | |
2053 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | | |
2054 | NUM_VS_THREADS(48) | | |
2055 | NUM_GS_THREADS(4) | | |
2056 | NUM_ES_THREADS(4)); | |
2057 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | | |
2058 | NUM_VS_STACK_ENTRIES(128)); | |
2059 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | | |
2060 | NUM_ES_STACK_ENTRIES(0)); | |
2061 | } else if (((rdev->family) == CHIP_RV610) || | |
2062 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2063 | ((rdev->family) == CHIP_RS780) || |
2064 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2065 | /* no vertex cache */ |
2066 | sq_config &= ~VC_ENABLE; | |
2067 | ||
2068 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
2069 | NUM_VS_GPRS(44) | | |
2070 | NUM_CLAUSE_TEMP_GPRS(2)); | |
2071 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
2072 | NUM_ES_GPRS(17)); | |
2073 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
2074 | NUM_VS_THREADS(78) | | |
2075 | NUM_GS_THREADS(4) | | |
2076 | NUM_ES_THREADS(31)); | |
2077 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
2078 | NUM_VS_STACK_ENTRIES(40)); | |
2079 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
2080 | NUM_ES_STACK_ENTRIES(16)); | |
2081 | } else if (((rdev->family) == CHIP_RV630) || | |
2082 | ((rdev->family) == CHIP_RV635)) { | |
2083 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
2084 | NUM_VS_GPRS(44) | | |
2085 | NUM_CLAUSE_TEMP_GPRS(2)); | |
2086 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | | |
2087 | NUM_ES_GPRS(18)); | |
2088 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
2089 | NUM_VS_THREADS(78) | | |
2090 | NUM_GS_THREADS(4) | | |
2091 | NUM_ES_THREADS(31)); | |
2092 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
2093 | NUM_VS_STACK_ENTRIES(40)); | |
2094 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
2095 | NUM_ES_STACK_ENTRIES(16)); | |
2096 | } else if ((rdev->family) == CHIP_RV670) { | |
2097 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
2098 | NUM_VS_GPRS(44) | | |
2099 | NUM_CLAUSE_TEMP_GPRS(2)); | |
2100 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
2101 | NUM_ES_GPRS(17)); | |
2102 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
2103 | NUM_VS_THREADS(78) | | |
2104 | NUM_GS_THREADS(4) | | |
2105 | NUM_ES_THREADS(31)); | |
2106 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | | |
2107 | NUM_VS_STACK_ENTRIES(64)); | |
2108 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | | |
2109 | NUM_ES_STACK_ENTRIES(64)); | |
2110 | } | |
2111 | ||
2112 | WREG32(SQ_CONFIG, sq_config); | |
2113 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
2114 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
2115 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
2116 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
2117 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
2118 | ||
2119 | if (((rdev->family) == CHIP_RV610) || | |
2120 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2121 | ((rdev->family) == CHIP_RS780) || |
2122 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2123 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
2124 | } else { | |
2125 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); | |
2126 | } | |
2127 | ||
2128 | /* More default values. 2D/3D driver should adjust as needed */ | |
2129 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | | |
2130 | S1_X(0x4) | S1_Y(0xc))); | |
2131 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | | |
2132 | S1_X(0x2) | S1_Y(0x2) | | |
2133 | S2_X(0xa) | S2_Y(0x6) | | |
2134 | S3_X(0x6) | S3_Y(0xa))); | |
2135 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | | |
2136 | S1_X(0x4) | S1_Y(0xc) | | |
2137 | S2_X(0x1) | S2_Y(0x6) | | |
2138 | S3_X(0xa) | S3_Y(0xe))); | |
2139 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | | |
2140 | S5_X(0x0) | S5_Y(0x0) | | |
2141 | S6_X(0xb) | S6_Y(0x4) | | |
2142 | S7_X(0x7) | S7_Y(0x8))); | |
2143 | ||
2144 | WREG32(VGT_STRMOUT_EN, 0); | |
2145 | tmp = rdev->config.r600.max_pipes * 16; | |
2146 | switch (rdev->family) { | |
2147 | case CHIP_RV610: | |
3ce0a23d | 2148 | case CHIP_RV620: |
ee59f2b4 AD |
2149 | case CHIP_RS780: |
2150 | case CHIP_RS880: | |
3ce0a23d JG |
2151 | tmp += 32; |
2152 | break; | |
2153 | case CHIP_RV670: | |
2154 | tmp += 128; | |
2155 | break; | |
2156 | default: | |
2157 | break; | |
2158 | } | |
2159 | if (tmp > 256) { | |
2160 | tmp = 256; | |
2161 | } | |
2162 | WREG32(VGT_ES_PER_GS, 128); | |
2163 | WREG32(VGT_GS_PER_ES, tmp); | |
2164 | WREG32(VGT_GS_PER_VS, 2); | |
2165 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
2166 | ||
2167 | /* more default values. 2D/3D driver should adjust as needed */ | |
2168 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
2169 | WREG32(VGT_STRMOUT_EN, 0); | |
2170 | WREG32(SX_MISC, 0); | |
2171 | WREG32(PA_SC_MODE_CNTL, 0); | |
2172 | WREG32(PA_SC_AA_CONFIG, 0); | |
2173 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
2174 | WREG32(SPI_INPUT_Z, 0); | |
2175 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
2176 | WREG32(CB_COLOR7_FRAG, 0); | |
2177 | ||
2178 | /* Clear render buffer base addresses */ | |
2179 | WREG32(CB_COLOR0_BASE, 0); | |
2180 | WREG32(CB_COLOR1_BASE, 0); | |
2181 | WREG32(CB_COLOR2_BASE, 0); | |
2182 | WREG32(CB_COLOR3_BASE, 0); | |
2183 | WREG32(CB_COLOR4_BASE, 0); | |
2184 | WREG32(CB_COLOR5_BASE, 0); | |
2185 | WREG32(CB_COLOR6_BASE, 0); | |
2186 | WREG32(CB_COLOR7_BASE, 0); | |
2187 | WREG32(CB_COLOR7_FRAG, 0); | |
2188 | ||
2189 | switch (rdev->family) { | |
2190 | case CHIP_RV610: | |
3ce0a23d | 2191 | case CHIP_RV620: |
ee59f2b4 AD |
2192 | case CHIP_RS780: |
2193 | case CHIP_RS880: | |
3ce0a23d JG |
2194 | tmp = TC_L2_SIZE(8); |
2195 | break; | |
2196 | case CHIP_RV630: | |
2197 | case CHIP_RV635: | |
2198 | tmp = TC_L2_SIZE(4); | |
2199 | break; | |
2200 | case CHIP_R600: | |
2201 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; | |
2202 | break; | |
2203 | default: | |
2204 | tmp = TC_L2_SIZE(0); | |
2205 | break; | |
2206 | } | |
2207 | WREG32(TC_CNTL, tmp); | |
2208 | ||
2209 | tmp = RREG32(HDP_HOST_PATH_CNTL); | |
2210 | WREG32(HDP_HOST_PATH_CNTL, tmp); | |
2211 | ||
2212 | tmp = RREG32(ARB_POP); | |
2213 | tmp |= ENABLE_TC128; | |
2214 | WREG32(ARB_POP, tmp); | |
2215 | ||
2216 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
2217 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
2218 | NUM_CLIP_SEQ(3))); | |
2219 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); | |
b866d133 | 2220 | WREG32(VC_ENHANCE, 0); |
3ce0a23d JG |
2221 | } |
2222 | ||
2223 | ||
771fe6b9 JG |
2224 | /* |
2225 | * Indirect registers accessor | |
2226 | */ | |
3ce0a23d JG |
2227 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
2228 | { | |
0a5b7b0b | 2229 | unsigned long flags; |
3ce0a23d JG |
2230 | u32 r; |
2231 | ||
0a5b7b0b | 2232 | spin_lock_irqsave(&rdev->pciep_idx_lock, flags); |
3ce0a23d JG |
2233 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
2234 | (void)RREG32(PCIE_PORT_INDEX); | |
2235 | r = RREG32(PCIE_PORT_DATA); | |
0a5b7b0b | 2236 | spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); |
3ce0a23d JG |
2237 | return r; |
2238 | } | |
2239 | ||
2240 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2241 | { | |
0a5b7b0b AD |
2242 | unsigned long flags; |
2243 | ||
2244 | spin_lock_irqsave(&rdev->pciep_idx_lock, flags); | |
3ce0a23d JG |
2245 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
2246 | (void)RREG32(PCIE_PORT_INDEX); | |
2247 | WREG32(PCIE_PORT_DATA, (v)); | |
2248 | (void)RREG32(PCIE_PORT_DATA); | |
0a5b7b0b | 2249 | spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); |
3ce0a23d JG |
2250 | } |
2251 | ||
3ce0a23d JG |
2252 | /* |
2253 | * CP & Ring | |
2254 | */ | |
2255 | void r600_cp_stop(struct radeon_device *rdev) | |
2256 | { | |
50efa51a AD |
2257 | if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
2258 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
3ce0a23d | 2259 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
724c80e1 | 2260 | WREG32(SCRATCH_UMSK, 0); |
4d75658b | 2261 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
3ce0a23d JG |
2262 | } |
2263 | ||
d8f60cfc | 2264 | int r600_init_microcode(struct radeon_device *rdev) |
3ce0a23d | 2265 | { |
3ce0a23d | 2266 | const char *chip_name; |
d8f60cfc | 2267 | const char *rlc_chip_name; |
66229b20 AD |
2268 | const char *smc_chip_name = "RV770"; |
2269 | size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; | |
3ce0a23d JG |
2270 | char fw_name[30]; |
2271 | int err; | |
2272 | ||
2273 | DRM_DEBUG("\n"); | |
2274 | ||
3ce0a23d | 2275 | switch (rdev->family) { |
d8f60cfc AD |
2276 | case CHIP_R600: |
2277 | chip_name = "R600"; | |
2278 | rlc_chip_name = "R600"; | |
2279 | break; | |
2280 | case CHIP_RV610: | |
2281 | chip_name = "RV610"; | |
2282 | rlc_chip_name = "R600"; | |
2283 | break; | |
2284 | case CHIP_RV630: | |
2285 | chip_name = "RV630"; | |
2286 | rlc_chip_name = "R600"; | |
2287 | break; | |
2288 | case CHIP_RV620: | |
2289 | chip_name = "RV620"; | |
2290 | rlc_chip_name = "R600"; | |
2291 | break; | |
2292 | case CHIP_RV635: | |
2293 | chip_name = "RV635"; | |
2294 | rlc_chip_name = "R600"; | |
2295 | break; | |
2296 | case CHIP_RV670: | |
2297 | chip_name = "RV670"; | |
2298 | rlc_chip_name = "R600"; | |
2299 | break; | |
3ce0a23d | 2300 | case CHIP_RS780: |
d8f60cfc AD |
2301 | case CHIP_RS880: |
2302 | chip_name = "RS780"; | |
2303 | rlc_chip_name = "R600"; | |
2304 | break; | |
2305 | case CHIP_RV770: | |
2306 | chip_name = "RV770"; | |
2307 | rlc_chip_name = "R700"; | |
66229b20 AD |
2308 | smc_chip_name = "RV770"; |
2309 | smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); | |
d8f60cfc | 2310 | break; |
3ce0a23d | 2311 | case CHIP_RV730: |
d8f60cfc AD |
2312 | chip_name = "RV730"; |
2313 | rlc_chip_name = "R700"; | |
66229b20 AD |
2314 | smc_chip_name = "RV730"; |
2315 | smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); | |
d8f60cfc AD |
2316 | break; |
2317 | case CHIP_RV710: | |
2318 | chip_name = "RV710"; | |
2319 | rlc_chip_name = "R700"; | |
66229b20 AD |
2320 | smc_chip_name = "RV710"; |
2321 | smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); | |
2322 | break; | |
2323 | case CHIP_RV740: | |
2324 | chip_name = "RV730"; | |
2325 | rlc_chip_name = "R700"; | |
2326 | smc_chip_name = "RV740"; | |
2327 | smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); | |
d8f60cfc | 2328 | break; |
fe251e2f AD |
2329 | case CHIP_CEDAR: |
2330 | chip_name = "CEDAR"; | |
45f9a39b | 2331 | rlc_chip_name = "CEDAR"; |
dc50ba7f AD |
2332 | smc_chip_name = "CEDAR"; |
2333 | smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); | |
fe251e2f AD |
2334 | break; |
2335 | case CHIP_REDWOOD: | |
2336 | chip_name = "REDWOOD"; | |
45f9a39b | 2337 | rlc_chip_name = "REDWOOD"; |
dc50ba7f AD |
2338 | smc_chip_name = "REDWOOD"; |
2339 | smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); | |
fe251e2f AD |
2340 | break; |
2341 | case CHIP_JUNIPER: | |
2342 | chip_name = "JUNIPER"; | |
45f9a39b | 2343 | rlc_chip_name = "JUNIPER"; |
dc50ba7f AD |
2344 | smc_chip_name = "JUNIPER"; |
2345 | smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); | |
fe251e2f AD |
2346 | break; |
2347 | case CHIP_CYPRESS: | |
2348 | case CHIP_HEMLOCK: | |
2349 | chip_name = "CYPRESS"; | |
45f9a39b | 2350 | rlc_chip_name = "CYPRESS"; |
dc50ba7f AD |
2351 | smc_chip_name = "CYPRESS"; |
2352 | smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); | |
fe251e2f | 2353 | break; |
439bd6cd AD |
2354 | case CHIP_PALM: |
2355 | chip_name = "PALM"; | |
2356 | rlc_chip_name = "SUMO"; | |
2357 | break; | |
d5c5a72f AD |
2358 | case CHIP_SUMO: |
2359 | chip_name = "SUMO"; | |
2360 | rlc_chip_name = "SUMO"; | |
2361 | break; | |
2362 | case CHIP_SUMO2: | |
2363 | chip_name = "SUMO2"; | |
2364 | rlc_chip_name = "SUMO"; | |
2365 | break; | |
3ce0a23d JG |
2366 | default: BUG(); |
2367 | } | |
2368 | ||
fe251e2f AD |
2369 | if (rdev->family >= CHIP_CEDAR) { |
2370 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; | |
2371 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; | |
45f9a39b | 2372 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
fe251e2f | 2373 | } else if (rdev->family >= CHIP_RV770) { |
3ce0a23d JG |
2374 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
2375 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
d8f60cfc | 2376 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
3ce0a23d | 2377 | } else { |
138e4e16 AD |
2378 | pfp_req_size = R600_PFP_UCODE_SIZE * 4; |
2379 | me_req_size = R600_PM4_UCODE_SIZE * 12; | |
2380 | rlc_req_size = R600_RLC_UCODE_SIZE * 4; | |
3ce0a23d JG |
2381 | } |
2382 | ||
d8f60cfc | 2383 | DRM_INFO("Loading %s Microcode\n", chip_name); |
3ce0a23d JG |
2384 | |
2385 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
0a168933 | 2386 | err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); |
3ce0a23d JG |
2387 | if (err) |
2388 | goto out; | |
2389 | if (rdev->pfp_fw->size != pfp_req_size) { | |
2390 | printk(KERN_ERR | |
2391 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2392 | rdev->pfp_fw->size, fw_name); | |
2393 | err = -EINVAL; | |
2394 | goto out; | |
2395 | } | |
2396 | ||
2397 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
0a168933 | 2398 | err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
3ce0a23d JG |
2399 | if (err) |
2400 | goto out; | |
2401 | if (rdev->me_fw->size != me_req_size) { | |
2402 | printk(KERN_ERR | |
2403 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2404 | rdev->me_fw->size, fw_name); | |
2405 | err = -EINVAL; | |
2406 | } | |
d8f60cfc AD |
2407 | |
2408 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
0a168933 | 2409 | err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); |
d8f60cfc AD |
2410 | if (err) |
2411 | goto out; | |
2412 | if (rdev->rlc_fw->size != rlc_req_size) { | |
2413 | printk(KERN_ERR | |
2414 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", | |
2415 | rdev->rlc_fw->size, fw_name); | |
2416 | err = -EINVAL; | |
2417 | } | |
2418 | ||
dc50ba7f | 2419 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { |
66229b20 | 2420 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); |
0a168933 | 2421 | err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); |
8a53fa23 AD |
2422 | if (err) { |
2423 | printk(KERN_ERR | |
2424 | "smc: error loading firmware \"%s\"\n", | |
2425 | fw_name); | |
2426 | release_firmware(rdev->smc_fw); | |
2427 | rdev->smc_fw = NULL; | |
d8367112 | 2428 | err = 0; |
8a53fa23 | 2429 | } else if (rdev->smc_fw->size != smc_req_size) { |
66229b20 AD |
2430 | printk(KERN_ERR |
2431 | "smc: Bogus length %zu in firmware \"%s\"\n", | |
2432 | rdev->smc_fw->size, fw_name); | |
2433 | err = -EINVAL; | |
2434 | } | |
2435 | } | |
2436 | ||
3ce0a23d | 2437 | out: |
3ce0a23d JG |
2438 | if (err) { |
2439 | if (err != -EINVAL) | |
2440 | printk(KERN_ERR | |
2441 | "r600_cp: Failed to load firmware \"%s\"\n", | |
2442 | fw_name); | |
2443 | release_firmware(rdev->pfp_fw); | |
2444 | rdev->pfp_fw = NULL; | |
2445 | release_firmware(rdev->me_fw); | |
2446 | rdev->me_fw = NULL; | |
d8f60cfc AD |
2447 | release_firmware(rdev->rlc_fw); |
2448 | rdev->rlc_fw = NULL; | |
66229b20 AD |
2449 | release_firmware(rdev->smc_fw); |
2450 | rdev->smc_fw = NULL; | |
3ce0a23d JG |
2451 | } |
2452 | return err; | |
2453 | } | |
2454 | ||
ea31bf69 AD |
2455 | u32 r600_gfx_get_rptr(struct radeon_device *rdev, |
2456 | struct radeon_ring *ring) | |
2457 | { | |
2458 | u32 rptr; | |
2459 | ||
2460 | if (rdev->wb.enabled) | |
2461 | rptr = rdev->wb.wb[ring->rptr_offs/4]; | |
2462 | else | |
2463 | rptr = RREG32(R600_CP_RB_RPTR); | |
2464 | ||
2465 | return rptr; | |
2466 | } | |
2467 | ||
2468 | u32 r600_gfx_get_wptr(struct radeon_device *rdev, | |
2469 | struct radeon_ring *ring) | |
2470 | { | |
2471 | u32 wptr; | |
2472 | ||
2473 | wptr = RREG32(R600_CP_RB_WPTR); | |
2474 | ||
2475 | return wptr; | |
2476 | } | |
2477 | ||
2478 | void r600_gfx_set_wptr(struct radeon_device *rdev, | |
2479 | struct radeon_ring *ring) | |
2480 | { | |
2481 | WREG32(R600_CP_RB_WPTR, ring->wptr); | |
2482 | (void)RREG32(R600_CP_RB_WPTR); | |
2483 | } | |
2484 | ||
3ce0a23d JG |
2485 | static int r600_cp_load_microcode(struct radeon_device *rdev) |
2486 | { | |
2487 | const __be32 *fw_data; | |
2488 | int i; | |
2489 | ||
2490 | if (!rdev->me_fw || !rdev->pfp_fw) | |
2491 | return -EINVAL; | |
2492 | ||
2493 | r600_cp_stop(rdev); | |
2494 | ||
4eace7fd CC |
2495 | WREG32(CP_RB_CNTL, |
2496 | #ifdef __BIG_ENDIAN | |
2497 | BUF_SWAP_32BIT | | |
2498 | #endif | |
2499 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
3ce0a23d JG |
2500 | |
2501 | /* Reset cp */ | |
2502 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2503 | RREG32(GRBM_SOFT_RESET); | |
2504 | mdelay(15); | |
2505 | WREG32(GRBM_SOFT_RESET, 0); | |
2506 | ||
2507 | WREG32(CP_ME_RAM_WADDR, 0); | |
2508 | ||
2509 | fw_data = (const __be32 *)rdev->me_fw->data; | |
2510 | WREG32(CP_ME_RAM_WADDR, 0); | |
138e4e16 | 2511 | for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) |
3ce0a23d JG |
2512 | WREG32(CP_ME_RAM_DATA, |
2513 | be32_to_cpup(fw_data++)); | |
2514 | ||
2515 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
2516 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
138e4e16 | 2517 | for (i = 0; i < R600_PFP_UCODE_SIZE; i++) |
3ce0a23d JG |
2518 | WREG32(CP_PFP_UCODE_DATA, |
2519 | be32_to_cpup(fw_data++)); | |
2520 | ||
2521 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
2522 | WREG32(CP_ME_RAM_WADDR, 0); | |
2523 | WREG32(CP_ME_RAM_RADDR, 0); | |
2524 | return 0; | |
2525 | } | |
2526 | ||
2527 | int r600_cp_start(struct radeon_device *rdev) | |
2528 | { | |
e32eb50d | 2529 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3ce0a23d JG |
2530 | int r; |
2531 | uint32_t cp_me; | |
2532 | ||
e32eb50d | 2533 | r = radeon_ring_lock(rdev, ring, 7); |
3ce0a23d JG |
2534 | if (r) { |
2535 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
2536 | return r; | |
2537 | } | |
e32eb50d CK |
2538 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
2539 | radeon_ring_write(ring, 0x1); | |
7e7b41d2 | 2540 | if (rdev->family >= CHIP_RV770) { |
e32eb50d CK |
2541 | radeon_ring_write(ring, 0x0); |
2542 | radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); | |
fe251e2f | 2543 | } else { |
e32eb50d CK |
2544 | radeon_ring_write(ring, 0x3); |
2545 | radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); | |
3ce0a23d | 2546 | } |
e32eb50d CK |
2547 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
2548 | radeon_ring_write(ring, 0); | |
2549 | radeon_ring_write(ring, 0); | |
2550 | radeon_ring_unlock_commit(rdev, ring); | |
3ce0a23d JG |
2551 | |
2552 | cp_me = 0xff; | |
2553 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | |
2554 | return 0; | |
2555 | } | |
2556 | ||
2557 | int r600_cp_resume(struct radeon_device *rdev) | |
2558 | { | |
e32eb50d | 2559 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3ce0a23d JG |
2560 | u32 tmp; |
2561 | u32 rb_bufsz; | |
2562 | int r; | |
2563 | ||
2564 | /* Reset cp */ | |
2565 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2566 | RREG32(GRBM_SOFT_RESET); | |
2567 | mdelay(15); | |
2568 | WREG32(GRBM_SOFT_RESET, 0); | |
2569 | ||
2570 | /* Set ring buffer size */ | |
b72a8925 DV |
2571 | rb_bufsz = order_base_2(ring->ring_size / 8); |
2572 | tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | |
3ce0a23d | 2573 | #ifdef __BIG_ENDIAN |
d6f28938 | 2574 | tmp |= BUF_SWAP_32BIT; |
3ce0a23d | 2575 | #endif |
d6f28938 | 2576 | WREG32(CP_RB_CNTL, tmp); |
15d3332f | 2577 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
3ce0a23d JG |
2578 | |
2579 | /* Set the write pointer delay */ | |
2580 | WREG32(CP_RB_WPTR_DELAY, 0); | |
2581 | ||
2582 | /* Initialize the ring buffer's read and write pointers */ | |
3ce0a23d JG |
2583 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
2584 | WREG32(CP_RB_RPTR_WR, 0); | |
e32eb50d CK |
2585 | ring->wptr = 0; |
2586 | WREG32(CP_RB_WPTR, ring->wptr); | |
724c80e1 AD |
2587 | |
2588 | /* set the wb address whether it's enabled or not */ | |
4eace7fd | 2589 | WREG32(CP_RB_RPTR_ADDR, |
4eace7fd | 2590 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
724c80e1 AD |
2591 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
2592 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | |
2593 | ||
2594 | if (rdev->wb.enabled) | |
2595 | WREG32(SCRATCH_UMSK, 0xff); | |
2596 | else { | |
2597 | tmp |= RB_NO_UPDATE; | |
2598 | WREG32(SCRATCH_UMSK, 0); | |
2599 | } | |
2600 | ||
3ce0a23d JG |
2601 | mdelay(1); |
2602 | WREG32(CP_RB_CNTL, tmp); | |
2603 | ||
e32eb50d | 2604 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
3ce0a23d JG |
2605 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
2606 | ||
e32eb50d | 2607 | ring->rptr = RREG32(CP_RB_RPTR); |
3ce0a23d JG |
2608 | |
2609 | r600_cp_start(rdev); | |
e32eb50d | 2610 | ring->ready = true; |
f712812e | 2611 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
3ce0a23d | 2612 | if (r) { |
e32eb50d | 2613 | ring->ready = false; |
3ce0a23d JG |
2614 | return r; |
2615 | } | |
b9ace36f | 2616 | |
50efa51a | 2617 | if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
b9ace36f AD |
2618 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
2619 | ||
3ce0a23d JG |
2620 | return 0; |
2621 | } | |
2622 | ||
e32eb50d | 2623 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) |
3ce0a23d JG |
2624 | { |
2625 | u32 rb_bufsz; | |
45df6803 | 2626 | int r; |
3ce0a23d JG |
2627 | |
2628 | /* Align ring size */ | |
b72a8925 | 2629 | rb_bufsz = order_base_2(ring_size / 8); |
3ce0a23d | 2630 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
e32eb50d CK |
2631 | ring->ring_size = ring_size; |
2632 | ring->align_mask = 16 - 1; | |
45df6803 | 2633 | |
89d35807 AD |
2634 | if (radeon_ring_supports_scratch_reg(rdev, ring)) { |
2635 | r = radeon_scratch_get(rdev, &ring->rptr_save_reg); | |
2636 | if (r) { | |
2637 | DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); | |
2638 | ring->rptr_save_reg = 0; | |
2639 | } | |
45df6803 | 2640 | } |
3ce0a23d JG |
2641 | } |
2642 | ||
655efd3d JG |
2643 | void r600_cp_fini(struct radeon_device *rdev) |
2644 | { | |
45df6803 | 2645 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
655efd3d | 2646 | r600_cp_stop(rdev); |
45df6803 CK |
2647 | radeon_ring_fini(rdev, ring); |
2648 | radeon_scratch_free(rdev, ring->rptr_save_reg); | |
655efd3d JG |
2649 | } |
2650 | ||
3ce0a23d JG |
2651 | /* |
2652 | * GPU scratch registers helpers function. | |
2653 | */ | |
2654 | void r600_scratch_init(struct radeon_device *rdev) | |
2655 | { | |
2656 | int i; | |
2657 | ||
2658 | rdev->scratch.num_reg = 7; | |
724c80e1 | 2659 | rdev->scratch.reg_base = SCRATCH_REG0; |
3ce0a23d JG |
2660 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
2661 | rdev->scratch.free[i] = true; | |
724c80e1 | 2662 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
3ce0a23d JG |
2663 | } |
2664 | } | |
2665 | ||
e32eb50d | 2666 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d JG |
2667 | { |
2668 | uint32_t scratch; | |
2669 | uint32_t tmp = 0; | |
8b25ed34 | 2670 | unsigned i; |
3ce0a23d JG |
2671 | int r; |
2672 | ||
2673 | r = radeon_scratch_get(rdev, &scratch); | |
2674 | if (r) { | |
2675 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
2676 | return r; | |
2677 | } | |
2678 | WREG32(scratch, 0xCAFEDEAD); | |
e32eb50d | 2679 | r = radeon_ring_lock(rdev, ring, 3); |
3ce0a23d | 2680 | if (r) { |
8b25ed34 | 2681 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); |
3ce0a23d JG |
2682 | radeon_scratch_free(rdev, scratch); |
2683 | return r; | |
2684 | } | |
e32eb50d CK |
2685 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2686 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2687 | radeon_ring_write(ring, 0xDEADBEEF); | |
2688 | radeon_ring_unlock_commit(rdev, ring); | |
3ce0a23d JG |
2689 | for (i = 0; i < rdev->usec_timeout; i++) { |
2690 | tmp = RREG32(scratch); | |
2691 | if (tmp == 0xDEADBEEF) | |
2692 | break; | |
2693 | DRM_UDELAY(1); | |
2694 | } | |
2695 | if (i < rdev->usec_timeout) { | |
8b25ed34 | 2696 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
3ce0a23d | 2697 | } else { |
bf852799 | 2698 | DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
8b25ed34 | 2699 | ring->idx, scratch, tmp); |
3ce0a23d JG |
2700 | r = -EINVAL; |
2701 | } | |
2702 | radeon_scratch_free(rdev, scratch); | |
2703 | return r; | |
2704 | } | |
2705 | ||
4d75658b AD |
2706 | /* |
2707 | * CP fences/semaphores | |
2708 | */ | |
2709 | ||
3ce0a23d JG |
2710 | void r600_fence_ring_emit(struct radeon_device *rdev, |
2711 | struct radeon_fence *fence) | |
2712 | { | |
e32eb50d | 2713 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
d45b964a AD |
2714 | u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | |
2715 | PACKET3_SH_ACTION_ENA; | |
2716 | ||
2717 | if (rdev->family >= CHIP_RV770) | |
2718 | cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; | |
7b1f2485 | 2719 | |
d0f8a854 | 2720 | if (rdev->wb.use_event) { |
30eb77f4 | 2721 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
77b1bad4 | 2722 | /* flush read cache over gart */ |
e32eb50d | 2723 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
d45b964a | 2724 | radeon_ring_write(ring, cp_coher_cntl); |
e32eb50d CK |
2725 | radeon_ring_write(ring, 0xFFFFFFFF); |
2726 | radeon_ring_write(ring, 0); | |
2727 | radeon_ring_write(ring, 10); /* poll interval */ | |
d0f8a854 | 2728 | /* EVENT_WRITE_EOP - flush caches, send int */ |
e32eb50d CK |
2729 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
2730 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); | |
2731 | radeon_ring_write(ring, addr & 0xffffffff); | |
2732 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); | |
2733 | radeon_ring_write(ring, fence->seq); | |
2734 | radeon_ring_write(ring, 0); | |
d0f8a854 | 2735 | } else { |
77b1bad4 | 2736 | /* flush read cache over gart */ |
e32eb50d | 2737 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
d45b964a | 2738 | radeon_ring_write(ring, cp_coher_cntl); |
e32eb50d CK |
2739 | radeon_ring_write(ring, 0xFFFFFFFF); |
2740 | radeon_ring_write(ring, 0); | |
2741 | radeon_ring_write(ring, 10); /* poll interval */ | |
2742 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); | |
2743 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); | |
d0f8a854 | 2744 | /* wait for 3D idle clean */ |
e32eb50d CK |
2745 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2746 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2747 | radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | |
d0f8a854 | 2748 | /* Emit fence sequence & fire IRQ */ |
e32eb50d CK |
2749 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2750 | radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2751 | radeon_ring_write(ring, fence->seq); | |
d0f8a854 | 2752 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
e32eb50d CK |
2753 | radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); |
2754 | radeon_ring_write(ring, RB_INT_STAT); | |
d0f8a854 | 2755 | } |
3ce0a23d JG |
2756 | } |
2757 | ||
1654b817 | 2758 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 2759 | struct radeon_ring *ring, |
15d3332f | 2760 | struct radeon_semaphore *semaphore, |
7b1f2485 | 2761 | bool emit_wait) |
15d3332f CK |
2762 | { |
2763 | uint64_t addr = semaphore->gpu_addr; | |
2764 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; | |
2765 | ||
0be70439 CK |
2766 | if (rdev->family < CHIP_CAYMAN) |
2767 | sel |= PACKET3_SEM_WAIT_ON_SIGNAL; | |
2768 | ||
e32eb50d CK |
2769 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); |
2770 | radeon_ring_write(ring, addr & 0xffffffff); | |
2771 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); | |
1654b817 CK |
2772 | |
2773 | return true; | |
15d3332f CK |
2774 | } |
2775 | ||
072b5acc AD |
2776 | /** |
2777 | * r600_copy_cpdma - copy pages using the CP DMA engine | |
2778 | * | |
2779 | * @rdev: radeon_device pointer | |
2780 | * @src_offset: src GPU address | |
2781 | * @dst_offset: dst GPU address | |
2782 | * @num_gpu_pages: number of GPU pages to xfer | |
2783 | * @fence: radeon fence object | |
2784 | * | |
2785 | * Copy GPU paging using the CP DMA engine (r6xx+). | |
2786 | * Used by the radeon ttm implementation to move pages if | |
2787 | * registered as the asic copy callback. | |
2788 | */ | |
2789 | int r600_copy_cpdma(struct radeon_device *rdev, | |
2790 | uint64_t src_offset, uint64_t dst_offset, | |
2791 | unsigned num_gpu_pages, | |
2792 | struct radeon_fence **fence) | |
2793 | { | |
2794 | struct radeon_semaphore *sem = NULL; | |
2795 | int ring_index = rdev->asic->copy.blit_ring_index; | |
2796 | struct radeon_ring *ring = &rdev->ring[ring_index]; | |
2797 | u32 size_in_bytes, cur_size_in_bytes, tmp; | |
2798 | int i, num_loops; | |
2799 | int r = 0; | |
2800 | ||
2801 | r = radeon_semaphore_create(rdev, &sem); | |
2802 | if (r) { | |
2803 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
2804 | return r; | |
2805 | } | |
2806 | ||
2807 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); | |
2808 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); | |
745a39a9 | 2809 | r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); |
072b5acc AD |
2810 | if (r) { |
2811 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
2812 | radeon_semaphore_free(rdev, &sem, NULL); | |
2813 | return r; | |
2814 | } | |
2815 | ||
1654b817 CK |
2816 | radeon_semaphore_sync_to(sem, *fence); |
2817 | radeon_semaphore_sync_rings(rdev, sem, ring->idx); | |
072b5acc | 2818 | |
745a39a9 AD |
2819 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2820 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2821 | radeon_ring_write(ring, WAIT_3D_IDLE_bit); | |
072b5acc AD |
2822 | for (i = 0; i < num_loops; i++) { |
2823 | cur_size_in_bytes = size_in_bytes; | |
2824 | if (cur_size_in_bytes > 0x1fffff) | |
2825 | cur_size_in_bytes = 0x1fffff; | |
2826 | size_in_bytes -= cur_size_in_bytes; | |
2827 | tmp = upper_32_bits(src_offset) & 0xff; | |
2828 | if (size_in_bytes == 0) | |
2829 | tmp |= PACKET3_CP_DMA_CP_SYNC; | |
2830 | radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); | |
2831 | radeon_ring_write(ring, src_offset & 0xffffffff); | |
2832 | radeon_ring_write(ring, tmp); | |
2833 | radeon_ring_write(ring, dst_offset & 0xffffffff); | |
2834 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); | |
2835 | radeon_ring_write(ring, cur_size_in_bytes); | |
2836 | src_offset += cur_size_in_bytes; | |
2837 | dst_offset += cur_size_in_bytes; | |
2838 | } | |
2839 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
2840 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2841 | radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); | |
2842 | ||
2843 | r = radeon_fence_emit(rdev, fence, ring->idx); | |
2844 | if (r) { | |
2845 | radeon_ring_unlock_undo(rdev, ring); | |
2846 | return r; | |
2847 | } | |
2848 | ||
2849 | radeon_ring_unlock_commit(rdev, ring); | |
2850 | radeon_semaphore_free(rdev, &sem, *fence); | |
2851 | ||
2852 | return r; | |
2853 | } | |
2854 | ||
3ce0a23d JG |
2855 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
2856 | uint32_t tiling_flags, uint32_t pitch, | |
2857 | uint32_t offset, uint32_t obj_size) | |
2858 | { | |
2859 | /* FIXME: implement */ | |
2860 | return 0; | |
2861 | } | |
2862 | ||
2863 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |
2864 | { | |
2865 | /* FIXME: implement */ | |
2866 | } | |
2867 | ||
1109ca09 | 2868 | static int r600_startup(struct radeon_device *rdev) |
3ce0a23d | 2869 | { |
4d75658b | 2870 | struct radeon_ring *ring; |
3ce0a23d JG |
2871 | int r; |
2872 | ||
9e46a48d AD |
2873 | /* enable pcie gen2 link */ |
2874 | r600_pcie_gen2_enable(rdev); | |
2875 | ||
e5903d39 AD |
2876 | /* scratch needs to be initialized before MC */ |
2877 | r = r600_vram_scratch_init(rdev); | |
2878 | if (r) | |
2879 | return r; | |
2880 | ||
6fab3feb AD |
2881 | r600_mc_program(rdev); |
2882 | ||
1a029b76 JG |
2883 | if (rdev->flags & RADEON_IS_AGP) { |
2884 | r600_agp_enable(rdev); | |
2885 | } else { | |
2886 | r = r600_pcie_gart_enable(rdev); | |
2887 | if (r) | |
2888 | return r; | |
2889 | } | |
3ce0a23d | 2890 | r600_gpu_init(rdev); |
b70d6bb3 | 2891 | |
724c80e1 AD |
2892 | /* allocate wb buffer */ |
2893 | r = radeon_wb_init(rdev); | |
2894 | if (r) | |
2895 | return r; | |
2896 | ||
30eb77f4 JG |
2897 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2898 | if (r) { | |
2899 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
2900 | return r; | |
2901 | } | |
2902 | ||
d8f60cfc | 2903 | /* Enable IRQ */ |
e49f3959 AH |
2904 | if (!rdev->irq.installed) { |
2905 | r = radeon_irq_kms_init(rdev); | |
2906 | if (r) | |
2907 | return r; | |
2908 | } | |
2909 | ||
d8f60cfc AD |
2910 | r = r600_irq_init(rdev); |
2911 | if (r) { | |
2912 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
2913 | radeon_irq_kms_fini(rdev); | |
2914 | return r; | |
2915 | } | |
2916 | r600_irq_set(rdev); | |
2917 | ||
4d75658b | 2918 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
e32eb50d | 2919 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
2e1e6dad | 2920 | RADEON_CP_PACKET2); |
4d75658b AD |
2921 | if (r) |
2922 | return r; | |
5596a9db | 2923 | |
3ce0a23d JG |
2924 | r = r600_cp_load_microcode(rdev); |
2925 | if (r) | |
2926 | return r; | |
2927 | r = r600_cp_resume(rdev); | |
2928 | if (r) | |
2929 | return r; | |
724c80e1 | 2930 | |
2898c348 CK |
2931 | r = radeon_ib_pool_init(rdev); |
2932 | if (r) { | |
2933 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 2934 | return r; |
2898c348 | 2935 | } |
b15ba512 | 2936 | |
d4e30ef0 AD |
2937 | r = r600_audio_init(rdev); |
2938 | if (r) { | |
2939 | DRM_ERROR("radeon: audio init failed\n"); | |
2940 | return r; | |
2941 | } | |
2942 | ||
3ce0a23d JG |
2943 | return 0; |
2944 | } | |
2945 | ||
28d52043 DA |
2946 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
2947 | { | |
2948 | uint32_t temp; | |
2949 | ||
2950 | temp = RREG32(CONFIG_CNTL); | |
2951 | if (state == false) { | |
2952 | temp &= ~(1<<0); | |
2953 | temp |= (1<<1); | |
2954 | } else { | |
2955 | temp &= ~(1<<1); | |
2956 | } | |
2957 | WREG32(CONFIG_CNTL, temp); | |
2958 | } | |
2959 | ||
fc30b8ef DA |
2960 | int r600_resume(struct radeon_device *rdev) |
2961 | { | |
2962 | int r; | |
2963 | ||
1a029b76 JG |
2964 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
2965 | * posting will perform necessary task to bring back GPU into good | |
2966 | * shape. | |
2967 | */ | |
fc30b8ef | 2968 | /* post card */ |
e7d40b9a | 2969 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef | 2970 | |
6c7bccea AD |
2971 | radeon_pm_resume(rdev); |
2972 | ||
b15ba512 | 2973 | rdev->accel_working = true; |
fc30b8ef DA |
2974 | r = r600_startup(rdev); |
2975 | if (r) { | |
2976 | DRM_ERROR("r600 startup failed on resume\n"); | |
6b7746e8 | 2977 | rdev->accel_working = false; |
fc30b8ef DA |
2978 | return r; |
2979 | } | |
2980 | ||
fc30b8ef DA |
2981 | return r; |
2982 | } | |
2983 | ||
3ce0a23d JG |
2984 | int r600_suspend(struct radeon_device *rdev) |
2985 | { | |
6c7bccea | 2986 | radeon_pm_suspend(rdev); |
38fd2c6f | 2987 | r600_audio_fini(rdev); |
3ce0a23d | 2988 | r600_cp_stop(rdev); |
0c45249f | 2989 | r600_irq_suspend(rdev); |
724c80e1 | 2990 | radeon_wb_disable(rdev); |
4aac0473 | 2991 | r600_pcie_gart_disable(rdev); |
6ddddfe7 | 2992 | |
3ce0a23d JG |
2993 | return 0; |
2994 | } | |
2995 | ||
2996 | /* Plan is to move initialization in that function and use | |
2997 | * helper function so that radeon_device_init pretty much | |
2998 | * do nothing more than calling asic specific function. This | |
2999 | * should also allow to remove a bunch of callback function | |
3000 | * like vram_info. | |
3001 | */ | |
3002 | int r600_init(struct radeon_device *rdev) | |
771fe6b9 | 3003 | { |
3ce0a23d | 3004 | int r; |
771fe6b9 | 3005 | |
3ce0a23d JG |
3006 | if (r600_debugfs_mc_info_init(rdev)) { |
3007 | DRM_ERROR("Failed to register debugfs file for mc !\n"); | |
3008 | } | |
3ce0a23d JG |
3009 | /* Read BIOS */ |
3010 | if (!radeon_get_bios(rdev)) { | |
3011 | if (ASIC_IS_AVIVO(rdev)) | |
3012 | return -EINVAL; | |
3013 | } | |
3014 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
3015 | if (!rdev->is_atom_bios) { |
3016 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 3017 | return -EINVAL; |
e7d40b9a | 3018 | } |
3ce0a23d JG |
3019 | r = radeon_atombios_init(rdev); |
3020 | if (r) | |
3021 | return r; | |
3022 | /* Post card if necessary */ | |
fd909c37 | 3023 | if (!radeon_card_posted(rdev)) { |
72542d77 DA |
3024 | if (!rdev->bios) { |
3025 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
3026 | return -EINVAL; | |
3027 | } | |
3ce0a23d JG |
3028 | DRM_INFO("GPU not posted. posting now...\n"); |
3029 | atom_asic_init(rdev->mode_info.atom_context); | |
3030 | } | |
3031 | /* Initialize scratch registers */ | |
3032 | r600_scratch_init(rdev); | |
3033 | /* Initialize surface registers */ | |
3034 | radeon_surface_init(rdev); | |
7433874e | 3035 | /* Initialize clocks */ |
5e6dde7e | 3036 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d | 3037 | /* Fence driver */ |
30eb77f4 | 3038 | r = radeon_fence_driver_init(rdev); |
3ce0a23d JG |
3039 | if (r) |
3040 | return r; | |
700a0cc0 JG |
3041 | if (rdev->flags & RADEON_IS_AGP) { |
3042 | r = radeon_agp_init(rdev); | |
3043 | if (r) | |
3044 | radeon_agp_disable(rdev); | |
3045 | } | |
3ce0a23d | 3046 | r = r600_mc_init(rdev); |
b574f251 | 3047 | if (r) |
3ce0a23d | 3048 | return r; |
3ce0a23d | 3049 | /* Memory manager */ |
4c788679 | 3050 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
3051 | if (r) |
3052 | return r; | |
d8f60cfc | 3053 | |
01ac8794 AD |
3054 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
3055 | r = r600_init_microcode(rdev); | |
3056 | if (r) { | |
3057 | DRM_ERROR("Failed to load firmware!\n"); | |
3058 | return r; | |
3059 | } | |
3060 | } | |
3061 | ||
6c7bccea AD |
3062 | /* Initialize power management */ |
3063 | radeon_pm_init(rdev); | |
3064 | ||
e32eb50d CK |
3065 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
3066 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); | |
3ce0a23d | 3067 | |
d8f60cfc AD |
3068 | rdev->ih.ring_obj = NULL; |
3069 | r600_ih_ring_init(rdev, 64 * 1024); | |
3ce0a23d | 3070 | |
4aac0473 JG |
3071 | r = r600_pcie_gart_init(rdev); |
3072 | if (r) | |
3073 | return r; | |
3074 | ||
779720a3 | 3075 | rdev->accel_working = true; |
fc30b8ef | 3076 | r = r600_startup(rdev); |
3ce0a23d | 3077 | if (r) { |
655efd3d JG |
3078 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
3079 | r600_cp_fini(rdev); | |
655efd3d | 3080 | r600_irq_fini(rdev); |
724c80e1 | 3081 | radeon_wb_fini(rdev); |
2898c348 | 3082 | radeon_ib_pool_fini(rdev); |
655efd3d | 3083 | radeon_irq_kms_fini(rdev); |
75c81298 | 3084 | r600_pcie_gart_fini(rdev); |
733289c2 | 3085 | rdev->accel_working = false; |
3ce0a23d | 3086 | } |
dafc3bd5 | 3087 | |
3ce0a23d JG |
3088 | return 0; |
3089 | } | |
3090 | ||
3091 | void r600_fini(struct radeon_device *rdev) | |
3092 | { | |
6c7bccea | 3093 | radeon_pm_fini(rdev); |
dafc3bd5 | 3094 | r600_audio_fini(rdev); |
655efd3d | 3095 | r600_cp_fini(rdev); |
d8f60cfc | 3096 | r600_irq_fini(rdev); |
724c80e1 | 3097 | radeon_wb_fini(rdev); |
2898c348 | 3098 | radeon_ib_pool_fini(rdev); |
d8f60cfc | 3099 | radeon_irq_kms_fini(rdev); |
4aac0473 | 3100 | r600_pcie_gart_fini(rdev); |
16cdf04d | 3101 | r600_vram_scratch_fini(rdev); |
655efd3d | 3102 | radeon_agp_fini(rdev); |
3ce0a23d JG |
3103 | radeon_gem_fini(rdev); |
3104 | radeon_fence_driver_fini(rdev); | |
4c788679 | 3105 | radeon_bo_fini(rdev); |
e7d40b9a | 3106 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
3107 | kfree(rdev->bios); |
3108 | rdev->bios = NULL; | |
3ce0a23d JG |
3109 | } |
3110 | ||
3111 | ||
3112 | /* | |
3113 | * CS stuff | |
3114 | */ | |
3115 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
3116 | { | |
876dc9f3 | 3117 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
89d35807 | 3118 | u32 next_rptr; |
7b1f2485 | 3119 | |
45df6803 | 3120 | if (ring->rptr_save_reg) { |
89d35807 | 3121 | next_rptr = ring->wptr + 3 + 4; |
45df6803 CK |
3122 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
3123 | radeon_ring_write(ring, ((ring->rptr_save_reg - | |
3124 | PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
3125 | radeon_ring_write(ring, next_rptr); | |
89d35807 AD |
3126 | } else if (rdev->wb.enabled) { |
3127 | next_rptr = ring->wptr + 5 + 4; | |
3128 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); | |
3129 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
3130 | radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); | |
3131 | radeon_ring_write(ring, next_rptr); | |
3132 | radeon_ring_write(ring, 0); | |
45df6803 CK |
3133 | } |
3134 | ||
e32eb50d CK |
3135 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
3136 | radeon_ring_write(ring, | |
4eace7fd CC |
3137 | #ifdef __BIG_ENDIAN |
3138 | (2 << 0) | | |
3139 | #endif | |
3140 | (ib->gpu_addr & 0xFFFFFFFC)); | |
e32eb50d CK |
3141 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
3142 | radeon_ring_write(ring, ib->length_dw); | |
3ce0a23d JG |
3143 | } |
3144 | ||
f712812e | 3145 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d | 3146 | { |
f2e39221 | 3147 | struct radeon_ib ib; |
3ce0a23d JG |
3148 | uint32_t scratch; |
3149 | uint32_t tmp = 0; | |
3150 | unsigned i; | |
3151 | int r; | |
3152 | ||
3153 | r = radeon_scratch_get(rdev, &scratch); | |
3154 | if (r) { | |
3155 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
3156 | return r; | |
3157 | } | |
3158 | WREG32(scratch, 0xCAFEDEAD); | |
4bf3dd92 | 3159 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
3ce0a23d JG |
3160 | if (r) { |
3161 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
af026c5b | 3162 | goto free_scratch; |
3ce0a23d | 3163 | } |
f2e39221 JG |
3164 | ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); |
3165 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
3166 | ib.ptr[2] = 0xDEADBEEF; | |
3167 | ib.length_dw = 3; | |
4ef72566 | 3168 | r = radeon_ib_schedule(rdev, &ib, NULL); |
3ce0a23d | 3169 | if (r) { |
3ce0a23d | 3170 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
af026c5b | 3171 | goto free_ib; |
3ce0a23d | 3172 | } |
f2e39221 | 3173 | r = radeon_fence_wait(ib.fence, false); |
3ce0a23d JG |
3174 | if (r) { |
3175 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
af026c5b | 3176 | goto free_ib; |
3ce0a23d JG |
3177 | } |
3178 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3179 | tmp = RREG32(scratch); | |
3180 | if (tmp == 0xDEADBEEF) | |
3181 | break; | |
3182 | DRM_UDELAY(1); | |
3183 | } | |
3184 | if (i < rdev->usec_timeout) { | |
f2e39221 | 3185 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
3ce0a23d | 3186 | } else { |
4417d7f6 | 3187 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
3ce0a23d JG |
3188 | scratch, tmp); |
3189 | r = -EINVAL; | |
3190 | } | |
af026c5b | 3191 | free_ib: |
3ce0a23d | 3192 | radeon_ib_free(rdev, &ib); |
af026c5b MD |
3193 | free_scratch: |
3194 | radeon_scratch_free(rdev, scratch); | |
771fe6b9 JG |
3195 | return r; |
3196 | } | |
3197 | ||
d8f60cfc AD |
3198 | /* |
3199 | * Interrupts | |
3200 | * | |
3201 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty | |
3202 | * the same as the CP ring buffer, but in reverse. Rather than the CPU | |
3203 | * writing to the ring and the GPU consuming, the GPU writes to the ring | |
3204 | * and host consumes. As the host irq handler processes interrupts, it | |
3205 | * increments the rptr. When the rptr catches up with the wptr, all the | |
3206 | * current interrupts have been processed. | |
3207 | */ | |
3208 | ||
3209 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
3210 | { | |
3211 | u32 rb_bufsz; | |
3212 | ||
3213 | /* Align ring size */ | |
b72a8925 | 3214 | rb_bufsz = order_base_2(ring_size / 4); |
d8f60cfc AD |
3215 | ring_size = (1 << rb_bufsz) * 4; |
3216 | rdev->ih.ring_size = ring_size; | |
0c45249f JG |
3217 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
3218 | rdev->ih.rptr = 0; | |
d8f60cfc AD |
3219 | } |
3220 | ||
25a857fb | 3221 | int r600_ih_ring_alloc(struct radeon_device *rdev) |
d8f60cfc AD |
3222 | { |
3223 | int r; | |
3224 | ||
d8f60cfc AD |
3225 | /* Allocate ring buffer */ |
3226 | if (rdev->ih.ring_obj == NULL) { | |
441921d5 | 3227 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
268b2510 | 3228 | PAGE_SIZE, true, |
4c788679 | 3229 | RADEON_GEM_DOMAIN_GTT, |
40f5cf99 | 3230 | NULL, &rdev->ih.ring_obj); |
d8f60cfc AD |
3231 | if (r) { |
3232 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); | |
3233 | return r; | |
3234 | } | |
4c788679 JG |
3235 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
3236 | if (unlikely(r != 0)) | |
3237 | return r; | |
3238 | r = radeon_bo_pin(rdev->ih.ring_obj, | |
3239 | RADEON_GEM_DOMAIN_GTT, | |
3240 | &rdev->ih.gpu_addr); | |
d8f60cfc | 3241 | if (r) { |
4c788679 | 3242 | radeon_bo_unreserve(rdev->ih.ring_obj); |
d8f60cfc AD |
3243 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
3244 | return r; | |
3245 | } | |
4c788679 JG |
3246 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
3247 | (void **)&rdev->ih.ring); | |
3248 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
d8f60cfc AD |
3249 | if (r) { |
3250 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); | |
3251 | return r; | |
3252 | } | |
3253 | } | |
d8f60cfc AD |
3254 | return 0; |
3255 | } | |
3256 | ||
25a857fb | 3257 | void r600_ih_ring_fini(struct radeon_device *rdev) |
d8f60cfc | 3258 | { |
4c788679 | 3259 | int r; |
d8f60cfc | 3260 | if (rdev->ih.ring_obj) { |
4c788679 JG |
3261 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
3262 | if (likely(r == 0)) { | |
3263 | radeon_bo_kunmap(rdev->ih.ring_obj); | |
3264 | radeon_bo_unpin(rdev->ih.ring_obj); | |
3265 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
3266 | } | |
3267 | radeon_bo_unref(&rdev->ih.ring_obj); | |
d8f60cfc AD |
3268 | rdev->ih.ring = NULL; |
3269 | rdev->ih.ring_obj = NULL; | |
3270 | } | |
3271 | } | |
3272 | ||
45f9a39b | 3273 | void r600_rlc_stop(struct radeon_device *rdev) |
d8f60cfc AD |
3274 | { |
3275 | ||
45f9a39b AD |
3276 | if ((rdev->family >= CHIP_RV770) && |
3277 | (rdev->family <= CHIP_RV740)) { | |
d8f60cfc AD |
3278 | /* r7xx asics need to soft reset RLC before halting */ |
3279 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); | |
3280 | RREG32(SRBM_SOFT_RESET); | |
4de833c3 | 3281 | mdelay(15); |
d8f60cfc AD |
3282 | WREG32(SRBM_SOFT_RESET, 0); |
3283 | RREG32(SRBM_SOFT_RESET); | |
3284 | } | |
3285 | ||
3286 | WREG32(RLC_CNTL, 0); | |
3287 | } | |
3288 | ||
3289 | static void r600_rlc_start(struct radeon_device *rdev) | |
3290 | { | |
3291 | WREG32(RLC_CNTL, RLC_ENABLE); | |
3292 | } | |
3293 | ||
2948f5e6 | 3294 | static int r600_rlc_resume(struct radeon_device *rdev) |
d8f60cfc AD |
3295 | { |
3296 | u32 i; | |
3297 | const __be32 *fw_data; | |
3298 | ||
3299 | if (!rdev->rlc_fw) | |
3300 | return -EINVAL; | |
3301 | ||
3302 | r600_rlc_stop(rdev); | |
3303 | ||
d8f60cfc | 3304 | WREG32(RLC_HB_CNTL, 0); |
c420c745 | 3305 | |
2948f5e6 AD |
3306 | WREG32(RLC_HB_BASE, 0); |
3307 | WREG32(RLC_HB_RPTR, 0); | |
3308 | WREG32(RLC_HB_WPTR, 0); | |
3309 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); | |
3310 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); | |
d8f60cfc AD |
3311 | WREG32(RLC_MC_CNTL, 0); |
3312 | WREG32(RLC_UCODE_CNTL, 0); | |
3313 | ||
3314 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
2948f5e6 | 3315 | if (rdev->family >= CHIP_RV770) { |
d8f60cfc AD |
3316 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { |
3317 | WREG32(RLC_UCODE_ADDR, i); | |
3318 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
3319 | } | |
3320 | } else { | |
138e4e16 | 3321 | for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { |
d8f60cfc AD |
3322 | WREG32(RLC_UCODE_ADDR, i); |
3323 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
3324 | } | |
3325 | } | |
3326 | WREG32(RLC_UCODE_ADDR, 0); | |
3327 | ||
3328 | r600_rlc_start(rdev); | |
3329 | ||
3330 | return 0; | |
3331 | } | |
3332 | ||
3333 | static void r600_enable_interrupts(struct radeon_device *rdev) | |
3334 | { | |
3335 | u32 ih_cntl = RREG32(IH_CNTL); | |
3336 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
3337 | ||
3338 | ih_cntl |= ENABLE_INTR; | |
3339 | ih_rb_cntl |= IH_RB_ENABLE; | |
3340 | WREG32(IH_CNTL, ih_cntl); | |
3341 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3342 | rdev->ih.enabled = true; | |
3343 | } | |
3344 | ||
45f9a39b | 3345 | void r600_disable_interrupts(struct radeon_device *rdev) |
d8f60cfc AD |
3346 | { |
3347 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
3348 | u32 ih_cntl = RREG32(IH_CNTL); | |
3349 | ||
3350 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
3351 | ih_cntl &= ~ENABLE_INTR; | |
3352 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3353 | WREG32(IH_CNTL, ih_cntl); | |
3354 | /* set rptr, wptr to 0 */ | |
3355 | WREG32(IH_RB_RPTR, 0); | |
3356 | WREG32(IH_RB_WPTR, 0); | |
3357 | rdev->ih.enabled = false; | |
d8f60cfc AD |
3358 | rdev->ih.rptr = 0; |
3359 | } | |
3360 | ||
e0df1ac5 AD |
3361 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
3362 | { | |
3363 | u32 tmp; | |
3364 | ||
3555e53b | 3365 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
4d75658b AD |
3366 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
3367 | WREG32(DMA_CNTL, tmp); | |
e0df1ac5 AD |
3368 | WREG32(GRBM_INT_CNTL, 0); |
3369 | WREG32(DxMODE_INT_MASK, 0); | |
6f34be50 AD |
3370 | WREG32(D1GRPH_INTERRUPT_CONTROL, 0); |
3371 | WREG32(D2GRPH_INTERRUPT_CONTROL, 0); | |
e0df1ac5 AD |
3372 | if (ASIC_IS_DCE3(rdev)) { |
3373 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); | |
3374 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); | |
3375 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3376 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3377 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3378 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3379 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3380 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3381 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3382 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3383 | if (ASIC_IS_DCE32(rdev)) { | |
3384 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
5898b1f3 | 3385 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
e0df1ac5 | 3386 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
5898b1f3 | 3387 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
c6543a6e RM |
3388 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
3389 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); | |
3390 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3391 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); | |
f122c610 AD |
3392 | } else { |
3393 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3394 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | |
3395 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3396 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
e0df1ac5 AD |
3397 | } |
3398 | } else { | |
3399 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
3400 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
3401 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
5898b1f3 | 3402 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
e0df1ac5 | 3403 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 3404 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
e0df1ac5 | 3405 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 3406 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
f122c610 AD |
3407 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
3408 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | |
3409 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3410 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
e0df1ac5 AD |
3411 | } |
3412 | } | |
3413 | ||
d8f60cfc AD |
3414 | int r600_irq_init(struct radeon_device *rdev) |
3415 | { | |
3416 | int ret = 0; | |
3417 | int rb_bufsz; | |
3418 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
3419 | ||
3420 | /* allocate ring */ | |
0c45249f | 3421 | ret = r600_ih_ring_alloc(rdev); |
d8f60cfc AD |
3422 | if (ret) |
3423 | return ret; | |
3424 | ||
3425 | /* disable irqs */ | |
3426 | r600_disable_interrupts(rdev); | |
3427 | ||
3428 | /* init rlc */ | |
2948f5e6 AD |
3429 | if (rdev->family >= CHIP_CEDAR) |
3430 | ret = evergreen_rlc_resume(rdev); | |
3431 | else | |
3432 | ret = r600_rlc_resume(rdev); | |
d8f60cfc AD |
3433 | if (ret) { |
3434 | r600_ih_ring_fini(rdev); | |
3435 | return ret; | |
3436 | } | |
3437 | ||
3438 | /* setup interrupt control */ | |
3439 | /* set dummy read address to ring address */ | |
3440 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
3441 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
3442 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
3443 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
3444 | */ | |
3445 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
3446 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
3447 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
3448 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
3449 | ||
3450 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
b72a8925 | 3451 | rb_bufsz = order_base_2(rdev->ih.ring_size / 4); |
d8f60cfc AD |
3452 | |
3453 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
3454 | IH_WPTR_OVERFLOW_CLEAR | | |
3455 | (rb_bufsz << 1)); | |
724c80e1 AD |
3456 | |
3457 | if (rdev->wb.enabled) | |
3458 | ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; | |
3459 | ||
3460 | /* set the writeback address whether it's enabled or not */ | |
3461 | WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); | |
3462 | WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); | |
d8f60cfc AD |
3463 | |
3464 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3465 | ||
3466 | /* set rptr, wptr to 0 */ | |
3467 | WREG32(IH_RB_RPTR, 0); | |
3468 | WREG32(IH_RB_WPTR, 0); | |
3469 | ||
3470 | /* Default settings for IH_CNTL (disabled at first) */ | |
3471 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); | |
3472 | /* RPTR_REARM only works if msi's are enabled */ | |
3473 | if (rdev->msi_enabled) | |
3474 | ih_cntl |= RPTR_REARM; | |
d8f60cfc AD |
3475 | WREG32(IH_CNTL, ih_cntl); |
3476 | ||
3477 | /* force the active interrupt state to all disabled */ | |
45f9a39b AD |
3478 | if (rdev->family >= CHIP_CEDAR) |
3479 | evergreen_disable_interrupt_state(rdev); | |
3480 | else | |
3481 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 3482 | |
2099810f DA |
3483 | /* at this point everything should be setup correctly to enable master */ |
3484 | pci_set_master(rdev->pdev); | |
3485 | ||
d8f60cfc AD |
3486 | /* enable irqs */ |
3487 | r600_enable_interrupts(rdev); | |
3488 | ||
3489 | return ret; | |
3490 | } | |
3491 | ||
0c45249f | 3492 | void r600_irq_suspend(struct radeon_device *rdev) |
d8f60cfc | 3493 | { |
45f9a39b | 3494 | r600_irq_disable(rdev); |
d8f60cfc | 3495 | r600_rlc_stop(rdev); |
0c45249f JG |
3496 | } |
3497 | ||
3498 | void r600_irq_fini(struct radeon_device *rdev) | |
3499 | { | |
3500 | r600_irq_suspend(rdev); | |
d8f60cfc AD |
3501 | r600_ih_ring_fini(rdev); |
3502 | } | |
3503 | ||
3504 | int r600_irq_set(struct radeon_device *rdev) | |
3505 | { | |
e0df1ac5 AD |
3506 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
3507 | u32 mode_int = 0; | |
3508 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | |
2031f77c | 3509 | u32 grbm_int_cntl = 0; |
f122c610 | 3510 | u32 hdmi0, hdmi1; |
6f34be50 | 3511 | u32 d1grph = 0, d2grph = 0; |
4d75658b | 3512 | u32 dma_cntl; |
4a6369e9 | 3513 | u32 thermal_int = 0; |
d8f60cfc | 3514 | |
003e69f9 | 3515 | if (!rdev->irq.installed) { |
fce7d61b | 3516 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
003e69f9 JG |
3517 | return -EINVAL; |
3518 | } | |
d8f60cfc | 3519 | /* don't enable anything if the ih is disabled */ |
79c2bbc5 JG |
3520 | if (!rdev->ih.enabled) { |
3521 | r600_disable_interrupts(rdev); | |
3522 | /* force the active interrupt state to all disabled */ | |
3523 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 3524 | return 0; |
79c2bbc5 | 3525 | } |
d8f60cfc | 3526 | |
e0df1ac5 AD |
3527 | if (ASIC_IS_DCE3(rdev)) { |
3528 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3529 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3530 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3531 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3532 | if (ASIC_IS_DCE32(rdev)) { | |
3533 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3534 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
c6543a6e RM |
3535 | hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
3536 | hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | |
f122c610 AD |
3537 | } else { |
3538 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3539 | hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
e0df1ac5 AD |
3540 | } |
3541 | } else { | |
3542 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3543 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3544 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
f122c610 AD |
3545 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
3546 | hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
e0df1ac5 | 3547 | } |
4a6369e9 | 3548 | |
4d75658b | 3549 | dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
e0df1ac5 | 3550 | |
4a6369e9 AD |
3551 | if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { |
3552 | thermal_int = RREG32(CG_THERMAL_INT) & | |
3553 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); | |
66229b20 AD |
3554 | } else if (rdev->family >= CHIP_RV770) { |
3555 | thermal_int = RREG32(RV770_CG_THERMAL_INT) & | |
3556 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); | |
3557 | } | |
3558 | if (rdev->irq.dpm_thermal) { | |
3559 | DRM_DEBUG("dpm thermal\n"); | |
3560 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; | |
4a6369e9 AD |
3561 | } |
3562 | ||
736fc37f | 3563 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
d8f60cfc AD |
3564 | DRM_DEBUG("r600_irq_set: sw int\n"); |
3565 | cp_int_cntl |= RB_INT_ENABLE; | |
d0f8a854 | 3566 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
d8f60cfc | 3567 | } |
4d75658b AD |
3568 | |
3569 | if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { | |
3570 | DRM_DEBUG("r600_irq_set: sw int dma\n"); | |
3571 | dma_cntl |= TRAP_ENABLE; | |
3572 | } | |
3573 | ||
6f34be50 | 3574 | if (rdev->irq.crtc_vblank_int[0] || |
736fc37f | 3575 | atomic_read(&rdev->irq.pflip[0])) { |
d8f60cfc AD |
3576 | DRM_DEBUG("r600_irq_set: vblank 0\n"); |
3577 | mode_int |= D1MODE_VBLANK_INT_MASK; | |
3578 | } | |
6f34be50 | 3579 | if (rdev->irq.crtc_vblank_int[1] || |
736fc37f | 3580 | atomic_read(&rdev->irq.pflip[1])) { |
d8f60cfc AD |
3581 | DRM_DEBUG("r600_irq_set: vblank 1\n"); |
3582 | mode_int |= D2MODE_VBLANK_INT_MASK; | |
3583 | } | |
e0df1ac5 AD |
3584 | if (rdev->irq.hpd[0]) { |
3585 | DRM_DEBUG("r600_irq_set: hpd 1\n"); | |
3586 | hpd1 |= DC_HPDx_INT_EN; | |
3587 | } | |
3588 | if (rdev->irq.hpd[1]) { | |
3589 | DRM_DEBUG("r600_irq_set: hpd 2\n"); | |
3590 | hpd2 |= DC_HPDx_INT_EN; | |
3591 | } | |
3592 | if (rdev->irq.hpd[2]) { | |
3593 | DRM_DEBUG("r600_irq_set: hpd 3\n"); | |
3594 | hpd3 |= DC_HPDx_INT_EN; | |
3595 | } | |
3596 | if (rdev->irq.hpd[3]) { | |
3597 | DRM_DEBUG("r600_irq_set: hpd 4\n"); | |
3598 | hpd4 |= DC_HPDx_INT_EN; | |
3599 | } | |
3600 | if (rdev->irq.hpd[4]) { | |
3601 | DRM_DEBUG("r600_irq_set: hpd 5\n"); | |
3602 | hpd5 |= DC_HPDx_INT_EN; | |
3603 | } | |
3604 | if (rdev->irq.hpd[5]) { | |
3605 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | |
3606 | hpd6 |= DC_HPDx_INT_EN; | |
3607 | } | |
f122c610 AD |
3608 | if (rdev->irq.afmt[0]) { |
3609 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); | |
3610 | hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; | |
f2594933 | 3611 | } |
f122c610 AD |
3612 | if (rdev->irq.afmt[1]) { |
3613 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); | |
3614 | hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; | |
f2594933 | 3615 | } |
d8f60cfc AD |
3616 | |
3617 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
4d75658b | 3618 | WREG32(DMA_CNTL, dma_cntl); |
d8f60cfc | 3619 | WREG32(DxMODE_INT_MASK, mode_int); |
6f34be50 AD |
3620 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); |
3621 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); | |
2031f77c | 3622 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
e0df1ac5 AD |
3623 | if (ASIC_IS_DCE3(rdev)) { |
3624 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | |
3625 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
3626 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
3627 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
3628 | if (ASIC_IS_DCE32(rdev)) { | |
3629 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
3630 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
c6543a6e RM |
3631 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); |
3632 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); | |
f122c610 AD |
3633 | } else { |
3634 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | |
3635 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); | |
e0df1ac5 AD |
3636 | } |
3637 | } else { | |
3638 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); | |
3639 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
3640 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | |
f122c610 AD |
3641 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
3642 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); | |
e0df1ac5 | 3643 | } |
4a6369e9 AD |
3644 | if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { |
3645 | WREG32(CG_THERMAL_INT, thermal_int); | |
66229b20 AD |
3646 | } else if (rdev->family >= CHIP_RV770) { |
3647 | WREG32(RV770_CG_THERMAL_INT, thermal_int); | |
4a6369e9 | 3648 | } |
d8f60cfc AD |
3649 | |
3650 | return 0; | |
3651 | } | |
3652 | ||
ce580fab | 3653 | static void r600_irq_ack(struct radeon_device *rdev) |
d8f60cfc | 3654 | { |
e0df1ac5 AD |
3655 | u32 tmp; |
3656 | ||
3657 | if (ASIC_IS_DCE3(rdev)) { | |
6f34be50 AD |
3658 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
3659 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | |
3660 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | |
f122c610 | 3661 | if (ASIC_IS_DCE32(rdev)) { |
c6543a6e RM |
3662 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); |
3663 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); | |
f122c610 AD |
3664 | } else { |
3665 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); | |
3666 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); | |
3667 | } | |
e0df1ac5 | 3668 | } else { |
6f34be50 AD |
3669 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
3670 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
3671 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; | |
f122c610 AD |
3672 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); |
3673 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); | |
6f34be50 AD |
3674 | } |
3675 | rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); | |
3676 | rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); | |
3677 | ||
3678 | if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) | |
3679 | WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); | |
3680 | if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) | |
3681 | WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); | |
3682 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) | |
d8f60cfc | 3683 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
6f34be50 | 3684 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) |
d8f60cfc | 3685 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
6f34be50 | 3686 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) |
d8f60cfc | 3687 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
6f34be50 | 3688 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) |
d8f60cfc | 3689 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
6f34be50 | 3690 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
e0df1ac5 AD |
3691 | if (ASIC_IS_DCE3(rdev)) { |
3692 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
3693 | tmp |= DC_HPDx_INT_ACK; | |
3694 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3695 | } else { | |
3696 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
3697 | tmp |= DC_HPDx_INT_ACK; | |
3698 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
3699 | } | |
3700 | } | |
6f34be50 | 3701 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
e0df1ac5 AD |
3702 | if (ASIC_IS_DCE3(rdev)) { |
3703 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
3704 | tmp |= DC_HPDx_INT_ACK; | |
3705 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3706 | } else { | |
3707 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
3708 | tmp |= DC_HPDx_INT_ACK; | |
3709 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
3710 | } | |
3711 | } | |
6f34be50 | 3712 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
e0df1ac5 AD |
3713 | if (ASIC_IS_DCE3(rdev)) { |
3714 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
3715 | tmp |= DC_HPDx_INT_ACK; | |
3716 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3717 | } else { | |
3718 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
3719 | tmp |= DC_HPDx_INT_ACK; | |
3720 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
3721 | } | |
3722 | } | |
6f34be50 | 3723 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
e0df1ac5 AD |
3724 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
3725 | tmp |= DC_HPDx_INT_ACK; | |
3726 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3727 | } | |
3728 | if (ASIC_IS_DCE32(rdev)) { | |
6f34be50 | 3729 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
e0df1ac5 AD |
3730 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
3731 | tmp |= DC_HPDx_INT_ACK; | |
3732 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
3733 | } | |
6f34be50 | 3734 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
e0df1ac5 AD |
3735 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
3736 | tmp |= DC_HPDx_INT_ACK; | |
3737 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
3738 | } | |
f122c610 | 3739 | if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { |
c6543a6e | 3740 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); |
f122c610 | 3741 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
c6543a6e | 3742 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); |
f122c610 AD |
3743 | } |
3744 | if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { | |
c6543a6e | 3745 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); |
f122c610 | 3746 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
c6543a6e | 3747 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); |
f2594933 CK |
3748 | } |
3749 | } else { | |
f122c610 AD |
3750 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { |
3751 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); | |
3752 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | |
3753 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | |
3754 | } | |
3755 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { | |
3756 | if (ASIC_IS_DCE3(rdev)) { | |
3757 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); | |
3758 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | |
3759 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
3760 | } else { | |
3761 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); | |
3762 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | |
3763 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
3764 | } | |
f2594933 CK |
3765 | } |
3766 | } | |
d8f60cfc AD |
3767 | } |
3768 | ||
3769 | void r600_irq_disable(struct radeon_device *rdev) | |
3770 | { | |
d8f60cfc AD |
3771 | r600_disable_interrupts(rdev); |
3772 | /* Wait and acknowledge irq */ | |
3773 | mdelay(1); | |
6f34be50 | 3774 | r600_irq_ack(rdev); |
e0df1ac5 | 3775 | r600_disable_interrupt_state(rdev); |
d8f60cfc AD |
3776 | } |
3777 | ||
ce580fab | 3778 | static u32 r600_get_ih_wptr(struct radeon_device *rdev) |
d8f60cfc AD |
3779 | { |
3780 | u32 wptr, tmp; | |
3ce0a23d | 3781 | |
724c80e1 | 3782 | if (rdev->wb.enabled) |
204ae24d | 3783 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
724c80e1 AD |
3784 | else |
3785 | wptr = RREG32(IH_RB_WPTR); | |
3ce0a23d | 3786 | |
d8f60cfc | 3787 | if (wptr & RB_OVERFLOW) { |
7924e5eb JG |
3788 | /* When a ring buffer overflow happen start parsing interrupt |
3789 | * from the last not overwritten vector (wptr + 16). Hopefully | |
3790 | * this should allow us to catchup. | |
3791 | */ | |
3792 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
3793 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
3794 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
d8f60cfc AD |
3795 | tmp = RREG32(IH_RB_CNTL); |
3796 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
3797 | WREG32(IH_RB_CNTL, tmp); | |
3798 | } | |
0c45249f | 3799 | return (wptr & rdev->ih.ptr_mask); |
d8f60cfc | 3800 | } |
3ce0a23d | 3801 | |
d8f60cfc AD |
3802 | /* r600 IV Ring |
3803 | * Each IV ring entry is 128 bits: | |
3804 | * [7:0] - interrupt source id | |
3805 | * [31:8] - reserved | |
3806 | * [59:32] - interrupt source data | |
3807 | * [127:60] - reserved | |
3808 | * | |
3809 | * The basic interrupt vector entries | |
3810 | * are decoded as follows: | |
3811 | * src_id src_data description | |
3812 | * 1 0 D1 Vblank | |
3813 | * 1 1 D1 Vline | |
3814 | * 5 0 D2 Vblank | |
3815 | * 5 1 D2 Vline | |
3816 | * 19 0 FP Hot plug detection A | |
3817 | * 19 1 FP Hot plug detection B | |
3818 | * 19 2 DAC A auto-detection | |
3819 | * 19 3 DAC B auto-detection | |
f2594933 CK |
3820 | * 21 4 HDMI block A |
3821 | * 21 5 HDMI block B | |
d8f60cfc AD |
3822 | * 176 - CP_INT RB |
3823 | * 177 - CP_INT IB1 | |
3824 | * 178 - CP_INT IB2 | |
3825 | * 181 - EOP Interrupt | |
3826 | * 233 - GUI Idle | |
3827 | * | |
3828 | * Note, these are based on r600 and may need to be | |
3829 | * adjusted or added to on newer asics | |
3830 | */ | |
3831 | ||
3832 | int r600_irq_process(struct radeon_device *rdev) | |
3833 | { | |
682f1a54 DA |
3834 | u32 wptr; |
3835 | u32 rptr; | |
d8f60cfc | 3836 | u32 src_id, src_data; |
6f34be50 | 3837 | u32 ring_index; |
d4877cf2 | 3838 | bool queue_hotplug = false; |
f122c610 | 3839 | bool queue_hdmi = false; |
4a6369e9 | 3840 | bool queue_thermal = false; |
d8f60cfc | 3841 | |
682f1a54 | 3842 | if (!rdev->ih.enabled || rdev->shutdown) |
79c2bbc5 | 3843 | return IRQ_NONE; |
d8f60cfc | 3844 | |
f6a56939 BH |
3845 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
3846 | if (!rdev->msi_enabled) | |
3847 | RREG32(IH_RB_WPTR); | |
3848 | ||
682f1a54 | 3849 | wptr = r600_get_ih_wptr(rdev); |
d8f60cfc | 3850 | |
c20dc369 CK |
3851 | restart_ih: |
3852 | /* is somebody else already processing irqs? */ | |
3853 | if (atomic_xchg(&rdev->ih.lock, 1)) | |
d8f60cfc | 3854 | return IRQ_NONE; |
d8f60cfc | 3855 | |
c20dc369 CK |
3856 | rptr = rdev->ih.rptr; |
3857 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
3858 | ||
964f6645 BH |
3859 | /* Order reading of wptr vs. reading of IH ring data */ |
3860 | rmb(); | |
3861 | ||
d8f60cfc | 3862 | /* display interrupts */ |
6f34be50 | 3863 | r600_irq_ack(rdev); |
d8f60cfc | 3864 | |
d8f60cfc AD |
3865 | while (rptr != wptr) { |
3866 | /* wptr/rptr are in bytes! */ | |
3867 | ring_index = rptr / 4; | |
4eace7fd CC |
3868 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
3869 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; | |
d8f60cfc AD |
3870 | |
3871 | switch (src_id) { | |
3872 | case 1: /* D1 vblank/vline */ | |
3873 | switch (src_data) { | |
3874 | case 0: /* D1 vblank */ | |
6f34be50 | 3875 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { |
6f34be50 AD |
3876 | if (rdev->irq.crtc_vblank_int[0]) { |
3877 | drm_handle_vblank(rdev->ddev, 0); | |
3878 | rdev->pm.vblank_sync = true; | |
3879 | wake_up(&rdev->irq.vblank_queue); | |
3880 | } | |
736fc37f | 3881 | if (atomic_read(&rdev->irq.pflip[0])) |
3e4ea742 | 3882 | radeon_crtc_handle_flip(rdev, 0); |
6f34be50 | 3883 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
d8f60cfc AD |
3884 | DRM_DEBUG("IH: D1 vblank\n"); |
3885 | } | |
3886 | break; | |
3887 | case 1: /* D1 vline */ | |
6f34be50 AD |
3888 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { |
3889 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
d8f60cfc AD |
3890 | DRM_DEBUG("IH: D1 vline\n"); |
3891 | } | |
3892 | break; | |
3893 | default: | |
b042589c | 3894 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3895 | break; |
3896 | } | |
3897 | break; | |
3898 | case 5: /* D2 vblank/vline */ | |
3899 | switch (src_data) { | |
3900 | case 0: /* D2 vblank */ | |
6f34be50 | 3901 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { |
6f34be50 AD |
3902 | if (rdev->irq.crtc_vblank_int[1]) { |
3903 | drm_handle_vblank(rdev->ddev, 1); | |
3904 | rdev->pm.vblank_sync = true; | |
3905 | wake_up(&rdev->irq.vblank_queue); | |
3906 | } | |
736fc37f | 3907 | if (atomic_read(&rdev->irq.pflip[1])) |
3e4ea742 | 3908 | radeon_crtc_handle_flip(rdev, 1); |
6f34be50 | 3909 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; |
d8f60cfc AD |
3910 | DRM_DEBUG("IH: D2 vblank\n"); |
3911 | } | |
3912 | break; | |
3913 | case 1: /* D1 vline */ | |
6f34be50 AD |
3914 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { |
3915 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; | |
d8f60cfc AD |
3916 | DRM_DEBUG("IH: D2 vline\n"); |
3917 | } | |
3918 | break; | |
3919 | default: | |
b042589c | 3920 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3921 | break; |
3922 | } | |
3923 | break; | |
e0df1ac5 AD |
3924 | case 19: /* HPD/DAC hotplug */ |
3925 | switch (src_data) { | |
3926 | case 0: | |
6f34be50 AD |
3927 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
3928 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; | |
d4877cf2 AD |
3929 | queue_hotplug = true; |
3930 | DRM_DEBUG("IH: HPD1\n"); | |
e0df1ac5 AD |
3931 | } |
3932 | break; | |
3933 | case 1: | |
6f34be50 AD |
3934 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
3935 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; | |
d4877cf2 AD |
3936 | queue_hotplug = true; |
3937 | DRM_DEBUG("IH: HPD2\n"); | |
e0df1ac5 AD |
3938 | } |
3939 | break; | |
3940 | case 4: | |
6f34be50 AD |
3941 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
3942 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; | |
d4877cf2 AD |
3943 | queue_hotplug = true; |
3944 | DRM_DEBUG("IH: HPD3\n"); | |
e0df1ac5 AD |
3945 | } |
3946 | break; | |
3947 | case 5: | |
6f34be50 AD |
3948 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
3949 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; | |
d4877cf2 AD |
3950 | queue_hotplug = true; |
3951 | DRM_DEBUG("IH: HPD4\n"); | |
e0df1ac5 AD |
3952 | } |
3953 | break; | |
3954 | case 10: | |
6f34be50 AD |
3955 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
3956 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; | |
d4877cf2 AD |
3957 | queue_hotplug = true; |
3958 | DRM_DEBUG("IH: HPD5\n"); | |
e0df1ac5 AD |
3959 | } |
3960 | break; | |
3961 | case 12: | |
6f34be50 AD |
3962 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
3963 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; | |
d4877cf2 AD |
3964 | queue_hotplug = true; |
3965 | DRM_DEBUG("IH: HPD6\n"); | |
e0df1ac5 AD |
3966 | } |
3967 | break; | |
3968 | default: | |
b042589c | 3969 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
e0df1ac5 AD |
3970 | break; |
3971 | } | |
3972 | break; | |
f122c610 AD |
3973 | case 21: /* hdmi */ |
3974 | switch (src_data) { | |
3975 | case 4: | |
3976 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { | |
3977 | rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; | |
3978 | queue_hdmi = true; | |
3979 | DRM_DEBUG("IH: HDMI0\n"); | |
3980 | } | |
3981 | break; | |
3982 | case 5: | |
3983 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { | |
3984 | rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; | |
3985 | queue_hdmi = true; | |
3986 | DRM_DEBUG("IH: HDMI1\n"); | |
3987 | } | |
3988 | break; | |
3989 | default: | |
3990 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3991 | break; | |
3992 | } | |
f2594933 | 3993 | break; |
858a41c8 AD |
3994 | case 124: /* UVD */ |
3995 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); | |
3996 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); | |
3997 | break; | |
d8f60cfc AD |
3998 | case 176: /* CP_INT in ring buffer */ |
3999 | case 177: /* CP_INT in IB1 */ | |
4000 | case 178: /* CP_INT in IB2 */ | |
4001 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
7465280c | 4002 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
d8f60cfc AD |
4003 | break; |
4004 | case 181: /* CP EOP event */ | |
4005 | DRM_DEBUG("IH: CP EOP\n"); | |
7465280c | 4006 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
d8f60cfc | 4007 | break; |
4d75658b AD |
4008 | case 224: /* DMA trap event */ |
4009 | DRM_DEBUG("IH: DMA trap\n"); | |
4010 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); | |
4011 | break; | |
4a6369e9 AD |
4012 | case 230: /* thermal low to high */ |
4013 | DRM_DEBUG("IH: thermal low to high\n"); | |
4014 | rdev->pm.dpm.thermal.high_to_low = false; | |
4015 | queue_thermal = true; | |
4016 | break; | |
4017 | case 231: /* thermal high to low */ | |
4018 | DRM_DEBUG("IH: thermal high to low\n"); | |
4019 | rdev->pm.dpm.thermal.high_to_low = true; | |
4020 | queue_thermal = true; | |
4021 | break; | |
2031f77c | 4022 | case 233: /* GUI IDLE */ |
303c805c | 4023 | DRM_DEBUG("IH: GUI idle\n"); |
2031f77c | 4024 | break; |
d8f60cfc | 4025 | default: |
b042589c | 4026 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
4027 | break; |
4028 | } | |
4029 | ||
4030 | /* wptr/rptr are in bytes! */ | |
0c45249f JG |
4031 | rptr += 16; |
4032 | rptr &= rdev->ih.ptr_mask; | |
d8f60cfc | 4033 | } |
d4877cf2 | 4034 | if (queue_hotplug) |
32c87fca | 4035 | schedule_work(&rdev->hotplug_work); |
f122c610 AD |
4036 | if (queue_hdmi) |
4037 | schedule_work(&rdev->audio_work); | |
4a6369e9 AD |
4038 | if (queue_thermal && rdev->pm.dpm_enabled) |
4039 | schedule_work(&rdev->pm.dpm.thermal.work); | |
d8f60cfc AD |
4040 | rdev->ih.rptr = rptr; |
4041 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
c20dc369 CK |
4042 | atomic_set(&rdev->ih.lock, 0); |
4043 | ||
4044 | /* make sure wptr hasn't changed while processing */ | |
4045 | wptr = r600_get_ih_wptr(rdev); | |
4046 | if (wptr != rptr) | |
4047 | goto restart_ih; | |
4048 | ||
d8f60cfc AD |
4049 | return IRQ_HANDLED; |
4050 | } | |
3ce0a23d JG |
4051 | |
4052 | /* | |
4053 | * Debugfs info | |
4054 | */ | |
4055 | #if defined(CONFIG_DEBUG_FS) | |
4056 | ||
3ce0a23d JG |
4057 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
4058 | { | |
4059 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
4060 | struct drm_device *dev = node->minor->dev; | |
4061 | struct radeon_device *rdev = dev->dev_private; | |
4062 | ||
4063 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); | |
4064 | DREG32_SYS(m, rdev, VM_L2_STATUS); | |
4065 | return 0; | |
4066 | } | |
4067 | ||
4068 | static struct drm_info_list r600_mc_info_list[] = { | |
4069 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, | |
3ce0a23d JG |
4070 | }; |
4071 | #endif | |
4072 | ||
4073 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) | |
4074 | { | |
4075 | #if defined(CONFIG_DEBUG_FS) | |
4076 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); | |
4077 | #else | |
4078 | return 0; | |
4079 | #endif | |
771fe6b9 | 4080 | } |
062b389c JG |
4081 | |
4082 | /** | |
4083 | * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl | |
4084 | * rdev: radeon device structure | |
4085 | * bo: buffer object struct which userspace is waiting for idle | |
4086 | * | |
4087 | * Some R6XX/R7XX doesn't seems to take into account HDP flush performed | |
4088 | * through ring buffer, this leads to corruption in rendering, see | |
4089 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we | |
4090 | * directly perform HDP flush by writing register through MMIO. | |
4091 | */ | |
4092 | void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) | |
4093 | { | |
812d0469 | 4094 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
f3886f85 AD |
4095 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. |
4096 | * This seems to cause problems on some AGP cards. Just use the old | |
4097 | * method for them. | |
812d0469 | 4098 | */ |
e488459a | 4099 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
f3886f85 | 4100 | rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { |
87cbf8f2 | 4101 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
812d0469 AD |
4102 | u32 tmp; |
4103 | ||
4104 | WREG32(HDP_DEBUG1, 0); | |
4105 | tmp = readl((void __iomem *)ptr); | |
4106 | } else | |
4107 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
062b389c | 4108 | } |
3313e3d4 AD |
4109 | |
4110 | void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) | |
4111 | { | |
d5445a17 | 4112 | u32 link_width_cntl, mask; |
3313e3d4 AD |
4113 | |
4114 | if (rdev->flags & RADEON_IS_IGP) | |
4115 | return; | |
4116 | ||
4117 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
4118 | return; | |
4119 | ||
4120 | /* x2 cards have a special sequence */ | |
4121 | if (ASIC_IS_X2(rdev)) | |
4122 | return; | |
4123 | ||
d5445a17 | 4124 | radeon_gui_idle(rdev); |
3313e3d4 AD |
4125 | |
4126 | switch (lanes) { | |
4127 | case 0: | |
4128 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; | |
4129 | break; | |
4130 | case 1: | |
4131 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; | |
4132 | break; | |
4133 | case 2: | |
4134 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; | |
4135 | break; | |
4136 | case 4: | |
4137 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; | |
4138 | break; | |
4139 | case 8: | |
4140 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; | |
4141 | break; | |
4142 | case 12: | |
d5445a17 | 4143 | /* not actually supported */ |
3313e3d4 AD |
4144 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
4145 | break; | |
4146 | case 16: | |
3313e3d4 AD |
4147 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
4148 | break; | |
d5445a17 AD |
4149 | default: |
4150 | DRM_ERROR("invalid pcie lane request: %d\n", lanes); | |
4151 | return; | |
3313e3d4 AD |
4152 | } |
4153 | ||
492d2b61 | 4154 | link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
d5445a17 AD |
4155 | link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; |
4156 | link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; | |
4157 | link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | | |
4158 | R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); | |
3313e3d4 | 4159 | |
492d2b61 | 4160 | WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
3313e3d4 AD |
4161 | } |
4162 | ||
4163 | int r600_get_pcie_lanes(struct radeon_device *rdev) | |
4164 | { | |
4165 | u32 link_width_cntl; | |
4166 | ||
4167 | if (rdev->flags & RADEON_IS_IGP) | |
4168 | return 0; | |
4169 | ||
4170 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
4171 | return 0; | |
4172 | ||
4173 | /* x2 cards have a special sequence */ | |
4174 | if (ASIC_IS_X2(rdev)) | |
4175 | return 0; | |
4176 | ||
d5445a17 | 4177 | radeon_gui_idle(rdev); |
3313e3d4 | 4178 | |
492d2b61 | 4179 | link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
3313e3d4 AD |
4180 | |
4181 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { | |
3313e3d4 AD |
4182 | case RADEON_PCIE_LC_LINK_WIDTH_X1: |
4183 | return 1; | |
4184 | case RADEON_PCIE_LC_LINK_WIDTH_X2: | |
4185 | return 2; | |
4186 | case RADEON_PCIE_LC_LINK_WIDTH_X4: | |
4187 | return 4; | |
4188 | case RADEON_PCIE_LC_LINK_WIDTH_X8: | |
4189 | return 8; | |
d5445a17 AD |
4190 | case RADEON_PCIE_LC_LINK_WIDTH_X12: |
4191 | /* not actually supported */ | |
4192 | return 12; | |
4193 | case RADEON_PCIE_LC_LINK_WIDTH_X0: | |
3313e3d4 AD |
4194 | case RADEON_PCIE_LC_LINK_WIDTH_X16: |
4195 | default: | |
4196 | return 16; | |
4197 | } | |
4198 | } | |
4199 | ||
9e46a48d AD |
4200 | static void r600_pcie_gen2_enable(struct radeon_device *rdev) |
4201 | { | |
4202 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; | |
4203 | u16 link_cntl2; | |
4204 | ||
d42dd579 AD |
4205 | if (radeon_pcie_gen2 == 0) |
4206 | return; | |
4207 | ||
9e46a48d AD |
4208 | if (rdev->flags & RADEON_IS_IGP) |
4209 | return; | |
4210 | ||
4211 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
4212 | return; | |
4213 | ||
4214 | /* x2 cards have a special sequence */ | |
4215 | if (ASIC_IS_X2(rdev)) | |
4216 | return; | |
4217 | ||
4218 | /* only RV6xx+ chips are supported */ | |
4219 | if (rdev->family <= CHIP_R600) | |
4220 | return; | |
4221 | ||
7e0e4196 KSS |
4222 | if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && |
4223 | (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) | |
197bbb3d DA |
4224 | return; |
4225 | ||
492d2b61 | 4226 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
3691feea AD |
4227 | if (speed_cntl & LC_CURRENT_DATA_RATE) { |
4228 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); | |
4229 | return; | |
4230 | } | |
4231 | ||
197bbb3d DA |
4232 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
4233 | ||
9e46a48d AD |
4234 | /* 55 nm r6xx asics */ |
4235 | if ((rdev->family == CHIP_RV670) || | |
4236 | (rdev->family == CHIP_RV620) || | |
4237 | (rdev->family == CHIP_RV635)) { | |
4238 | /* advertise upconfig capability */ | |
492d2b61 | 4239 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
9e46a48d | 4240 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
492d2b61 AD |
4241 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
4242 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); | |
9e46a48d AD |
4243 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
4244 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; | |
4245 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | | |
4246 | LC_RECONFIG_ARC_MISSING_ESCAPE); | |
4247 | link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; | |
492d2b61 | 4248 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
9e46a48d AD |
4249 | } else { |
4250 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
492d2b61 | 4251 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
9e46a48d AD |
4252 | } |
4253 | } | |
4254 | ||
492d2b61 | 4255 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
9e46a48d AD |
4256 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
4257 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | |
4258 | ||
4259 | /* 55 nm r6xx asics */ | |
4260 | if ((rdev->family == CHIP_RV670) || | |
4261 | (rdev->family == CHIP_RV620) || | |
4262 | (rdev->family == CHIP_RV635)) { | |
4263 | WREG32(MM_CFGREGS_CNTL, 0x8); | |
4264 | link_cntl2 = RREG32(0x4088); | |
4265 | WREG32(MM_CFGREGS_CNTL, 0); | |
4266 | /* not supported yet */ | |
4267 | if (link_cntl2 & SELECTABLE_DEEMPHASIS) | |
4268 | return; | |
4269 | } | |
4270 | ||
4271 | speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; | |
4272 | speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); | |
4273 | speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; | |
4274 | speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; | |
4275 | speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; | |
492d2b61 | 4276 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
9e46a48d AD |
4277 | |
4278 | tmp = RREG32(0x541c); | |
4279 | WREG32(0x541c, tmp | 0x8); | |
4280 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); | |
4281 | link_cntl2 = RREG16(0x4088); | |
4282 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; | |
4283 | link_cntl2 |= 0x2; | |
4284 | WREG16(0x4088, link_cntl2); | |
4285 | WREG32(MM_CFGREGS_CNTL, 0); | |
4286 | ||
4287 | if ((rdev->family == CHIP_RV670) || | |
4288 | (rdev->family == CHIP_RV620) || | |
4289 | (rdev->family == CHIP_RV635)) { | |
492d2b61 | 4290 | training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); |
9e46a48d | 4291 | training_cntl &= ~LC_POINT_7_PLUS_EN; |
492d2b61 | 4292 | WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); |
9e46a48d | 4293 | } else { |
492d2b61 | 4294 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
9e46a48d | 4295 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
492d2b61 | 4296 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
9e46a48d AD |
4297 | } |
4298 | ||
492d2b61 | 4299 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
9e46a48d | 4300 | speed_cntl |= LC_GEN2_EN_STRAP; |
492d2b61 | 4301 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
9e46a48d AD |
4302 | |
4303 | } else { | |
492d2b61 | 4304 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
9e46a48d AD |
4305 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
4306 | if (1) | |
4307 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
4308 | else | |
4309 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
492d2b61 | 4310 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
9e46a48d AD |
4311 | } |
4312 | } | |
6759a0a7 MO |
4313 | |
4314 | /** | |
d0418894 | 4315 | * r600_get_gpu_clock_counter - return GPU clock counter snapshot |
6759a0a7 MO |
4316 | * |
4317 | * @rdev: radeon_device pointer | |
4318 | * | |
4319 | * Fetches a GPU clock counter snapshot (R6xx-cayman). | |
4320 | * Returns the 64 bit clock counter snapshot. | |
4321 | */ | |
d0418894 | 4322 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) |
6759a0a7 MO |
4323 | { |
4324 | uint64_t clock; | |
4325 | ||
4326 | mutex_lock(&rdev->gpu_clock_mutex); | |
4327 | WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); | |
4328 | clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | | |
4329 | ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); | |
4330 | mutex_unlock(&rdev->gpu_clock_mutex); | |
4331 | return clock; | |
4332 | } |