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drm/amdgpu: refine code for code style.
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
e0cd3608 31#include <linux/module.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
bfc1f97d 36#include "radeon_audio.h"
3ce0a23d 37#include "radeon_mode.h"
3ce0a23d 38#include "r600d.h"
3ce0a23d 39#include "atom.h"
d39c3b89 40#include "avivod.h"
138e4e16 41#include "radeon_ucode.h"
3ce0a23d
JG		 42
43/* Firmware Names */
44MODULE_FIRMWARE("radeon/R600_pfp.bin");
45MODULE_FIRMWARE("radeon/R600_me.bin");
46MODULE_FIRMWARE("radeon/RV610_pfp.bin");
47MODULE_FIRMWARE("radeon/RV610_me.bin");
48MODULE_FIRMWARE("radeon/RV630_pfp.bin");
49MODULE_FIRMWARE("radeon/RV630_me.bin");
50MODULE_FIRMWARE("radeon/RV620_pfp.bin");
51MODULE_FIRMWARE("radeon/RV620_me.bin");
52MODULE_FIRMWARE("radeon/RV635_pfp.bin");
53MODULE_FIRMWARE("radeon/RV635_me.bin");
54MODULE_FIRMWARE("radeon/RV670_pfp.bin");
55MODULE_FIRMWARE("radeon/RV670_me.bin");
56MODULE_FIRMWARE("radeon/RS780_pfp.bin");
57MODULE_FIRMWARE("radeon/RS780_me.bin");
58MODULE_FIRMWARE("radeon/RV770_pfp.bin");
59MODULE_FIRMWARE("radeon/RV770_me.bin");
66229b20 60MODULE_FIRMWARE("radeon/RV770_smc.bin");
3ce0a23d
JG		 61MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62MODULE_FIRMWARE("radeon/RV730_me.bin");
66229b20
AD		 63MODULE_FIRMWARE("radeon/RV730_smc.bin");
64MODULE_FIRMWARE("radeon/RV740_smc.bin");
3ce0a23d
JG		 65MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66MODULE_FIRMWARE("radeon/RV710_me.bin");
66229b20 67MODULE_FIRMWARE("radeon/RV710_smc.bin");
d8f60cfc
AD		 68MODULE_FIRMWARE("radeon/R600_rlc.bin");
69MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 70MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
71MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 72MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
dc50ba7f 73MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
75MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
dc50ba7f 77MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
fe251e2f
AD		 78MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
79MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 80MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
dc50ba7f 81MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
a7433742 82MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 83MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 84MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
dc50ba7f 85MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
439bd6cd
AD		 86MODULE_FIRMWARE("radeon/PALM_pfp.bin");
87MODULE_FIRMWARE("radeon/PALM_me.bin");
88MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 89MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
90MODULE_FIRMWARE("radeon/SUMO_me.bin");
91MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
92MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d 93
f13f7731
AD		 94static const u32 crtc_offsets[2] =
95{
96 0,
97 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
98};
99
3ce0a23d 100int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 101
1a029b76 102/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9 103int r600_mc_wait_for_idle(struct radeon_device *rdev);
1109ca09 104static void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 105void r600_fini(struct radeon_device *rdev);
45f9a39b 106void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 107static void r600_pcie_gen2_enable(struct radeon_device *rdev);
2948f5e6 108extern int evergreen_rlc_resume(struct radeon_device *rdev);
de9ae744 109extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
771fe6b9 110
9e5acbc2
DV		 111/*
112 * Indirect registers accessor
113 */
114u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
115{
116 unsigned long flags;
117 u32 r;
118
119 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
120 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
121 r = RREG32(R600_RCU_DATA);
122 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
123 return r;
124}
125
126void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
127{
128 unsigned long flags;
129
130 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
131 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
132 WREG32(R600_RCU_DATA, (v));
133 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
134}
135
136u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
137{
138 unsigned long flags;
139 u32 r;
140
141 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
142 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
143 r = RREG32(R600_UVD_CTX_DATA);
144 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
145 return r;
146}
147
148void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
153 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
154 WREG32(R600_UVD_CTX_DATA, (v));
155 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
156}
157
c6d2ac2c
AD		 158/**
159 * r600_get_allowed_info_register - fetch the register for the info ioctl
160 *
161 * @rdev: radeon_device pointer
162 * @reg: register offset in bytes
163 * @val: register value
164 *
165 * Returns 0 for success or -EINVAL for an invalid register
166 *
167 */
168int r600_get_allowed_info_register(struct radeon_device *rdev,
169 u32 reg, u32 *val)
170{
171 switch (reg) {
172 case GRBM_STATUS:
173 case GRBM_STATUS2:
174 case R_000E50_SRBM_STATUS:
175 case DMA_STATUS_REG:
176 case UVD_STATUS:
177 *val = RREG32(reg);
178 return 0;
179 default:
180 return -EINVAL;
181 }
182}
183
454d2e2a
AD		 184/**
185 * r600_get_xclk - get the xclk
186 *
187 * @rdev: radeon_device pointer
188 *
189 * Returns the reference clock used by the gfx engine
190 * (r6xx, IGPs, APUs).
191 */
192u32 r600_get_xclk(struct radeon_device *rdev)
193{
194 return rdev->clock.spll.reference_freq;
195}
196
1b9ba70a
AD		 197int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
198{
4a956a70
AD		 199 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
200 int r;
201
202 /* bypass vclk and dclk with bclk */
203 WREG32_P(CG_UPLL_FUNC_CNTL_2,
204 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
205 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
206
207 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
208 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
209 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
210
211 if (rdev->family >= CHIP_RS780)
212 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
213 ~UPLL_BYPASS_CNTL);
214
215 if (!vclk || !dclk) {
216 /* keep the Bypass mode, put PLL to sleep */
217 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
218 return 0;
219 }
220
221 if (rdev->clock.spll.reference_freq == 10000)
222 ref_div = 34;
223 else
224 ref_div = 4;
225
226 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
227 ref_div + 1, 0xFFF, 2, 30, ~0,
228 &fb_div, &vclk_div, &dclk_div);
229 if (r)
230 return r;
231
232 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
233 fb_div >>= 1;
234 else
235 fb_div |= 1;
236
237 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
3cf8bb1a
JG		 238 if (r)
239 return r;
4a956a70
AD		 240
241 /* assert PLL_RESET */
242 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
243
244 /* For RS780 we have to choose ref clk */
245 if (rdev->family >= CHIP_RS780)
246 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
247 ~UPLL_REFCLK_SRC_SEL_MASK);
248
249 /* set the required fb, ref and post divder values */
250 WREG32_P(CG_UPLL_FUNC_CNTL,
251 UPLL_FB_DIV(fb_div) |
252 UPLL_REF_DIV(ref_div),
253 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
254 WREG32_P(CG_UPLL_FUNC_CNTL_2,
255 UPLL_SW_HILEN(vclk_div >> 1) |
256 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
257 UPLL_SW_HILEN2(dclk_div >> 1) |
258 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
259 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
260 ~UPLL_SW_MASK);
261
262 /* give the PLL some time to settle */
263 mdelay(15);
264
265 /* deassert PLL_RESET */
266 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
267
268 mdelay(15);
269
270 /* deassert BYPASS EN */
271 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
272
273 if (rdev->family >= CHIP_RS780)
274 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
275
276 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
277 if (r)
278 return r;
279
280 /* switch VCLK and DCLK selection */
281 WREG32_P(CG_UPLL_FUNC_CNTL_2,
282 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
283 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
284
285 mdelay(100);
286
1b9ba70a
AD		 287 return 0;
288}
289
134b480f
AD		 290void dce3_program_fmt(struct drm_encoder *encoder)
291{
292 struct drm_device *dev = encoder->dev;
293 struct radeon_device *rdev = dev->dev_private;
294 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
296 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
297 int bpc = 0;
298 u32 tmp = 0;
6214bb74 299 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
134b480f 300
6214bb74
AD		 301 if (connector) {
302 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
134b480f 303 bpc = radeon_get_monitor_bpc(connector);
6214bb74
AD		 304 dither = radeon_connector->dither;
305 }
134b480f
AD		 306
307 /* LVDS FMT is set up by atom */
308 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
309 return;
310
311 /* not needed for analog */
312 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
313 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
314 return;
315
316 if (bpc == 0)
317 return;
318
319 switch (bpc) {
320 case 6:
6214bb74 321 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 322 /* XXX sort out optimal dither settings */
323 tmp |= FMT_SPATIAL_DITHER_EN;
324 else
325 tmp |= FMT_TRUNCATE_EN;
326 break;
327 case 8:
6214bb74 328 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 329 /* XXX sort out optimal dither settings */
330 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
331 else
332 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
333 break;
334 case 10:
335 default:
336 /* not needed */
337 break;
338 }
339
340 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
341}
342
21a8122a 343/* get temperature in millidegrees */
20d391d7 344int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 345{
346 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
347 ASIC_T_SHIFT;
20d391d7 348 int actual_temp = temp & 0xff;
21a8122a 349
20d391d7
AD		 350 if (temp & 0x100)
351 actual_temp -= 256;
352
353 return actual_temp * 1000;
21a8122a
AD		 354}
355
ce8f5370 356void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 357{
358 int i;
359
ce8f5370
AD		 360 rdev->pm.dynpm_can_upclock = true;
361 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 362
363 /* power state array is low to high, default is first */
364 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
365 int min_power_state_index = 0;
366
367 if (rdev->pm.num_power_states > 2)
368 min_power_state_index = 1;
369
ce8f5370
AD		 370 switch (rdev->pm.dynpm_planned_action) {
371 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 372 rdev->pm.requested_power_state_index = min_power_state_index;
373 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 374 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 375 break;
ce8f5370 376 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 377 if (rdev->pm.current_power_state_index == min_power_state_index) {
378 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 379 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 380 } else {
381 if (rdev->pm.active_crtc_count > 1) {
382 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 383 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 384 continue;
385 else if (i >= rdev->pm.current_power_state_index) {
386 rdev->pm.requested_power_state_index =
387 rdev->pm.current_power_state_index;
388 break;
389 } else {
390 rdev->pm.requested_power_state_index = i;
391 break;
392 }
393 }
773c3fa3
AD		 394 } else {
395 if (rdev->pm.current_power_state_index == 0)
396 rdev->pm.requested_power_state_index =
397 rdev->pm.num_power_states - 1;
398 else
399 rdev->pm.requested_power_state_index =
400 rdev->pm.current_power_state_index - 1;
401 }
a48b9b4e
AD		 402 }
403 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 404 /* don't use the power state if crtcs are active and no display flag is set */
405 if ((rdev->pm.active_crtc_count > 0) &&
406 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
407 clock_info[rdev->pm.requested_clock_mode_index].flags &
408 RADEON_PM_MODE_NO_DISPLAY)) {
409 rdev->pm.requested_power_state_index++;
410 }
a48b9b4e 411 break;
ce8f5370 412 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 413 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
414 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 415 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 416 } else {
417 if (rdev->pm.active_crtc_count > 1) {
418 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 419 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 420 continue;
421 else if (i <= rdev->pm.current_power_state_index) {
422 rdev->pm.requested_power_state_index =
423 rdev->pm.current_power_state_index;
424 break;
425 } else {
426 rdev->pm.requested_power_state_index = i;
427 break;
428 }
429 }
430 } else
431 rdev->pm.requested_power_state_index =
432 rdev->pm.current_power_state_index + 1;
433 }
434 rdev->pm.requested_clock_mode_index = 0;
435 break;
ce8f5370 436 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 437 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
438 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 439 rdev->pm.dynpm_can_upclock = false;
58e21dff 440 break;
ce8f5370 441 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 442 default:
443 DRM_ERROR("Requested mode for not defined action\n");
444 return;
445 }
446 } else {
447 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
448 /* for now just select the first power state and switch between clock modes */
449 /* power state array is low to high, default is first (0) */
450 if (rdev->pm.active_crtc_count > 1) {
451 rdev->pm.requested_power_state_index = -1;
452 /* start at 1 as we don't want the default mode */
453 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 454 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 455 continue;
456 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
457 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
458 rdev->pm.requested_power_state_index = i;
459 break;
460 }
461 }
462 /* if nothing selected, grab the default state. */
463 if (rdev->pm.requested_power_state_index == -1)
464 rdev->pm.requested_power_state_index = 0;
465 } else
466 rdev->pm.requested_power_state_index = 1;
467
ce8f5370
AD		 468 switch (rdev->pm.dynpm_planned_action) {
469 case DYNPM_ACTION_MINIMUM:
a48b9b4e 470 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 471 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 472 break;
ce8f5370 473 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 474 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
475 if (rdev->pm.current_clock_mode_index == 0) {
476 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 477 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 478 } else
479 rdev->pm.requested_clock_mode_index =
480 rdev->pm.current_clock_mode_index - 1;
481 } else {
482 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 483 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 484 }
d7311171
AD		 485 /* don't use the power state if crtcs are active and no display flag is set */
486 if ((rdev->pm.active_crtc_count > 0) &&
487 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
488 clock_info[rdev->pm.requested_clock_mode_index].flags &
489 RADEON_PM_MODE_NO_DISPLAY)) {
490 rdev->pm.requested_clock_mode_index++;
491 }
a48b9b4e 492 break;
ce8f5370 493 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 494 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
495 if (rdev->pm.current_clock_mode_index ==
496 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
497 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 498 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 499 } else
500 rdev->pm.requested_clock_mode_index =
501 rdev->pm.current_clock_mode_index + 1;
502 } else {
503 rdev->pm.requested_clock_mode_index =
504 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 505 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 506 }
507 break;
ce8f5370 508 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 509 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
510 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 511 rdev->pm.dynpm_can_upclock = false;
58e21dff 512 break;
ce8f5370 513 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 514 default:
515 DRM_ERROR("Requested mode for not defined action\n");
516 return;
517 }
518 }
519
d9fdaafb 520 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 521 rdev->pm.power_state[rdev->pm.requested_power_state_index].
522 clock_info[rdev->pm.requested_clock_mode_index].sclk,
523 rdev->pm.power_state[rdev->pm.requested_power_state_index].
524 clock_info[rdev->pm.requested_clock_mode_index].mclk,
525 rdev->pm.power_state[rdev->pm.requested_power_state_index].
526 pcie_lanes);
a48b9b4e
AD		 527}
528
ce8f5370
AD		 529void rs780_pm_init_profile(struct radeon_device *rdev)
530{
531 if (rdev->pm.num_power_states == 2) {
532 /* default */
533 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
534 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
535 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
536 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
537 /* low sh */
538 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
539 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
540 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 542 /* mid sh */
543 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
544 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
546 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 547 /* high sh */
548 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
550 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
551 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
552 /* low mh */
553 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
554 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
555 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
556 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 557 /* mid mh */
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
559 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
561 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 562 /* high mh */
563 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
564 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
565 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
566 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
567 } else if (rdev->pm.num_power_states == 3) {
568 /* default */
569 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
570 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
571 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
573 /* low sh */
574 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
575 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
576 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
577 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 578 /* mid sh */
579 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
580 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
581 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
582 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 583 /* high sh */
584 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
585 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
586 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
587 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
588 /* low mh */
589 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
590 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
591 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
592 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 593 /* mid mh */
594 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
595 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
596 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
597 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 598 /* high mh */
599 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
600 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
601 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
602 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
603 } else {
604 /* default */
605 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
606 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
607 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
608 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
609 /* low sh */
610 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
611 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
612 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
613 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 614 /* mid sh */
615 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
616 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
617 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
618 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 619 /* high sh */
620 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
621 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
622 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
623 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
624 /* low mh */
625 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
626 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
627 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
628 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 629 /* mid mh */
630 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
631 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
632 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
633 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 634 /* high mh */
635 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
636 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
637 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
638 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
639 }
640}
bae6b562 641
ce8f5370
AD		 642void r600_pm_init_profile(struct radeon_device *rdev)
643{
bbe26ffe
AD		 644 int idx;
645
ce8f5370
AD		 646 if (rdev->family == CHIP_R600) {
647 /* XXX */
648 /* default */
649 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
650 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
651 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 652 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 653 /* low sh */
654 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
655 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
656 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 657 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 658 /* mid sh */
659 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
660 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
661 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
662 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 663 /* high sh */
664 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
665 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
666 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 667 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 668 /* low mh */
669 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
670 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
671 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 672 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 673 /* mid mh */
674 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
675 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
676 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
677 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 678 /* high mh */
679 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
680 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
681 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 682 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 683 } else {
684 if (rdev->pm.num_power_states < 4) {
685 /* default */
686 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
687 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
688 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
689 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
690 /* low sh */
4bff5171
AD		 691 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
692 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 693 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 694 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
695 /* mid sh */
696 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
697 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
698 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
699 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 700 /* high sh */
4bff5171
AD		 701 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
702 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 703 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
704 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
705 /* low mh */
4bff5171
AD		 706 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
707 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 708 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 709 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
710 /* low mh */
711 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
712 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
713 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
714 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 715 /* high mh */
4bff5171
AD		 716 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
717 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 718 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
719 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
720 } else {
721 /* default */
722 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
723 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
724 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
725 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
726 /* low sh */
bbe26ffe
AD		 727 if (rdev->flags & RADEON_IS_MOBILITY)
728 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
729 else
730 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
731 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
732 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
733 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
734 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 735 /* mid sh */
bbe26ffe
AD		 736 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
737 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
738 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
739 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 740 /* high sh */
bbe26ffe
AD		 741 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
742 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
743 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 744 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
745 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
746 /* low mh */
bbe26ffe
AD		 747 if (rdev->flags & RADEON_IS_MOBILITY)
748 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
749 else
750 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
751 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
752 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
753 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
754 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 755 /* mid mh */
bbe26ffe
AD		 756 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
757 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
758 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
759 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 760 /* high mh */
bbe26ffe
AD		 761 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
762 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
763 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 764 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
765 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
766 }
767 }
bae6b562
AD		 768}
769
49e02b73
AD		 770void r600_pm_misc(struct radeon_device *rdev)
771{
a081a9d6
RM		 772 int req_ps_idx = rdev->pm.requested_power_state_index;
773 int req_cm_idx = rdev->pm.requested_clock_mode_index;
774 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
775 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 776
4d60173f 777 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 778 /* 0xff01 is a flag rather then an actual voltage */
779 if (voltage->voltage == 0xff01)
780 return;
4d60173f 781 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 782 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 783 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 784 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 785 }
786 }
49e02b73
AD		 787}
788
def9ba9c
AD		 789bool r600_gui_idle(struct radeon_device *rdev)
790{
791 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
792 return false;
793 else
794 return true;
795}
796
e0df1ac5
AD		 797/* hpd for digital panel detect/disconnect */
798bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
799{
800 bool connected = false;
801
802 if (ASIC_IS_DCE3(rdev)) {
803 switch (hpd) {
804 case RADEON_HPD_1:
805 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
806 connected = true;
807 break;
808 case RADEON_HPD_2:
809 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
810 connected = true;
811 break;
812 case RADEON_HPD_3:
813 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
814 connected = true;
815 break;
816 case RADEON_HPD_4:
817 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
818 connected = true;
819 break;
820 /* DCE 3.2 */
821 case RADEON_HPD_5:
822 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
823 connected = true;
824 break;
825 case RADEON_HPD_6:
826 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
827 connected = true;
828 break;
829 default:
830 break;
831 }
832 } else {
833 switch (hpd) {
834 case RADEON_HPD_1:
835 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
836 connected = true;
837 break;
838 case RADEON_HPD_2:
839 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
840 connected = true;
841 break;
842 case RADEON_HPD_3:
843 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
844 connected = true;
845 break;
846 default:
847 break;
848 }
849 }
850 return connected;
851}
852
853void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 854 enum radeon_hpd_id hpd)
e0df1ac5
AD		 855{
856 u32 tmp;
857 bool connected = r600_hpd_sense(rdev, hpd);
858
859 if (ASIC_IS_DCE3(rdev)) {
860 switch (hpd) {
861 case RADEON_HPD_1:
862 tmp = RREG32(DC_HPD1_INT_CONTROL);
863 if (connected)
864 tmp &= ~DC_HPDx_INT_POLARITY;
865 else
866 tmp |= DC_HPDx_INT_POLARITY;
867 WREG32(DC_HPD1_INT_CONTROL, tmp);
868 break;
869 case RADEON_HPD_2:
870 tmp = RREG32(DC_HPD2_INT_CONTROL);
871 if (connected)
872 tmp &= ~DC_HPDx_INT_POLARITY;
873 else
874 tmp |= DC_HPDx_INT_POLARITY;
875 WREG32(DC_HPD2_INT_CONTROL, tmp);
876 break;
877 case RADEON_HPD_3:
878 tmp = RREG32(DC_HPD3_INT_CONTROL);
879 if (connected)
880 tmp &= ~DC_HPDx_INT_POLARITY;
881 else
882 tmp |= DC_HPDx_INT_POLARITY;
883 WREG32(DC_HPD3_INT_CONTROL, tmp);
884 break;
885 case RADEON_HPD_4:
886 tmp = RREG32(DC_HPD4_INT_CONTROL);
887 if (connected)
888 tmp &= ~DC_HPDx_INT_POLARITY;
889 else
890 tmp |= DC_HPDx_INT_POLARITY;
891 WREG32(DC_HPD4_INT_CONTROL, tmp);
892 break;
893 case RADEON_HPD_5:
894 tmp = RREG32(DC_HPD5_INT_CONTROL);
895 if (connected)
896 tmp &= ~DC_HPDx_INT_POLARITY;
897 else
898 tmp |= DC_HPDx_INT_POLARITY;
899 WREG32(DC_HPD5_INT_CONTROL, tmp);
900 break;
901 /* DCE 3.2 */
902 case RADEON_HPD_6:
903 tmp = RREG32(DC_HPD6_INT_CONTROL);
904 if (connected)
905 tmp &= ~DC_HPDx_INT_POLARITY;
906 else
907 tmp |= DC_HPDx_INT_POLARITY;
908 WREG32(DC_HPD6_INT_CONTROL, tmp);
909 break;
910 default:
911 break;
912 }
913 } else {
914 switch (hpd) {
915 case RADEON_HPD_1:
916 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
917 if (connected)
918 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
919 else
920 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
921 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
922 break;
923 case RADEON_HPD_2:
924 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
925 if (connected)
926 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
927 else
928 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
929 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
930 break;
931 case RADEON_HPD_3:
932 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
933 if (connected)
934 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
935 else
936 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
937 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
938 break;
939 default:
940 break;
941 }
942 }
943}
944
945void r600_hpd_init(struct radeon_device *rdev)
946{
947 struct drm_device *dev = rdev->ddev;
948 struct drm_connector *connector;
fb98257a 949 unsigned enable = 0;
e0df1ac5 950
64912e99
AD		 951 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
952 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
953
455c89b9
JG		 954 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
955 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
956 /* don't try to enable hpd on eDP or LVDS avoid breaking the
957 * aux dp channel on imac and help (but not completely fix)
958 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
959 */
960 continue;
961 }
64912e99
AD		 962 if (ASIC_IS_DCE3(rdev)) {
963 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
964 if (ASIC_IS_DCE32(rdev))
965 tmp |= DC_HPDx_EN;
e0df1ac5 966
e0df1ac5
AD		 967 switch (radeon_connector->hpd.hpd) {
968 case RADEON_HPD_1:
969 WREG32(DC_HPD1_CONTROL, tmp);
e0df1ac5
AD		 970 break;
971 case RADEON_HPD_2:
972 WREG32(DC_HPD2_CONTROL, tmp);
e0df1ac5
AD		 973 break;
974 case RADEON_HPD_3:
975 WREG32(DC_HPD3_CONTROL, tmp);
e0df1ac5
AD		 976 break;
977 case RADEON_HPD_4:
978 WREG32(DC_HPD4_CONTROL, tmp);
e0df1ac5
AD		 979 break;
980 /* DCE 3.2 */
981 case RADEON_HPD_5:
982 WREG32(DC_HPD5_CONTROL, tmp);
e0df1ac5
AD		 983 break;
984 case RADEON_HPD_6:
985 WREG32(DC_HPD6_CONTROL, tmp);
e0df1ac5
AD		 986 break;
987 default:
988 break;
989 }
64912e99 990 } else {
e0df1ac5
AD		 991 switch (radeon_connector->hpd.hpd) {
992 case RADEON_HPD_1:
993 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 994 break;
995 case RADEON_HPD_2:
996 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 997 break;
998 case RADEON_HPD_3:
999 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 1000 break;
1001 default:
1002 break;
1003 }
1004 }
fb98257a 1005 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 1006 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 1007 }
fb98257a 1008 radeon_irq_kms_enable_hpd(rdev, enable);
e0df1ac5
AD		 1009}
1010
1011void r600_hpd_fini(struct radeon_device *rdev)
1012{
1013 struct drm_device *dev = rdev->ddev;
1014 struct drm_connector *connector;
fb98257a 1015 unsigned disable = 0;
e0df1ac5 1016
fb98257a
CK		 1017 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1018 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1019 if (ASIC_IS_DCE3(rdev)) {
e0df1ac5
AD		 1020 switch (radeon_connector->hpd.hpd) {
1021 case RADEON_HPD_1:
1022 WREG32(DC_HPD1_CONTROL, 0);
e0df1ac5
AD		 1023 break;
1024 case RADEON_HPD_2:
1025 WREG32(DC_HPD2_CONTROL, 0);
e0df1ac5
AD		 1026 break;
1027 case RADEON_HPD_3:
1028 WREG32(DC_HPD3_CONTROL, 0);
e0df1ac5
AD		 1029 break;
1030 case RADEON_HPD_4:
1031 WREG32(DC_HPD4_CONTROL, 0);
e0df1ac5
AD		 1032 break;
1033 /* DCE 3.2 */
1034 case RADEON_HPD_5:
1035 WREG32(DC_HPD5_CONTROL, 0);
e0df1ac5
AD		 1036 break;
1037 case RADEON_HPD_6:
1038 WREG32(DC_HPD6_CONTROL, 0);
e0df1ac5
AD		 1039 break;
1040 default:
1041 break;
1042 }
fb98257a 1043 } else {
e0df1ac5
AD		 1044 switch (radeon_connector->hpd.hpd) {
1045 case RADEON_HPD_1:
1046 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
e0df1ac5
AD		 1047 break;
1048 case RADEON_HPD_2:
1049 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
e0df1ac5
AD		 1050 break;
1051 case RADEON_HPD_3:
1052 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
e0df1ac5
AD		 1053 break;
1054 default:
1055 break;
1056 }
1057 }
fb98257a 1058 disable |= 1 << radeon_connector->hpd.hpd;
e0df1ac5 1059 }
fb98257a 1060 radeon_irq_kms_disable_hpd(rdev, disable);
e0df1ac5
AD		 1061}
1062
771fe6b9 1063/*
3ce0a23d 1064 * R600 PCIE GART
771fe6b9 1065 */
3ce0a23d
JG		 1066void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
1067{
1068 unsigned i;
1069 u32 tmp;
1070
2e98f10a 1071 /* flush hdp cache so updates hit vram */
f3886f85
AD		 1072 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
1073 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 1074 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 1075 u32 tmp;
1076
1077 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
1078 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 1079 * This seems to cause problems on some AGP cards. Just use the old
1080 * method for them.
812d0469
AD		 1081 */
1082 WREG32(HDP_DEBUG1, 0);
1083 tmp = readl((void __iomem *)ptr);
1084 } else
1085 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 1086
3ce0a23d
JG		 1087 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1088 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1089 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1090 for (i = 0; i < rdev->usec_timeout; i++) {
1091 /* read MC_STATUS */
1092 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1093 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1094 if (tmp == 2) {
1095 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1096 return;
1097 }
1098 if (tmp) {
1099 return;
1100 }
1101 udelay(1);
1102 }
1103}
1104
4aac0473 1105int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 1106{
4aac0473 1107 int r;
3ce0a23d 1108
c9a1be96 1109 if (rdev->gart.robj) {
fce7d61b 1110 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 1111 return 0;
1112 }
3ce0a23d
JG		 1113 /* Initialize common gart structure */
1114 r = radeon_gart_init(rdev);
4aac0473 1115 if (r)
3ce0a23d 1116 return r;
3ce0a23d 1117 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 1118 return radeon_gart_table_vram_alloc(rdev);
1119}
1120
1109ca09 1121static int r600_pcie_gart_enable(struct radeon_device *rdev)
4aac0473
JG		 1122{
1123 u32 tmp;
1124 int r, i;
1125
c9a1be96 1126 if (rdev->gart.robj == NULL) {
4aac0473
JG		 1127 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1128 return -EINVAL;
771fe6b9 1129 }
4aac0473
JG		 1130 r = radeon_gart_table_vram_pin(rdev);
1131 if (r)
1132 return r;
bc1a631e 1133
3ce0a23d
JG		 1134 /* Setup L2 cache */
1135 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1136 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1137 EFFECTIVE_L2_QUEUE_SIZE(7));
1138 WREG32(VM_L2_CNTL2, 0);
1139 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1140 /* Setup TLB control */
1141 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1142 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1143 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1144 ENABLE_WAIT_L2_QUERY;
1145 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1146 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1147 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1148 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1149 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1150 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1151 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1152 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1153 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1154 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1155 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1156 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
a8fba64a
CK		 1157 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1158 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
3ce0a23d
JG		 1159 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1160 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1161 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
7c0411d2 1162 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 1163 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1164 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1165 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1166 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1167 (u32)(rdev->dummy_page.addr >> 12));
1168 for (i = 1; i < 7; i++)
1169 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 1170
3ce0a23d 1171 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1172 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1173 (unsigned)(rdev->mc.gtt_size >> 20),
1174 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 1175 rdev->gart.ready = true;
771fe6b9
JG		 1176 return 0;
1177}
1178
1109ca09 1179static void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 1180{
3ce0a23d 1181 u32 tmp;
c9a1be96 1182 int i;
771fe6b9 1183
3ce0a23d
JG		 1184 /* Disable all tables */
1185 for (i = 0; i < 7; i++)
1186 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 1187
3ce0a23d
JG		 1188 /* Disable L2 cache */
1189 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1190 EFFECTIVE_L2_QUEUE_SIZE(7));
1191 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1192 /* Setup L1 TLB control */
1193 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1194 ENABLE_WAIT_L2_QUERY;
1195 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1196 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1197 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1198 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1199 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1200 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1201 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1202 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1203 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1204 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1205 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1206 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1207 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1208 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
a8fba64a
CK		 1209 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1210 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
c9a1be96 1211 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 1212}
1213
1109ca09 1214static void r600_pcie_gart_fini(struct radeon_device *rdev)
4aac0473 1215{
f9274562 1216 radeon_gart_fini(rdev);
4aac0473
JG		 1217 r600_pcie_gart_disable(rdev);
1218 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1219}
1220
1109ca09 1221static void r600_agp_enable(struct radeon_device *rdev)
1a029b76
JG		 1222{
1223 u32 tmp;
1224 int i;
1225
1226 /* Setup L2 cache */
1227 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1228 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1229 EFFECTIVE_L2_QUEUE_SIZE(7));
1230 WREG32(VM_L2_CNTL2, 0);
1231 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1232 /* Setup TLB control */
1233 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1234 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1235 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1236 ENABLE_WAIT_L2_QUERY;
1237 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1238 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1239 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1240 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1241 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1242 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1243 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1244 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1245 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1246 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1247 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1248 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1249 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1250 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1251 for (i = 0; i < 7; i++)
1252 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1253}
1254
771fe6b9
JG		 1255int r600_mc_wait_for_idle(struct radeon_device *rdev)
1256{
3ce0a23d
JG		 1257 unsigned i;
1258 u32 tmp;
1259
1260 for (i = 0; i < rdev->usec_timeout; i++) {
1261 /* read MC_STATUS */
1262 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1263 if (!tmp)
1264 return 0;
1265 udelay(1);
1266 }
1267 return -1;
771fe6b9
JG		 1268}
1269
65337e60
SL		 1270uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1271{
0a5b7b0b 1272 unsigned long flags;
65337e60
SL		 1273 uint32_t r;
1274
0a5b7b0b 1275 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1276 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1277 r = RREG32(R_0028FC_MC_DATA);
1278 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
0a5b7b0b 1279 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1280 return r;
1281}
1282
1283void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1284{
0a5b7b0b
AD		 1285 unsigned long flags;
1286
1287 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1288 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1289 S_0028F8_MC_IND_WR_EN(1));
1290 WREG32(R_0028FC_MC_DATA, v);
1291 WREG32(R_0028F8_MC_INDEX, 0x7F);
0a5b7b0b 1292 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1293}
1294
a3c1945a 1295static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1296{
a3c1945a 1297 struct rv515_mc_save save;
3ce0a23d
JG		 1298 u32 tmp;
1299 int i, j;
771fe6b9 1300
3ce0a23d
JG		 1301 /* Initialize HDP */
1302 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1303 WREG32((0x2c14 + j), 0x00000000);
1304 WREG32((0x2c18 + j), 0x00000000);
1305 WREG32((0x2c1c + j), 0x00000000);
1306 WREG32((0x2c20 + j), 0x00000000);
1307 WREG32((0x2c24 + j), 0x00000000);
1308 }
1309 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1310
a3c1945a 1311 rv515_mc_stop(rdev, &save);
3ce0a23d 1312 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1313 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1314 }
a3c1945a 1315 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1316 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1317 /* Update configuration */
1a029b76
JG		 1318 if (rdev->flags & RADEON_IS_AGP) {
1319 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1320 /* VRAM before AGP */
1321 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1322 rdev->mc.vram_start >> 12);
1323 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1324 rdev->mc.gtt_end >> 12);
1325 } else {
1326 /* VRAM after AGP */
1327 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1328 rdev->mc.gtt_start >> 12);
1329 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1330 rdev->mc.vram_end >> 12);
1331 }
1332 } else {
1333 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1334 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1335 }
16cdf04d 1336 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1337 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1338 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1339 WREG32(MC_VM_FB_LOCATION, tmp);
1340 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1341 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1342 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1343 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1344 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1345 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1346 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1347 } else {
1348 WREG32(MC_VM_AGP_BASE, 0);
1349 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1350 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1351 }
3ce0a23d 1352 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1353 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1354 }
a3c1945a 1355 rv515_mc_resume(rdev, &save);
698443d9
DA		 1356 /* we need to own VRAM, so turn off the VGA renderer here
1357 * to stop it overwriting our objects */
d39c3b89 1358 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1359}
1360
d594e46a
JG		 1361/**
1362 * r600_vram_gtt_location - try to find VRAM & GTT location
1363 * @rdev: radeon device structure holding all necessary informations
1364 * @mc: memory controller structure holding memory informations
1365 *
1366 * Function will place try to place VRAM at same place as in CPU (PCI)
1367 * address space as some GPU seems to have issue when we reprogram at
1368 * different address space.
1369 *
1370 * If there is not enough space to fit the unvisible VRAM after the
1371 * aperture then we limit the VRAM size to the aperture.
1372 *
1373 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1374 * them to be in one from GPU point of view so that we can program GPU to
1375 * catch access outside them (weird GPU policy see ??).
1376 *
1377 * This function will never fails, worst case are limiting VRAM or GTT.
1378 *
1379 * Note: GTT start, end, size should be initialized before calling this
1380 * function on AGP platform.
1381 */
0ef0c1f7 1382static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1383{
1384 u64 size_bf, size_af;
1385
1386 if (mc->mc_vram_size > 0xE0000000) {
1387 /* leave room for at least 512M GTT */
1388 dev_warn(rdev->dev, "limiting VRAM\n");
1389 mc->real_vram_size = 0xE0000000;
1390 mc->mc_vram_size = 0xE0000000;
1391 }
1392 if (rdev->flags & RADEON_IS_AGP) {
1393 size_bf = mc->gtt_start;
9ed8b1f9 1394 size_af = mc->mc_mask - mc->gtt_end;
d594e46a
JG		 1395 if (size_bf > size_af) {
1396 if (mc->mc_vram_size > size_bf) {
1397 dev_warn(rdev->dev, "limiting VRAM\n");
1398 mc->real_vram_size = size_bf;
1399 mc->mc_vram_size = size_bf;
1400 }
1401 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1402 } else {
1403 if (mc->mc_vram_size > size_af) {
1404 dev_warn(rdev->dev, "limiting VRAM\n");
1405 mc->real_vram_size = size_af;
1406 mc->mc_vram_size = size_af;
1407 }
dfc6ae5b 1408 mc->vram_start = mc->gtt_end + 1;
d594e46a
JG		 1409 }
1410 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1411 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1412 mc->mc_vram_size >> 20, mc->vram_start,
1413 mc->vram_end, mc->real_vram_size >> 20);
1414 } else {
1415 u64 base = 0;
8961d52d
AD		 1416 if (rdev->flags & RADEON_IS_IGP) {
1417 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1418 base <<= 24;
1419 }
d594e46a 1420 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1421 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1422 radeon_gtt_location(rdev, mc);
1423 }
1424}
1425
1109ca09 1426static int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1427{
3ce0a23d 1428 u32 tmp;
5885b7a9 1429 int chansize, numchan;
65337e60
SL		 1430 uint32_t h_addr, l_addr;
1431 unsigned long long k8_addr;
771fe6b9 1432
3ce0a23d 1433 /* Get VRAM informations */
771fe6b9 1434 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1435 tmp = RREG32(RAMCFG);
1436 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1437 chansize = 16;
3ce0a23d 1438 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1439 chansize = 64;
1440 } else {
1441 chansize = 32;
1442 }
5885b7a9
AD		 1443 tmp = RREG32(CHMAP);
1444 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1445 case 0:
1446 default:
1447 numchan = 1;
1448 break;
1449 case 1:
1450 numchan = 2;
1451 break;
1452 case 2:
1453 numchan = 4;
1454 break;
1455 case 3:
1456 numchan = 8;
1457 break;
771fe6b9 1458 }
5885b7a9 1459 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1460 /* Could aper size report 0 ? */
01d73a69
JC		 1461 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1462 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1463 /* Setup GPU memory space */
1464 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1465 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1466 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1467 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1468
f892034a
AD		 1469 if (rdev->flags & RADEON_IS_IGP) {
1470 rs690_pm_info(rdev);
06b6476d 1471 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
65337e60
SL		 1472
1473 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1474 /* Use K8 direct mapping for fast fb access. */
1475 rdev->fastfb_working = false;
1476 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1477 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1478 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1479#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1480 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1481#endif
1482 {
1483 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1484 * memory is present.
1485 */
1486 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1487 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1488 (unsigned long long)rdev->mc.aper_base, k8_addr);
1489 rdev->mc.aper_base = (resource_size_t)k8_addr;
1490 rdev->fastfb_working = true;
1491 }
1492 }
3cf8bb1a 1493 }
f892034a 1494 }
65337e60 1495
f47299c5 1496 radeon_update_bandwidth_info(rdev);
3ce0a23d 1497 return 0;
771fe6b9
JG		 1498}
1499
16cdf04d
AD		 1500int r600_vram_scratch_init(struct radeon_device *rdev)
1501{
1502 int r;
1503
1504 if (rdev->vram_scratch.robj == NULL) {
1505 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1506 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
831b6966 1507 0, NULL, NULL, &rdev->vram_scratch.robj);
16cdf04d
AD		 1508 if (r) {
1509 return r;
1510 }
1511 }
1512
1513 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1514 if (unlikely(r != 0))
1515 return r;
1516 r = radeon_bo_pin(rdev->vram_scratch.robj,
1517 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1518 if (r) {
1519 radeon_bo_unreserve(rdev->vram_scratch.robj);
1520 return r;
1521 }
1522 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1523 (void **)&rdev->vram_scratch.ptr);
1524 if (r)
1525 radeon_bo_unpin(rdev->vram_scratch.robj);
1526 radeon_bo_unreserve(rdev->vram_scratch.robj);
1527
1528 return r;
1529}
1530
1531void r600_vram_scratch_fini(struct radeon_device *rdev)
1532{
1533 int r;
1534
1535 if (rdev->vram_scratch.robj == NULL) {
1536 return;
1537 }
1538 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1539 if (likely(r == 0)) {
1540 radeon_bo_kunmap(rdev->vram_scratch.robj);
1541 radeon_bo_unpin(rdev->vram_scratch.robj);
1542 radeon_bo_unreserve(rdev->vram_scratch.robj);
1543 }
1544 radeon_bo_unref(&rdev->vram_scratch.robj);
1545}
1546
410a3418
AD		 1547void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1548{
1549 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1550
1551 if (hung)
1552 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1553 else
1554 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1555
1556 WREG32(R600_BIOS_3_SCRATCH, tmp);
1557}
1558
d3cb781e 1559static void r600_print_gpu_status_regs(struct radeon_device *rdev)
771fe6b9 1560{
64c56e8c 1561 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
d3cb781e 1562 RREG32(R_008010_GRBM_STATUS));
64c56e8c 1563 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
d3cb781e 1564 RREG32(R_008014_GRBM_STATUS2));
64c56e8c 1565 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
d3cb781e 1566 RREG32(R_000E50_SRBM_STATUS));
440a7cd8 1567 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
d3cb781e 1568 RREG32(CP_STALLED_STAT1));
440a7cd8 1569 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
d3cb781e 1570 RREG32(CP_STALLED_STAT2));
440a7cd8 1571 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
d3cb781e 1572 RREG32(CP_BUSY_STAT));
440a7cd8 1573 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
d3cb781e 1574 RREG32(CP_STAT));
71e3d157
AD		 1575 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1576 RREG32(DMA_STATUS_REG));
1577}
1578
f13f7731 1579static bool r600_is_display_hung(struct radeon_device *rdev)
71e3d157 1580{
f13f7731
AD		 1581 u32 crtc_hung = 0;
1582 u32 crtc_status[2];
1583 u32 i, j, tmp;
1584
1585 for (i = 0; i < rdev->num_crtc; i++) {
1586 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1587 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1588 crtc_hung |= (1 << i);
1589 }
1590 }
1591
1592 for (j = 0; j < 10; j++) {
1593 for (i = 0; i < rdev->num_crtc; i++) {
1594 if (crtc_hung & (1 << i)) {
1595 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1596 if (tmp != crtc_status[i])
1597 crtc_hung &= ~(1 << i);
1598 }
1599 }
1600 if (crtc_hung == 0)
1601 return false;
1602 udelay(100);
1603 }
1604
1605 return true;
1606}
1607
2483b4ea 1608u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
f13f7731
AD		 1609{
1610 u32 reset_mask = 0;
d3cb781e 1611 u32 tmp;
71e3d157 1612
f13f7731
AD		 1613 /* GRBM_STATUS */
1614 tmp = RREG32(R_008010_GRBM_STATUS);
1615 if (rdev->family >= CHIP_RV770) {
1616 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1617 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1618 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1619 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1620 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1621 reset_mask |= RADEON_RESET_GFX;
1622 } else {
1623 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1624 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1625 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1626 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1627 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1628 reset_mask |= RADEON_RESET_GFX;
1629 }
1630
1631 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1632 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1633 reset_mask |= RADEON_RESET_CP;
1634
1635 if (G_008010_GRBM_EE_BUSY(tmp))
1636 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1637
1638 /* DMA_STATUS_REG */
1639 tmp = RREG32(DMA_STATUS_REG);
1640 if (!(tmp & DMA_IDLE))
1641 reset_mask |= RADEON_RESET_DMA;
1642
1643 /* SRBM_STATUS */
1644 tmp = RREG32(R_000E50_SRBM_STATUS);
1645 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1646 reset_mask |= RADEON_RESET_RLC;
1647
1648 if (G_000E50_IH_BUSY(tmp))
1649 reset_mask |= RADEON_RESET_IH;
1650
1651 if (G_000E50_SEM_BUSY(tmp))
1652 reset_mask |= RADEON_RESET_SEM;
19fc42ed 1653
f13f7731
AD		 1654 if (G_000E50_GRBM_RQ_PENDING(tmp))
1655 reset_mask |= RADEON_RESET_GRBM;
1656
1657 if (G_000E50_VMC_BUSY(tmp))
1658 reset_mask |= RADEON_RESET_VMC;
1659
1660 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1661 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1662 G_000E50_MCDW_BUSY(tmp))
1663 reset_mask |= RADEON_RESET_MC;
1664
1665 if (r600_is_display_hung(rdev))
1666 reset_mask |= RADEON_RESET_DISPLAY;
1667
d808fc88
AD		 1668 /* Skip MC reset as it's mostly likely not hung, just busy */
1669 if (reset_mask & RADEON_RESET_MC) {
1670 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1671 reset_mask &= ~RADEON_RESET_MC;
1672 }
1673
f13f7731
AD		 1674 return reset_mask;
1675}
1676
1677static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1678{
1679 struct rv515_mc_save save;
1680 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1681 u32 tmp;
19fc42ed 1682
71e3d157 1683 if (reset_mask == 0)
f13f7731 1684 return;
71e3d157
AD		 1685
1686 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1687
d3cb781e
AD		 1688 r600_print_gpu_status_regs(rdev);
1689
d3cb781e
AD		 1690 /* Disable CP parsing/prefetching */
1691 if (rdev->family >= CHIP_RV770)
1692 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1693 else
1694 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1695
1696 /* disable the RLC */
1697 WREG32(RLC_CNTL, 0);
1698
1699 if (reset_mask & RADEON_RESET_DMA) {
1700 /* Disable DMA */
1701 tmp = RREG32(DMA_RB_CNTL);
1702 tmp &= ~DMA_RB_ENABLE;
1703 WREG32(DMA_RB_CNTL, tmp);
1704 }
1705
1706 mdelay(50);
1707
ca57802e
AD		 1708 rv515_mc_stop(rdev, &save);
1709 if (r600_mc_wait_for_idle(rdev)) {
1710 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1711 }
1712
d3cb781e
AD		 1713 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1714 if (rdev->family >= CHIP_RV770)
1715 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1716 S_008020_SOFT_RESET_CB(1) |
1717 S_008020_SOFT_RESET_PA(1) |
1718 S_008020_SOFT_RESET_SC(1) |
1719 S_008020_SOFT_RESET_SPI(1) |
1720 S_008020_SOFT_RESET_SX(1) |
1721 S_008020_SOFT_RESET_SH(1) |
1722 S_008020_SOFT_RESET_TC(1) |
1723 S_008020_SOFT_RESET_TA(1) |
1724 S_008020_SOFT_RESET_VC(1) |
1725 S_008020_SOFT_RESET_VGT(1);
1726 else
1727 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1728 S_008020_SOFT_RESET_DB(1) |
1729 S_008020_SOFT_RESET_CB(1) |
1730 S_008020_SOFT_RESET_PA(1) |
1731 S_008020_SOFT_RESET_SC(1) |
1732 S_008020_SOFT_RESET_SMX(1) |
1733 S_008020_SOFT_RESET_SPI(1) |
1734 S_008020_SOFT_RESET_SX(1) |
1735 S_008020_SOFT_RESET_SH(1) |
1736 S_008020_SOFT_RESET_TC(1) |
1737 S_008020_SOFT_RESET_TA(1) |
1738 S_008020_SOFT_RESET_VC(1) |
1739 S_008020_SOFT_RESET_VGT(1);
1740 }
1741
1742 if (reset_mask & RADEON_RESET_CP) {
1743 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1744 S_008020_SOFT_RESET_VGT(1);
1745
1746 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1747 }
1748
1749 if (reset_mask & RADEON_RESET_DMA) {
1750 if (rdev->family >= CHIP_RV770)
1751 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1752 else
1753 srbm_soft_reset |= SOFT_RESET_DMA;
1754 }
1755
f13f7731
AD		 1756 if (reset_mask & RADEON_RESET_RLC)
1757 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1758
1759 if (reset_mask & RADEON_RESET_SEM)
1760 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1761
1762 if (reset_mask & RADEON_RESET_IH)
1763 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1764
1765 if (reset_mask & RADEON_RESET_GRBM)
1766 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1767
24178ec4
AD		 1768 if (!(rdev->flags & RADEON_IS_IGP)) {
1769 if (reset_mask & RADEON_RESET_MC)
1770 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1771 }
f13f7731
AD		 1772
1773 if (reset_mask & RADEON_RESET_VMC)
1774 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1775
d3cb781e
AD		 1776 if (grbm_soft_reset) {
1777 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1778 tmp |= grbm_soft_reset;
1779 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1780 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1781 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1782
1783 udelay(50);
1784
1785 tmp &= ~grbm_soft_reset;
1786 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1787 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1788 }
1789
1790 if (srbm_soft_reset) {
1791 tmp = RREG32(SRBM_SOFT_RESET);
1792 tmp |= srbm_soft_reset;
1793 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1794 WREG32(SRBM_SOFT_RESET, tmp);
1795 tmp = RREG32(SRBM_SOFT_RESET);
1796
1797 udelay(50);
71e3d157 1798
d3cb781e
AD		 1799 tmp &= ~srbm_soft_reset;
1800 WREG32(SRBM_SOFT_RESET, tmp);
1801 tmp = RREG32(SRBM_SOFT_RESET);
1802 }
71e3d157
AD		 1803
1804 /* Wait a little for things to settle down */
1805 mdelay(1);
1806
a3c1945a 1807 rv515_mc_resume(rdev, &save);
d3cb781e 1808 udelay(50);
410a3418 1809
d3cb781e 1810 r600_print_gpu_status_regs(rdev);
d3cb781e
AD		 1811}
1812
de9ae744
AD		 1813static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1814{
1815 struct rv515_mc_save save;
1816 u32 tmp, i;
1817
1818 dev_info(rdev->dev, "GPU pci config reset\n");
1819
1820 /* disable dpm? */
1821
1822 /* Disable CP parsing/prefetching */
1823 if (rdev->family >= CHIP_RV770)
1824 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1825 else
1826 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1827
1828 /* disable the RLC */
1829 WREG32(RLC_CNTL, 0);
1830
1831 /* Disable DMA */
1832 tmp = RREG32(DMA_RB_CNTL);
1833 tmp &= ~DMA_RB_ENABLE;
1834 WREG32(DMA_RB_CNTL, tmp);
1835
1836 mdelay(50);
1837
1838 /* set mclk/sclk to bypass */
1839 if (rdev->family >= CHIP_RV770)
1840 rv770_set_clk_bypass_mode(rdev);
1841 /* disable BM */
1842 pci_clear_master(rdev->pdev);
1843 /* disable mem access */
1844 rv515_mc_stop(rdev, &save);
1845 if (r600_mc_wait_for_idle(rdev)) {
1846 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1847 }
1848
1849 /* BIF reset workaround. Not sure if this is needed on 6xx */
1850 tmp = RREG32(BUS_CNTL);
1851 tmp |= VGA_COHE_SPEC_TIMER_DIS;
1852 WREG32(BUS_CNTL, tmp);
1853
1854 tmp = RREG32(BIF_SCRATCH0);
1855
1856 /* reset */
1857 radeon_pci_config_reset(rdev);
1858 mdelay(1);
1859
1860 /* BIF reset workaround. Not sure if this is needed on 6xx */
1861 tmp = SOFT_RESET_BIF;
1862 WREG32(SRBM_SOFT_RESET, tmp);
1863 mdelay(1);
1864 WREG32(SRBM_SOFT_RESET, 0);
1865
1866 /* wait for asic to come out of reset */
1867 for (i = 0; i < rdev->usec_timeout; i++) {
1868 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1869 break;
1870 udelay(1);
1871 }
1872}
1873
71fe2899 1874int r600_asic_reset(struct radeon_device *rdev, bool hard)
d3cb781e 1875{
f13f7731
AD		 1876 u32 reset_mask;
1877
71fe2899
JG		 1878 if (hard) {
1879 r600_gpu_pci_config_reset(rdev);
1880 return 0;
1881 }
1882
f13f7731
AD		 1883 reset_mask = r600_gpu_check_soft_reset(rdev);
1884
1885 if (reset_mask)
1886 r600_set_bios_scratch_engine_hung(rdev, true);
1887
de9ae744 1888 /* try soft reset */
f13f7731
AD		 1889 r600_gpu_soft_reset(rdev, reset_mask);
1890
1891 reset_mask = r600_gpu_check_soft_reset(rdev);
1892
de9ae744
AD		 1893 /* try pci config reset */
1894 if (reset_mask && radeon_hard_reset)
1895 r600_gpu_pci_config_reset(rdev);
1896
1897 reset_mask = r600_gpu_check_soft_reset(rdev);
1898
f13f7731
AD		 1899 if (!reset_mask)
1900 r600_set_bios_scratch_engine_hung(rdev, false);
1901
1902 return 0;
3ce0a23d
JG		 1903}
1904
123bc183
AD		 1905/**
1906 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1907 *
1908 * @rdev: radeon_device pointer
1909 * @ring: radeon_ring structure holding ring information
1910 *
1911 * Check if the GFX engine is locked up.
1912 * Returns true if the engine appears to be locked up, false if not.
1913 */
1914bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 1915{
123bc183
AD		 1916 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1917
1918 if (!(reset_mask & (RADEON_RESET_GFX |
1919 RADEON_RESET_COMPUTE |
1920 RADEON_RESET_CP))) {
ff212f25 1921 radeon_ring_lockup_update(rdev, ring);
225758d8
JG		 1922 return false;
1923 }
069211e5 1924 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 1925}
1926
416a2bd2
AD		 1927u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1928 u32 tiling_pipe_num,
1929 u32 max_rb_num,
1930 u32 total_max_rb_num,
1931 u32 disabled_rb_mask)
3ce0a23d 1932{
416a2bd2 1933 u32 rendering_pipe_num, rb_num_width, req_rb_num;
f689e3ac 1934 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
416a2bd2
AD		 1935 u32 data = 0, mask = 1 << (max_rb_num - 1);
1936 unsigned i, j;
3ce0a23d 1937
416a2bd2 1938 /* mask out the RBs that don't exist on that asic */
f689e3ac
MT		 1939 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1940 /* make sure at least one RB is available */
1941 if ((tmp & 0xff) != 0xff)
1942 disabled_rb_mask = tmp;
3ce0a23d 1943
416a2bd2
AD		 1944 rendering_pipe_num = 1 << tiling_pipe_num;
1945 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1946 BUG_ON(rendering_pipe_num < req_rb_num);
3ce0a23d 1947
416a2bd2
AD		 1948 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1949 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
3ce0a23d 1950
416a2bd2
AD		 1951 if (rdev->family <= CHIP_RV740) {
1952 /* r6xx/r7xx */
1953 rb_num_width = 2;
1954 } else {
1955 /* eg+ */
1956 rb_num_width = 4;
1957 }
3ce0a23d 1958
416a2bd2
AD		 1959 for (i = 0; i < max_rb_num; i++) {
1960 if (!(mask & disabled_rb_mask)) {
1961 for (j = 0; j < pipe_rb_ratio; j++) {
1962 data <<= rb_num_width;
1963 data |= max_rb_num - i - 1;
1964 }
1965 if (pipe_rb_remain) {
1966 data <<= rb_num_width;
1967 data |= max_rb_num - i - 1;
1968 pipe_rb_remain--;
1969 }
1970 }
1971 mask >>= 1;
3ce0a23d
JG		 1972 }
1973
416a2bd2 1974 return data;
3ce0a23d
JG		 1975}
1976
1977int r600_count_pipe_bits(uint32_t val)
1978{
ef8cf3a1 1979 return hweight32(val);
771fe6b9
JG		 1980}
1981
1109ca09 1982static void r600_gpu_init(struct radeon_device *rdev)
3ce0a23d
JG		 1983{
1984 u32 tiling_config;
1985 u32 ramcfg;
d03f5d59 1986 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1987 u32 tmp;
1988 int i, j;
1989 u32 sq_config;
1990 u32 sq_gpr_resource_mgmt_1 = 0;
1991 u32 sq_gpr_resource_mgmt_2 = 0;
1992 u32 sq_thread_resource_mgmt = 0;
1993 u32 sq_stack_resource_mgmt_1 = 0;
1994 u32 sq_stack_resource_mgmt_2 = 0;
416a2bd2 1995 u32 disabled_rb_mask;
3ce0a23d 1996
416a2bd2 1997 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1998 switch (rdev->family) {
1999 case CHIP_R600:
2000 rdev->config.r600.max_pipes = 4;
2001 rdev->config.r600.max_tile_pipes = 8;
2002 rdev->config.r600.max_simds = 4;
2003 rdev->config.r600.max_backends = 4;
2004 rdev->config.r600.max_gprs = 256;
2005 rdev->config.r600.max_threads = 192;
2006 rdev->config.r600.max_stack_entries = 256;
2007 rdev->config.r600.max_hw_contexts = 8;
2008 rdev->config.r600.max_gs_threads = 16;
2009 rdev->config.r600.sx_max_export_size = 128;
2010 rdev->config.r600.sx_max_export_pos_size = 16;
2011 rdev->config.r600.sx_max_export_smx_size = 128;
2012 rdev->config.r600.sq_num_cf_insts = 2;
2013 break;
2014 case CHIP_RV630:
2015 case CHIP_RV635:
2016 rdev->config.r600.max_pipes = 2;
2017 rdev->config.r600.max_tile_pipes = 2;
2018 rdev->config.r600.max_simds = 3;
2019 rdev->config.r600.max_backends = 1;
2020 rdev->config.r600.max_gprs = 128;
2021 rdev->config.r600.max_threads = 192;
2022 rdev->config.r600.max_stack_entries = 128;
2023 rdev->config.r600.max_hw_contexts = 8;
2024 rdev->config.r600.max_gs_threads = 4;
2025 rdev->config.r600.sx_max_export_size = 128;
2026 rdev->config.r600.sx_max_export_pos_size = 16;
2027 rdev->config.r600.sx_max_export_smx_size = 128;
2028 rdev->config.r600.sq_num_cf_insts = 2;
2029 break;
2030 case CHIP_RV610:
2031 case CHIP_RV620:
2032 case CHIP_RS780:
2033 case CHIP_RS880:
2034 rdev->config.r600.max_pipes = 1;
2035 rdev->config.r600.max_tile_pipes = 1;
2036 rdev->config.r600.max_simds = 2;
2037 rdev->config.r600.max_backends = 1;
2038 rdev->config.r600.max_gprs = 128;
2039 rdev->config.r600.max_threads = 192;
2040 rdev->config.r600.max_stack_entries = 128;
2041 rdev->config.r600.max_hw_contexts = 4;
2042 rdev->config.r600.max_gs_threads = 4;
2043 rdev->config.r600.sx_max_export_size = 128;
2044 rdev->config.r600.sx_max_export_pos_size = 16;
2045 rdev->config.r600.sx_max_export_smx_size = 128;
2046 rdev->config.r600.sq_num_cf_insts = 1;
2047 break;
2048 case CHIP_RV670:
2049 rdev->config.r600.max_pipes = 4;
2050 rdev->config.r600.max_tile_pipes = 4;
2051 rdev->config.r600.max_simds = 4;
2052 rdev->config.r600.max_backends = 4;
2053 rdev->config.r600.max_gprs = 192;
2054 rdev->config.r600.max_threads = 192;
2055 rdev->config.r600.max_stack_entries = 256;
2056 rdev->config.r600.max_hw_contexts = 8;
2057 rdev->config.r600.max_gs_threads = 16;
2058 rdev->config.r600.sx_max_export_size = 128;
2059 rdev->config.r600.sx_max_export_pos_size = 16;
2060 rdev->config.r600.sx_max_export_smx_size = 128;
2061 rdev->config.r600.sq_num_cf_insts = 2;
2062 break;
2063 default:
2064 break;
2065 }
2066
2067 /* Initialize HDP */
2068 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2069 WREG32((0x2c14 + j), 0x00000000);
2070 WREG32((0x2c18 + j), 0x00000000);
2071 WREG32((0x2c1c + j), 0x00000000);
2072 WREG32((0x2c20 + j), 0x00000000);
2073 WREG32((0x2c24 + j), 0x00000000);
2074 }
2075
2076 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2077
2078 /* Setup tiling */
2079 tiling_config = 0;
2080 ramcfg = RREG32(RAMCFG);
2081 switch (rdev->config.r600.max_tile_pipes) {
2082 case 1:
2083 tiling_config |= PIPE_TILING(0);
2084 break;
2085 case 2:
2086 tiling_config |= PIPE_TILING(1);
2087 break;
2088 case 4:
2089 tiling_config |= PIPE_TILING(2);
2090 break;
2091 case 8:
2092 tiling_config |= PIPE_TILING(3);
2093 break;
2094 default:
2095 break;
2096 }
d03f5d59 2097 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 2098 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 2099 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1 2100 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
416a2bd2 2101
3ce0a23d
JG		 2102 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2103 if (tmp > 3) {
2104 tiling_config |= ROW_TILING(3);
2105 tiling_config |= SAMPLE_SPLIT(3);
2106 } else {
2107 tiling_config |= ROW_TILING(tmp);
2108 tiling_config |= SAMPLE_SPLIT(tmp);
2109 }
2110 tiling_config |= BANK_SWAPS(1);
d03f5d59 2111
416a2bd2 2112 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
65fcf668
AD		 2113 tmp = rdev->config.r600.max_simds -
2114 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2115 rdev->config.r600.active_simds = tmp;
416a2bd2
AD		 2116
2117 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
0a5f6e9d
AD		 2118 tmp = 0;
2119 for (i = 0; i < rdev->config.r600.max_backends; i++)
2120 tmp |= (1 << i);
2121 /* if all the backends are disabled, fix it up here */
2122 if ((disabled_rb_mask & tmp) == tmp) {
2123 for (i = 0; i < rdev->config.r600.max_backends; i++)
2124 disabled_rb_mask &= ~(1 << i);
2125 }
416a2bd2
AD		 2126 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2127 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2128 R6XX_MAX_BACKENDS, disabled_rb_mask);
2129 tiling_config |= tmp << 16;
2130 rdev->config.r600.backend_map = tmp;
2131
e7aeeba6 2132 rdev->config.r600.tile_config = tiling_config;
3ce0a23d
JG		 2133 WREG32(GB_TILING_CONFIG, tiling_config);
2134 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2135 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
4d75658b 2136 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
3ce0a23d 2137
d03f5d59 2138 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 2139 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2140 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2141
2142 /* Setup some CP states */
2143 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2144 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2145
2146 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2147 SYNC_WALKER | SYNC_ALIGNER));
2148 /* Setup various GPU states */
2149 if (rdev->family == CHIP_RV670)
2150 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2151
2152 tmp = RREG32(SX_DEBUG_1);
2153 tmp |= SMX_EVENT_RELEASE;
2154 if ((rdev->family > CHIP_R600))
2155 tmp |= ENABLE_NEW_SMX_ADDRESS;
2156 WREG32(SX_DEBUG_1, tmp);
2157
2158 if (((rdev->family) == CHIP_R600) ||
2159 ((rdev->family) == CHIP_RV630) ||
2160 ((rdev->family) == CHIP_RV610) ||
2161 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2162 ((rdev->family) == CHIP_RS780) ||
2163 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2164 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2165 } else {
2166 WREG32(DB_DEBUG, 0);
2167 }
2168 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2169 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2170
2171 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2172 WREG32(VGT_NUM_INSTANCES, 0);
2173
2174 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2175 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2176
2177 tmp = RREG32(SQ_MS_FIFO_SIZES);
2178 if (((rdev->family) == CHIP_RV610) ||
2179 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2180 ((rdev->family) == CHIP_RS780) ||
2181 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2182 tmp = (CACHE_FIFO_SIZE(0xa) |
2183 FETCH_FIFO_HIWATER(0xa) |
2184 DONE_FIFO_HIWATER(0xe0) |
2185 ALU_UPDATE_FIFO_HIWATER(0x8));
2186 } else if (((rdev->family) == CHIP_R600) ||
2187 ((rdev->family) == CHIP_RV630)) {
2188 tmp &= ~DONE_FIFO_HIWATER(0xff);
2189 tmp |= DONE_FIFO_HIWATER(0x4);
2190 }
2191 WREG32(SQ_MS_FIFO_SIZES, tmp);
2192
2193 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2194 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
2195 */
2196 sq_config = RREG32(SQ_CONFIG);
2197 sq_config &= ~(PS_PRIO(3) |
2198 VS_PRIO(3) |
2199 GS_PRIO(3) |
2200 ES_PRIO(3));
2201 sq_config |= (DX9_CONSTS |
2202 VC_ENABLE |
2203 PS_PRIO(0) |
2204 VS_PRIO(1) |
2205 GS_PRIO(2) |
2206 ES_PRIO(3));
2207
2208 if ((rdev->family) == CHIP_R600) {
2209 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2210 NUM_VS_GPRS(124) |
2211 NUM_CLAUSE_TEMP_GPRS(4));
2212 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2213 NUM_ES_GPRS(0));
2214 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2215 NUM_VS_THREADS(48) |
2216 NUM_GS_THREADS(4) |
2217 NUM_ES_THREADS(4));
2218 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2219 NUM_VS_STACK_ENTRIES(128));
2220 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2221 NUM_ES_STACK_ENTRIES(0));
2222 } else if (((rdev->family) == CHIP_RV610) ||
2223 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2224 ((rdev->family) == CHIP_RS780) ||
2225 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2226 /* no vertex cache */
2227 sq_config &= ~VC_ENABLE;
2228
2229 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2230 NUM_VS_GPRS(44) |
2231 NUM_CLAUSE_TEMP_GPRS(2));
2232 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2233 NUM_ES_GPRS(17));
2234 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2235 NUM_VS_THREADS(78) |
2236 NUM_GS_THREADS(4) |
2237 NUM_ES_THREADS(31));
2238 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2239 NUM_VS_STACK_ENTRIES(40));
2240 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2241 NUM_ES_STACK_ENTRIES(16));
2242 } else if (((rdev->family) == CHIP_RV630) ||
2243 ((rdev->family) == CHIP_RV635)) {
2244 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2245 NUM_VS_GPRS(44) |
2246 NUM_CLAUSE_TEMP_GPRS(2));
2247 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2248 NUM_ES_GPRS(18));
2249 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2250 NUM_VS_THREADS(78) |
2251 NUM_GS_THREADS(4) |
2252 NUM_ES_THREADS(31));
2253 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2254 NUM_VS_STACK_ENTRIES(40));
2255 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2256 NUM_ES_STACK_ENTRIES(16));
2257 } else if ((rdev->family) == CHIP_RV670) {
2258 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2259 NUM_VS_GPRS(44) |
2260 NUM_CLAUSE_TEMP_GPRS(2));
2261 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2262 NUM_ES_GPRS(17));
2263 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2264 NUM_VS_THREADS(78) |
2265 NUM_GS_THREADS(4) |
2266 NUM_ES_THREADS(31));
2267 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2268 NUM_VS_STACK_ENTRIES(64));
2269 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2270 NUM_ES_STACK_ENTRIES(64));
2271 }
2272
2273 WREG32(SQ_CONFIG, sq_config);
2274 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2275 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2276 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2277 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2278 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2279
2280 if (((rdev->family) == CHIP_RV610) ||
2281 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2282 ((rdev->family) == CHIP_RS780) ||
2283 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2284 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2285 } else {
2286 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2287 }
2288
2289 /* More default values. 2D/3D driver should adjust as needed */
2290 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2291 S1_X(0x4) | S1_Y(0xc)));
2292 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2293 S1_X(0x2) | S1_Y(0x2) |
2294 S2_X(0xa) | S2_Y(0x6) |
2295 S3_X(0x6) | S3_Y(0xa)));
2296 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2297 S1_X(0x4) | S1_Y(0xc) |
2298 S2_X(0x1) | S2_Y(0x6) |
2299 S3_X(0xa) | S3_Y(0xe)));
2300 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2301 S5_X(0x0) | S5_Y(0x0) |
2302 S6_X(0xb) | S6_Y(0x4) |
2303 S7_X(0x7) | S7_Y(0x8)));
2304
2305 WREG32(VGT_STRMOUT_EN, 0);
2306 tmp = rdev->config.r600.max_pipes * 16;
2307 switch (rdev->family) {
2308 case CHIP_RV610:
3ce0a23d 2309 case CHIP_RV620:
ee59f2b4
AD		 2310 case CHIP_RS780:
2311 case CHIP_RS880:
3ce0a23d
JG		 2312 tmp += 32;
2313 break;
2314 case CHIP_RV670:
2315 tmp += 128;
2316 break;
2317 default:
2318 break;
2319 }
2320 if (tmp > 256) {
2321 tmp = 256;
2322 }
2323 WREG32(VGT_ES_PER_GS, 128);
2324 WREG32(VGT_GS_PER_ES, tmp);
2325 WREG32(VGT_GS_PER_VS, 2);
2326 WREG32(VGT_GS_VERTEX_REUSE, 16);
2327
2328 /* more default values. 2D/3D driver should adjust as needed */
2329 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2330 WREG32(VGT_STRMOUT_EN, 0);
2331 WREG32(SX_MISC, 0);
2332 WREG32(PA_SC_MODE_CNTL, 0);
2333 WREG32(PA_SC_AA_CONFIG, 0);
2334 WREG32(PA_SC_LINE_STIPPLE, 0);
2335 WREG32(SPI_INPUT_Z, 0);
2336 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2337 WREG32(CB_COLOR7_FRAG, 0);
2338
2339 /* Clear render buffer base addresses */
2340 WREG32(CB_COLOR0_BASE, 0);
2341 WREG32(CB_COLOR1_BASE, 0);
2342 WREG32(CB_COLOR2_BASE, 0);
2343 WREG32(CB_COLOR3_BASE, 0);
2344 WREG32(CB_COLOR4_BASE, 0);
2345 WREG32(CB_COLOR5_BASE, 0);
2346 WREG32(CB_COLOR6_BASE, 0);
2347 WREG32(CB_COLOR7_BASE, 0);
2348 WREG32(CB_COLOR7_FRAG, 0);
2349
2350 switch (rdev->family) {
2351 case CHIP_RV610:
3ce0a23d 2352 case CHIP_RV620:
ee59f2b4
AD		 2353 case CHIP_RS780:
2354 case CHIP_RS880:
3ce0a23d
JG		 2355 tmp = TC_L2_SIZE(8);
2356 break;
2357 case CHIP_RV630:
2358 case CHIP_RV635:
2359 tmp = TC_L2_SIZE(4);
2360 break;
2361 case CHIP_R600:
2362 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2363 break;
2364 default:
2365 tmp = TC_L2_SIZE(0);
2366 break;
2367 }
2368 WREG32(TC_CNTL, tmp);
2369
2370 tmp = RREG32(HDP_HOST_PATH_CNTL);
2371 WREG32(HDP_HOST_PATH_CNTL, tmp);
2372
2373 tmp = RREG32(ARB_POP);
2374 tmp |= ENABLE_TC128;
2375 WREG32(ARB_POP, tmp);
2376
2377 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2378 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2379 NUM_CLIP_SEQ(3)));
2380 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
b866d133 2381 WREG32(VC_ENHANCE, 0);
3ce0a23d
JG		 2382}
2383
2384
771fe6b9
JG		 2385/*
2386 * Indirect registers accessor
2387 */
3ce0a23d
JG		 2388u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2389{
0a5b7b0b 2390 unsigned long flags;
3ce0a23d
JG		 2391 u32 r;
2392
0a5b7b0b 2393 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2394 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2395 (void)RREG32(PCIE_PORT_INDEX);
2396 r = RREG32(PCIE_PORT_DATA);
0a5b7b0b 2397 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2398 return r;
2399}
2400
2401void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2402{
0a5b7b0b
AD		 2403 unsigned long flags;
2404
2405 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2406 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2407 (void)RREG32(PCIE_PORT_INDEX);
2408 WREG32(PCIE_PORT_DATA, (v));
2409 (void)RREG32(PCIE_PORT_DATA);
0a5b7b0b 2410 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2411}
2412
3ce0a23d
JG		 2413/*
2414 * CP & Ring
2415 */
2416void r600_cp_stop(struct radeon_device *rdev)
2417{
50efa51a
AD		 2418 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2419 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 2420 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 2421 WREG32(SCRATCH_UMSK, 0);
4d75658b 2422 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3ce0a23d
JG		 2423}
2424
d8f60cfc 2425int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d 2426{
3ce0a23d 2427 const char *chip_name;
d8f60cfc 2428 const char *rlc_chip_name;
66229b20
AD		 2429 const char *smc_chip_name = "RV770";
2430 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
3ce0a23d
JG		 2431 char fw_name[30];
2432 int err;
2433
2434 DRM_DEBUG("\n");
2435
3ce0a23d 2436 switch (rdev->family) {
d8f60cfc
AD		 2437 case CHIP_R600:
2438 chip_name = "R600";
2439 rlc_chip_name = "R600";
2440 break;
2441 case CHIP_RV610:
2442 chip_name = "RV610";
2443 rlc_chip_name = "R600";
2444 break;
2445 case CHIP_RV630:
2446 chip_name = "RV630";
2447 rlc_chip_name = "R600";
2448 break;
2449 case CHIP_RV620:
2450 chip_name = "RV620";
2451 rlc_chip_name = "R600";
2452 break;
2453 case CHIP_RV635:
2454 chip_name = "RV635";
2455 rlc_chip_name = "R600";
2456 break;
2457 case CHIP_RV670:
2458 chip_name = "RV670";
2459 rlc_chip_name = "R600";
2460 break;
3ce0a23d 2461 case CHIP_RS780:
d8f60cfc
AD		 2462 case CHIP_RS880:
2463 chip_name = "RS780";
2464 rlc_chip_name = "R600";
2465 break;
2466 case CHIP_RV770:
2467 chip_name = "RV770";
2468 rlc_chip_name = "R700";
66229b20
AD		 2469 smc_chip_name = "RV770";
2470 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
d8f60cfc 2471 break;
3ce0a23d 2472 case CHIP_RV730:
d8f60cfc
AD		 2473 chip_name = "RV730";
2474 rlc_chip_name = "R700";
66229b20
AD		 2475 smc_chip_name = "RV730";
2476 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
d8f60cfc
AD		 2477 break;
2478 case CHIP_RV710:
2479 chip_name = "RV710";
2480 rlc_chip_name = "R700";
66229b20
AD		 2481 smc_chip_name = "RV710";
2482 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2483 break;
2484 case CHIP_RV740:
2485 chip_name = "RV730";
2486 rlc_chip_name = "R700";
2487 smc_chip_name = "RV740";
2488 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
d8f60cfc 2489 break;
fe251e2f
AD		 2490 case CHIP_CEDAR:
2491 chip_name = "CEDAR";
45f9a39b 2492 rlc_chip_name = "CEDAR";
dc50ba7f
AD		 2493 smc_chip_name = "CEDAR";
2494 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2495 break;
2496 case CHIP_REDWOOD:
2497 chip_name = "REDWOOD";
45f9a39b 2498 rlc_chip_name = "REDWOOD";
dc50ba7f
AD		 2499 smc_chip_name = "REDWOOD";
2500 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2501 break;
2502 case CHIP_JUNIPER:
2503 chip_name = "JUNIPER";
45f9a39b 2504 rlc_chip_name = "JUNIPER";
dc50ba7f
AD		 2505 smc_chip_name = "JUNIPER";
2506 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2507 break;
2508 case CHIP_CYPRESS:
2509 case CHIP_HEMLOCK:
2510 chip_name = "CYPRESS";
45f9a39b 2511 rlc_chip_name = "CYPRESS";
dc50ba7f
AD		 2512 smc_chip_name = "CYPRESS";
2513 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
fe251e2f 2514 break;
439bd6cd
AD		 2515 case CHIP_PALM:
2516 chip_name = "PALM";
2517 rlc_chip_name = "SUMO";
2518 break;
d5c5a72f
AD		 2519 case CHIP_SUMO:
2520 chip_name = "SUMO";
2521 rlc_chip_name = "SUMO";
2522 break;
2523 case CHIP_SUMO2:
2524 chip_name = "SUMO2";
2525 rlc_chip_name = "SUMO";
2526 break;
3ce0a23d
JG		 2527 default: BUG();
2528 }
2529
fe251e2f
AD		 2530 if (rdev->family >= CHIP_CEDAR) {
2531 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2532 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2533 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2534 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2535 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2536 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2537 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d 2538 } else {
138e4e16
AD		 2539 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2540 me_req_size = R600_PM4_UCODE_SIZE * 12;
2541 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2542 }
2543
d8f60cfc 2544 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2545
2546 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
0a168933 2547 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2548 if (err)
2549 goto out;
2550 if (rdev->pfp_fw->size != pfp_req_size) {
2551 printk(KERN_ERR
2552 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2553 rdev->pfp_fw->size, fw_name);
2554 err = -EINVAL;
2555 goto out;
2556 }
2557
2558 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
0a168933 2559 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2560 if (err)
2561 goto out;
2562 if (rdev->me_fw->size != me_req_size) {
2563 printk(KERN_ERR
2564 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2565 rdev->me_fw->size, fw_name);
2566 err = -EINVAL;
2567 }
d8f60cfc
AD		 2568
2569 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
0a168933 2570 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
d8f60cfc
AD		 2571 if (err)
2572 goto out;
2573 if (rdev->rlc_fw->size != rlc_req_size) {
2574 printk(KERN_ERR
2575 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2576 rdev->rlc_fw->size, fw_name);
2577 err = -EINVAL;
2578 }
2579
dc50ba7f 2580 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
66229b20 2581 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
0a168933 2582 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
8a53fa23
AD		 2583 if (err) {
2584 printk(KERN_ERR
2585 "smc: error loading firmware \"%s\"\n",
2586 fw_name);
2587 release_firmware(rdev->smc_fw);
2588 rdev->smc_fw = NULL;
d8367112 2589 err = 0;
8a53fa23 2590 } else if (rdev->smc_fw->size != smc_req_size) {
66229b20
AD		 2591 printk(KERN_ERR
2592 "smc: Bogus length %zu in firmware \"%s\"\n",
2593 rdev->smc_fw->size, fw_name);
2594 err = -EINVAL;
2595 }
2596 }
2597
3ce0a23d 2598out:
3ce0a23d
JG		 2599 if (err) {
2600 if (err != -EINVAL)
2601 printk(KERN_ERR
2602 "r600_cp: Failed to load firmware \"%s\"\n",
2603 fw_name);
2604 release_firmware(rdev->pfp_fw);
2605 rdev->pfp_fw = NULL;
2606 release_firmware(rdev->me_fw);
2607 rdev->me_fw = NULL;
d8f60cfc
AD		 2608 release_firmware(rdev->rlc_fw);
2609 rdev->rlc_fw = NULL;
66229b20
AD		 2610 release_firmware(rdev->smc_fw);
2611 rdev->smc_fw = NULL;
3ce0a23d
JG		 2612 }
2613 return err;
2614}
2615
ea31bf69
AD		 2616u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2617 struct radeon_ring *ring)
2618{
2619 u32 rptr;
2620
2621 if (rdev->wb.enabled)
2622 rptr = rdev->wb.wb[ring->rptr_offs/4];
2623 else
2624 rptr = RREG32(R600_CP_RB_RPTR);
2625
2626 return rptr;
2627}
2628
2629u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2630 struct radeon_ring *ring)
2631{
2632 u32 wptr;
2633
2634 wptr = RREG32(R600_CP_RB_WPTR);
2635
2636 return wptr;
2637}
2638
2639void r600_gfx_set_wptr(struct radeon_device *rdev,
2640 struct radeon_ring *ring)
2641{
2642 WREG32(R600_CP_RB_WPTR, ring->wptr);
2643 (void)RREG32(R600_CP_RB_WPTR);
2644}
2645
3ce0a23d
JG		 2646static int r600_cp_load_microcode(struct radeon_device *rdev)
2647{
2648 const __be32 *fw_data;
2649 int i;
2650
2651 if (!rdev->me_fw || !rdev->pfp_fw)
2652 return -EINVAL;
2653
2654 r600_cp_stop(rdev);
2655
4eace7fd
CC		 2656 WREG32(CP_RB_CNTL,
2657#ifdef __BIG_ENDIAN
2658 BUF_SWAP_32BIT |
2659#endif
2660 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2661
2662 /* Reset cp */
2663 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2664 RREG32(GRBM_SOFT_RESET);
2665 mdelay(15);
2666 WREG32(GRBM_SOFT_RESET, 0);
2667
2668 WREG32(CP_ME_RAM_WADDR, 0);
2669
2670 fw_data = (const __be32 *)rdev->me_fw->data;
2671 WREG32(CP_ME_RAM_WADDR, 0);
138e4e16 2672 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
3ce0a23d
JG		 2673 WREG32(CP_ME_RAM_DATA,
2674 be32_to_cpup(fw_data++));
2675
2676 fw_data = (const __be32 *)rdev->pfp_fw->data;
2677 WREG32(CP_PFP_UCODE_ADDR, 0);
138e4e16 2678 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
3ce0a23d
JG		 2679 WREG32(CP_PFP_UCODE_DATA,
2680 be32_to_cpup(fw_data++));
2681
2682 WREG32(CP_PFP_UCODE_ADDR, 0);
2683 WREG32(CP_ME_RAM_WADDR, 0);
2684 WREG32(CP_ME_RAM_RADDR, 0);
2685 return 0;
2686}
2687
2688int r600_cp_start(struct radeon_device *rdev)
2689{
e32eb50d 2690 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2691 int r;
2692 uint32_t cp_me;
2693
e32eb50d 2694 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2695 if (r) {
2696 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2697 return r;
2698 }
e32eb50d
CK		 2699 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2700 radeon_ring_write(ring, 0x1);
7e7b41d2 2701 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2702 radeon_ring_write(ring, 0x0);
2703 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2704 } else {
e32eb50d
CK		 2705 radeon_ring_write(ring, 0x3);
2706 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2707 }
e32eb50d
CK		 2708 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2709 radeon_ring_write(ring, 0);
2710 radeon_ring_write(ring, 0);
1538a9e0 2711 radeon_ring_unlock_commit(rdev, ring, false);
3ce0a23d
JG		 2712
2713 cp_me = 0xff;
2714 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2715 return 0;
2716}
2717
2718int r600_cp_resume(struct radeon_device *rdev)
2719{
e32eb50d 2720 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2721 u32 tmp;
2722 u32 rb_bufsz;
2723 int r;
2724
2725 /* Reset cp */
2726 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2727 RREG32(GRBM_SOFT_RESET);
2728 mdelay(15);
2729 WREG32(GRBM_SOFT_RESET, 0);
2730
2731 /* Set ring buffer size */
b72a8925
DV		 2732 rb_bufsz = order_base_2(ring->ring_size / 8);
2733 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2734#ifdef __BIG_ENDIAN
d6f28938 2735 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2736#endif
d6f28938 2737 WREG32(CP_RB_CNTL, tmp);
15d3332f 2738 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2739
2740 /* Set the write pointer delay */
2741 WREG32(CP_RB_WPTR_DELAY, 0);
2742
2743 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2744 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2745 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2746 ring->wptr = 0;
2747 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2748
2749 /* set the wb address whether it's enabled or not */
4eace7fd 2750 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2751 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2752 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2753 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2754
2755 if (rdev->wb.enabled)
2756 WREG32(SCRATCH_UMSK, 0xff);
2757 else {
2758 tmp |= RB_NO_UPDATE;
2759 WREG32(SCRATCH_UMSK, 0);
2760 }
2761
3ce0a23d
JG		 2762 mdelay(1);
2763 WREG32(CP_RB_CNTL, tmp);
2764
e32eb50d 2765 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2766 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2767
3ce0a23d 2768 r600_cp_start(rdev);
e32eb50d 2769 ring->ready = true;
f712812e 2770 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3ce0a23d 2771 if (r) {
e32eb50d 2772 ring->ready = false;
3ce0a23d
JG		 2773 return r;
2774 }
b9ace36f 2775
50efa51a 2776 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
b9ace36f
AD		 2777 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2778
3ce0a23d
JG		 2779 return 0;
2780}
2781
e32eb50d 2782void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2783{
2784 u32 rb_bufsz;
45df6803 2785 int r;
3ce0a23d
JG		 2786
2787 /* Align ring size */
b72a8925 2788 rb_bufsz = order_base_2(ring_size / 8);
3ce0a23d 2789 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2790 ring->ring_size = ring_size;
2791 ring->align_mask = 16 - 1;
45df6803 2792
89d35807
AD		 2793 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2794 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2795 if (r) {
2796 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2797 ring->rptr_save_reg = 0;
2798 }
45df6803 2799 }
3ce0a23d
JG		 2800}
2801
655efd3d
JG		 2802void r600_cp_fini(struct radeon_device *rdev)
2803{
45df6803 2804 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
655efd3d 2805 r600_cp_stop(rdev);
45df6803
CK		 2806 radeon_ring_fini(rdev, ring);
2807 radeon_scratch_free(rdev, ring->rptr_save_reg);
655efd3d
JG		 2808}
2809
3ce0a23d
JG		 2810/*
2811 * GPU scratch registers helpers function.
2812 */
2813void r600_scratch_init(struct radeon_device *rdev)
2814{
2815 int i;
2816
2817 rdev->scratch.num_reg = 7;
724c80e1 2818 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2819 for (i = 0; i < rdev->scratch.num_reg; i++) {
2820 rdev->scratch.free[i] = true;
724c80e1 2821 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2822 }
2823}
2824
e32eb50d 2825int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2826{
2827 uint32_t scratch;
2828 uint32_t tmp = 0;
8b25ed34 2829 unsigned i;
3ce0a23d
JG		 2830 int r;
2831
2832 r = radeon_scratch_get(rdev, &scratch);
2833 if (r) {
2834 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2835 return r;
2836 }
2837 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2838 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2839 if (r) {
8b25ed34 2840 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3ce0a23d
JG		 2841 radeon_scratch_free(rdev, scratch);
2842 return r;
2843 }
e32eb50d
CK		 2844 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2845 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2846 radeon_ring_write(ring, 0xDEADBEEF);
1538a9e0 2847 radeon_ring_unlock_commit(rdev, ring, false);
3ce0a23d
JG		 2848 for (i = 0; i < rdev->usec_timeout; i++) {
2849 tmp = RREG32(scratch);
2850 if (tmp == 0xDEADBEEF)
2851 break;
2852 DRM_UDELAY(1);
2853 }
2854 if (i < rdev->usec_timeout) {
8b25ed34 2855 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3ce0a23d 2856 } else {
bf852799 2857 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
8b25ed34 2858 ring->idx, scratch, tmp);
3ce0a23d
JG		 2859 r = -EINVAL;
2860 }
2861 radeon_scratch_free(rdev, scratch);
2862 return r;
2863}
2864
4d75658b
AD		 2865/*
2866 * CP fences/semaphores
2867 */
2868
3ce0a23d
JG		 2869void r600_fence_ring_emit(struct radeon_device *rdev,
2870 struct radeon_fence *fence)
2871{
e32eb50d 2872 struct radeon_ring *ring = &rdev->ring[fence->ring];
d45b964a
AD		 2873 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2874 PACKET3_SH_ACTION_ENA;
2875
2876 if (rdev->family >= CHIP_RV770)
2877 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
7b1f2485 2878
d0f8a854 2879 if (rdev->wb.use_event) {
30eb77f4 2880 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
77b1bad4 2881 /* flush read cache over gart */
e32eb50d 2882 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
d45b964a 2883 radeon_ring_write(ring, cp_coher_cntl);
e32eb50d
CK		 2884 radeon_ring_write(ring, 0xFFFFFFFF);
2885 radeon_ring_write(ring, 0);
2886 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2887 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2888 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2889 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
5e167cdb 2890 radeon_ring_write(ring, lower_32_bits(addr));
e32eb50d
CK		 2891 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2892 radeon_ring_write(ring, fence->seq);
2893 radeon_ring_write(ring, 0);
d0f8a854 2894 } else {
77b1bad4 2895 /* flush read cache over gart */
e32eb50d 2896 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
d45b964a 2897 radeon_ring_write(ring, cp_coher_cntl);
e32eb50d
CK		 2898 radeon_ring_write(ring, 0xFFFFFFFF);
2899 radeon_ring_write(ring, 0);
2900 radeon_ring_write(ring, 10); /* poll interval */
2901 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2902 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2903 /* wait for 3D idle clean */
e32eb50d
CK		 2904 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2905 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2906 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2907 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2908 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2909 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2910 radeon_ring_write(ring, fence->seq);
d0f8a854 2911 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2912 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2913 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2914 }
3ce0a23d
JG		 2915}
2916
86302eea
CK		 2917/**
2918 * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2919 *
2920 * @rdev: radeon_device pointer
2921 * @ring: radeon ring buffer object
2922 * @semaphore: radeon semaphore object
2923 * @emit_wait: Is this a sempahore wait?
2924 *
2925 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2926 * from running ahead of semaphore waits.
2927 */
1654b817 2928bool r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2929 struct radeon_ring *ring,
15d3332f 2930 struct radeon_semaphore *semaphore,
7b1f2485 2931 bool emit_wait)
15d3332f
CK		 2932{
2933 uint64_t addr = semaphore->gpu_addr;
2934 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2935
0be70439
CK		 2936 if (rdev->family < CHIP_CAYMAN)
2937 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2938
e32eb50d 2939 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
5e167cdb 2940 radeon_ring_write(ring, lower_32_bits(addr));
e32eb50d 2941 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
1654b817 2942
b6c2b4fa
AD		 2943 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2944 if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
86302eea
CK		 2945 /* Prevent the PFP from running ahead of the semaphore wait */
2946 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2947 radeon_ring_write(ring, 0x0);
2948 }
2949
1654b817 2950 return true;
15d3332f
CK		 2951}
2952
072b5acc
AD		 2953/**
2954 * r600_copy_cpdma - copy pages using the CP DMA engine
2955 *
2956 * @rdev: radeon_device pointer
2957 * @src_offset: src GPU address
2958 * @dst_offset: dst GPU address
2959 * @num_gpu_pages: number of GPU pages to xfer
2960 * @fence: radeon fence object
2961 *
2962 * Copy GPU paging using the CP DMA engine (r6xx+).
2963 * Used by the radeon ttm implementation to move pages if
2964 * registered as the asic copy callback.
2965 */
57d20a43
CK		 2966struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2967 uint64_t src_offset, uint64_t dst_offset,
2968 unsigned num_gpu_pages,
2969 struct reservation_object *resv)
072b5acc 2970{
57d20a43 2971 struct radeon_fence *fence;
975700d2 2972 struct radeon_sync sync;
072b5acc
AD		 2973 int ring_index = rdev->asic->copy.blit_ring_index;
2974 struct radeon_ring *ring = &rdev->ring[ring_index];
2975 u32 size_in_bytes, cur_size_in_bytes, tmp;
2976 int i, num_loops;
2977 int r = 0;
2978
975700d2 2979 radeon_sync_create(&sync);
072b5acc
AD		 2980
2981 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2982 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
745a39a9 2983 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
072b5acc
AD		 2984 if (r) {
2985 DRM_ERROR("radeon: moving bo (%d).\n", r);
975700d2 2986 radeon_sync_free(rdev, &sync, NULL);
57d20a43 2987 return ERR_PTR(r);
072b5acc
AD		 2988 }
2989
975700d2
CK		 2990 radeon_sync_resv(rdev, &sync, resv, false);
2991 radeon_sync_rings(rdev, &sync, ring->idx);
072b5acc 2992
745a39a9
AD		 2993 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2994 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2995 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
072b5acc
AD		 2996 for (i = 0; i < num_loops; i++) {
2997 cur_size_in_bytes = size_in_bytes;
2998 if (cur_size_in_bytes > 0x1fffff)
2999 cur_size_in_bytes = 0x1fffff;
3000 size_in_bytes -= cur_size_in_bytes;
3001 tmp = upper_32_bits(src_offset) & 0xff;
3002 if (size_in_bytes == 0)
3003 tmp |= PACKET3_CP_DMA_CP_SYNC;
3004 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
5e167cdb 3005 radeon_ring_write(ring, lower_32_bits(src_offset));
072b5acc 3006 radeon_ring_write(ring, tmp);
5e167cdb 3007 radeon_ring_write(ring, lower_32_bits(dst_offset));
072b5acc
AD		 3008 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3009 radeon_ring_write(ring, cur_size_in_bytes);
3010 src_offset += cur_size_in_bytes;
3011 dst_offset += cur_size_in_bytes;
3012 }
3013 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3014 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3015 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
3016
57d20a43 3017 r = radeon_fence_emit(rdev, &fence, ring->idx);
072b5acc
AD		 3018 if (r) {
3019 radeon_ring_unlock_undo(rdev, ring);
975700d2 3020 radeon_sync_free(rdev, &sync, NULL);
57d20a43 3021 return ERR_PTR(r);
072b5acc
AD		 3022 }
3023
1538a9e0 3024 radeon_ring_unlock_commit(rdev, ring, false);
975700d2 3025 radeon_sync_free(rdev, &sync, fence);
072b5acc 3026
57d20a43 3027 return fence;
072b5acc
AD		 3028}
3029
3ce0a23d
JG		 3030int r600_set_surface_reg(struct radeon_device *rdev, int reg,
3031 uint32_t tiling_flags, uint32_t pitch,
3032 uint32_t offset, uint32_t obj_size)
3033{
3034 /* FIXME: implement */
3035 return 0;
3036}
3037
3038void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
3039{
3040 /* FIXME: implement */
3041}
3042
c91f9368
JG		 3043static void r600_uvd_init(struct radeon_device *rdev)
3044{
3045 int r;
3046
3047 if (!rdev->has_uvd)
3048 return;
3049
3050 r = radeon_uvd_init(rdev);
3051 if (r) {
3052 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
3053 /*
3054 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
3055 * to early fails uvd_v1_0_resume() and thus nothing happens
3056 * there. So it is pointless to try to go through that code
3057 * hence why we disable uvd here.
3058 */
3059 rdev->has_uvd = 0;
3060 return;
3061 }
3062 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3063 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3064}
3065
3066static void r600_uvd_start(struct radeon_device *rdev)
3067{
3068 int r;
3069
3070 if (!rdev->has_uvd)
3071 return;
3072
3073 r = uvd_v1_0_resume(rdev);
3074 if (r) {
3075 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
3076 goto error;
3077 }
3078 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3079 if (r) {
3080 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3081 goto error;
3082 }
3083 return;
3084
3085error:
3086 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3087}
3088
3089static void r600_uvd_resume(struct radeon_device *rdev)
3090{
3091 struct radeon_ring *ring;
3092 int r;
3093
3094 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
3095 return;
3096
3097 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3098 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, RADEON_CP_PACKET2);
3099 if (r) {
3100 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
3101 return;
3102 }
3103 r = uvd_v1_0_init(rdev);
3104 if (r) {
3105 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
3106 return;
3107 }
3108}
3109
1109ca09 3110static int r600_startup(struct radeon_device *rdev)
3ce0a23d 3111{
4d75658b 3112 struct radeon_ring *ring;
3ce0a23d
JG		 3113 int r;
3114
9e46a48d
AD		 3115 /* enable pcie gen2 link */
3116 r600_pcie_gen2_enable(rdev);
3117
e5903d39
AD		 3118 /* scratch needs to be initialized before MC */
3119 r = r600_vram_scratch_init(rdev);
3120 if (r)
3121 return r;
3122
6fab3feb
AD		 3123 r600_mc_program(rdev);
3124
1a029b76
JG		 3125 if (rdev->flags & RADEON_IS_AGP) {
3126 r600_agp_enable(rdev);
3127 } else {
3128 r = r600_pcie_gart_enable(rdev);
3129 if (r)
3130 return r;
3131 }
3ce0a23d 3132 r600_gpu_init(rdev);
b70d6bb3 3133
724c80e1
AD		 3134 /* allocate wb buffer */
3135 r = radeon_wb_init(rdev);
3136 if (r)
3137 return r;
3138
30eb77f4
JG		 3139 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3140 if (r) {
3141 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3142 return r;
3143 }
3144
c91f9368 3145 r600_uvd_start(rdev);
856754c3 3146
d8f60cfc 3147 /* Enable IRQ */
e49f3959
AH		 3148 if (!rdev->irq.installed) {
3149 r = radeon_irq_kms_init(rdev);
3150 if (r)
3151 return r;
3152 }
3153
d8f60cfc
AD		 3154 r = r600_irq_init(rdev);
3155 if (r) {
3156 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3157 radeon_irq_kms_fini(rdev);
3158 return r;
3159 }
3160 r600_irq_set(rdev);
3161
4d75658b 3162 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 3163 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2e1e6dad 3164 RADEON_CP_PACKET2);
4d75658b
AD		 3165 if (r)
3166 return r;
5596a9db 3167
3ce0a23d
JG		 3168 r = r600_cp_load_microcode(rdev);
3169 if (r)
3170 return r;
3171 r = r600_cp_resume(rdev);
3172 if (r)
3173 return r;
724c80e1 3174
c91f9368 3175 r600_uvd_resume(rdev);
856754c3 3176
2898c348
CK		 3177 r = radeon_ib_pool_init(rdev);
3178 if (r) {
3179 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3180 return r;
2898c348 3181 }
b15ba512 3182
bfc1f97d 3183 r = radeon_audio_init(rdev);
d4e30ef0
AD		 3184 if (r) {
3185 DRM_ERROR("radeon: audio init failed\n");
3186 return r;
3187 }
3188
3ce0a23d
JG		 3189 return 0;
3190}
3191
28d52043
DA		 3192void r600_vga_set_state(struct radeon_device *rdev, bool state)
3193{
3194 uint32_t temp;
3195
3196 temp = RREG32(CONFIG_CNTL);
3197 if (state == false) {
3198 temp &= ~(1<<0);
3199 temp |= (1<<1);
3200 } else {
3201 temp &= ~(1<<1);
3202 }
3203 WREG32(CONFIG_CNTL, temp);
3204}
3205
fc30b8ef
DA		 3206int r600_resume(struct radeon_device *rdev)
3207{
3208 int r;
3209
1a029b76
JG		 3210 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3211 * posting will perform necessary task to bring back GPU into good
3212 * shape.
3213 */
fc30b8ef 3214 /* post card */
e7d40b9a 3215 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 3216
bc6a6295
AD		 3217 if (rdev->pm.pm_method == PM_METHOD_DPM)
3218 radeon_pm_resume(rdev);
6c7bccea 3219
b15ba512 3220 rdev->accel_working = true;
fc30b8ef
DA		 3221 r = r600_startup(rdev);
3222 if (r) {
3223 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 3224 rdev->accel_working = false;
fc30b8ef
DA		 3225 return r;
3226 }
3227
fc30b8ef
DA		 3228 return r;
3229}
3230
3ce0a23d
JG		 3231int r600_suspend(struct radeon_device *rdev)
3232{
6c7bccea 3233 radeon_pm_suspend(rdev);
7991d665 3234 radeon_audio_fini(rdev);
3ce0a23d 3235 r600_cp_stop(rdev);
bdc99722
AD		 3236 if (rdev->has_uvd) {
3237 uvd_v1_0_fini(rdev);
3238 radeon_uvd_suspend(rdev);
3239 }
0c45249f 3240 r600_irq_suspend(rdev);
724c80e1 3241 radeon_wb_disable(rdev);
4aac0473 3242 r600_pcie_gart_disable(rdev);
6ddddfe7 3243
3ce0a23d
JG		 3244 return 0;
3245}
3246
3247/* Plan is to move initialization in that function and use
3248 * helper function so that radeon_device_init pretty much
3249 * do nothing more than calling asic specific function. This
3250 * should also allow to remove a bunch of callback function
3251 * like vram_info.
3252 */
3253int r600_init(struct radeon_device *rdev)
771fe6b9 3254{
3ce0a23d 3255 int r;
771fe6b9 3256
3ce0a23d
JG		 3257 if (r600_debugfs_mc_info_init(rdev)) {
3258 DRM_ERROR("Failed to register debugfs file for mc !\n");
3259 }
3ce0a23d
JG		 3260 /* Read BIOS */
3261 if (!radeon_get_bios(rdev)) {
3262 if (ASIC_IS_AVIVO(rdev))
3263 return -EINVAL;
3264 }
3265 /* Must be an ATOMBIOS */
e7d40b9a
JG		 3266 if (!rdev->is_atom_bios) {
3267 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 3268 return -EINVAL;
e7d40b9a 3269 }
3ce0a23d
JG		 3270 r = radeon_atombios_init(rdev);
3271 if (r)
3272 return r;
3273 /* Post card if necessary */
fd909c37 3274 if (!radeon_card_posted(rdev)) {
72542d77
DA		 3275 if (!rdev->bios) {
3276 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3277 return -EINVAL;
3278 }
3ce0a23d
JG		 3279 DRM_INFO("GPU not posted. posting now...\n");
3280 atom_asic_init(rdev->mode_info.atom_context);
3281 }
3282 /* Initialize scratch registers */
3283 r600_scratch_init(rdev);
3284 /* Initialize surface registers */
3285 radeon_surface_init(rdev);
7433874e 3286 /* Initialize clocks */
5e6dde7e 3287 radeon_get_clock_info(rdev->ddev);
3ce0a23d 3288 /* Fence driver */
30eb77f4 3289 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 3290 if (r)
3291 return r;
700a0cc0
JG		 3292 if (rdev->flags & RADEON_IS_AGP) {
3293 r = radeon_agp_init(rdev);
3294 if (r)
3295 radeon_agp_disable(rdev);
3296 }
3ce0a23d 3297 r = r600_mc_init(rdev);
b574f251 3298 if (r)
3ce0a23d 3299 return r;
3ce0a23d 3300 /* Memory manager */
4c788679 3301 r = radeon_bo_init(rdev);
3ce0a23d
JG		 3302 if (r)
3303 return r;
d8f60cfc 3304
01ac8794
AD		 3305 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3306 r = r600_init_microcode(rdev);
3307 if (r) {
3308 DRM_ERROR("Failed to load firmware!\n");
3309 return r;
3310 }
3311 }
3312
6c7bccea
AD		 3313 /* Initialize power management */
3314 radeon_pm_init(rdev);
3315
e32eb50d
CK		 3316 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3317 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 3318
c91f9368 3319 r600_uvd_init(rdev);
856754c3 3320
d8f60cfc
AD		 3321 rdev->ih.ring_obj = NULL;
3322 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 3323
4aac0473
JG		 3324 r = r600_pcie_gart_init(rdev);
3325 if (r)
3326 return r;
3327
779720a3 3328 rdev->accel_working = true;
fc30b8ef 3329 r = r600_startup(rdev);
3ce0a23d 3330 if (r) {
655efd3d
JG		 3331 dev_err(rdev->dev, "disabling GPU acceleration\n");
3332 r600_cp_fini(rdev);
655efd3d 3333 r600_irq_fini(rdev);
724c80e1 3334 radeon_wb_fini(rdev);
2898c348 3335 radeon_ib_pool_fini(rdev);
655efd3d 3336 radeon_irq_kms_fini(rdev);
75c81298 3337 r600_pcie_gart_fini(rdev);
733289c2 3338 rdev->accel_working = false;
3ce0a23d 3339 }
dafc3bd5 3340
3ce0a23d
JG		 3341 return 0;
3342}
3343
3344void r600_fini(struct radeon_device *rdev)
3345{
6c7bccea 3346 radeon_pm_fini(rdev);
7991d665 3347 radeon_audio_fini(rdev);
655efd3d 3348 r600_cp_fini(rdev);
d8f60cfc 3349 r600_irq_fini(rdev);
bdc99722
AD		 3350 if (rdev->has_uvd) {
3351 uvd_v1_0_fini(rdev);
3352 radeon_uvd_fini(rdev);
3353 }
724c80e1 3354 radeon_wb_fini(rdev);
2898c348 3355 radeon_ib_pool_fini(rdev);
d8f60cfc 3356 radeon_irq_kms_fini(rdev);
4aac0473 3357 r600_pcie_gart_fini(rdev);
16cdf04d 3358 r600_vram_scratch_fini(rdev);
655efd3d 3359 radeon_agp_fini(rdev);
3ce0a23d
JG		 3360 radeon_gem_fini(rdev);
3361 radeon_fence_driver_fini(rdev);
4c788679 3362 radeon_bo_fini(rdev);
e7d40b9a 3363 radeon_atombios_fini(rdev);
3ce0a23d
JG		 3364 kfree(rdev->bios);
3365 rdev->bios = NULL;
3ce0a23d
JG		 3366}
3367
3368
3369/*
3370 * CS stuff
3371 */
3372void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3373{
876dc9f3 3374 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 3375 u32 next_rptr;
7b1f2485 3376
45df6803 3377 if (ring->rptr_save_reg) {
89d35807 3378 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 3379 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3380 radeon_ring_write(ring, ((ring->rptr_save_reg -
3381 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3382 radeon_ring_write(ring, next_rptr);
89d35807
AD		 3383 } else if (rdev->wb.enabled) {
3384 next_rptr = ring->wptr + 5 + 4;
3385 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3386 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3387 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3388 radeon_ring_write(ring, next_rptr);
3389 radeon_ring_write(ring, 0);
45df6803
CK		 3390 }
3391
e32eb50d
CK		 3392 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3393 radeon_ring_write(ring,
4eace7fd
CC		 3394#ifdef __BIG_ENDIAN
3395 (2 << 0) |
3396#endif
3397 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 3398 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3399 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3400}
3401
f712812e 3402int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3403{
f2e39221 3404 struct radeon_ib ib;
3ce0a23d
JG		 3405 uint32_t scratch;
3406 uint32_t tmp = 0;
3407 unsigned i;
3408 int r;
3409
3410 r = radeon_scratch_get(rdev, &scratch);
3411 if (r) {
3412 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3413 return r;
3414 }
3415 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3416 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3ce0a23d
JG		 3417 if (r) {
3418 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
af026c5b 3419 goto free_scratch;
3ce0a23d 3420 }
f2e39221
JG		 3421 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3422 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3423 ib.ptr[2] = 0xDEADBEEF;
3424 ib.length_dw = 3;
1538a9e0 3425 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3ce0a23d 3426 if (r) {
3ce0a23d 3427 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
af026c5b 3428 goto free_ib;
3ce0a23d 3429 }
04db4caf
MD		 3430 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3431 RADEON_USEC_IB_TEST_TIMEOUT));
3432 if (r < 0) {
3ce0a23d 3433 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
af026c5b 3434 goto free_ib;
04db4caf
MD		 3435 } else if (r == 0) {
3436 DRM_ERROR("radeon: fence wait timed out.\n");
3437 r = -ETIMEDOUT;
3438 goto free_ib;
3ce0a23d 3439 }
04db4caf 3440 r = 0;
3ce0a23d
JG		 3441 for (i = 0; i < rdev->usec_timeout; i++) {
3442 tmp = RREG32(scratch);
3443 if (tmp == 0xDEADBEEF)
3444 break;
3445 DRM_UDELAY(1);
3446 }
3447 if (i < rdev->usec_timeout) {
f2e39221 3448 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3ce0a23d 3449 } else {
4417d7f6 3450 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3451 scratch, tmp);
3452 r = -EINVAL;
3453 }
af026c5b 3454free_ib:
3ce0a23d 3455 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3456free_scratch:
3457 radeon_scratch_free(rdev, scratch);
771fe6b9
JG		 3458 return r;
3459}
3460
d8f60cfc
AD		 3461/*
3462 * Interrupts
3463 *
3464 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3465 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3466 * writing to the ring and the GPU consuming, the GPU writes to the ring
3467 * and host consumes. As the host irq handler processes interrupts, it
3468 * increments the rptr. When the rptr catches up with the wptr, all the
3469 * current interrupts have been processed.
3470 */
3471
3472void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3473{
3474 u32 rb_bufsz;
3475
3476 /* Align ring size */
b72a8925 3477 rb_bufsz = order_base_2(ring_size / 4);
d8f60cfc
AD		 3478 ring_size = (1 << rb_bufsz) * 4;
3479 rdev->ih.ring_size = ring_size;
0c45249f
JG		 3480 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3481 rdev->ih.rptr = 0;
d8f60cfc
AD		 3482}
3483
25a857fb 3484int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 3485{
3486 int r;
3487
d8f60cfc
AD		 3488 /* Allocate ring buffer */
3489 if (rdev->ih.ring_obj == NULL) {
441921d5 3490 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 3491 PAGE_SIZE, true,
02376d82 3492 RADEON_GEM_DOMAIN_GTT, 0,
831b6966 3493 NULL, NULL, &rdev->ih.ring_obj);
d8f60cfc
AD		 3494 if (r) {
3495 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3496 return r;
3497 }
4c788679
JG		 3498 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3499 if (unlikely(r != 0))
3500 return r;
3501 r = radeon_bo_pin(rdev->ih.ring_obj,
3502 RADEON_GEM_DOMAIN_GTT,
3503 &rdev->ih.gpu_addr);
d8f60cfc 3504 if (r) {
4c788679 3505 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3506 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3507 return r;
3508 }
4c788679
JG		 3509 r = radeon_bo_kmap(rdev->ih.ring_obj,
3510 (void **)&rdev->ih.ring);
3511 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3512 if (r) {
3513 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3514 return r;
3515 }
3516 }
d8f60cfc
AD		 3517 return 0;
3518}
3519
25a857fb 3520void r600_ih_ring_fini(struct radeon_device *rdev)
d8f60cfc 3521{
4c788679 3522 int r;
d8f60cfc 3523 if (rdev->ih.ring_obj) {
4c788679
JG		 3524 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3525 if (likely(r == 0)) {
3526 radeon_bo_kunmap(rdev->ih.ring_obj);
3527 radeon_bo_unpin(rdev->ih.ring_obj);
3528 radeon_bo_unreserve(rdev->ih.ring_obj);
3529 }
3530 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 3531 rdev->ih.ring = NULL;
3532 rdev->ih.ring_obj = NULL;
3533 }
3534}
3535
45f9a39b 3536void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 3537{
3538
45f9a39b
AD		 3539 if ((rdev->family >= CHIP_RV770) &&
3540 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 3541 /* r7xx asics need to soft reset RLC before halting */
3542 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3543 RREG32(SRBM_SOFT_RESET);
4de833c3 3544 mdelay(15);
d8f60cfc
AD		 3545 WREG32(SRBM_SOFT_RESET, 0);
3546 RREG32(SRBM_SOFT_RESET);
3547 }
3548
3549 WREG32(RLC_CNTL, 0);
3550}
3551
3552static void r600_rlc_start(struct radeon_device *rdev)
3553{
3554 WREG32(RLC_CNTL, RLC_ENABLE);
3555}
3556
2948f5e6 3557static int r600_rlc_resume(struct radeon_device *rdev)
d8f60cfc
AD		 3558{
3559 u32 i;
3560 const __be32 *fw_data;
3561
3562 if (!rdev->rlc_fw)
3563 return -EINVAL;
3564
3565 r600_rlc_stop(rdev);
3566
d8f60cfc 3567 WREG32(RLC_HB_CNTL, 0);
c420c745 3568
2948f5e6
AD		 3569 WREG32(RLC_HB_BASE, 0);
3570 WREG32(RLC_HB_RPTR, 0);
3571 WREG32(RLC_HB_WPTR, 0);
3572 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3573 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
d8f60cfc
AD		 3574 WREG32(RLC_MC_CNTL, 0);
3575 WREG32(RLC_UCODE_CNTL, 0);
3576
3577 fw_data = (const __be32 *)rdev->rlc_fw->data;
2948f5e6 3578 if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 3579 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3580 WREG32(RLC_UCODE_ADDR, i);
3581 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3582 }
3583 } else {
138e4e16 3584 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
d8f60cfc
AD		 3585 WREG32(RLC_UCODE_ADDR, i);
3586 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3587 }
3588 }
3589 WREG32(RLC_UCODE_ADDR, 0);
3590
3591 r600_rlc_start(rdev);
3592
3593 return 0;
3594}
3595
3596static void r600_enable_interrupts(struct radeon_device *rdev)
3597{
3598 u32 ih_cntl = RREG32(IH_CNTL);
3599 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3600
3601 ih_cntl |= ENABLE_INTR;
3602 ih_rb_cntl |= IH_RB_ENABLE;
3603 WREG32(IH_CNTL, ih_cntl);
3604 WREG32(IH_RB_CNTL, ih_rb_cntl);
3605 rdev->ih.enabled = true;
3606}
3607
45f9a39b 3608void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 3609{
3610 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3611 u32 ih_cntl = RREG32(IH_CNTL);
3612
3613 ih_rb_cntl &= ~IH_RB_ENABLE;
3614 ih_cntl &= ~ENABLE_INTR;
3615 WREG32(IH_RB_CNTL, ih_rb_cntl);
3616 WREG32(IH_CNTL, ih_cntl);
3617 /* set rptr, wptr to 0 */
3618 WREG32(IH_RB_RPTR, 0);
3619 WREG32(IH_RB_WPTR, 0);
3620 rdev->ih.enabled = false;
d8f60cfc
AD		 3621 rdev->ih.rptr = 0;
3622}
3623
e0df1ac5
AD		 3624static void r600_disable_interrupt_state(struct radeon_device *rdev)
3625{
3626 u32 tmp;
3627
3555e53b 3628 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4d75658b
AD		 3629 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3630 WREG32(DMA_CNTL, tmp);
e0df1ac5
AD		 3631 WREG32(GRBM_INT_CNTL, 0);
3632 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 3633 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3634 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 3635 if (ASIC_IS_DCE3(rdev)) {
3636 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3637 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3638 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3639 WREG32(DC_HPD1_INT_CONTROL, tmp);
3640 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3641 WREG32(DC_HPD2_INT_CONTROL, tmp);
3642 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3643 WREG32(DC_HPD3_INT_CONTROL, tmp);
3644 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3645 WREG32(DC_HPD4_INT_CONTROL, tmp);
3646 if (ASIC_IS_DCE32(rdev)) {
3647 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3648 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 3649 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3650 WREG32(DC_HPD6_INT_CONTROL, tmp);
c6543a6e
RM		 3651 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3652 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3653 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3654 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f122c610
AD		 3655 } else {
3656 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3657 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3658 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3659 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3660 }
3661 } else {
3662 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3663 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3664 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3665 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 3666 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3667 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 3668 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3669 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
f122c610
AD		 3670 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3671 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3672 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3673 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3674 }
3675}
3676
d8f60cfc
AD		 3677int r600_irq_init(struct radeon_device *rdev)
3678{
3679 int ret = 0;
3680 int rb_bufsz;
3681 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3682
3683 /* allocate ring */
0c45249f 3684 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 3685 if (ret)
3686 return ret;
3687
3688 /* disable irqs */
3689 r600_disable_interrupts(rdev);
3690
3691 /* init rlc */
2948f5e6
AD		 3692 if (rdev->family >= CHIP_CEDAR)
3693 ret = evergreen_rlc_resume(rdev);
3694 else
3695 ret = r600_rlc_resume(rdev);
d8f60cfc
AD		 3696 if (ret) {
3697 r600_ih_ring_fini(rdev);
3698 return ret;
3699 }
3700
3701 /* setup interrupt control */
3702 /* set dummy read address to ring address */
3703 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3704 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3705 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3706 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3707 */
3708 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3709 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3710 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3711 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3712
3713 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
b72a8925 3714 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
d8f60cfc
AD		 3715
3716 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3717 IH_WPTR_OVERFLOW_CLEAR |
3718 (rb_bufsz << 1));
724c80e1
AD		 3719
3720 if (rdev->wb.enabled)
3721 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3722
3723 /* set the writeback address whether it's enabled or not */
3724 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3725 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3726
3727 WREG32(IH_RB_CNTL, ih_rb_cntl);
3728
3729 /* set rptr, wptr to 0 */
3730 WREG32(IH_RB_RPTR, 0);
3731 WREG32(IH_RB_WPTR, 0);
3732
3733 /* Default settings for IH_CNTL (disabled at first) */
3734 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3735 /* RPTR_REARM only works if msi's are enabled */
3736 if (rdev->msi_enabled)
3737 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3738 WREG32(IH_CNTL, ih_cntl);
3739
3740 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3741 if (rdev->family >= CHIP_CEDAR)
3742 evergreen_disable_interrupt_state(rdev);
3743 else
3744 r600_disable_interrupt_state(rdev);
d8f60cfc 3745
2099810f
DA		 3746 /* at this point everything should be setup correctly to enable master */
3747 pci_set_master(rdev->pdev);
3748
d8f60cfc
AD		 3749 /* enable irqs */
3750 r600_enable_interrupts(rdev);
3751
3752 return ret;
3753}
3754
0c45249f 3755void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3756{
45f9a39b 3757 r600_irq_disable(rdev);
d8f60cfc 3758 r600_rlc_stop(rdev);
0c45249f
JG		 3759}
3760
3761void r600_irq_fini(struct radeon_device *rdev)
3762{
3763 r600_irq_suspend(rdev);
d8f60cfc
AD		 3764 r600_ih_ring_fini(rdev);
3765}
3766
3767int r600_irq_set(struct radeon_device *rdev)
3768{
e0df1ac5
AD		 3769 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3770 u32 mode_int = 0;
3771 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3772 u32 grbm_int_cntl = 0;
f122c610 3773 u32 hdmi0, hdmi1;
4d75658b 3774 u32 dma_cntl;
4a6369e9 3775 u32 thermal_int = 0;
d8f60cfc 3776
003e69f9 3777 if (!rdev->irq.installed) {
fce7d61b 3778 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3779 return -EINVAL;
3780 }
d8f60cfc 3781 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3782 if (!rdev->ih.enabled) {
3783 r600_disable_interrupts(rdev);
3784 /* force the active interrupt state to all disabled */
3785 r600_disable_interrupt_state(rdev);
d8f60cfc 3786 return 0;
79c2bbc5 3787 }
d8f60cfc 3788
e0df1ac5
AD		 3789 if (ASIC_IS_DCE3(rdev)) {
3790 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3791 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3792 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3793 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3794 if (ASIC_IS_DCE32(rdev)) {
3795 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3796 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
c6543a6e
RM		 3797 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3798 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
f122c610
AD		 3799 } else {
3800 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3801 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3802 }
3803 } else {
3804 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3805 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3806 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
f122c610
AD		 3807 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3808 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5 3809 }
4a6369e9 3810
4d75658b 3811 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
e0df1ac5 3812
4a6369e9
AD		 3813 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3814 thermal_int = RREG32(CG_THERMAL_INT) &
3815 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
66229b20
AD		 3816 } else if (rdev->family >= CHIP_RV770) {
3817 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3818 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3819 }
3820 if (rdev->irq.dpm_thermal) {
3821 DRM_DEBUG("dpm thermal\n");
3822 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
4a6369e9
AD		 3823 }
3824
736fc37f 3825 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
d8f60cfc
AD		 3826 DRM_DEBUG("r600_irq_set: sw int\n");
3827 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3828 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3829 }
4d75658b
AD		 3830
3831 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3832 DRM_DEBUG("r600_irq_set: sw int dma\n");
3833 dma_cntl |= TRAP_ENABLE;
3834 }
3835
6f34be50 3836 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3837 atomic_read(&rdev->irq.pflip[0])) {
d8f60cfc
AD		 3838 DRM_DEBUG("r600_irq_set: vblank 0\n");
3839 mode_int |= D1MODE_VBLANK_INT_MASK;
3840 }
6f34be50 3841 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3842 atomic_read(&rdev->irq.pflip[1])) {
d8f60cfc
AD		 3843 DRM_DEBUG("r600_irq_set: vblank 1\n");
3844 mode_int |= D2MODE_VBLANK_INT_MASK;
3845 }
e0df1ac5
AD		 3846 if (rdev->irq.hpd[0]) {
3847 DRM_DEBUG("r600_irq_set: hpd 1\n");
3848 hpd1 |= DC_HPDx_INT_EN;
3849 }
3850 if (rdev->irq.hpd[1]) {
3851 DRM_DEBUG("r600_irq_set: hpd 2\n");
3852 hpd2 |= DC_HPDx_INT_EN;
3853 }
3854 if (rdev->irq.hpd[2]) {
3855 DRM_DEBUG("r600_irq_set: hpd 3\n");
3856 hpd3 |= DC_HPDx_INT_EN;
3857 }
3858 if (rdev->irq.hpd[3]) {
3859 DRM_DEBUG("r600_irq_set: hpd 4\n");
3860 hpd4 |= DC_HPDx_INT_EN;
3861 }
3862 if (rdev->irq.hpd[4]) {
3863 DRM_DEBUG("r600_irq_set: hpd 5\n");
3864 hpd5 |= DC_HPDx_INT_EN;
3865 }
3866 if (rdev->irq.hpd[5]) {
3867 DRM_DEBUG("r600_irq_set: hpd 6\n");
3868 hpd6 |= DC_HPDx_INT_EN;
3869 }
f122c610
AD		 3870 if (rdev->irq.afmt[0]) {
3871 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3872 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3873 }
f122c610
AD		 3874 if (rdev->irq.afmt[1]) {
3875 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3876 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3877 }
d8f60cfc
AD		 3878
3879 WREG32(CP_INT_CNTL, cp_int_cntl);
4d75658b 3880 WREG32(DMA_CNTL, dma_cntl);
d8f60cfc 3881 WREG32(DxMODE_INT_MASK, mode_int);
f5d636d2
CK		 3882 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3883 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
2031f77c 3884 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
e0df1ac5
AD		 3885 if (ASIC_IS_DCE3(rdev)) {
3886 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3887 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3888 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3889 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3890 if (ASIC_IS_DCE32(rdev)) {
3891 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3892 WREG32(DC_HPD6_INT_CONTROL, hpd6);
c6543a6e
RM		 3893 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3894 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
f122c610
AD		 3895 } else {
3896 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3897 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5
AD		 3898 }
3899 } else {
3900 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3901 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3902 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
f122c610
AD		 3903 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3904 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5 3905 }
4a6369e9
AD		 3906 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3907 WREG32(CG_THERMAL_INT, thermal_int);
66229b20
AD		 3908 } else if (rdev->family >= CHIP_RV770) {
3909 WREG32(RV770_CG_THERMAL_INT, thermal_int);
4a6369e9 3910 }
d8f60cfc 3911
9d1393f2
AD		 3912 /* posting read */
3913 RREG32(R_000E50_SRBM_STATUS);
3914
d8f60cfc
AD		 3915 return 0;
3916}
3917
ce580fab 3918static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3919{
e0df1ac5
AD		 3920 u32 tmp;
3921
3922 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3923 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3924 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3925 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
f122c610 3926 if (ASIC_IS_DCE32(rdev)) {
c6543a6e
RM		 3927 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3928 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
f122c610
AD		 3929 } else {
3930 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3931 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3932 }
e0df1ac5 3933 } else {
6f34be50
AD		 3934 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3935 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3936 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
f122c610
AD		 3937 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3938 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
6f34be50
AD		 3939 }
3940 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3941 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3942
3943 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3944 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3945 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3946 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3947 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3948 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3949 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3950 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3951 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3952 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3953 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3954 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3955 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3956 if (ASIC_IS_DCE3(rdev)) {
3957 tmp = RREG32(DC_HPD1_INT_CONTROL);
3958 tmp |= DC_HPDx_INT_ACK;
3959 WREG32(DC_HPD1_INT_CONTROL, tmp);
3960 } else {
3961 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3962 tmp |= DC_HPDx_INT_ACK;
3963 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3964 }
3965 }
6f34be50 3966 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3967 if (ASIC_IS_DCE3(rdev)) {
3968 tmp = RREG32(DC_HPD2_INT_CONTROL);
3969 tmp |= DC_HPDx_INT_ACK;
3970 WREG32(DC_HPD2_INT_CONTROL, tmp);
3971 } else {
3972 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3973 tmp |= DC_HPDx_INT_ACK;
3974 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3975 }
3976 }
6f34be50 3977 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3978 if (ASIC_IS_DCE3(rdev)) {
3979 tmp = RREG32(DC_HPD3_INT_CONTROL);
3980 tmp |= DC_HPDx_INT_ACK;
3981 WREG32(DC_HPD3_INT_CONTROL, tmp);
3982 } else {
3983 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3984 tmp |= DC_HPDx_INT_ACK;
3985 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3986 }
3987 }
6f34be50 3988 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3989 tmp = RREG32(DC_HPD4_INT_CONTROL);
3990 tmp |= DC_HPDx_INT_ACK;
3991 WREG32(DC_HPD4_INT_CONTROL, tmp);
3992 }
3993 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3994 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3995 tmp = RREG32(DC_HPD5_INT_CONTROL);
3996 tmp |= DC_HPDx_INT_ACK;
3997 WREG32(DC_HPD5_INT_CONTROL, tmp);
3998 }
6f34be50 3999 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 4000 tmp = RREG32(DC_HPD5_INT_CONTROL);
4001 tmp |= DC_HPDx_INT_ACK;
4002 WREG32(DC_HPD6_INT_CONTROL, tmp);
4003 }
f122c610 4004 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 4005 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
f122c610 4006 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 4007 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
f122c610
AD		 4008 }
4009 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 4010 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
f122c610 4011 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 4012 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f2594933
CK		 4013 }
4014 } else {
f122c610
AD		 4015 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4016 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
4017 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4018 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
4019 }
4020 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4021 if (ASIC_IS_DCE3(rdev)) {
4022 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
4023 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4024 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
4025 } else {
4026 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
4027 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
4028 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
4029 }
f2594933
CK		 4030 }
4031 }
d8f60cfc
AD		 4032}
4033
4034void r600_irq_disable(struct radeon_device *rdev)
4035{
d8f60cfc
AD		 4036 r600_disable_interrupts(rdev);
4037 /* Wait and acknowledge irq */
4038 mdelay(1);
6f34be50 4039 r600_irq_ack(rdev);
e0df1ac5 4040 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 4041}
4042
ce580fab 4043static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 4044{
4045 u32 wptr, tmp;
3ce0a23d 4046
724c80e1 4047 if (rdev->wb.enabled)
204ae24d 4048 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 4049 else
4050 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 4051
d8f60cfc 4052 if (wptr & RB_OVERFLOW) {
11bab0ae 4053 wptr &= ~RB_OVERFLOW;
7924e5eb
JG		 4054 /* When a ring buffer overflow happen start parsing interrupt
4055 * from the last not overwritten vector (wptr + 16). Hopefully
4056 * this should allow us to catchup.
4057 */
6cc2fda2
MD		 4058 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
4059 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
7924e5eb 4060 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 4061 tmp = RREG32(IH_RB_CNTL);
4062 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4063 WREG32(IH_RB_CNTL, tmp);
4064 }
0c45249f 4065 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 4066}
3ce0a23d 4067
d8f60cfc
AD		 4068/* r600 IV Ring
4069 * Each IV ring entry is 128 bits:
4070 * [7:0] - interrupt source id
4071 * [31:8] - reserved
4072 * [59:32] - interrupt source data
4073 * [127:60] - reserved
4074 *
4075 * The basic interrupt vector entries
4076 * are decoded as follows:
4077 * src_id src_data description
4078 * 1 0 D1 Vblank
4079 * 1 1 D1 Vline
4080 * 5 0 D2 Vblank
4081 * 5 1 D2 Vline
4082 * 19 0 FP Hot plug detection A
4083 * 19 1 FP Hot plug detection B
4084 * 19 2 DAC A auto-detection
4085 * 19 3 DAC B auto-detection
f2594933
CK		 4086 * 21 4 HDMI block A
4087 * 21 5 HDMI block B
d8f60cfc
AD		 4088 * 176 - CP_INT RB
4089 * 177 - CP_INT IB1
4090 * 178 - CP_INT IB2
4091 * 181 - EOP Interrupt
4092 * 233 - GUI Idle
4093 *
4094 * Note, these are based on r600 and may need to be
4095 * adjusted or added to on newer asics
4096 */
4097
4098int r600_irq_process(struct radeon_device *rdev)
4099{
682f1a54
DA		 4100 u32 wptr;
4101 u32 rptr;
d8f60cfc 4102 u32 src_id, src_data;
6f34be50 4103 u32 ring_index;
d4877cf2 4104 bool queue_hotplug = false;
f122c610 4105 bool queue_hdmi = false;
4a6369e9 4106 bool queue_thermal = false;
d8f60cfc 4107
682f1a54 4108 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 4109 return IRQ_NONE;
d8f60cfc 4110
f6a56939
BH		 4111 /* No MSIs, need a dummy read to flush PCI DMAs */
4112 if (!rdev->msi_enabled)
4113 RREG32(IH_RB_WPTR);
4114
682f1a54 4115 wptr = r600_get_ih_wptr(rdev);
d8f60cfc 4116
c20dc369
CK		 4117restart_ih:
4118 /* is somebody else already processing irqs? */
4119 if (atomic_xchg(&rdev->ih.lock, 1))
d8f60cfc 4120 return IRQ_NONE;
d8f60cfc 4121
c20dc369
CK		 4122 rptr = rdev->ih.rptr;
4123 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4124
964f6645
BH		 4125 /* Order reading of wptr vs. reading of IH ring data */
4126 rmb();
4127
d8f60cfc 4128 /* display interrupts */
6f34be50 4129 r600_irq_ack(rdev);
d8f60cfc 4130
d8f60cfc
AD		 4131 while (rptr != wptr) {
4132 /* wptr/rptr are in bytes! */
4133 ring_index = rptr / 4;
4eace7fd
CC		 4134 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4135 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 4136
4137 switch (src_id) {
4138 case 1: /* D1 vblank/vline */
4139 switch (src_data) {
4140 case 0: /* D1 vblank */
07f18f0b
MK		 4141 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4142 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n");
4143
4144 if (rdev->irq.crtc_vblank_int[0]) {
4145 drm_handle_vblank(rdev->ddev, 0);
4146 rdev->pm.vblank_sync = true;
4147 wake_up(&rdev->irq.vblank_queue);
d8f60cfc 4148 }
07f18f0b
MK		 4149 if (atomic_read(&rdev->irq.pflip[0]))
4150 radeon_crtc_handle_vblank(rdev, 0);
4151 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4152 DRM_DEBUG("IH: D1 vblank\n");
4153
d8f60cfc
AD		 4154 break;
4155 case 1: /* D1 vline */
07f18f0b
MK		 4156 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT))
4157 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n");
4158
4159 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4160 DRM_DEBUG("IH: D1 vline\n");
4161
d8f60cfc
AD		 4162 break;
4163 default:
b042589c 4164 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4165 break;
4166 }
4167 break;
4168 case 5: /* D2 vblank/vline */
4169 switch (src_data) {
4170 case 0: /* D2 vblank */
07f18f0b
MK		 4171 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT))
4172 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n");
4173
4174 if (rdev->irq.crtc_vblank_int[1]) {
4175 drm_handle_vblank(rdev->ddev, 1);
4176 rdev->pm.vblank_sync = true;
4177 wake_up(&rdev->irq.vblank_queue);
d8f60cfc 4178 }
07f18f0b
MK		 4179 if (atomic_read(&rdev->irq.pflip[1]))
4180 radeon_crtc_handle_vblank(rdev, 1);
4181 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
4182 DRM_DEBUG("IH: D2 vblank\n");
4183
d8f60cfc
AD		 4184 break;
4185 case 1: /* D1 vline */
07f18f0b
MK		 4186 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT))
4187 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n");
4188
4189 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
4190 DRM_DEBUG("IH: D2 vline\n");
4191
d8f60cfc
AD		 4192 break;
4193 default:
b042589c 4194 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4195 break;
4196 }
4197 break;
f5d636d2
CK		 4198 case 9: /* D1 pflip */
4199 DRM_DEBUG("IH: D1 flip\n");
39dc5454
MK		 4200 if (radeon_use_pflipirq > 0)
4201 radeon_crtc_handle_flip(rdev, 0);
f5d636d2
CK		 4202 break;
4203 case 11: /* D2 pflip */
4204 DRM_DEBUG("IH: D2 flip\n");
39dc5454
MK		 4205 if (radeon_use_pflipirq > 0)
4206 radeon_crtc_handle_flip(rdev, 1);
f5d636d2 4207 break;
e0df1ac5
AD		 4208 case 19: /* HPD/DAC hotplug */
4209 switch (src_data) {
4210 case 0:
07f18f0b
MK		 4211 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT))
4212 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n");
4213
4214 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
4215 queue_hotplug = true;
4216 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 4217 break;
4218 case 1:
07f18f0b
MK		 4219 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT))
4220 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n");
4221
4222 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
4223 queue_hotplug = true;
4224 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 4225 break;
4226 case 4:
07f18f0b
MK		 4227 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT))
4228 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n");
4229
4230 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
4231 queue_hotplug = true;
4232 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 4233 break;
4234 case 5:
07f18f0b
MK		 4235 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT))
4236 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n");
4237
4238 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
4239 queue_hotplug = true;
4240 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 4241 break;
4242 case 10:
07f18f0b
MK		 4243 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT))
4244 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n");
4245
4246 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
4247 queue_hotplug = true;
4248 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 4249 break;
4250 case 12:
07f18f0b
MK		 4251 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT))
4252 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n");
4253
4254 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
4255 queue_hotplug = true;
4256 DRM_DEBUG("IH: HPD6\n");
4257
e0df1ac5
AD		 4258 break;
4259 default:
b042589c 4260 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 4261 break;
4262 }
4263 break;
f122c610
AD		 4264 case 21: /* hdmi */
4265 switch (src_data) {
4266 case 4:
07f18f0b
MK		 4267 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG))
4268 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n");
4269
4270 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4271 queue_hdmi = true;
4272 DRM_DEBUG("IH: HDMI0\n");
4273
f122c610
AD		 4274 break;
4275 case 5:
07f18f0b
MK		 4276 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG))
4277 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n");
4278
4279 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4280 queue_hdmi = true;
4281 DRM_DEBUG("IH: HDMI1\n");
4282
f122c610
AD		 4283 break;
4284 default:
4285 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4286 break;
4287 }
f2594933 4288 break;
858a41c8
AD		 4289 case 124: /* UVD */
4290 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4291 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4292 break;
d8f60cfc
AD		 4293 case 176: /* CP_INT in ring buffer */
4294 case 177: /* CP_INT in IB1 */
4295 case 178: /* CP_INT in IB2 */
4296 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 4297 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 4298 break;
4299 case 181: /* CP EOP event */
4300 DRM_DEBUG("IH: CP EOP\n");
7465280c 4301 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 4302 break;
4d75658b
AD		 4303 case 224: /* DMA trap event */
4304 DRM_DEBUG("IH: DMA trap\n");
4305 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4306 break;
4a6369e9
AD		 4307 case 230: /* thermal low to high */
4308 DRM_DEBUG("IH: thermal low to high\n");
4309 rdev->pm.dpm.thermal.high_to_low = false;
4310 queue_thermal = true;
4311 break;
4312 case 231: /* thermal high to low */
4313 DRM_DEBUG("IH: thermal high to low\n");
4314 rdev->pm.dpm.thermal.high_to_low = true;
4315 queue_thermal = true;
4316 break;
2031f77c 4317 case 233: /* GUI IDLE */
303c805c 4318 DRM_DEBUG("IH: GUI idle\n");
2031f77c 4319 break;
d8f60cfc 4320 default:
b042589c 4321 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4322 break;
4323 }
4324
4325 /* wptr/rptr are in bytes! */
0c45249f
JG		 4326 rptr += 16;
4327 rptr &= rdev->ih.ptr_mask;
f55e03b9 4328 WREG32(IH_RB_RPTR, rptr);
d8f60cfc 4329 }
d4877cf2 4330 if (queue_hotplug)
cb5d4166 4331 schedule_delayed_work(&rdev->hotplug_work, 0);
f122c610
AD		 4332 if (queue_hdmi)
4333 schedule_work(&rdev->audio_work);
4a6369e9
AD		 4334 if (queue_thermal && rdev->pm.dpm_enabled)
4335 schedule_work(&rdev->pm.dpm.thermal.work);
d8f60cfc 4336 rdev->ih.rptr = rptr;
c20dc369
CK		 4337 atomic_set(&rdev->ih.lock, 0);
4338
4339 /* make sure wptr hasn't changed while processing */
4340 wptr = r600_get_ih_wptr(rdev);
4341 if (wptr != rptr)
4342 goto restart_ih;
4343
d8f60cfc
AD		 4344 return IRQ_HANDLED;
4345}
3ce0a23d
JG		 4346
4347/*
4348 * Debugfs info
4349 */
4350#if defined(CONFIG_DEBUG_FS)
4351
3ce0a23d
JG		 4352static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4353{
4354 struct drm_info_node *node = (struct drm_info_node *) m->private;
4355 struct drm_device *dev = node->minor->dev;
4356 struct radeon_device *rdev = dev->dev_private;
4357
4358 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4359 DREG32_SYS(m, rdev, VM_L2_STATUS);
4360 return 0;
4361}
4362
4363static struct drm_info_list r600_mc_info_list[] = {
4364 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 4365};
4366#endif
4367
4368int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4369{
4370#if defined(CONFIG_DEBUG_FS)
4371 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4372#else
4373 return 0;
4374#endif
771fe6b9 4375}
062b389c
JG		 4376
4377/**
124764f1 4378 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
062b389c 4379 * rdev: radeon device structure
062b389c 4380 *
124764f1
MD		 4381 * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4382 * through the ring buffer. This leads to corruption in rendering, see
4383 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4384 * directly perform the HDP flush by writing the register through MMIO.
062b389c 4385 */
124764f1 4386void r600_mmio_hdp_flush(struct radeon_device *rdev)
062b389c 4387{
812d0469 4388 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 4389 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4390 * This seems to cause problems on some AGP cards. Just use the old
4391 * method for them.
812d0469 4392 */
e488459a 4393 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 4394 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 4395 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 4396 u32 tmp;
4397
4398 WREG32(HDP_DEBUG1, 0);
4399 tmp = readl((void __iomem *)ptr);
4400 } else
4401 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 4402}
3313e3d4
AD		 4403
4404void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4405{
d5445a17 4406 u32 link_width_cntl, mask;
3313e3d4
AD		 4407
4408 if (rdev->flags & RADEON_IS_IGP)
4409 return;
4410
4411 if (!(rdev->flags & RADEON_IS_PCIE))
4412 return;
4413
4414 /* x2 cards have a special sequence */
4415 if (ASIC_IS_X2(rdev))
4416 return;
4417
d5445a17 4418 radeon_gui_idle(rdev);
3313e3d4
AD		 4419
4420 switch (lanes) {
4421 case 0:
4422 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4423 break;
4424 case 1:
4425 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4426 break;
4427 case 2:
4428 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4429 break;
4430 case 4:
4431 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4432 break;
4433 case 8:
4434 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4435 break;
4436 case 12:
d5445a17 4437 /* not actually supported */
3313e3d4
AD		 4438 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4439 break;
4440 case 16:
3313e3d4
AD		 4441 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4442 break;
d5445a17
AD		 4443 default:
4444 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4445 return;
3313e3d4
AD		 4446 }
4447
492d2b61 4448 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
d5445a17
AD		 4449 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4450 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4451 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4452 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3313e3d4 4453
492d2b61 4454 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3313e3d4
AD		 4455}
4456
4457int r600_get_pcie_lanes(struct radeon_device *rdev)
4458{
4459 u32 link_width_cntl;
4460
4461 if (rdev->flags & RADEON_IS_IGP)
4462 return 0;
4463
4464 if (!(rdev->flags & RADEON_IS_PCIE))
4465 return 0;
4466
4467 /* x2 cards have a special sequence */
4468 if (ASIC_IS_X2(rdev))
4469 return 0;
4470
d5445a17 4471 radeon_gui_idle(rdev);
3313e3d4 4472
492d2b61 4473 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3313e3d4
AD		 4474
4475 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3313e3d4
AD		 4476 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4477 return 1;
4478 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4479 return 2;
4480 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4481 return 4;
4482 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4483 return 8;
d5445a17
AD		 4484 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4485 /* not actually supported */
4486 return 12;
4487 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3313e3d4
AD		 4488 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4489 default:
4490 return 16;
4491 }
4492}
4493
9e46a48d
AD		 4494static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4495{
4496 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4497 u16 link_cntl2;
4498
d42dd579
AD		 4499 if (radeon_pcie_gen2 == 0)
4500 return;
4501
9e46a48d
AD		 4502 if (rdev->flags & RADEON_IS_IGP)
4503 return;
4504
4505 if (!(rdev->flags & RADEON_IS_PCIE))
4506 return;
4507
4508 /* x2 cards have a special sequence */
4509 if (ASIC_IS_X2(rdev))
4510 return;
4511
4512 /* only RV6xx+ chips are supported */
4513 if (rdev->family <= CHIP_R600)
4514 return;
4515
7e0e4196
KSS		 4516 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4517 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
197bbb3d
DA		 4518 return;
4519
492d2b61 4520 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3691feea
AD		 4521 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4522 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4523 return;
4524 }
4525
197bbb3d
DA		 4526 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4527
9e46a48d
AD		 4528 /* 55 nm r6xx asics */
4529 if ((rdev->family == CHIP_RV670) ||
4530 (rdev->family == CHIP_RV620) ||
4531 (rdev->family == CHIP_RV635)) {
4532 /* advertise upconfig capability */
492d2b61 4533 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d 4534 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61
AD		 4535 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4536 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4537 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4538 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4539 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4540 LC_RECONFIG_ARC_MISSING_ESCAPE);
4541 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
492d2b61 4542 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4543 } else {
4544 link_width_cntl |= LC_UPCONFIGURE_DIS;
492d2b61 4545 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4546 }
4547 }
4548
492d2b61 4549 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d
AD		 4550 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4551 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4552
4553 /* 55 nm r6xx asics */
4554 if ((rdev->family == CHIP_RV670) ||
4555 (rdev->family == CHIP_RV620) ||
4556 (rdev->family == CHIP_RV635)) {
4557 WREG32(MM_CFGREGS_CNTL, 0x8);
4558 link_cntl2 = RREG32(0x4088);
4559 WREG32(MM_CFGREGS_CNTL, 0);
4560 /* not supported yet */
4561 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4562 return;
4563 }
4564
4565 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4566 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4567 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4568 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4569 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
492d2b61 4570 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4571
4572 tmp = RREG32(0x541c);
4573 WREG32(0x541c, tmp | 0x8);
4574 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4575 link_cntl2 = RREG16(0x4088);
4576 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4577 link_cntl2 |= 0x2;
4578 WREG16(0x4088, link_cntl2);
4579 WREG32(MM_CFGREGS_CNTL, 0);
4580
4581 if ((rdev->family == CHIP_RV670) ||
4582 (rdev->family == CHIP_RV620) ||
4583 (rdev->family == CHIP_RV635)) {
492d2b61 4584 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
9e46a48d 4585 training_cntl &= ~LC_POINT_7_PLUS_EN;
492d2b61 4586 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
9e46a48d 4587 } else {
492d2b61 4588 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4589 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
492d2b61 4590 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4591 }
4592
492d2b61 4593 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4594 speed_cntl |= LC_GEN2_EN_STRAP;
492d2b61 4595 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4596
4597 } else {
492d2b61 4598 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4599 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4600 if (1)
4601 link_width_cntl |= LC_UPCONFIGURE_DIS;
4602 else
4603 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 4604 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4605 }
4606}
6759a0a7
MO		 4607
4608/**
d0418894 4609 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
6759a0a7
MO		 4610 *
4611 * @rdev: radeon_device pointer
4612 *
4613 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4614 * Returns the 64 bit clock counter snapshot.
4615 */
d0418894 4616uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
6759a0a7
MO		 4617{
4618 uint64_t clock;
4619
4620 mutex_lock(&rdev->gpu_clock_mutex);
4621 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4622 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
3cf8bb1a 4623 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
6759a0a7
MO		 4624 mutex_unlock(&rdev->gpu_clock_mutex);
4625 return clock;
4626}
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