]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
3ce0a23d JG |
29 | #include <linux/seq_file.h> |
30 | #include <linux/firmware.h> | |
31 | #include <linux/platform_device.h> | |
771fe6b9 | 32 | #include "drmP.h" |
3ce0a23d | 33 | #include "radeon_drm.h" |
771fe6b9 | 34 | #include "radeon.h" |
e6990375 | 35 | #include "radeon_asic.h" |
3ce0a23d | 36 | #include "radeon_mode.h" |
3ce0a23d | 37 | #include "r600d.h" |
3ce0a23d | 38 | #include "atom.h" |
d39c3b89 | 39 | #include "avivod.h" |
771fe6b9 | 40 | |
3ce0a23d JG |
41 | #define PFP_UCODE_SIZE 576 |
42 | #define PM4_UCODE_SIZE 1792 | |
d8f60cfc | 43 | #define RLC_UCODE_SIZE 768 |
3ce0a23d JG |
44 | #define R700_PFP_UCODE_SIZE 848 |
45 | #define R700_PM4_UCODE_SIZE 1360 | |
d8f60cfc | 46 | #define R700_RLC_UCODE_SIZE 1024 |
fe251e2f AD |
47 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
48 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | |
45f9a39b | 49 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
3ce0a23d JG |
50 | |
51 | /* Firmware Names */ | |
52 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
53 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
54 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
55 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
56 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
57 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
59 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
60 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
61 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
62 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
63 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
64 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
65 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
66 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
67 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
68 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); | |
69 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
70 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); | |
71 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
d8f60cfc AD |
72 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
73 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); | |
fe251e2f AD |
74 | MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); |
75 | MODULE_FIRMWARE("radeon/CEDAR_me.bin"); | |
45f9a39b | 76 | MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); |
fe251e2f AD |
77 | MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); |
78 | MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); | |
45f9a39b | 79 | MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); |
fe251e2f AD |
80 | MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); |
81 | MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); | |
45f9a39b | 82 | MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); |
a7433742 | 83 | MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); |
fe251e2f | 84 | MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); |
45f9a39b | 85 | MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); |
3ce0a23d JG |
86 | |
87 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); | |
771fe6b9 | 88 | |
1a029b76 | 89 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
771fe6b9 JG |
90 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
91 | void r600_gpu_init(struct radeon_device *rdev); | |
3ce0a23d | 92 | void r600_fini(struct radeon_device *rdev); |
45f9a39b | 93 | void r600_irq_disable(struct radeon_device *rdev); |
771fe6b9 | 94 | |
ce8f5370 | 95 | void r600_pm_get_dynpm_state(struct radeon_device *rdev) |
a48b9b4e AD |
96 | { |
97 | int i; | |
98 | ||
ce8f5370 AD |
99 | rdev->pm.dynpm_can_upclock = true; |
100 | rdev->pm.dynpm_can_downclock = true; | |
a48b9b4e AD |
101 | |
102 | /* power state array is low to high, default is first */ | |
103 | if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { | |
104 | int min_power_state_index = 0; | |
105 | ||
106 | if (rdev->pm.num_power_states > 2) | |
107 | min_power_state_index = 1; | |
108 | ||
ce8f5370 AD |
109 | switch (rdev->pm.dynpm_planned_action) { |
110 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e AD |
111 | rdev->pm.requested_power_state_index = min_power_state_index; |
112 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 113 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 114 | break; |
ce8f5370 | 115 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
116 | if (rdev->pm.current_power_state_index == min_power_state_index) { |
117 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 118 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
119 | } else { |
120 | if (rdev->pm.active_crtc_count > 1) { | |
121 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 122 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
123 | continue; |
124 | else if (i >= rdev->pm.current_power_state_index) { | |
125 | rdev->pm.requested_power_state_index = | |
126 | rdev->pm.current_power_state_index; | |
127 | break; | |
128 | } else { | |
129 | rdev->pm.requested_power_state_index = i; | |
130 | break; | |
131 | } | |
132 | } | |
773c3fa3 AD |
133 | } else { |
134 | if (rdev->pm.current_power_state_index == 0) | |
135 | rdev->pm.requested_power_state_index = | |
136 | rdev->pm.num_power_states - 1; | |
137 | else | |
138 | rdev->pm.requested_power_state_index = | |
139 | rdev->pm.current_power_state_index - 1; | |
140 | } | |
a48b9b4e AD |
141 | } |
142 | rdev->pm.requested_clock_mode_index = 0; | |
d7311171 AD |
143 | /* don't use the power state if crtcs are active and no display flag is set */ |
144 | if ((rdev->pm.active_crtc_count > 0) && | |
145 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
146 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
147 | RADEON_PM_MODE_NO_DISPLAY)) { | |
148 | rdev->pm.requested_power_state_index++; | |
149 | } | |
a48b9b4e | 150 | break; |
ce8f5370 | 151 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
152 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
153 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 154 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
155 | } else { |
156 | if (rdev->pm.active_crtc_count > 1) { | |
157 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { | |
d7311171 | 158 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
159 | continue; |
160 | else if (i <= rdev->pm.current_power_state_index) { | |
161 | rdev->pm.requested_power_state_index = | |
162 | rdev->pm.current_power_state_index; | |
163 | break; | |
164 | } else { | |
165 | rdev->pm.requested_power_state_index = i; | |
166 | break; | |
167 | } | |
168 | } | |
169 | } else | |
170 | rdev->pm.requested_power_state_index = | |
171 | rdev->pm.current_power_state_index + 1; | |
172 | } | |
173 | rdev->pm.requested_clock_mode_index = 0; | |
174 | break; | |
ce8f5370 | 175 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
176 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
177 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 178 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 179 | break; |
ce8f5370 | 180 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
181 | default: |
182 | DRM_ERROR("Requested mode for not defined action\n"); | |
183 | return; | |
184 | } | |
185 | } else { | |
186 | /* XXX select a power state based on AC/DC, single/dualhead, etc. */ | |
187 | /* for now just select the first power state and switch between clock modes */ | |
188 | /* power state array is low to high, default is first (0) */ | |
189 | if (rdev->pm.active_crtc_count > 1) { | |
190 | rdev->pm.requested_power_state_index = -1; | |
191 | /* start at 1 as we don't want the default mode */ | |
192 | for (i = 1; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 193 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
194 | continue; |
195 | else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || | |
196 | (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { | |
197 | rdev->pm.requested_power_state_index = i; | |
198 | break; | |
199 | } | |
200 | } | |
201 | /* if nothing selected, grab the default state. */ | |
202 | if (rdev->pm.requested_power_state_index == -1) | |
203 | rdev->pm.requested_power_state_index = 0; | |
204 | } else | |
205 | rdev->pm.requested_power_state_index = 1; | |
206 | ||
ce8f5370 AD |
207 | switch (rdev->pm.dynpm_planned_action) { |
208 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e | 209 | rdev->pm.requested_clock_mode_index = 0; |
ce8f5370 | 210 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 211 | break; |
ce8f5370 | 212 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
213 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
214 | if (rdev->pm.current_clock_mode_index == 0) { | |
215 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 216 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
217 | } else |
218 | rdev->pm.requested_clock_mode_index = | |
219 | rdev->pm.current_clock_mode_index - 1; | |
220 | } else { | |
221 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 222 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 223 | } |
d7311171 AD |
224 | /* don't use the power state if crtcs are active and no display flag is set */ |
225 | if ((rdev->pm.active_crtc_count > 0) && | |
226 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
227 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
228 | RADEON_PM_MODE_NO_DISPLAY)) { | |
229 | rdev->pm.requested_clock_mode_index++; | |
230 | } | |
a48b9b4e | 231 | break; |
ce8f5370 | 232 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
233 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
234 | if (rdev->pm.current_clock_mode_index == | |
235 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { | |
236 | rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; | |
ce8f5370 | 237 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
238 | } else |
239 | rdev->pm.requested_clock_mode_index = | |
240 | rdev->pm.current_clock_mode_index + 1; | |
241 | } else { | |
242 | rdev->pm.requested_clock_mode_index = | |
243 | rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; | |
ce8f5370 | 244 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
245 | } |
246 | break; | |
ce8f5370 | 247 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
248 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
249 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 250 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 251 | break; |
ce8f5370 | 252 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
253 | default: |
254 | DRM_ERROR("Requested mode for not defined action\n"); | |
255 | return; | |
256 | } | |
257 | } | |
258 | ||
ce8a3eb2 AD |
259 | DRM_DEBUG("Requested: e: %d m: %d p: %d\n", |
260 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
261 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | |
262 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
263 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | |
264 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
265 | pcie_lanes); | |
a48b9b4e AD |
266 | } |
267 | ||
ce8f5370 AD |
268 | static int r600_pm_get_type_index(struct radeon_device *rdev, |
269 | enum radeon_pm_state_type ps_type, | |
270 | int instance) | |
bae6b562 | 271 | { |
ce8f5370 AD |
272 | int i; |
273 | int found_instance = -1; | |
bae6b562 | 274 | |
ce8f5370 AD |
275 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
276 | if (rdev->pm.power_state[i].type == ps_type) { | |
277 | found_instance++; | |
278 | if (found_instance == instance) | |
279 | return i; | |
a424816f | 280 | } |
ce8f5370 AD |
281 | } |
282 | /* return default if no match */ | |
283 | return rdev->pm.default_power_state_index; | |
284 | } | |
285 | ||
286 | void rs780_pm_init_profile(struct radeon_device *rdev) | |
287 | { | |
288 | if (rdev->pm.num_power_states == 2) { | |
289 | /* default */ | |
290 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
291 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
292 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
293 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
294 | /* low sh */ | |
295 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; | |
296 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; | |
297 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
298 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
299 | /* mid sh */ |
300 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; | |
301 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; | |
302 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
303 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
304 | /* high sh */ |
305 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; | |
306 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
307 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
308 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
309 | /* low mh */ | |
310 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; | |
311 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
312 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
313 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
314 | /* mid mh */ |
315 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; | |
316 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
317 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
318 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
319 | /* high mh */ |
320 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; | |
321 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; | |
322 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
323 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
324 | } else if (rdev->pm.num_power_states == 3) { | |
325 | /* default */ | |
326 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
327 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
328 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
329 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
330 | /* low sh */ | |
331 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; | |
332 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
333 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
334 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
335 | /* mid sh */ |
336 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
337 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
338 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
339 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
340 | /* high sh */ |
341 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; | |
342 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; | |
343 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
344 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
345 | /* low mh */ | |
346 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; | |
347 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; | |
348 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
349 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
350 | /* mid mh */ |
351 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; | |
352 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; | |
353 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
354 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
355 | /* high mh */ |
356 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; | |
357 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
358 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
359 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
360 | } else { | |
361 | /* default */ | |
362 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
363 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
364 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
365 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
366 | /* low sh */ | |
367 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; | |
368 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; | |
369 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
370 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
371 | /* mid sh */ |
372 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; | |
373 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; | |
374 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
375 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
376 | /* high sh */ |
377 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; | |
378 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; | |
379 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
380 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
381 | /* low mh */ | |
382 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; | |
383 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
384 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
385 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
386 | /* mid mh */ |
387 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
388 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
389 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
390 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
391 | /* high mh */ |
392 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; | |
393 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; | |
394 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
395 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
396 | } | |
397 | } | |
bae6b562 | 398 | |
ce8f5370 AD |
399 | void r600_pm_init_profile(struct radeon_device *rdev) |
400 | { | |
401 | if (rdev->family == CHIP_R600) { | |
402 | /* XXX */ | |
403 | /* default */ | |
404 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
405 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
406 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 407 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
408 | /* low sh */ |
409 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
410 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
411 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 412 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
413 | /* mid sh */ |
414 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
415 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
416 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
417 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
418 | /* high sh */ |
419 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
420 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
421 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 422 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
423 | /* low mh */ |
424 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
425 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
426 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 427 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
428 | /* mid mh */ |
429 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
430 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
431 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
432 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
433 | /* high mh */ |
434 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
435 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
436 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 437 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
438 | } else { |
439 | if (rdev->pm.num_power_states < 4) { | |
440 | /* default */ | |
441 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
442 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
443 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
444 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
445 | /* low sh */ | |
4bff5171 AD |
446 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
447 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 | 448 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
449 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
450 | /* mid sh */ | |
451 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
452 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
453 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
454 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 455 | /* high sh */ |
4bff5171 AD |
456 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
457 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 AD |
458 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
459 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
460 | /* low mh */ | |
4bff5171 AD |
461 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
462 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 | 463 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
464 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
465 | /* low mh */ | |
466 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
467 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; | |
468 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
469 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 470 | /* high mh */ |
4bff5171 AD |
471 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
472 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 AD |
473 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
474 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
475 | } else { | |
476 | /* default */ | |
477 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
478 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
479 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
480 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
481 | /* low sh */ | |
4bff5171 AD |
482 | if (rdev->flags & RADEON_IS_MOBILITY) { |
483 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = | |
484 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
485 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = | |
486 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
487 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
c9e75b21 | 488 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
4bff5171 AD |
489 | } else { |
490 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = | |
491 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
492 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = | |
493 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
494 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
c9e75b21 AD |
495 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
496 | } | |
497 | /* mid sh */ | |
498 | if (rdev->flags & RADEON_IS_MOBILITY) { | |
499 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = | |
500 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
501 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = | |
502 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
503 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
504 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
505 | } else { | |
506 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = | |
507 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
508 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = | |
509 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
510 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
511 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
4bff5171 | 512 | } |
ce8f5370 | 513 | /* high sh */ |
4bff5171 AD |
514 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = |
515 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
516 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = | |
517 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
ce8f5370 AD |
518 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
519 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
520 | /* low mh */ | |
4bff5171 AD |
521 | if (rdev->flags & RADEON_IS_MOBILITY) { |
522 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = | |
523 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); | |
524 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = | |
525 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); | |
526 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
c9e75b21 | 527 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
4bff5171 AD |
528 | } else { |
529 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = | |
530 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
531 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = | |
532 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
533 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
c9e75b21 AD |
534 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
535 | } | |
536 | /* mid mh */ | |
537 | if (rdev->flags & RADEON_IS_MOBILITY) { | |
538 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = | |
539 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); | |
540 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = | |
541 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); | |
542 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
543 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
544 | } else { | |
545 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = | |
546 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
547 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = | |
548 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
549 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
550 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
4bff5171 | 551 | } |
ce8f5370 | 552 | /* high mh */ |
4bff5171 AD |
553 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = |
554 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
555 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = | |
556 | r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
ce8f5370 AD |
557 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
558 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
559 | } | |
560 | } | |
bae6b562 AD |
561 | } |
562 | ||
49e02b73 AD |
563 | void r600_pm_misc(struct radeon_device *rdev) |
564 | { | |
a081a9d6 RM |
565 | int req_ps_idx = rdev->pm.requested_power_state_index; |
566 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
567 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
568 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
7ac9aa5a | 569 | |
4d60173f AD |
570 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
571 | if (voltage->voltage != rdev->pm.current_vddc) { | |
572 | radeon_atom_set_voltage(rdev, voltage->voltage); | |
573 | rdev->pm.current_vddc = voltage->voltage; | |
0fcbe947 | 574 | DRM_DEBUG("Setting: v: %d\n", voltage->voltage); |
4d60173f AD |
575 | } |
576 | } | |
49e02b73 AD |
577 | } |
578 | ||
def9ba9c AD |
579 | bool r600_gui_idle(struct radeon_device *rdev) |
580 | { | |
581 | if (RREG32(GRBM_STATUS) & GUI_ACTIVE) | |
582 | return false; | |
583 | else | |
584 | return true; | |
585 | } | |
586 | ||
e0df1ac5 AD |
587 | /* hpd for digital panel detect/disconnect */ |
588 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
589 | { | |
590 | bool connected = false; | |
591 | ||
592 | if (ASIC_IS_DCE3(rdev)) { | |
593 | switch (hpd) { | |
594 | case RADEON_HPD_1: | |
595 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
596 | connected = true; | |
597 | break; | |
598 | case RADEON_HPD_2: | |
599 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
600 | connected = true; | |
601 | break; | |
602 | case RADEON_HPD_3: | |
603 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
604 | connected = true; | |
605 | break; | |
606 | case RADEON_HPD_4: | |
607 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
608 | connected = true; | |
609 | break; | |
610 | /* DCE 3.2 */ | |
611 | case RADEON_HPD_5: | |
612 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
613 | connected = true; | |
614 | break; | |
615 | case RADEON_HPD_6: | |
616 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
617 | connected = true; | |
618 | break; | |
619 | default: | |
620 | break; | |
621 | } | |
622 | } else { | |
623 | switch (hpd) { | |
624 | case RADEON_HPD_1: | |
625 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
626 | connected = true; | |
627 | break; | |
628 | case RADEON_HPD_2: | |
629 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
630 | connected = true; | |
631 | break; | |
632 | case RADEON_HPD_3: | |
633 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
634 | connected = true; | |
635 | break; | |
636 | default: | |
637 | break; | |
638 | } | |
639 | } | |
640 | return connected; | |
641 | } | |
642 | ||
643 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
429770b3 | 644 | enum radeon_hpd_id hpd) |
e0df1ac5 AD |
645 | { |
646 | u32 tmp; | |
647 | bool connected = r600_hpd_sense(rdev, hpd); | |
648 | ||
649 | if (ASIC_IS_DCE3(rdev)) { | |
650 | switch (hpd) { | |
651 | case RADEON_HPD_1: | |
652 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
653 | if (connected) | |
654 | tmp &= ~DC_HPDx_INT_POLARITY; | |
655 | else | |
656 | tmp |= DC_HPDx_INT_POLARITY; | |
657 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
658 | break; | |
659 | case RADEON_HPD_2: | |
660 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
661 | if (connected) | |
662 | tmp &= ~DC_HPDx_INT_POLARITY; | |
663 | else | |
664 | tmp |= DC_HPDx_INT_POLARITY; | |
665 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
666 | break; | |
667 | case RADEON_HPD_3: | |
668 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
669 | if (connected) | |
670 | tmp &= ~DC_HPDx_INT_POLARITY; | |
671 | else | |
672 | tmp |= DC_HPDx_INT_POLARITY; | |
673 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
674 | break; | |
675 | case RADEON_HPD_4: | |
676 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
677 | if (connected) | |
678 | tmp &= ~DC_HPDx_INT_POLARITY; | |
679 | else | |
680 | tmp |= DC_HPDx_INT_POLARITY; | |
681 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
682 | break; | |
683 | case RADEON_HPD_5: | |
684 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
685 | if (connected) | |
686 | tmp &= ~DC_HPDx_INT_POLARITY; | |
687 | else | |
688 | tmp |= DC_HPDx_INT_POLARITY; | |
689 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
690 | break; | |
691 | /* DCE 3.2 */ | |
692 | case RADEON_HPD_6: | |
693 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
694 | if (connected) | |
695 | tmp &= ~DC_HPDx_INT_POLARITY; | |
696 | else | |
697 | tmp |= DC_HPDx_INT_POLARITY; | |
698 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
699 | break; | |
700 | default: | |
701 | break; | |
702 | } | |
703 | } else { | |
704 | switch (hpd) { | |
705 | case RADEON_HPD_1: | |
706 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
707 | if (connected) | |
708 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
709 | else | |
710 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
711 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
712 | break; | |
713 | case RADEON_HPD_2: | |
714 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
715 | if (connected) | |
716 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
717 | else | |
718 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
719 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
720 | break; | |
721 | case RADEON_HPD_3: | |
722 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
723 | if (connected) | |
724 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
725 | else | |
726 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
727 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
728 | break; | |
729 | default: | |
730 | break; | |
731 | } | |
732 | } | |
733 | } | |
734 | ||
735 | void r600_hpd_init(struct radeon_device *rdev) | |
736 | { | |
737 | struct drm_device *dev = rdev->ddev; | |
738 | struct drm_connector *connector; | |
739 | ||
740 | if (ASIC_IS_DCE3(rdev)) { | |
741 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); | |
742 | if (ASIC_IS_DCE32(rdev)) | |
743 | tmp |= DC_HPDx_EN; | |
744 | ||
745 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
746 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
747 | switch (radeon_connector->hpd.hpd) { | |
748 | case RADEON_HPD_1: | |
749 | WREG32(DC_HPD1_CONTROL, tmp); | |
750 | rdev->irq.hpd[0] = true; | |
751 | break; | |
752 | case RADEON_HPD_2: | |
753 | WREG32(DC_HPD2_CONTROL, tmp); | |
754 | rdev->irq.hpd[1] = true; | |
755 | break; | |
756 | case RADEON_HPD_3: | |
757 | WREG32(DC_HPD3_CONTROL, tmp); | |
758 | rdev->irq.hpd[2] = true; | |
759 | break; | |
760 | case RADEON_HPD_4: | |
761 | WREG32(DC_HPD4_CONTROL, tmp); | |
762 | rdev->irq.hpd[3] = true; | |
763 | break; | |
764 | /* DCE 3.2 */ | |
765 | case RADEON_HPD_5: | |
766 | WREG32(DC_HPD5_CONTROL, tmp); | |
767 | rdev->irq.hpd[4] = true; | |
768 | break; | |
769 | case RADEON_HPD_6: | |
770 | WREG32(DC_HPD6_CONTROL, tmp); | |
771 | rdev->irq.hpd[5] = true; | |
772 | break; | |
773 | default: | |
774 | break; | |
775 | } | |
776 | } | |
777 | } else { | |
778 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
779 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
780 | switch (radeon_connector->hpd.hpd) { | |
781 | case RADEON_HPD_1: | |
782 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
783 | rdev->irq.hpd[0] = true; | |
784 | break; | |
785 | case RADEON_HPD_2: | |
786 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
787 | rdev->irq.hpd[1] = true; | |
788 | break; | |
789 | case RADEON_HPD_3: | |
790 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
791 | rdev->irq.hpd[2] = true; | |
792 | break; | |
793 | default: | |
794 | break; | |
795 | } | |
796 | } | |
797 | } | |
003e69f9 JG |
798 | if (rdev->irq.installed) |
799 | r600_irq_set(rdev); | |
e0df1ac5 AD |
800 | } |
801 | ||
802 | void r600_hpd_fini(struct radeon_device *rdev) | |
803 | { | |
804 | struct drm_device *dev = rdev->ddev; | |
805 | struct drm_connector *connector; | |
806 | ||
807 | if (ASIC_IS_DCE3(rdev)) { | |
808 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
809 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
810 | switch (radeon_connector->hpd.hpd) { | |
811 | case RADEON_HPD_1: | |
812 | WREG32(DC_HPD1_CONTROL, 0); | |
813 | rdev->irq.hpd[0] = false; | |
814 | break; | |
815 | case RADEON_HPD_2: | |
816 | WREG32(DC_HPD2_CONTROL, 0); | |
817 | rdev->irq.hpd[1] = false; | |
818 | break; | |
819 | case RADEON_HPD_3: | |
820 | WREG32(DC_HPD3_CONTROL, 0); | |
821 | rdev->irq.hpd[2] = false; | |
822 | break; | |
823 | case RADEON_HPD_4: | |
824 | WREG32(DC_HPD4_CONTROL, 0); | |
825 | rdev->irq.hpd[3] = false; | |
826 | break; | |
827 | /* DCE 3.2 */ | |
828 | case RADEON_HPD_5: | |
829 | WREG32(DC_HPD5_CONTROL, 0); | |
830 | rdev->irq.hpd[4] = false; | |
831 | break; | |
832 | case RADEON_HPD_6: | |
833 | WREG32(DC_HPD6_CONTROL, 0); | |
834 | rdev->irq.hpd[5] = false; | |
835 | break; | |
836 | default: | |
837 | break; | |
838 | } | |
839 | } | |
840 | } else { | |
841 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
842 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
843 | switch (radeon_connector->hpd.hpd) { | |
844 | case RADEON_HPD_1: | |
845 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); | |
846 | rdev->irq.hpd[0] = false; | |
847 | break; | |
848 | case RADEON_HPD_2: | |
849 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); | |
850 | rdev->irq.hpd[1] = false; | |
851 | break; | |
852 | case RADEON_HPD_3: | |
853 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); | |
854 | rdev->irq.hpd[2] = false; | |
855 | break; | |
856 | default: | |
857 | break; | |
858 | } | |
859 | } | |
860 | } | |
861 | } | |
862 | ||
771fe6b9 | 863 | /* |
3ce0a23d | 864 | * R600 PCIE GART |
771fe6b9 | 865 | */ |
3ce0a23d JG |
866 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
867 | { | |
868 | unsigned i; | |
869 | u32 tmp; | |
870 | ||
2e98f10a DA |
871 | /* flush hdp cache so updates hit vram */ |
872 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
873 | ||
3ce0a23d JG |
874 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
875 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); | |
876 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
877 | for (i = 0; i < rdev->usec_timeout; i++) { | |
878 | /* read MC_STATUS */ | |
879 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
880 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
881 | if (tmp == 2) { | |
882 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
883 | return; | |
884 | } | |
885 | if (tmp) { | |
886 | return; | |
887 | } | |
888 | udelay(1); | |
889 | } | |
890 | } | |
891 | ||
4aac0473 | 892 | int r600_pcie_gart_init(struct radeon_device *rdev) |
3ce0a23d | 893 | { |
4aac0473 | 894 | int r; |
3ce0a23d | 895 | |
4aac0473 JG |
896 | if (rdev->gart.table.vram.robj) { |
897 | WARN(1, "R600 PCIE GART already initialized.\n"); | |
898 | return 0; | |
899 | } | |
3ce0a23d JG |
900 | /* Initialize common gart structure */ |
901 | r = radeon_gart_init(rdev); | |
4aac0473 | 902 | if (r) |
3ce0a23d | 903 | return r; |
3ce0a23d | 904 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
4aac0473 JG |
905 | return radeon_gart_table_vram_alloc(rdev); |
906 | } | |
907 | ||
908 | int r600_pcie_gart_enable(struct radeon_device *rdev) | |
909 | { | |
910 | u32 tmp; | |
911 | int r, i; | |
912 | ||
913 | if (rdev->gart.table.vram.robj == NULL) { | |
914 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
915 | return -EINVAL; | |
771fe6b9 | 916 | } |
4aac0473 JG |
917 | r = radeon_gart_table_vram_pin(rdev); |
918 | if (r) | |
919 | return r; | |
82568565 | 920 | radeon_gart_restore(rdev); |
bc1a631e | 921 | |
3ce0a23d JG |
922 | /* Setup L2 cache */ |
923 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
924 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
925 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
926 | WREG32(VM_L2_CNTL2, 0); | |
927 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
928 | /* Setup TLB control */ | |
929 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
930 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
931 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
932 | ENABLE_WAIT_L2_QUERY; | |
933 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
934 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
935 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
936 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
937 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
938 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
939 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
940 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
941 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
942 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
943 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
944 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
945 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
946 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
947 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1a029b76 | 948 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
949 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
950 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
951 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
952 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
953 | (u32)(rdev->dummy_page.addr >> 12)); | |
954 | for (i = 1; i < 7; i++) | |
955 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 956 | |
3ce0a23d JG |
957 | r600_pcie_gart_tlb_flush(rdev); |
958 | rdev->gart.ready = true; | |
771fe6b9 JG |
959 | return 0; |
960 | } | |
961 | ||
3ce0a23d | 962 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 963 | { |
3ce0a23d | 964 | u32 tmp; |
4c788679 | 965 | int i, r; |
771fe6b9 | 966 | |
3ce0a23d JG |
967 | /* Disable all tables */ |
968 | for (i = 0; i < 7; i++) | |
969 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 970 | |
3ce0a23d JG |
971 | /* Disable L2 cache */ |
972 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
973 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
974 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
975 | /* Setup L1 TLB control */ | |
976 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
977 | ENABLE_WAIT_L2_QUERY; | |
978 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
979 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
980 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
981 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
982 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
983 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
984 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
985 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
986 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); | |
987 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); | |
988 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
989 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
990 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); | |
991 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
4aac0473 | 992 | if (rdev->gart.table.vram.robj) { |
4c788679 JG |
993 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
994 | if (likely(r == 0)) { | |
995 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
996 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
997 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
998 | } | |
4aac0473 JG |
999 | } |
1000 | } | |
1001 | ||
1002 | void r600_pcie_gart_fini(struct radeon_device *rdev) | |
1003 | { | |
f9274562 | 1004 | radeon_gart_fini(rdev); |
4aac0473 JG |
1005 | r600_pcie_gart_disable(rdev); |
1006 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
1007 | } |
1008 | ||
1a029b76 JG |
1009 | void r600_agp_enable(struct radeon_device *rdev) |
1010 | { | |
1011 | u32 tmp; | |
1012 | int i; | |
1013 | ||
1014 | /* Setup L2 cache */ | |
1015 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
1016 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
1017 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1018 | WREG32(VM_L2_CNTL2, 0); | |
1019 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
1020 | /* Setup TLB control */ | |
1021 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1022 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1023 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
1024 | ENABLE_WAIT_L2_QUERY; | |
1025 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
1026 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
1027 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
1028 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
1029 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
1030 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
1031 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
1032 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
1033 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
1034 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
1035 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
1036 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
1037 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1038 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1039 | for (i = 0; i < 7; i++) | |
1040 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
1041 | } | |
1042 | ||
771fe6b9 JG |
1043 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
1044 | { | |
3ce0a23d JG |
1045 | unsigned i; |
1046 | u32 tmp; | |
1047 | ||
1048 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1049 | /* read MC_STATUS */ | |
1050 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; | |
1051 | if (!tmp) | |
1052 | return 0; | |
1053 | udelay(1); | |
1054 | } | |
1055 | return -1; | |
771fe6b9 JG |
1056 | } |
1057 | ||
a3c1945a | 1058 | static void r600_mc_program(struct radeon_device *rdev) |
771fe6b9 | 1059 | { |
a3c1945a | 1060 | struct rv515_mc_save save; |
3ce0a23d JG |
1061 | u32 tmp; |
1062 | int i, j; | |
771fe6b9 | 1063 | |
3ce0a23d JG |
1064 | /* Initialize HDP */ |
1065 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1066 | WREG32((0x2c14 + j), 0x00000000); | |
1067 | WREG32((0x2c18 + j), 0x00000000); | |
1068 | WREG32((0x2c1c + j), 0x00000000); | |
1069 | WREG32((0x2c20 + j), 0x00000000); | |
1070 | WREG32((0x2c24 + j), 0x00000000); | |
1071 | } | |
1072 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
771fe6b9 | 1073 | |
a3c1945a | 1074 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 1075 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1076 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1077 | } |
a3c1945a | 1078 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
3ce0a23d | 1079 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
3ce0a23d | 1080 | /* Update configuration */ |
1a029b76 JG |
1081 | if (rdev->flags & RADEON_IS_AGP) { |
1082 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
1083 | /* VRAM before AGP */ | |
1084 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1085 | rdev->mc.vram_start >> 12); | |
1086 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1087 | rdev->mc.gtt_end >> 12); | |
1088 | } else { | |
1089 | /* VRAM after AGP */ | |
1090 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1091 | rdev->mc.gtt_start >> 12); | |
1092 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1093 | rdev->mc.vram_end >> 12); | |
1094 | } | |
1095 | } else { | |
1096 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); | |
1097 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); | |
1098 | } | |
3ce0a23d | 1099 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
1a029b76 | 1100 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
1101 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
1102 | WREG32(MC_VM_FB_LOCATION, tmp); | |
1103 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
1104 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
46fcd2b3 | 1105 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
3ce0a23d | 1106 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 JG |
1107 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
1108 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | |
3ce0a23d JG |
1109 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
1110 | } else { | |
1111 | WREG32(MC_VM_AGP_BASE, 0); | |
1112 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
1113 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
1114 | } | |
3ce0a23d | 1115 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1116 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1117 | } |
a3c1945a | 1118 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
1119 | /* we need to own VRAM, so turn off the VGA renderer here |
1120 | * to stop it overwriting our objects */ | |
d39c3b89 | 1121 | rv515_vga_render_disable(rdev); |
3ce0a23d JG |
1122 | } |
1123 | ||
d594e46a JG |
1124 | /** |
1125 | * r600_vram_gtt_location - try to find VRAM & GTT location | |
1126 | * @rdev: radeon device structure holding all necessary informations | |
1127 | * @mc: memory controller structure holding memory informations | |
1128 | * | |
1129 | * Function will place try to place VRAM at same place as in CPU (PCI) | |
1130 | * address space as some GPU seems to have issue when we reprogram at | |
1131 | * different address space. | |
1132 | * | |
1133 | * If there is not enough space to fit the unvisible VRAM after the | |
1134 | * aperture then we limit the VRAM size to the aperture. | |
1135 | * | |
1136 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need | |
1137 | * them to be in one from GPU point of view so that we can program GPU to | |
1138 | * catch access outside them (weird GPU policy see ??). | |
1139 | * | |
1140 | * This function will never fails, worst case are limiting VRAM or GTT. | |
1141 | * | |
1142 | * Note: GTT start, end, size should be initialized before calling this | |
1143 | * function on AGP platform. | |
1144 | */ | |
1145 | void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
1146 | { | |
1147 | u64 size_bf, size_af; | |
1148 | ||
1149 | if (mc->mc_vram_size > 0xE0000000) { | |
1150 | /* leave room for at least 512M GTT */ | |
1151 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1152 | mc->real_vram_size = 0xE0000000; | |
1153 | mc->mc_vram_size = 0xE0000000; | |
1154 | } | |
1155 | if (rdev->flags & RADEON_IS_AGP) { | |
1156 | size_bf = mc->gtt_start; | |
1157 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; | |
1158 | if (size_bf > size_af) { | |
1159 | if (mc->mc_vram_size > size_bf) { | |
1160 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1161 | mc->real_vram_size = size_bf; | |
1162 | mc->mc_vram_size = size_bf; | |
1163 | } | |
1164 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; | |
1165 | } else { | |
1166 | if (mc->mc_vram_size > size_af) { | |
1167 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1168 | mc->real_vram_size = size_af; | |
1169 | mc->mc_vram_size = size_af; | |
1170 | } | |
1171 | mc->vram_start = mc->gtt_end; | |
1172 | } | |
1173 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
1174 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
1175 | mc->mc_vram_size >> 20, mc->vram_start, | |
1176 | mc->vram_end, mc->real_vram_size >> 20); | |
1177 | } else { | |
1178 | u64 base = 0; | |
1179 | if (rdev->flags & RADEON_IS_IGP) | |
1180 | base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; | |
1181 | radeon_vram_location(rdev, &rdev->mc, base); | |
1182 | radeon_gtt_location(rdev, mc); | |
1183 | } | |
1184 | } | |
1185 | ||
3ce0a23d | 1186 | int r600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 1187 | { |
3ce0a23d | 1188 | u32 tmp; |
5885b7a9 | 1189 | int chansize, numchan; |
771fe6b9 | 1190 | |
3ce0a23d | 1191 | /* Get VRAM informations */ |
771fe6b9 | 1192 | rdev->mc.vram_is_ddr = true; |
3ce0a23d JG |
1193 | tmp = RREG32(RAMCFG); |
1194 | if (tmp & CHANSIZE_OVERRIDE) { | |
771fe6b9 | 1195 | chansize = 16; |
3ce0a23d | 1196 | } else if (tmp & CHANSIZE_MASK) { |
771fe6b9 JG |
1197 | chansize = 64; |
1198 | } else { | |
1199 | chansize = 32; | |
1200 | } | |
5885b7a9 AD |
1201 | tmp = RREG32(CHMAP); |
1202 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
1203 | case 0: | |
1204 | default: | |
1205 | numchan = 1; | |
1206 | break; | |
1207 | case 1: | |
1208 | numchan = 2; | |
1209 | break; | |
1210 | case 2: | |
1211 | numchan = 4; | |
1212 | break; | |
1213 | case 3: | |
1214 | numchan = 8; | |
1215 | break; | |
771fe6b9 | 1216 | } |
5885b7a9 | 1217 | rdev->mc.vram_width = numchan * chansize; |
3ce0a23d | 1218 | /* Could aper size report 0 ? */ |
01d73a69 JC |
1219 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
1220 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
3ce0a23d JG |
1221 | /* Setup GPU memory space */ |
1222 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
1223 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
51e5fcd3 | 1224 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a | 1225 | r600_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 | 1226 | |
f892034a AD |
1227 | if (rdev->flags & RADEON_IS_IGP) { |
1228 | rs690_pm_info(rdev); | |
06b6476d | 1229 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
f892034a | 1230 | } |
f47299c5 | 1231 | radeon_update_bandwidth_info(rdev); |
3ce0a23d | 1232 | return 0; |
771fe6b9 JG |
1233 | } |
1234 | ||
3ce0a23d JG |
1235 | /* We doesn't check that the GPU really needs a reset we simply do the |
1236 | * reset, it's up to the caller to determine if the GPU needs one. We | |
1237 | * might add an helper function to check that. | |
1238 | */ | |
1239 | int r600_gpu_soft_reset(struct radeon_device *rdev) | |
771fe6b9 | 1240 | { |
a3c1945a | 1241 | struct rv515_mc_save save; |
3ce0a23d JG |
1242 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
1243 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | | |
1244 | S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | | |
1245 | S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | | |
1246 | S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | | |
1247 | S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | | |
1248 | S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | | |
1249 | S_008010_GUI_ACTIVE(1); | |
1250 | u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | | |
1251 | S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | | |
1252 | S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | | |
1253 | S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | | |
1254 | S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | | |
1255 | S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | | |
1256 | S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | | |
1257 | S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); | |
a3c1945a | 1258 | u32 tmp; |
771fe6b9 | 1259 | |
1a029b76 JG |
1260 | dev_info(rdev->dev, "GPU softreset \n"); |
1261 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", | |
1262 | RREG32(R_008010_GRBM_STATUS)); | |
1263 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
a3c1945a | 1264 | RREG32(R_008014_GRBM_STATUS2)); |
1a029b76 JG |
1265 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
1266 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a JG |
1267 | rv515_mc_stop(rdev, &save); |
1268 | if (r600_mc_wait_for_idle(rdev)) { | |
1269 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1270 | } | |
3ce0a23d | 1271 | /* Disable CP parsing/prefetching */ |
90aca4d2 | 1272 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
3ce0a23d JG |
1273 | /* Check if any of the rendering block is busy and reset it */ |
1274 | if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || | |
1275 | (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { | |
a3c1945a | 1276 | tmp = S_008020_SOFT_RESET_CR(1) | |
3ce0a23d JG |
1277 | S_008020_SOFT_RESET_DB(1) | |
1278 | S_008020_SOFT_RESET_CB(1) | | |
1279 | S_008020_SOFT_RESET_PA(1) | | |
1280 | S_008020_SOFT_RESET_SC(1) | | |
1281 | S_008020_SOFT_RESET_SMX(1) | | |
1282 | S_008020_SOFT_RESET_SPI(1) | | |
1283 | S_008020_SOFT_RESET_SX(1) | | |
1284 | S_008020_SOFT_RESET_SH(1) | | |
1285 | S_008020_SOFT_RESET_TC(1) | | |
1286 | S_008020_SOFT_RESET_TA(1) | | |
1287 | S_008020_SOFT_RESET_VC(1) | | |
a3c1945a | 1288 | S_008020_SOFT_RESET_VGT(1); |
1a029b76 | 1289 | dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
a3c1945a | 1290 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
90aca4d2 JG |
1291 | RREG32(R_008020_GRBM_SOFT_RESET); |
1292 | mdelay(15); | |
3ce0a23d | 1293 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
3ce0a23d JG |
1294 | } |
1295 | /* Reset CP (we always reset CP) */ | |
a3c1945a JG |
1296 | tmp = S_008020_SOFT_RESET_CP(1); |
1297 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); | |
1298 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
90aca4d2 JG |
1299 | RREG32(R_008020_GRBM_SOFT_RESET); |
1300 | mdelay(15); | |
3ce0a23d | 1301 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
3ce0a23d | 1302 | /* Wait a little for things to settle down */ |
225758d8 | 1303 | mdelay(1); |
1a029b76 JG |
1304 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
1305 | RREG32(R_008010_GRBM_STATUS)); | |
1306 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
1307 | RREG32(R_008014_GRBM_STATUS2)); | |
1308 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", | |
1309 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a | 1310 | rv515_mc_resume(rdev, &save); |
3ce0a23d JG |
1311 | return 0; |
1312 | } | |
1313 | ||
225758d8 JG |
1314 | bool r600_gpu_is_lockup(struct radeon_device *rdev) |
1315 | { | |
1316 | u32 srbm_status; | |
1317 | u32 grbm_status; | |
1318 | u32 grbm_status2; | |
1319 | int r; | |
1320 | ||
1321 | srbm_status = RREG32(R_000E50_SRBM_STATUS); | |
1322 | grbm_status = RREG32(R_008010_GRBM_STATUS); | |
1323 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); | |
1324 | if (!G_008010_GUI_ACTIVE(grbm_status)) { | |
1325 | r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); | |
1326 | return false; | |
1327 | } | |
1328 | /* force CP activities */ | |
1329 | r = radeon_ring_lock(rdev, 2); | |
1330 | if (!r) { | |
1331 | /* PACKET2 NOP */ | |
1332 | radeon_ring_write(rdev, 0x80000000); | |
1333 | radeon_ring_write(rdev, 0x80000000); | |
1334 | radeon_ring_unlock_commit(rdev); | |
1335 | } | |
1336 | rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); | |
1337 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); | |
1338 | } | |
1339 | ||
a2d07b74 | 1340 | int r600_asic_reset(struct radeon_device *rdev) |
3ce0a23d JG |
1341 | { |
1342 | return r600_gpu_soft_reset(rdev); | |
1343 | } | |
1344 | ||
1345 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
1346 | u32 num_backends, | |
1347 | u32 backend_disable_mask) | |
1348 | { | |
1349 | u32 backend_map = 0; | |
1350 | u32 enabled_backends_mask; | |
1351 | u32 enabled_backends_count; | |
1352 | u32 cur_pipe; | |
1353 | u32 swizzle_pipe[R6XX_MAX_PIPES]; | |
1354 | u32 cur_backend; | |
1355 | u32 i; | |
1356 | ||
1357 | if (num_tile_pipes > R6XX_MAX_PIPES) | |
1358 | num_tile_pipes = R6XX_MAX_PIPES; | |
1359 | if (num_tile_pipes < 1) | |
1360 | num_tile_pipes = 1; | |
1361 | if (num_backends > R6XX_MAX_BACKENDS) | |
1362 | num_backends = R6XX_MAX_BACKENDS; | |
1363 | if (num_backends < 1) | |
1364 | num_backends = 1; | |
1365 | ||
1366 | enabled_backends_mask = 0; | |
1367 | enabled_backends_count = 0; | |
1368 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { | |
1369 | if (((backend_disable_mask >> i) & 1) == 0) { | |
1370 | enabled_backends_mask |= (1 << i); | |
1371 | ++enabled_backends_count; | |
1372 | } | |
1373 | if (enabled_backends_count == num_backends) | |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | if (enabled_backends_count == 0) { | |
1378 | enabled_backends_mask = 1; | |
1379 | enabled_backends_count = 1; | |
1380 | } | |
1381 | ||
1382 | if (enabled_backends_count != num_backends) | |
1383 | num_backends = enabled_backends_count; | |
1384 | ||
1385 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); | |
1386 | switch (num_tile_pipes) { | |
1387 | case 1: | |
1388 | swizzle_pipe[0] = 0; | |
1389 | break; | |
1390 | case 2: | |
1391 | swizzle_pipe[0] = 0; | |
1392 | swizzle_pipe[1] = 1; | |
1393 | break; | |
1394 | case 3: | |
1395 | swizzle_pipe[0] = 0; | |
1396 | swizzle_pipe[1] = 1; | |
1397 | swizzle_pipe[2] = 2; | |
1398 | break; | |
1399 | case 4: | |
1400 | swizzle_pipe[0] = 0; | |
1401 | swizzle_pipe[1] = 1; | |
1402 | swizzle_pipe[2] = 2; | |
1403 | swizzle_pipe[3] = 3; | |
1404 | break; | |
1405 | case 5: | |
1406 | swizzle_pipe[0] = 0; | |
1407 | swizzle_pipe[1] = 1; | |
1408 | swizzle_pipe[2] = 2; | |
1409 | swizzle_pipe[3] = 3; | |
1410 | swizzle_pipe[4] = 4; | |
1411 | break; | |
1412 | case 6: | |
1413 | swizzle_pipe[0] = 0; | |
1414 | swizzle_pipe[1] = 2; | |
1415 | swizzle_pipe[2] = 4; | |
1416 | swizzle_pipe[3] = 5; | |
1417 | swizzle_pipe[4] = 1; | |
1418 | swizzle_pipe[5] = 3; | |
1419 | break; | |
1420 | case 7: | |
1421 | swizzle_pipe[0] = 0; | |
1422 | swizzle_pipe[1] = 2; | |
1423 | swizzle_pipe[2] = 4; | |
1424 | swizzle_pipe[3] = 6; | |
1425 | swizzle_pipe[4] = 1; | |
1426 | swizzle_pipe[5] = 3; | |
1427 | swizzle_pipe[6] = 5; | |
1428 | break; | |
1429 | case 8: | |
1430 | swizzle_pipe[0] = 0; | |
1431 | swizzle_pipe[1] = 2; | |
1432 | swizzle_pipe[2] = 4; | |
1433 | swizzle_pipe[3] = 6; | |
1434 | swizzle_pipe[4] = 1; | |
1435 | swizzle_pipe[5] = 3; | |
1436 | swizzle_pipe[6] = 5; | |
1437 | swizzle_pipe[7] = 7; | |
1438 | break; | |
1439 | } | |
1440 | ||
1441 | cur_backend = 0; | |
1442 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
1443 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
1444 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
1445 | ||
1446 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
1447 | ||
1448 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
1449 | } | |
1450 | ||
1451 | return backend_map; | |
1452 | } | |
1453 | ||
1454 | int r600_count_pipe_bits(uint32_t val) | |
1455 | { | |
1456 | int i, ret = 0; | |
1457 | ||
1458 | for (i = 0; i < 32; i++) { | |
1459 | ret += val & 1; | |
1460 | val >>= 1; | |
1461 | } | |
1462 | return ret; | |
771fe6b9 JG |
1463 | } |
1464 | ||
3ce0a23d JG |
1465 | void r600_gpu_init(struct radeon_device *rdev) |
1466 | { | |
1467 | u32 tiling_config; | |
1468 | u32 ramcfg; | |
d03f5d59 AD |
1469 | u32 backend_map; |
1470 | u32 cc_rb_backend_disable; | |
1471 | u32 cc_gc_shader_pipe_config; | |
3ce0a23d JG |
1472 | u32 tmp; |
1473 | int i, j; | |
1474 | u32 sq_config; | |
1475 | u32 sq_gpr_resource_mgmt_1 = 0; | |
1476 | u32 sq_gpr_resource_mgmt_2 = 0; | |
1477 | u32 sq_thread_resource_mgmt = 0; | |
1478 | u32 sq_stack_resource_mgmt_1 = 0; | |
1479 | u32 sq_stack_resource_mgmt_2 = 0; | |
1480 | ||
1481 | /* FIXME: implement */ | |
1482 | switch (rdev->family) { | |
1483 | case CHIP_R600: | |
1484 | rdev->config.r600.max_pipes = 4; | |
1485 | rdev->config.r600.max_tile_pipes = 8; | |
1486 | rdev->config.r600.max_simds = 4; | |
1487 | rdev->config.r600.max_backends = 4; | |
1488 | rdev->config.r600.max_gprs = 256; | |
1489 | rdev->config.r600.max_threads = 192; | |
1490 | rdev->config.r600.max_stack_entries = 256; | |
1491 | rdev->config.r600.max_hw_contexts = 8; | |
1492 | rdev->config.r600.max_gs_threads = 16; | |
1493 | rdev->config.r600.sx_max_export_size = 128; | |
1494 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1495 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1496 | rdev->config.r600.sq_num_cf_insts = 2; | |
1497 | break; | |
1498 | case CHIP_RV630: | |
1499 | case CHIP_RV635: | |
1500 | rdev->config.r600.max_pipes = 2; | |
1501 | rdev->config.r600.max_tile_pipes = 2; | |
1502 | rdev->config.r600.max_simds = 3; | |
1503 | rdev->config.r600.max_backends = 1; | |
1504 | rdev->config.r600.max_gprs = 128; | |
1505 | rdev->config.r600.max_threads = 192; | |
1506 | rdev->config.r600.max_stack_entries = 128; | |
1507 | rdev->config.r600.max_hw_contexts = 8; | |
1508 | rdev->config.r600.max_gs_threads = 4; | |
1509 | rdev->config.r600.sx_max_export_size = 128; | |
1510 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1511 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1512 | rdev->config.r600.sq_num_cf_insts = 2; | |
1513 | break; | |
1514 | case CHIP_RV610: | |
1515 | case CHIP_RV620: | |
1516 | case CHIP_RS780: | |
1517 | case CHIP_RS880: | |
1518 | rdev->config.r600.max_pipes = 1; | |
1519 | rdev->config.r600.max_tile_pipes = 1; | |
1520 | rdev->config.r600.max_simds = 2; | |
1521 | rdev->config.r600.max_backends = 1; | |
1522 | rdev->config.r600.max_gprs = 128; | |
1523 | rdev->config.r600.max_threads = 192; | |
1524 | rdev->config.r600.max_stack_entries = 128; | |
1525 | rdev->config.r600.max_hw_contexts = 4; | |
1526 | rdev->config.r600.max_gs_threads = 4; | |
1527 | rdev->config.r600.sx_max_export_size = 128; | |
1528 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1529 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1530 | rdev->config.r600.sq_num_cf_insts = 1; | |
1531 | break; | |
1532 | case CHIP_RV670: | |
1533 | rdev->config.r600.max_pipes = 4; | |
1534 | rdev->config.r600.max_tile_pipes = 4; | |
1535 | rdev->config.r600.max_simds = 4; | |
1536 | rdev->config.r600.max_backends = 4; | |
1537 | rdev->config.r600.max_gprs = 192; | |
1538 | rdev->config.r600.max_threads = 192; | |
1539 | rdev->config.r600.max_stack_entries = 256; | |
1540 | rdev->config.r600.max_hw_contexts = 8; | |
1541 | rdev->config.r600.max_gs_threads = 16; | |
1542 | rdev->config.r600.sx_max_export_size = 128; | |
1543 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1544 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1545 | rdev->config.r600.sq_num_cf_insts = 2; | |
1546 | break; | |
1547 | default: | |
1548 | break; | |
1549 | } | |
1550 | ||
1551 | /* Initialize HDP */ | |
1552 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1553 | WREG32((0x2c14 + j), 0x00000000); | |
1554 | WREG32((0x2c18 + j), 0x00000000); | |
1555 | WREG32((0x2c1c + j), 0x00000000); | |
1556 | WREG32((0x2c20 + j), 0x00000000); | |
1557 | WREG32((0x2c24 + j), 0x00000000); | |
1558 | } | |
1559 | ||
1560 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1561 | ||
1562 | /* Setup tiling */ | |
1563 | tiling_config = 0; | |
1564 | ramcfg = RREG32(RAMCFG); | |
1565 | switch (rdev->config.r600.max_tile_pipes) { | |
1566 | case 1: | |
1567 | tiling_config |= PIPE_TILING(0); | |
1568 | break; | |
1569 | case 2: | |
1570 | tiling_config |= PIPE_TILING(1); | |
1571 | break; | |
1572 | case 4: | |
1573 | tiling_config |= PIPE_TILING(2); | |
1574 | break; | |
1575 | case 8: | |
1576 | tiling_config |= PIPE_TILING(3); | |
1577 | break; | |
1578 | default: | |
1579 | break; | |
1580 | } | |
d03f5d59 | 1581 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
961fb597 | 1582 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
3ce0a23d JG |
1583 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1584 | tiling_config |= GROUP_SIZE(0); | |
961fb597 | 1585 | rdev->config.r600.tiling_group_size = 256; |
3ce0a23d JG |
1586 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
1587 | if (tmp > 3) { | |
1588 | tiling_config |= ROW_TILING(3); | |
1589 | tiling_config |= SAMPLE_SPLIT(3); | |
1590 | } else { | |
1591 | tiling_config |= ROW_TILING(tmp); | |
1592 | tiling_config |= SAMPLE_SPLIT(tmp); | |
1593 | } | |
1594 | tiling_config |= BANK_SWAPS(1); | |
d03f5d59 AD |
1595 | |
1596 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; | |
1597 | cc_rb_backend_disable |= | |
1598 | BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); | |
1599 | ||
1600 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; | |
1601 | cc_gc_shader_pipe_config |= | |
1602 | INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); | |
1603 | cc_gc_shader_pipe_config |= | |
1604 | INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); | |
1605 | ||
1606 | backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, | |
1607 | (R6XX_MAX_BACKENDS - | |
1608 | r600_count_pipe_bits((cc_rb_backend_disable & | |
1609 | R6XX_MAX_BACKENDS_MASK) >> 16)), | |
1610 | (cc_rb_backend_disable >> 16)); | |
1611 | ||
1612 | tiling_config |= BACKEND_MAP(backend_map); | |
3ce0a23d JG |
1613 | WREG32(GB_TILING_CONFIG, tiling_config); |
1614 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); | |
1615 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); | |
1616 | ||
3ce0a23d | 1617 | /* Setup pipes */ |
d03f5d59 AD |
1618 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
1619 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
f867c60d | 1620 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
3ce0a23d | 1621 | |
d03f5d59 | 1622 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
3ce0a23d JG |
1623 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
1624 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
1625 | ||
1626 | /* Setup some CP states */ | |
1627 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); | |
1628 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); | |
1629 | ||
1630 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | | |
1631 | SYNC_WALKER | SYNC_ALIGNER)); | |
1632 | /* Setup various GPU states */ | |
1633 | if (rdev->family == CHIP_RV670) | |
1634 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); | |
1635 | ||
1636 | tmp = RREG32(SX_DEBUG_1); | |
1637 | tmp |= SMX_EVENT_RELEASE; | |
1638 | if ((rdev->family > CHIP_R600)) | |
1639 | tmp |= ENABLE_NEW_SMX_ADDRESS; | |
1640 | WREG32(SX_DEBUG_1, tmp); | |
1641 | ||
1642 | if (((rdev->family) == CHIP_R600) || | |
1643 | ((rdev->family) == CHIP_RV630) || | |
1644 | ((rdev->family) == CHIP_RV610) || | |
1645 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1646 | ((rdev->family) == CHIP_RS780) || |
1647 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1648 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
1649 | } else { | |
1650 | WREG32(DB_DEBUG, 0); | |
1651 | } | |
1652 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | | |
1653 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); | |
1654 | ||
1655 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1656 | WREG32(VGT_NUM_INSTANCES, 0); | |
1657 | ||
1658 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); | |
1659 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); | |
1660 | ||
1661 | tmp = RREG32(SQ_MS_FIFO_SIZES); | |
1662 | if (((rdev->family) == CHIP_RV610) || | |
1663 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1664 | ((rdev->family) == CHIP_RS780) || |
1665 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1666 | tmp = (CACHE_FIFO_SIZE(0xa) | |
1667 | FETCH_FIFO_HIWATER(0xa) | | |
1668 | DONE_FIFO_HIWATER(0xe0) | | |
1669 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
1670 | } else if (((rdev->family) == CHIP_R600) || | |
1671 | ((rdev->family) == CHIP_RV630)) { | |
1672 | tmp &= ~DONE_FIFO_HIWATER(0xff); | |
1673 | tmp |= DONE_FIFO_HIWATER(0x4); | |
1674 | } | |
1675 | WREG32(SQ_MS_FIFO_SIZES, tmp); | |
1676 | ||
1677 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
1678 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
1679 | */ | |
1680 | sq_config = RREG32(SQ_CONFIG); | |
1681 | sq_config &= ~(PS_PRIO(3) | | |
1682 | VS_PRIO(3) | | |
1683 | GS_PRIO(3) | | |
1684 | ES_PRIO(3)); | |
1685 | sq_config |= (DX9_CONSTS | | |
1686 | VC_ENABLE | | |
1687 | PS_PRIO(0) | | |
1688 | VS_PRIO(1) | | |
1689 | GS_PRIO(2) | | |
1690 | ES_PRIO(3)); | |
1691 | ||
1692 | if ((rdev->family) == CHIP_R600) { | |
1693 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | | |
1694 | NUM_VS_GPRS(124) | | |
1695 | NUM_CLAUSE_TEMP_GPRS(4)); | |
1696 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | | |
1697 | NUM_ES_GPRS(0)); | |
1698 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | | |
1699 | NUM_VS_THREADS(48) | | |
1700 | NUM_GS_THREADS(4) | | |
1701 | NUM_ES_THREADS(4)); | |
1702 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | | |
1703 | NUM_VS_STACK_ENTRIES(128)); | |
1704 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | | |
1705 | NUM_ES_STACK_ENTRIES(0)); | |
1706 | } else if (((rdev->family) == CHIP_RV610) || | |
1707 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1708 | ((rdev->family) == CHIP_RS780) || |
1709 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1710 | /* no vertex cache */ |
1711 | sq_config &= ~VC_ENABLE; | |
1712 | ||
1713 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1714 | NUM_VS_GPRS(44) | | |
1715 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1716 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1717 | NUM_ES_GPRS(17)); | |
1718 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1719 | NUM_VS_THREADS(78) | | |
1720 | NUM_GS_THREADS(4) | | |
1721 | NUM_ES_THREADS(31)); | |
1722 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1723 | NUM_VS_STACK_ENTRIES(40)); | |
1724 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1725 | NUM_ES_STACK_ENTRIES(16)); | |
1726 | } else if (((rdev->family) == CHIP_RV630) || | |
1727 | ((rdev->family) == CHIP_RV635)) { | |
1728 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1729 | NUM_VS_GPRS(44) | | |
1730 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1731 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | | |
1732 | NUM_ES_GPRS(18)); | |
1733 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1734 | NUM_VS_THREADS(78) | | |
1735 | NUM_GS_THREADS(4) | | |
1736 | NUM_ES_THREADS(31)); | |
1737 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1738 | NUM_VS_STACK_ENTRIES(40)); | |
1739 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1740 | NUM_ES_STACK_ENTRIES(16)); | |
1741 | } else if ((rdev->family) == CHIP_RV670) { | |
1742 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1743 | NUM_VS_GPRS(44) | | |
1744 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1745 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1746 | NUM_ES_GPRS(17)); | |
1747 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1748 | NUM_VS_THREADS(78) | | |
1749 | NUM_GS_THREADS(4) | | |
1750 | NUM_ES_THREADS(31)); | |
1751 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | | |
1752 | NUM_VS_STACK_ENTRIES(64)); | |
1753 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | | |
1754 | NUM_ES_STACK_ENTRIES(64)); | |
1755 | } | |
1756 | ||
1757 | WREG32(SQ_CONFIG, sq_config); | |
1758 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1759 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1760 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1761 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1762 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1763 | ||
1764 | if (((rdev->family) == CHIP_RV610) || | |
1765 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1766 | ((rdev->family) == CHIP_RS780) || |
1767 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1768 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
1769 | } else { | |
1770 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); | |
1771 | } | |
1772 | ||
1773 | /* More default values. 2D/3D driver should adjust as needed */ | |
1774 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | | |
1775 | S1_X(0x4) | S1_Y(0xc))); | |
1776 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | | |
1777 | S1_X(0x2) | S1_Y(0x2) | | |
1778 | S2_X(0xa) | S2_Y(0x6) | | |
1779 | S3_X(0x6) | S3_Y(0xa))); | |
1780 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | | |
1781 | S1_X(0x4) | S1_Y(0xc) | | |
1782 | S2_X(0x1) | S2_Y(0x6) | | |
1783 | S3_X(0xa) | S3_Y(0xe))); | |
1784 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | | |
1785 | S5_X(0x0) | S5_Y(0x0) | | |
1786 | S6_X(0xb) | S6_Y(0x4) | | |
1787 | S7_X(0x7) | S7_Y(0x8))); | |
1788 | ||
1789 | WREG32(VGT_STRMOUT_EN, 0); | |
1790 | tmp = rdev->config.r600.max_pipes * 16; | |
1791 | switch (rdev->family) { | |
1792 | case CHIP_RV610: | |
3ce0a23d | 1793 | case CHIP_RV620: |
ee59f2b4 AD |
1794 | case CHIP_RS780: |
1795 | case CHIP_RS880: | |
3ce0a23d JG |
1796 | tmp += 32; |
1797 | break; | |
1798 | case CHIP_RV670: | |
1799 | tmp += 128; | |
1800 | break; | |
1801 | default: | |
1802 | break; | |
1803 | } | |
1804 | if (tmp > 256) { | |
1805 | tmp = 256; | |
1806 | } | |
1807 | WREG32(VGT_ES_PER_GS, 128); | |
1808 | WREG32(VGT_GS_PER_ES, tmp); | |
1809 | WREG32(VGT_GS_PER_VS, 2); | |
1810 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
1811 | ||
1812 | /* more default values. 2D/3D driver should adjust as needed */ | |
1813 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
1814 | WREG32(VGT_STRMOUT_EN, 0); | |
1815 | WREG32(SX_MISC, 0); | |
1816 | WREG32(PA_SC_MODE_CNTL, 0); | |
1817 | WREG32(PA_SC_AA_CONFIG, 0); | |
1818 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
1819 | WREG32(SPI_INPUT_Z, 0); | |
1820 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
1821 | WREG32(CB_COLOR7_FRAG, 0); | |
1822 | ||
1823 | /* Clear render buffer base addresses */ | |
1824 | WREG32(CB_COLOR0_BASE, 0); | |
1825 | WREG32(CB_COLOR1_BASE, 0); | |
1826 | WREG32(CB_COLOR2_BASE, 0); | |
1827 | WREG32(CB_COLOR3_BASE, 0); | |
1828 | WREG32(CB_COLOR4_BASE, 0); | |
1829 | WREG32(CB_COLOR5_BASE, 0); | |
1830 | WREG32(CB_COLOR6_BASE, 0); | |
1831 | WREG32(CB_COLOR7_BASE, 0); | |
1832 | WREG32(CB_COLOR7_FRAG, 0); | |
1833 | ||
1834 | switch (rdev->family) { | |
1835 | case CHIP_RV610: | |
3ce0a23d | 1836 | case CHIP_RV620: |
ee59f2b4 AD |
1837 | case CHIP_RS780: |
1838 | case CHIP_RS880: | |
3ce0a23d JG |
1839 | tmp = TC_L2_SIZE(8); |
1840 | break; | |
1841 | case CHIP_RV630: | |
1842 | case CHIP_RV635: | |
1843 | tmp = TC_L2_SIZE(4); | |
1844 | break; | |
1845 | case CHIP_R600: | |
1846 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; | |
1847 | break; | |
1848 | default: | |
1849 | tmp = TC_L2_SIZE(0); | |
1850 | break; | |
1851 | } | |
1852 | WREG32(TC_CNTL, tmp); | |
1853 | ||
1854 | tmp = RREG32(HDP_HOST_PATH_CNTL); | |
1855 | WREG32(HDP_HOST_PATH_CNTL, tmp); | |
1856 | ||
1857 | tmp = RREG32(ARB_POP); | |
1858 | tmp |= ENABLE_TC128; | |
1859 | WREG32(ARB_POP, tmp); | |
1860 | ||
1861 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1862 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
1863 | NUM_CLIP_SEQ(3))); | |
1864 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); | |
1865 | } | |
1866 | ||
1867 | ||
771fe6b9 JG |
1868 | /* |
1869 | * Indirect registers accessor | |
1870 | */ | |
3ce0a23d JG |
1871 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
1872 | { | |
1873 | u32 r; | |
1874 | ||
1875 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1876 | (void)RREG32(PCIE_PORT_INDEX); | |
1877 | r = RREG32(PCIE_PORT_DATA); | |
1878 | return r; | |
1879 | } | |
1880 | ||
1881 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1882 | { | |
1883 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1884 | (void)RREG32(PCIE_PORT_INDEX); | |
1885 | WREG32(PCIE_PORT_DATA, (v)); | |
1886 | (void)RREG32(PCIE_PORT_DATA); | |
1887 | } | |
1888 | ||
3ce0a23d JG |
1889 | /* |
1890 | * CP & Ring | |
1891 | */ | |
1892 | void r600_cp_stop(struct radeon_device *rdev) | |
1893 | { | |
1894 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1895 | } | |
1896 | ||
d8f60cfc | 1897 | int r600_init_microcode(struct radeon_device *rdev) |
3ce0a23d JG |
1898 | { |
1899 | struct platform_device *pdev; | |
1900 | const char *chip_name; | |
d8f60cfc AD |
1901 | const char *rlc_chip_name; |
1902 | size_t pfp_req_size, me_req_size, rlc_req_size; | |
3ce0a23d JG |
1903 | char fw_name[30]; |
1904 | int err; | |
1905 | ||
1906 | DRM_DEBUG("\n"); | |
1907 | ||
1908 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); | |
1909 | err = IS_ERR(pdev); | |
1910 | if (err) { | |
1911 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
1912 | return -EINVAL; | |
1913 | } | |
1914 | ||
1915 | switch (rdev->family) { | |
d8f60cfc AD |
1916 | case CHIP_R600: |
1917 | chip_name = "R600"; | |
1918 | rlc_chip_name = "R600"; | |
1919 | break; | |
1920 | case CHIP_RV610: | |
1921 | chip_name = "RV610"; | |
1922 | rlc_chip_name = "R600"; | |
1923 | break; | |
1924 | case CHIP_RV630: | |
1925 | chip_name = "RV630"; | |
1926 | rlc_chip_name = "R600"; | |
1927 | break; | |
1928 | case CHIP_RV620: | |
1929 | chip_name = "RV620"; | |
1930 | rlc_chip_name = "R600"; | |
1931 | break; | |
1932 | case CHIP_RV635: | |
1933 | chip_name = "RV635"; | |
1934 | rlc_chip_name = "R600"; | |
1935 | break; | |
1936 | case CHIP_RV670: | |
1937 | chip_name = "RV670"; | |
1938 | rlc_chip_name = "R600"; | |
1939 | break; | |
3ce0a23d | 1940 | case CHIP_RS780: |
d8f60cfc AD |
1941 | case CHIP_RS880: |
1942 | chip_name = "RS780"; | |
1943 | rlc_chip_name = "R600"; | |
1944 | break; | |
1945 | case CHIP_RV770: | |
1946 | chip_name = "RV770"; | |
1947 | rlc_chip_name = "R700"; | |
1948 | break; | |
3ce0a23d | 1949 | case CHIP_RV730: |
d8f60cfc AD |
1950 | case CHIP_RV740: |
1951 | chip_name = "RV730"; | |
1952 | rlc_chip_name = "R700"; | |
1953 | break; | |
1954 | case CHIP_RV710: | |
1955 | chip_name = "RV710"; | |
1956 | rlc_chip_name = "R700"; | |
1957 | break; | |
fe251e2f AD |
1958 | case CHIP_CEDAR: |
1959 | chip_name = "CEDAR"; | |
45f9a39b | 1960 | rlc_chip_name = "CEDAR"; |
fe251e2f AD |
1961 | break; |
1962 | case CHIP_REDWOOD: | |
1963 | chip_name = "REDWOOD"; | |
45f9a39b | 1964 | rlc_chip_name = "REDWOOD"; |
fe251e2f AD |
1965 | break; |
1966 | case CHIP_JUNIPER: | |
1967 | chip_name = "JUNIPER"; | |
45f9a39b | 1968 | rlc_chip_name = "JUNIPER"; |
fe251e2f AD |
1969 | break; |
1970 | case CHIP_CYPRESS: | |
1971 | case CHIP_HEMLOCK: | |
1972 | chip_name = "CYPRESS"; | |
45f9a39b | 1973 | rlc_chip_name = "CYPRESS"; |
fe251e2f | 1974 | break; |
3ce0a23d JG |
1975 | default: BUG(); |
1976 | } | |
1977 | ||
fe251e2f AD |
1978 | if (rdev->family >= CHIP_CEDAR) { |
1979 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; | |
1980 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; | |
45f9a39b | 1981 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
fe251e2f | 1982 | } else if (rdev->family >= CHIP_RV770) { |
3ce0a23d JG |
1983 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
1984 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
d8f60cfc | 1985 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1986 | } else { |
1987 | pfp_req_size = PFP_UCODE_SIZE * 4; | |
1988 | me_req_size = PM4_UCODE_SIZE * 12; | |
d8f60cfc | 1989 | rlc_req_size = RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1990 | } |
1991 | ||
d8f60cfc | 1992 | DRM_INFO("Loading %s Microcode\n", chip_name); |
3ce0a23d JG |
1993 | |
1994 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
1995 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); | |
1996 | if (err) | |
1997 | goto out; | |
1998 | if (rdev->pfp_fw->size != pfp_req_size) { | |
1999 | printk(KERN_ERR | |
2000 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2001 | rdev->pfp_fw->size, fw_name); | |
2002 | err = -EINVAL; | |
2003 | goto out; | |
2004 | } | |
2005 | ||
2006 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
2007 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); | |
2008 | if (err) | |
2009 | goto out; | |
2010 | if (rdev->me_fw->size != me_req_size) { | |
2011 | printk(KERN_ERR | |
2012 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2013 | rdev->me_fw->size, fw_name); | |
2014 | err = -EINVAL; | |
2015 | } | |
d8f60cfc AD |
2016 | |
2017 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
2018 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); | |
2019 | if (err) | |
2020 | goto out; | |
2021 | if (rdev->rlc_fw->size != rlc_req_size) { | |
2022 | printk(KERN_ERR | |
2023 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", | |
2024 | rdev->rlc_fw->size, fw_name); | |
2025 | err = -EINVAL; | |
2026 | } | |
2027 | ||
3ce0a23d JG |
2028 | out: |
2029 | platform_device_unregister(pdev); | |
2030 | ||
2031 | if (err) { | |
2032 | if (err != -EINVAL) | |
2033 | printk(KERN_ERR | |
2034 | "r600_cp: Failed to load firmware \"%s\"\n", | |
2035 | fw_name); | |
2036 | release_firmware(rdev->pfp_fw); | |
2037 | rdev->pfp_fw = NULL; | |
2038 | release_firmware(rdev->me_fw); | |
2039 | rdev->me_fw = NULL; | |
d8f60cfc AD |
2040 | release_firmware(rdev->rlc_fw); |
2041 | rdev->rlc_fw = NULL; | |
3ce0a23d JG |
2042 | } |
2043 | return err; | |
2044 | } | |
2045 | ||
2046 | static int r600_cp_load_microcode(struct radeon_device *rdev) | |
2047 | { | |
2048 | const __be32 *fw_data; | |
2049 | int i; | |
2050 | ||
2051 | if (!rdev->me_fw || !rdev->pfp_fw) | |
2052 | return -EINVAL; | |
2053 | ||
2054 | r600_cp_stop(rdev); | |
2055 | ||
2056 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
2057 | ||
2058 | /* Reset cp */ | |
2059 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2060 | RREG32(GRBM_SOFT_RESET); | |
2061 | mdelay(15); | |
2062 | WREG32(GRBM_SOFT_RESET, 0); | |
2063 | ||
2064 | WREG32(CP_ME_RAM_WADDR, 0); | |
2065 | ||
2066 | fw_data = (const __be32 *)rdev->me_fw->data; | |
2067 | WREG32(CP_ME_RAM_WADDR, 0); | |
2068 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) | |
2069 | WREG32(CP_ME_RAM_DATA, | |
2070 | be32_to_cpup(fw_data++)); | |
2071 | ||
2072 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
2073 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
2074 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
2075 | WREG32(CP_PFP_UCODE_DATA, | |
2076 | be32_to_cpup(fw_data++)); | |
2077 | ||
2078 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
2079 | WREG32(CP_ME_RAM_WADDR, 0); | |
2080 | WREG32(CP_ME_RAM_RADDR, 0); | |
2081 | return 0; | |
2082 | } | |
2083 | ||
2084 | int r600_cp_start(struct radeon_device *rdev) | |
2085 | { | |
2086 | int r; | |
2087 | uint32_t cp_me; | |
2088 | ||
2089 | r = radeon_ring_lock(rdev, 7); | |
2090 | if (r) { | |
2091 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
2092 | return r; | |
2093 | } | |
2094 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | |
2095 | radeon_ring_write(rdev, 0x1); | |
fe251e2f AD |
2096 | if (rdev->family >= CHIP_CEDAR) { |
2097 | radeon_ring_write(rdev, 0x0); | |
2098 | radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); | |
2099 | } else if (rdev->family >= CHIP_RV770) { | |
3ce0a23d JG |
2100 | radeon_ring_write(rdev, 0x0); |
2101 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); | |
fe251e2f AD |
2102 | } else { |
2103 | radeon_ring_write(rdev, 0x3); | |
2104 | radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); | |
3ce0a23d JG |
2105 | } |
2106 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
2107 | radeon_ring_write(rdev, 0); | |
2108 | radeon_ring_write(rdev, 0); | |
2109 | radeon_ring_unlock_commit(rdev); | |
2110 | ||
2111 | cp_me = 0xff; | |
2112 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | |
2113 | return 0; | |
2114 | } | |
2115 | ||
2116 | int r600_cp_resume(struct radeon_device *rdev) | |
2117 | { | |
2118 | u32 tmp; | |
2119 | u32 rb_bufsz; | |
2120 | int r; | |
2121 | ||
2122 | /* Reset cp */ | |
2123 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2124 | RREG32(GRBM_SOFT_RESET); | |
2125 | mdelay(15); | |
2126 | WREG32(GRBM_SOFT_RESET, 0); | |
2127 | ||
2128 | /* Set ring buffer size */ | |
2129 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); | |
d6f28938 | 2130 | tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3ce0a23d | 2131 | #ifdef __BIG_ENDIAN |
d6f28938 | 2132 | tmp |= BUF_SWAP_32BIT; |
3ce0a23d | 2133 | #endif |
d6f28938 | 2134 | WREG32(CP_RB_CNTL, tmp); |
3ce0a23d JG |
2135 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
2136 | ||
2137 | /* Set the write pointer delay */ | |
2138 | WREG32(CP_RB_WPTR_DELAY, 0); | |
2139 | ||
2140 | /* Initialize the ring buffer's read and write pointers */ | |
3ce0a23d JG |
2141 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
2142 | WREG32(CP_RB_RPTR_WR, 0); | |
2143 | WREG32(CP_RB_WPTR, 0); | |
2144 | WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); | |
2145 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); | |
2146 | mdelay(1); | |
2147 | WREG32(CP_RB_CNTL, tmp); | |
2148 | ||
2149 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); | |
2150 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | |
2151 | ||
2152 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | |
2153 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | |
2154 | ||
2155 | r600_cp_start(rdev); | |
2156 | rdev->cp.ready = true; | |
2157 | r = radeon_ring_test(rdev); | |
2158 | if (r) { | |
2159 | rdev->cp.ready = false; | |
2160 | return r; | |
2161 | } | |
2162 | return 0; | |
2163 | } | |
2164 | ||
2165 | void r600_cp_commit(struct radeon_device *rdev) | |
2166 | { | |
2167 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | |
2168 | (void)RREG32(CP_RB_WPTR); | |
2169 | } | |
2170 | ||
2171 | void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
2172 | { | |
2173 | u32 rb_bufsz; | |
2174 | ||
2175 | /* Align ring size */ | |
2176 | rb_bufsz = drm_order(ring_size / 8); | |
2177 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
2178 | rdev->cp.ring_size = ring_size; | |
2179 | rdev->cp.align_mask = 16 - 1; | |
2180 | } | |
2181 | ||
655efd3d JG |
2182 | void r600_cp_fini(struct radeon_device *rdev) |
2183 | { | |
2184 | r600_cp_stop(rdev); | |
2185 | radeon_ring_fini(rdev); | |
2186 | } | |
2187 | ||
3ce0a23d JG |
2188 | |
2189 | /* | |
2190 | * GPU scratch registers helpers function. | |
2191 | */ | |
2192 | void r600_scratch_init(struct radeon_device *rdev) | |
2193 | { | |
2194 | int i; | |
2195 | ||
2196 | rdev->scratch.num_reg = 7; | |
2197 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
2198 | rdev->scratch.free[i] = true; | |
2199 | rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); | |
2200 | } | |
2201 | } | |
2202 | ||
2203 | int r600_ring_test(struct radeon_device *rdev) | |
2204 | { | |
2205 | uint32_t scratch; | |
2206 | uint32_t tmp = 0; | |
2207 | unsigned i; | |
2208 | int r; | |
2209 | ||
2210 | r = radeon_scratch_get(rdev, &scratch); | |
2211 | if (r) { | |
2212 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
2213 | return r; | |
2214 | } | |
2215 | WREG32(scratch, 0xCAFEDEAD); | |
2216 | r = radeon_ring_lock(rdev, 3); | |
2217 | if (r) { | |
2218 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
2219 | radeon_scratch_free(rdev, scratch); | |
2220 | return r; | |
2221 | } | |
2222 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
2223 | radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2224 | radeon_ring_write(rdev, 0xDEADBEEF); | |
2225 | radeon_ring_unlock_commit(rdev); | |
2226 | for (i = 0; i < rdev->usec_timeout; i++) { | |
2227 | tmp = RREG32(scratch); | |
2228 | if (tmp == 0xDEADBEEF) | |
2229 | break; | |
2230 | DRM_UDELAY(1); | |
2231 | } | |
2232 | if (i < rdev->usec_timeout) { | |
2233 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
2234 | } else { | |
2235 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", | |
2236 | scratch, tmp); | |
2237 | r = -EINVAL; | |
2238 | } | |
2239 | radeon_scratch_free(rdev, scratch); | |
2240 | return r; | |
2241 | } | |
2242 | ||
81cc35bf JG |
2243 | void r600_wb_disable(struct radeon_device *rdev) |
2244 | { | |
4c788679 JG |
2245 | int r; |
2246 | ||
81cc35bf JG |
2247 | WREG32(SCRATCH_UMSK, 0); |
2248 | if (rdev->wb.wb_obj) { | |
4c788679 JG |
2249 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
2250 | if (unlikely(r != 0)) | |
2251 | return; | |
2252 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
2253 | radeon_bo_unpin(rdev->wb.wb_obj); | |
2254 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
81cc35bf JG |
2255 | } |
2256 | } | |
2257 | ||
2258 | void r600_wb_fini(struct radeon_device *rdev) | |
2259 | { | |
2260 | r600_wb_disable(rdev); | |
2261 | if (rdev->wb.wb_obj) { | |
4c788679 | 2262 | radeon_bo_unref(&rdev->wb.wb_obj); |
81cc35bf JG |
2263 | rdev->wb.wb = NULL; |
2264 | rdev->wb.wb_obj = NULL; | |
2265 | } | |
2266 | } | |
2267 | ||
2268 | int r600_wb_enable(struct radeon_device *rdev) | |
3ce0a23d JG |
2269 | { |
2270 | int r; | |
2271 | ||
2272 | if (rdev->wb.wb_obj == NULL) { | |
4c788679 JG |
2273 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
2274 | RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); | |
3ce0a23d | 2275 | if (r) { |
4c788679 | 2276 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
3ce0a23d JG |
2277 | return r; |
2278 | } | |
4c788679 JG |
2279 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
2280 | if (unlikely(r != 0)) { | |
2281 | r600_wb_fini(rdev); | |
3ce0a23d JG |
2282 | return r; |
2283 | } | |
4c788679 | 2284 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
81cc35bf | 2285 | &rdev->wb.gpu_addr); |
3ce0a23d | 2286 | if (r) { |
4c788679 JG |
2287 | radeon_bo_unreserve(rdev->wb.wb_obj); |
2288 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); | |
81cc35bf | 2289 | r600_wb_fini(rdev); |
3ce0a23d JG |
2290 | return r; |
2291 | } | |
4c788679 JG |
2292 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
2293 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
3ce0a23d | 2294 | if (r) { |
4c788679 | 2295 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
81cc35bf | 2296 | r600_wb_fini(rdev); |
3ce0a23d JG |
2297 | return r; |
2298 | } | |
2299 | } | |
2300 | WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); | |
2301 | WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); | |
2302 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); | |
2303 | WREG32(SCRATCH_UMSK, 0xff); | |
2304 | return 0; | |
2305 | } | |
2306 | ||
3ce0a23d JG |
2307 | void r600_fence_ring_emit(struct radeon_device *rdev, |
2308 | struct radeon_fence *fence) | |
2309 | { | |
d8f60cfc | 2310 | /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ |
44224c3f AD |
2311 | |
2312 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); | |
2313 | radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); | |
2314 | /* wait for 3D idle clean */ | |
2315 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
2316 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2317 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | |
3ce0a23d JG |
2318 | /* Emit fence sequence & fire IRQ */ |
2319 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
2320 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2321 | radeon_ring_write(rdev, fence->seq); | |
d8f60cfc AD |
2322 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
2323 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); | |
2324 | radeon_ring_write(rdev, RB_INT_STAT); | |
3ce0a23d JG |
2325 | } |
2326 | ||
3ce0a23d JG |
2327 | int r600_copy_blit(struct radeon_device *rdev, |
2328 | uint64_t src_offset, uint64_t dst_offset, | |
2329 | unsigned num_pages, struct radeon_fence *fence) | |
2330 | { | |
ff82f052 JG |
2331 | int r; |
2332 | ||
2333 | mutex_lock(&rdev->r600_blit.mutex); | |
2334 | rdev->r600_blit.vb_ib = NULL; | |
2335 | r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); | |
2336 | if (r) { | |
2337 | if (rdev->r600_blit.vb_ib) | |
2338 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); | |
2339 | mutex_unlock(&rdev->r600_blit.mutex); | |
2340 | return r; | |
2341 | } | |
a77f1718 | 2342 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
3ce0a23d | 2343 | r600_blit_done_copy(rdev, fence); |
ff82f052 | 2344 | mutex_unlock(&rdev->r600_blit.mutex); |
3ce0a23d JG |
2345 | return 0; |
2346 | } | |
2347 | ||
3ce0a23d JG |
2348 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
2349 | uint32_t tiling_flags, uint32_t pitch, | |
2350 | uint32_t offset, uint32_t obj_size) | |
2351 | { | |
2352 | /* FIXME: implement */ | |
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |
2357 | { | |
2358 | /* FIXME: implement */ | |
2359 | } | |
2360 | ||
2361 | ||
2362 | bool r600_card_posted(struct radeon_device *rdev) | |
2363 | { | |
2364 | uint32_t reg; | |
2365 | ||
2366 | /* first check CRTCs */ | |
2367 | reg = RREG32(D1CRTC_CONTROL) | | |
2368 | RREG32(D2CRTC_CONTROL); | |
2369 | if (reg & CRTC_EN) | |
2370 | return true; | |
2371 | ||
2372 | /* then check MEM_SIZE, in case the crtcs are off */ | |
2373 | if (RREG32(CONFIG_MEMSIZE)) | |
2374 | return true; | |
2375 | ||
2376 | return false; | |
2377 | } | |
2378 | ||
fc30b8ef | 2379 | int r600_startup(struct radeon_device *rdev) |
3ce0a23d JG |
2380 | { |
2381 | int r; | |
2382 | ||
779720a3 AD |
2383 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
2384 | r = r600_init_microcode(rdev); | |
2385 | if (r) { | |
2386 | DRM_ERROR("Failed to load firmware!\n"); | |
2387 | return r; | |
2388 | } | |
2389 | } | |
2390 | ||
a3c1945a | 2391 | r600_mc_program(rdev); |
1a029b76 JG |
2392 | if (rdev->flags & RADEON_IS_AGP) { |
2393 | r600_agp_enable(rdev); | |
2394 | } else { | |
2395 | r = r600_pcie_gart_enable(rdev); | |
2396 | if (r) | |
2397 | return r; | |
2398 | } | |
3ce0a23d | 2399 | r600_gpu_init(rdev); |
c38c7b64 JG |
2400 | r = r600_blit_init(rdev); |
2401 | if (r) { | |
2402 | r600_blit_fini(rdev); | |
2403 | rdev->asic->copy = NULL; | |
2404 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | |
2405 | } | |
ff82f052 JG |
2406 | /* pin copy shader into vram */ |
2407 | if (rdev->r600_blit.shader_obj) { | |
2408 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
2409 | if (unlikely(r != 0)) | |
2410 | return r; | |
2411 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, | |
2412 | &rdev->r600_blit.shader_gpu_addr); | |
2413 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
7923c615 | 2414 | if (r) { |
ff82f052 | 2415 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
7923c615 AD |
2416 | return r; |
2417 | } | |
2418 | } | |
d8f60cfc | 2419 | /* Enable IRQ */ |
d8f60cfc AD |
2420 | r = r600_irq_init(rdev); |
2421 | if (r) { | |
2422 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
2423 | radeon_irq_kms_fini(rdev); | |
2424 | return r; | |
2425 | } | |
2426 | r600_irq_set(rdev); | |
2427 | ||
3ce0a23d JG |
2428 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
2429 | if (r) | |
2430 | return r; | |
2431 | r = r600_cp_load_microcode(rdev); | |
2432 | if (r) | |
2433 | return r; | |
2434 | r = r600_cp_resume(rdev); | |
2435 | if (r) | |
2436 | return r; | |
81cc35bf JG |
2437 | /* write back buffer are not vital so don't worry about failure */ |
2438 | r600_wb_enable(rdev); | |
3ce0a23d JG |
2439 | return 0; |
2440 | } | |
2441 | ||
28d52043 DA |
2442 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
2443 | { | |
2444 | uint32_t temp; | |
2445 | ||
2446 | temp = RREG32(CONFIG_CNTL); | |
2447 | if (state == false) { | |
2448 | temp &= ~(1<<0); | |
2449 | temp |= (1<<1); | |
2450 | } else { | |
2451 | temp &= ~(1<<1); | |
2452 | } | |
2453 | WREG32(CONFIG_CNTL, temp); | |
2454 | } | |
2455 | ||
fc30b8ef DA |
2456 | int r600_resume(struct radeon_device *rdev) |
2457 | { | |
2458 | int r; | |
2459 | ||
1a029b76 JG |
2460 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
2461 | * posting will perform necessary task to bring back GPU into good | |
2462 | * shape. | |
2463 | */ | |
fc30b8ef | 2464 | /* post card */ |
e7d40b9a | 2465 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef DA |
2466 | /* Initialize clocks */ |
2467 | r = radeon_clocks_init(rdev); | |
2468 | if (r) { | |
2469 | return r; | |
2470 | } | |
2471 | ||
2472 | r = r600_startup(rdev); | |
2473 | if (r) { | |
2474 | DRM_ERROR("r600 startup failed on resume\n"); | |
2475 | return r; | |
2476 | } | |
2477 | ||
62a8ea3f | 2478 | r = r600_ib_test(rdev); |
fc30b8ef DA |
2479 | if (r) { |
2480 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); | |
2481 | return r; | |
2482 | } | |
38fd2c6f RM |
2483 | |
2484 | r = r600_audio_init(rdev); | |
2485 | if (r) { | |
2486 | DRM_ERROR("radeon: audio resume failed\n"); | |
2487 | return r; | |
2488 | } | |
2489 | ||
fc30b8ef DA |
2490 | return r; |
2491 | } | |
2492 | ||
3ce0a23d JG |
2493 | int r600_suspend(struct radeon_device *rdev) |
2494 | { | |
4c788679 JG |
2495 | int r; |
2496 | ||
38fd2c6f | 2497 | r600_audio_fini(rdev); |
3ce0a23d JG |
2498 | /* FIXME: we should wait for ring to be empty */ |
2499 | r600_cp_stop(rdev); | |
bc1a631e | 2500 | rdev->cp.ready = false; |
0c45249f | 2501 | r600_irq_suspend(rdev); |
81cc35bf | 2502 | r600_wb_disable(rdev); |
4aac0473 | 2503 | r600_pcie_gart_disable(rdev); |
bc1a631e | 2504 | /* unpin shaders bo */ |
30d2d9a5 JG |
2505 | if (rdev->r600_blit.shader_obj) { |
2506 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); | |
2507 | if (!r) { | |
2508 | radeon_bo_unpin(rdev->r600_blit.shader_obj); | |
2509 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
2510 | } | |
2511 | } | |
3ce0a23d JG |
2512 | return 0; |
2513 | } | |
2514 | ||
2515 | /* Plan is to move initialization in that function and use | |
2516 | * helper function so that radeon_device_init pretty much | |
2517 | * do nothing more than calling asic specific function. This | |
2518 | * should also allow to remove a bunch of callback function | |
2519 | * like vram_info. | |
2520 | */ | |
2521 | int r600_init(struct radeon_device *rdev) | |
771fe6b9 | 2522 | { |
3ce0a23d | 2523 | int r; |
771fe6b9 | 2524 | |
3ce0a23d JG |
2525 | r = radeon_dummy_page_init(rdev); |
2526 | if (r) | |
2527 | return r; | |
2528 | if (r600_debugfs_mc_info_init(rdev)) { | |
2529 | DRM_ERROR("Failed to register debugfs file for mc !\n"); | |
2530 | } | |
2531 | /* This don't do much */ | |
2532 | r = radeon_gem_init(rdev); | |
2533 | if (r) | |
2534 | return r; | |
2535 | /* Read BIOS */ | |
2536 | if (!radeon_get_bios(rdev)) { | |
2537 | if (ASIC_IS_AVIVO(rdev)) | |
2538 | return -EINVAL; | |
2539 | } | |
2540 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
2541 | if (!rdev->is_atom_bios) { |
2542 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 2543 | return -EINVAL; |
e7d40b9a | 2544 | } |
3ce0a23d JG |
2545 | r = radeon_atombios_init(rdev); |
2546 | if (r) | |
2547 | return r; | |
2548 | /* Post card if necessary */ | |
72542d77 DA |
2549 | if (!r600_card_posted(rdev)) { |
2550 | if (!rdev->bios) { | |
2551 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
2552 | return -EINVAL; | |
2553 | } | |
3ce0a23d JG |
2554 | DRM_INFO("GPU not posted. posting now...\n"); |
2555 | atom_asic_init(rdev->mode_info.atom_context); | |
2556 | } | |
2557 | /* Initialize scratch registers */ | |
2558 | r600_scratch_init(rdev); | |
2559 | /* Initialize surface registers */ | |
2560 | radeon_surface_init(rdev); | |
7433874e | 2561 | /* Initialize clocks */ |
5e6dde7e | 2562 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d JG |
2563 | r = radeon_clocks_init(rdev); |
2564 | if (r) | |
2565 | return r; | |
2566 | /* Fence driver */ | |
2567 | r = radeon_fence_driver_init(rdev); | |
2568 | if (r) | |
2569 | return r; | |
700a0cc0 JG |
2570 | if (rdev->flags & RADEON_IS_AGP) { |
2571 | r = radeon_agp_init(rdev); | |
2572 | if (r) | |
2573 | radeon_agp_disable(rdev); | |
2574 | } | |
3ce0a23d | 2575 | r = r600_mc_init(rdev); |
b574f251 | 2576 | if (r) |
3ce0a23d | 2577 | return r; |
3ce0a23d | 2578 | /* Memory manager */ |
4c788679 | 2579 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
2580 | if (r) |
2581 | return r; | |
d8f60cfc AD |
2582 | |
2583 | r = radeon_irq_kms_init(rdev); | |
2584 | if (r) | |
2585 | return r; | |
2586 | ||
3ce0a23d JG |
2587 | rdev->cp.ring_obj = NULL; |
2588 | r600_ring_init(rdev, 1024 * 1024); | |
2589 | ||
d8f60cfc AD |
2590 | rdev->ih.ring_obj = NULL; |
2591 | r600_ih_ring_init(rdev, 64 * 1024); | |
3ce0a23d | 2592 | |
4aac0473 JG |
2593 | r = r600_pcie_gart_init(rdev); |
2594 | if (r) | |
2595 | return r; | |
2596 | ||
779720a3 | 2597 | rdev->accel_working = true; |
fc30b8ef | 2598 | r = r600_startup(rdev); |
3ce0a23d | 2599 | if (r) { |
655efd3d JG |
2600 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
2601 | r600_cp_fini(rdev); | |
75c81298 | 2602 | r600_wb_fini(rdev); |
655efd3d JG |
2603 | r600_irq_fini(rdev); |
2604 | radeon_irq_kms_fini(rdev); | |
75c81298 | 2605 | r600_pcie_gart_fini(rdev); |
733289c2 | 2606 | rdev->accel_working = false; |
3ce0a23d | 2607 | } |
733289c2 JG |
2608 | if (rdev->accel_working) { |
2609 | r = radeon_ib_pool_init(rdev); | |
2610 | if (r) { | |
db96380e | 2611 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
733289c2 | 2612 | rdev->accel_working = false; |
db96380e JG |
2613 | } else { |
2614 | r = r600_ib_test(rdev); | |
2615 | if (r) { | |
2616 | dev_err(rdev->dev, "IB test failed (%d).\n", r); | |
2617 | rdev->accel_working = false; | |
2618 | } | |
733289c2 | 2619 | } |
3ce0a23d | 2620 | } |
dafc3bd5 CK |
2621 | |
2622 | r = r600_audio_init(rdev); | |
2623 | if (r) | |
2624 | return r; /* TODO error handling */ | |
3ce0a23d JG |
2625 | return 0; |
2626 | } | |
2627 | ||
2628 | void r600_fini(struct radeon_device *rdev) | |
2629 | { | |
dafc3bd5 | 2630 | r600_audio_fini(rdev); |
3ce0a23d | 2631 | r600_blit_fini(rdev); |
655efd3d JG |
2632 | r600_cp_fini(rdev); |
2633 | r600_wb_fini(rdev); | |
d8f60cfc AD |
2634 | r600_irq_fini(rdev); |
2635 | radeon_irq_kms_fini(rdev); | |
4aac0473 | 2636 | r600_pcie_gart_fini(rdev); |
655efd3d | 2637 | radeon_agp_fini(rdev); |
3ce0a23d JG |
2638 | radeon_gem_fini(rdev); |
2639 | radeon_fence_driver_fini(rdev); | |
2640 | radeon_clocks_fini(rdev); | |
4c788679 | 2641 | radeon_bo_fini(rdev); |
e7d40b9a | 2642 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
2643 | kfree(rdev->bios); |
2644 | rdev->bios = NULL; | |
2645 | radeon_dummy_page_fini(rdev); | |
2646 | } | |
2647 | ||
2648 | ||
2649 | /* | |
2650 | * CS stuff | |
2651 | */ | |
2652 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
2653 | { | |
2654 | /* FIXME: implement */ | |
2655 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | |
2656 | radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); | |
2657 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | |
2658 | radeon_ring_write(rdev, ib->length_dw); | |
2659 | } | |
2660 | ||
2661 | int r600_ib_test(struct radeon_device *rdev) | |
2662 | { | |
2663 | struct radeon_ib *ib; | |
2664 | uint32_t scratch; | |
2665 | uint32_t tmp = 0; | |
2666 | unsigned i; | |
2667 | int r; | |
2668 | ||
2669 | r = radeon_scratch_get(rdev, &scratch); | |
2670 | if (r) { | |
2671 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
2672 | return r; | |
2673 | } | |
2674 | WREG32(scratch, 0xCAFEDEAD); | |
2675 | r = radeon_ib_get(rdev, &ib); | |
2676 | if (r) { | |
2677 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
2678 | return r; | |
2679 | } | |
2680 | ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); | |
2681 | ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2682 | ib->ptr[2] = 0xDEADBEEF; | |
2683 | ib->ptr[3] = PACKET2(0); | |
2684 | ib->ptr[4] = PACKET2(0); | |
2685 | ib->ptr[5] = PACKET2(0); | |
2686 | ib->ptr[6] = PACKET2(0); | |
2687 | ib->ptr[7] = PACKET2(0); | |
2688 | ib->ptr[8] = PACKET2(0); | |
2689 | ib->ptr[9] = PACKET2(0); | |
2690 | ib->ptr[10] = PACKET2(0); | |
2691 | ib->ptr[11] = PACKET2(0); | |
2692 | ib->ptr[12] = PACKET2(0); | |
2693 | ib->ptr[13] = PACKET2(0); | |
2694 | ib->ptr[14] = PACKET2(0); | |
2695 | ib->ptr[15] = PACKET2(0); | |
2696 | ib->length_dw = 16; | |
2697 | r = radeon_ib_schedule(rdev, ib); | |
2698 | if (r) { | |
2699 | radeon_scratch_free(rdev, scratch); | |
2700 | radeon_ib_free(rdev, &ib); | |
2701 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | |
2702 | return r; | |
2703 | } | |
2704 | r = radeon_fence_wait(ib->fence, false); | |
2705 | if (r) { | |
2706 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
2707 | return r; | |
2708 | } | |
2709 | for (i = 0; i < rdev->usec_timeout; i++) { | |
2710 | tmp = RREG32(scratch); | |
2711 | if (tmp == 0xDEADBEEF) | |
2712 | break; | |
2713 | DRM_UDELAY(1); | |
2714 | } | |
2715 | if (i < rdev->usec_timeout) { | |
2716 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
2717 | } else { | |
2718 | DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", | |
2719 | scratch, tmp); | |
2720 | r = -EINVAL; | |
2721 | } | |
2722 | radeon_scratch_free(rdev, scratch); | |
2723 | radeon_ib_free(rdev, &ib); | |
771fe6b9 JG |
2724 | return r; |
2725 | } | |
2726 | ||
d8f60cfc AD |
2727 | /* |
2728 | * Interrupts | |
2729 | * | |
2730 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty | |
2731 | * the same as the CP ring buffer, but in reverse. Rather than the CPU | |
2732 | * writing to the ring and the GPU consuming, the GPU writes to the ring | |
2733 | * and host consumes. As the host irq handler processes interrupts, it | |
2734 | * increments the rptr. When the rptr catches up with the wptr, all the | |
2735 | * current interrupts have been processed. | |
2736 | */ | |
2737 | ||
2738 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
2739 | { | |
2740 | u32 rb_bufsz; | |
2741 | ||
2742 | /* Align ring size */ | |
2743 | rb_bufsz = drm_order(ring_size / 4); | |
2744 | ring_size = (1 << rb_bufsz) * 4; | |
2745 | rdev->ih.ring_size = ring_size; | |
0c45249f JG |
2746 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
2747 | rdev->ih.rptr = 0; | |
d8f60cfc AD |
2748 | } |
2749 | ||
0c45249f | 2750 | static int r600_ih_ring_alloc(struct radeon_device *rdev) |
d8f60cfc AD |
2751 | { |
2752 | int r; | |
2753 | ||
d8f60cfc AD |
2754 | /* Allocate ring buffer */ |
2755 | if (rdev->ih.ring_obj == NULL) { | |
4c788679 JG |
2756 | r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, |
2757 | true, | |
2758 | RADEON_GEM_DOMAIN_GTT, | |
2759 | &rdev->ih.ring_obj); | |
d8f60cfc AD |
2760 | if (r) { |
2761 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); | |
2762 | return r; | |
2763 | } | |
4c788679 JG |
2764 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2765 | if (unlikely(r != 0)) | |
2766 | return r; | |
2767 | r = radeon_bo_pin(rdev->ih.ring_obj, | |
2768 | RADEON_GEM_DOMAIN_GTT, | |
2769 | &rdev->ih.gpu_addr); | |
d8f60cfc | 2770 | if (r) { |
4c788679 | 2771 | radeon_bo_unreserve(rdev->ih.ring_obj); |
d8f60cfc AD |
2772 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
2773 | return r; | |
2774 | } | |
4c788679 JG |
2775 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
2776 | (void **)&rdev->ih.ring); | |
2777 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
d8f60cfc AD |
2778 | if (r) { |
2779 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); | |
2780 | return r; | |
2781 | } | |
2782 | } | |
d8f60cfc AD |
2783 | return 0; |
2784 | } | |
2785 | ||
2786 | static void r600_ih_ring_fini(struct radeon_device *rdev) | |
2787 | { | |
4c788679 | 2788 | int r; |
d8f60cfc | 2789 | if (rdev->ih.ring_obj) { |
4c788679 JG |
2790 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2791 | if (likely(r == 0)) { | |
2792 | radeon_bo_kunmap(rdev->ih.ring_obj); | |
2793 | radeon_bo_unpin(rdev->ih.ring_obj); | |
2794 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
2795 | } | |
2796 | radeon_bo_unref(&rdev->ih.ring_obj); | |
d8f60cfc AD |
2797 | rdev->ih.ring = NULL; |
2798 | rdev->ih.ring_obj = NULL; | |
2799 | } | |
2800 | } | |
2801 | ||
45f9a39b | 2802 | void r600_rlc_stop(struct radeon_device *rdev) |
d8f60cfc AD |
2803 | { |
2804 | ||
45f9a39b AD |
2805 | if ((rdev->family >= CHIP_RV770) && |
2806 | (rdev->family <= CHIP_RV740)) { | |
d8f60cfc AD |
2807 | /* r7xx asics need to soft reset RLC before halting */ |
2808 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); | |
2809 | RREG32(SRBM_SOFT_RESET); | |
2810 | udelay(15000); | |
2811 | WREG32(SRBM_SOFT_RESET, 0); | |
2812 | RREG32(SRBM_SOFT_RESET); | |
2813 | } | |
2814 | ||
2815 | WREG32(RLC_CNTL, 0); | |
2816 | } | |
2817 | ||
2818 | static void r600_rlc_start(struct radeon_device *rdev) | |
2819 | { | |
2820 | WREG32(RLC_CNTL, RLC_ENABLE); | |
2821 | } | |
2822 | ||
2823 | static int r600_rlc_init(struct radeon_device *rdev) | |
2824 | { | |
2825 | u32 i; | |
2826 | const __be32 *fw_data; | |
2827 | ||
2828 | if (!rdev->rlc_fw) | |
2829 | return -EINVAL; | |
2830 | ||
2831 | r600_rlc_stop(rdev); | |
2832 | ||
2833 | WREG32(RLC_HB_BASE, 0); | |
2834 | WREG32(RLC_HB_CNTL, 0); | |
2835 | WREG32(RLC_HB_RPTR, 0); | |
2836 | WREG32(RLC_HB_WPTR, 0); | |
2837 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); | |
2838 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); | |
2839 | WREG32(RLC_MC_CNTL, 0); | |
2840 | WREG32(RLC_UCODE_CNTL, 0); | |
2841 | ||
2842 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
45f9a39b AD |
2843 | if (rdev->family >= CHIP_CEDAR) { |
2844 | for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { | |
2845 | WREG32(RLC_UCODE_ADDR, i); | |
2846 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2847 | } | |
2848 | } else if (rdev->family >= CHIP_RV770) { | |
d8f60cfc AD |
2849 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { |
2850 | WREG32(RLC_UCODE_ADDR, i); | |
2851 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2852 | } | |
2853 | } else { | |
2854 | for (i = 0; i < RLC_UCODE_SIZE; i++) { | |
2855 | WREG32(RLC_UCODE_ADDR, i); | |
2856 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2857 | } | |
2858 | } | |
2859 | WREG32(RLC_UCODE_ADDR, 0); | |
2860 | ||
2861 | r600_rlc_start(rdev); | |
2862 | ||
2863 | return 0; | |
2864 | } | |
2865 | ||
2866 | static void r600_enable_interrupts(struct radeon_device *rdev) | |
2867 | { | |
2868 | u32 ih_cntl = RREG32(IH_CNTL); | |
2869 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2870 | ||
2871 | ih_cntl |= ENABLE_INTR; | |
2872 | ih_rb_cntl |= IH_RB_ENABLE; | |
2873 | WREG32(IH_CNTL, ih_cntl); | |
2874 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2875 | rdev->ih.enabled = true; | |
2876 | } | |
2877 | ||
45f9a39b | 2878 | void r600_disable_interrupts(struct radeon_device *rdev) |
d8f60cfc AD |
2879 | { |
2880 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2881 | u32 ih_cntl = RREG32(IH_CNTL); | |
2882 | ||
2883 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
2884 | ih_cntl &= ~ENABLE_INTR; | |
2885 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2886 | WREG32(IH_CNTL, ih_cntl); | |
2887 | /* set rptr, wptr to 0 */ | |
2888 | WREG32(IH_RB_RPTR, 0); | |
2889 | WREG32(IH_RB_WPTR, 0); | |
2890 | rdev->ih.enabled = false; | |
2891 | rdev->ih.wptr = 0; | |
2892 | rdev->ih.rptr = 0; | |
2893 | } | |
2894 | ||
e0df1ac5 AD |
2895 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
2896 | { | |
2897 | u32 tmp; | |
2898 | ||
2899 | WREG32(CP_INT_CNTL, 0); | |
2900 | WREG32(GRBM_INT_CNTL, 0); | |
2901 | WREG32(DxMODE_INT_MASK, 0); | |
2902 | if (ASIC_IS_DCE3(rdev)) { | |
2903 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); | |
2904 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); | |
2905 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2906 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2907 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2908 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2909 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2910 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2911 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2912 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2913 | if (ASIC_IS_DCE32(rdev)) { | |
2914 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
5898b1f3 | 2915 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
e0df1ac5 | 2916 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
5898b1f3 | 2917 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
e0df1ac5 AD |
2918 | } |
2919 | } else { | |
2920 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
2921 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
2922 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
5898b1f3 | 2923 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
e0df1ac5 | 2924 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2925 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
e0df1ac5 | 2926 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 2927 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
e0df1ac5 AD |
2928 | } |
2929 | } | |
2930 | ||
d8f60cfc AD |
2931 | int r600_irq_init(struct radeon_device *rdev) |
2932 | { | |
2933 | int ret = 0; | |
2934 | int rb_bufsz; | |
2935 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
2936 | ||
2937 | /* allocate ring */ | |
0c45249f | 2938 | ret = r600_ih_ring_alloc(rdev); |
d8f60cfc AD |
2939 | if (ret) |
2940 | return ret; | |
2941 | ||
2942 | /* disable irqs */ | |
2943 | r600_disable_interrupts(rdev); | |
2944 | ||
2945 | /* init rlc */ | |
2946 | ret = r600_rlc_init(rdev); | |
2947 | if (ret) { | |
2948 | r600_ih_ring_fini(rdev); | |
2949 | return ret; | |
2950 | } | |
2951 | ||
2952 | /* setup interrupt control */ | |
2953 | /* set dummy read address to ring address */ | |
2954 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
2955 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
2956 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
2957 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
2958 | */ | |
2959 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
2960 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
2961 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
2962 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
2963 | ||
2964 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
2965 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); | |
2966 | ||
2967 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
2968 | IH_WPTR_OVERFLOW_CLEAR | | |
2969 | (rb_bufsz << 1)); | |
2970 | /* WPTR writeback, not yet */ | |
2971 | /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/ | |
2972 | WREG32(IH_RB_WPTR_ADDR_LO, 0); | |
2973 | WREG32(IH_RB_WPTR_ADDR_HI, 0); | |
2974 | ||
2975 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2976 | ||
2977 | /* set rptr, wptr to 0 */ | |
2978 | WREG32(IH_RB_RPTR, 0); | |
2979 | WREG32(IH_RB_WPTR, 0); | |
2980 | ||
2981 | /* Default settings for IH_CNTL (disabled at first) */ | |
2982 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); | |
2983 | /* RPTR_REARM only works if msi's are enabled */ | |
2984 | if (rdev->msi_enabled) | |
2985 | ih_cntl |= RPTR_REARM; | |
2986 | ||
2987 | #ifdef __BIG_ENDIAN | |
2988 | ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); | |
2989 | #endif | |
2990 | WREG32(IH_CNTL, ih_cntl); | |
2991 | ||
2992 | /* force the active interrupt state to all disabled */ | |
45f9a39b AD |
2993 | if (rdev->family >= CHIP_CEDAR) |
2994 | evergreen_disable_interrupt_state(rdev); | |
2995 | else | |
2996 | r600_disable_interrupt_state(rdev); | |
d8f60cfc AD |
2997 | |
2998 | /* enable irqs */ | |
2999 | r600_enable_interrupts(rdev); | |
3000 | ||
3001 | return ret; | |
3002 | } | |
3003 | ||
0c45249f | 3004 | void r600_irq_suspend(struct radeon_device *rdev) |
d8f60cfc | 3005 | { |
45f9a39b | 3006 | r600_irq_disable(rdev); |
d8f60cfc | 3007 | r600_rlc_stop(rdev); |
0c45249f JG |
3008 | } |
3009 | ||
3010 | void r600_irq_fini(struct radeon_device *rdev) | |
3011 | { | |
3012 | r600_irq_suspend(rdev); | |
d8f60cfc AD |
3013 | r600_ih_ring_fini(rdev); |
3014 | } | |
3015 | ||
3016 | int r600_irq_set(struct radeon_device *rdev) | |
3017 | { | |
e0df1ac5 AD |
3018 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
3019 | u32 mode_int = 0; | |
3020 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | |
2031f77c | 3021 | u32 grbm_int_cntl = 0; |
f2594933 | 3022 | u32 hdmi1, hdmi2; |
d8f60cfc | 3023 | |
003e69f9 JG |
3024 | if (!rdev->irq.installed) { |
3025 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
3026 | return -EINVAL; | |
3027 | } | |
d8f60cfc | 3028 | /* don't enable anything if the ih is disabled */ |
79c2bbc5 JG |
3029 | if (!rdev->ih.enabled) { |
3030 | r600_disable_interrupts(rdev); | |
3031 | /* force the active interrupt state to all disabled */ | |
3032 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 3033 | return 0; |
79c2bbc5 | 3034 | } |
d8f60cfc | 3035 | |
f2594933 | 3036 | hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 | 3037 | if (ASIC_IS_DCE3(rdev)) { |
f2594933 | 3038 | hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 AD |
3039 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3040 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3041 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3042 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3043 | if (ASIC_IS_DCE32(rdev)) { | |
3044 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3045 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3046 | } | |
3047 | } else { | |
f2594933 | 3048 | hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
e0df1ac5 AD |
3049 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3050 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3051 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3052 | } | |
3053 | ||
d8f60cfc AD |
3054 | if (rdev->irq.sw_int) { |
3055 | DRM_DEBUG("r600_irq_set: sw int\n"); | |
3056 | cp_int_cntl |= RB_INT_ENABLE; | |
3057 | } | |
3058 | if (rdev->irq.crtc_vblank_int[0]) { | |
3059 | DRM_DEBUG("r600_irq_set: vblank 0\n"); | |
3060 | mode_int |= D1MODE_VBLANK_INT_MASK; | |
3061 | } | |
3062 | if (rdev->irq.crtc_vblank_int[1]) { | |
3063 | DRM_DEBUG("r600_irq_set: vblank 1\n"); | |
3064 | mode_int |= D2MODE_VBLANK_INT_MASK; | |
3065 | } | |
e0df1ac5 AD |
3066 | if (rdev->irq.hpd[0]) { |
3067 | DRM_DEBUG("r600_irq_set: hpd 1\n"); | |
3068 | hpd1 |= DC_HPDx_INT_EN; | |
3069 | } | |
3070 | if (rdev->irq.hpd[1]) { | |
3071 | DRM_DEBUG("r600_irq_set: hpd 2\n"); | |
3072 | hpd2 |= DC_HPDx_INT_EN; | |
3073 | } | |
3074 | if (rdev->irq.hpd[2]) { | |
3075 | DRM_DEBUG("r600_irq_set: hpd 3\n"); | |
3076 | hpd3 |= DC_HPDx_INT_EN; | |
3077 | } | |
3078 | if (rdev->irq.hpd[3]) { | |
3079 | DRM_DEBUG("r600_irq_set: hpd 4\n"); | |
3080 | hpd4 |= DC_HPDx_INT_EN; | |
3081 | } | |
3082 | if (rdev->irq.hpd[4]) { | |
3083 | DRM_DEBUG("r600_irq_set: hpd 5\n"); | |
3084 | hpd5 |= DC_HPDx_INT_EN; | |
3085 | } | |
3086 | if (rdev->irq.hpd[5]) { | |
3087 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | |
3088 | hpd6 |= DC_HPDx_INT_EN; | |
3089 | } | |
f2594933 CK |
3090 | if (rdev->irq.hdmi[0]) { |
3091 | DRM_DEBUG("r600_irq_set: hdmi 1\n"); | |
3092 | hdmi1 |= R600_HDMI_INT_EN; | |
3093 | } | |
3094 | if (rdev->irq.hdmi[1]) { | |
3095 | DRM_DEBUG("r600_irq_set: hdmi 2\n"); | |
3096 | hdmi2 |= R600_HDMI_INT_EN; | |
3097 | } | |
2031f77c AD |
3098 | if (rdev->irq.gui_idle) { |
3099 | DRM_DEBUG("gui idle\n"); | |
3100 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; | |
3101 | } | |
d8f60cfc AD |
3102 | |
3103 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
3104 | WREG32(DxMODE_INT_MASK, mode_int); | |
2031f77c | 3105 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
f2594933 | 3106 | WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); |
e0df1ac5 | 3107 | if (ASIC_IS_DCE3(rdev)) { |
f2594933 | 3108 | WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); |
e0df1ac5 AD |
3109 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
3110 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
3111 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
3112 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
3113 | if (ASIC_IS_DCE32(rdev)) { | |
3114 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
3115 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
3116 | } | |
3117 | } else { | |
f2594933 | 3118 | WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2); |
e0df1ac5 AD |
3119 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
3120 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
3121 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | |
3122 | } | |
d8f60cfc AD |
3123 | |
3124 | return 0; | |
3125 | } | |
3126 | ||
e0df1ac5 AD |
3127 | static inline void r600_irq_ack(struct radeon_device *rdev, |
3128 | u32 *disp_int, | |
3129 | u32 *disp_int_cont, | |
3130 | u32 *disp_int_cont2) | |
d8f60cfc | 3131 | { |
e0df1ac5 AD |
3132 | u32 tmp; |
3133 | ||
3134 | if (ASIC_IS_DCE3(rdev)) { | |
3135 | *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); | |
3136 | *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | |
3137 | *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | |
3138 | } else { | |
3139 | *disp_int = RREG32(DISP_INTERRUPT_STATUS); | |
3140 | *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
3141 | *disp_int_cont2 = 0; | |
3142 | } | |
d8f60cfc | 3143 | |
e0df1ac5 | 3144 | if (*disp_int & LB_D1_VBLANK_INTERRUPT) |
d8f60cfc | 3145 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 3146 | if (*disp_int & LB_D1_VLINE_INTERRUPT) |
d8f60cfc | 3147 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 | 3148 | if (*disp_int & LB_D2_VBLANK_INTERRUPT) |
d8f60cfc | 3149 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 3150 | if (*disp_int & LB_D2_VLINE_INTERRUPT) |
d8f60cfc | 3151 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 AD |
3152 | if (*disp_int & DC_HPD1_INTERRUPT) { |
3153 | if (ASIC_IS_DCE3(rdev)) { | |
3154 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
3155 | tmp |= DC_HPDx_INT_ACK; | |
3156 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3157 | } else { | |
3158 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
3159 | tmp |= DC_HPDx_INT_ACK; | |
3160 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
3161 | } | |
3162 | } | |
3163 | if (*disp_int & DC_HPD2_INTERRUPT) { | |
3164 | if (ASIC_IS_DCE3(rdev)) { | |
3165 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
3166 | tmp |= DC_HPDx_INT_ACK; | |
3167 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3168 | } else { | |
3169 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
3170 | tmp |= DC_HPDx_INT_ACK; | |
3171 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
3172 | } | |
3173 | } | |
3174 | if (*disp_int_cont & DC_HPD3_INTERRUPT) { | |
3175 | if (ASIC_IS_DCE3(rdev)) { | |
3176 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
3177 | tmp |= DC_HPDx_INT_ACK; | |
3178 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3179 | } else { | |
3180 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
3181 | tmp |= DC_HPDx_INT_ACK; | |
3182 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
3183 | } | |
3184 | } | |
3185 | if (*disp_int_cont & DC_HPD4_INTERRUPT) { | |
3186 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
3187 | tmp |= DC_HPDx_INT_ACK; | |
3188 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3189 | } | |
3190 | if (ASIC_IS_DCE32(rdev)) { | |
3191 | if (*disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
3192 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
3193 | tmp |= DC_HPDx_INT_ACK; | |
3194 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
3195 | } | |
3196 | if (*disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
3197 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
3198 | tmp |= DC_HPDx_INT_ACK; | |
3199 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
3200 | } | |
3201 | } | |
f2594933 CK |
3202 | if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
3203 | WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
3204 | } | |
3205 | if (ASIC_IS_DCE3(rdev)) { | |
3206 | if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | |
3207 | WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
3208 | } | |
3209 | } else { | |
3210 | if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | |
3211 | WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | |
3212 | } | |
3213 | } | |
d8f60cfc AD |
3214 | } |
3215 | ||
3216 | void r600_irq_disable(struct radeon_device *rdev) | |
3217 | { | |
e0df1ac5 | 3218 | u32 disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc AD |
3219 | |
3220 | r600_disable_interrupts(rdev); | |
3221 | /* Wait and acknowledge irq */ | |
3222 | mdelay(1); | |
e0df1ac5 AD |
3223 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
3224 | r600_disable_interrupt_state(rdev); | |
d8f60cfc AD |
3225 | } |
3226 | ||
3227 | static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) | |
3228 | { | |
3229 | u32 wptr, tmp; | |
3ce0a23d | 3230 | |
d8f60cfc AD |
3231 | /* XXX use writeback */ |
3232 | wptr = RREG32(IH_RB_WPTR); | |
3ce0a23d | 3233 | |
d8f60cfc | 3234 | if (wptr & RB_OVERFLOW) { |
7924e5eb JG |
3235 | /* When a ring buffer overflow happen start parsing interrupt |
3236 | * from the last not overwritten vector (wptr + 16). Hopefully | |
3237 | * this should allow us to catchup. | |
3238 | */ | |
3239 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
3240 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
3241 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
d8f60cfc AD |
3242 | tmp = RREG32(IH_RB_CNTL); |
3243 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
3244 | WREG32(IH_RB_CNTL, tmp); | |
3245 | } | |
0c45249f | 3246 | return (wptr & rdev->ih.ptr_mask); |
d8f60cfc | 3247 | } |
3ce0a23d | 3248 | |
d8f60cfc AD |
3249 | /* r600 IV Ring |
3250 | * Each IV ring entry is 128 bits: | |
3251 | * [7:0] - interrupt source id | |
3252 | * [31:8] - reserved | |
3253 | * [59:32] - interrupt source data | |
3254 | * [127:60] - reserved | |
3255 | * | |
3256 | * The basic interrupt vector entries | |
3257 | * are decoded as follows: | |
3258 | * src_id src_data description | |
3259 | * 1 0 D1 Vblank | |
3260 | * 1 1 D1 Vline | |
3261 | * 5 0 D2 Vblank | |
3262 | * 5 1 D2 Vline | |
3263 | * 19 0 FP Hot plug detection A | |
3264 | * 19 1 FP Hot plug detection B | |
3265 | * 19 2 DAC A auto-detection | |
3266 | * 19 3 DAC B auto-detection | |
f2594933 CK |
3267 | * 21 4 HDMI block A |
3268 | * 21 5 HDMI block B | |
d8f60cfc AD |
3269 | * 176 - CP_INT RB |
3270 | * 177 - CP_INT IB1 | |
3271 | * 178 - CP_INT IB2 | |
3272 | * 181 - EOP Interrupt | |
3273 | * 233 - GUI Idle | |
3274 | * | |
3275 | * Note, these are based on r600 and may need to be | |
3276 | * adjusted or added to on newer asics | |
3277 | */ | |
3278 | ||
3279 | int r600_irq_process(struct radeon_device *rdev) | |
3280 | { | |
3281 | u32 wptr = r600_get_ih_wptr(rdev); | |
3282 | u32 rptr = rdev->ih.rptr; | |
3283 | u32 src_id, src_data; | |
e0df1ac5 | 3284 | u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc | 3285 | unsigned long flags; |
d4877cf2 | 3286 | bool queue_hotplug = false; |
d8f60cfc AD |
3287 | |
3288 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
79c2bbc5 JG |
3289 | if (!rdev->ih.enabled) |
3290 | return IRQ_NONE; | |
d8f60cfc AD |
3291 | |
3292 | spin_lock_irqsave(&rdev->ih.lock, flags); | |
3293 | ||
3294 | if (rptr == wptr) { | |
3295 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3296 | return IRQ_NONE; | |
3297 | } | |
3298 | if (rdev->shutdown) { | |
3299 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3300 | return IRQ_NONE; | |
3301 | } | |
3302 | ||
3303 | restart_ih: | |
3304 | /* display interrupts */ | |
e0df1ac5 | 3305 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
d8f60cfc AD |
3306 | |
3307 | rdev->ih.wptr = wptr; | |
3308 | while (rptr != wptr) { | |
3309 | /* wptr/rptr are in bytes! */ | |
3310 | ring_index = rptr / 4; | |
3311 | src_id = rdev->ih.ring[ring_index] & 0xff; | |
3312 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | |
3313 | ||
3314 | switch (src_id) { | |
3315 | case 1: /* D1 vblank/vline */ | |
3316 | switch (src_data) { | |
3317 | case 0: /* D1 vblank */ | |
3318 | if (disp_int & LB_D1_VBLANK_INTERRUPT) { | |
3319 | drm_handle_vblank(rdev->ddev, 0); | |
839461d3 | 3320 | rdev->pm.vblank_sync = true; |
73a6d3fc | 3321 | wake_up(&rdev->irq.vblank_queue); |
d8f60cfc AD |
3322 | disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
3323 | DRM_DEBUG("IH: D1 vblank\n"); | |
3324 | } | |
3325 | break; | |
3326 | case 1: /* D1 vline */ | |
3327 | if (disp_int & LB_D1_VLINE_INTERRUPT) { | |
3328 | disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
3329 | DRM_DEBUG("IH: D1 vline\n"); | |
3330 | } | |
3331 | break; | |
3332 | default: | |
b042589c | 3333 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3334 | break; |
3335 | } | |
3336 | break; | |
3337 | case 5: /* D2 vblank/vline */ | |
3338 | switch (src_data) { | |
3339 | case 0: /* D2 vblank */ | |
3340 | if (disp_int & LB_D2_VBLANK_INTERRUPT) { | |
3341 | drm_handle_vblank(rdev->ddev, 1); | |
839461d3 | 3342 | rdev->pm.vblank_sync = true; |
73a6d3fc | 3343 | wake_up(&rdev->irq.vblank_queue); |
d8f60cfc AD |
3344 | disp_int &= ~LB_D2_VBLANK_INTERRUPT; |
3345 | DRM_DEBUG("IH: D2 vblank\n"); | |
3346 | } | |
3347 | break; | |
3348 | case 1: /* D1 vline */ | |
3349 | if (disp_int & LB_D2_VLINE_INTERRUPT) { | |
3350 | disp_int &= ~LB_D2_VLINE_INTERRUPT; | |
3351 | DRM_DEBUG("IH: D2 vline\n"); | |
3352 | } | |
3353 | break; | |
3354 | default: | |
b042589c | 3355 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3356 | break; |
3357 | } | |
3358 | break; | |
e0df1ac5 AD |
3359 | case 19: /* HPD/DAC hotplug */ |
3360 | switch (src_data) { | |
3361 | case 0: | |
3362 | if (disp_int & DC_HPD1_INTERRUPT) { | |
3363 | disp_int &= ~DC_HPD1_INTERRUPT; | |
d4877cf2 AD |
3364 | queue_hotplug = true; |
3365 | DRM_DEBUG("IH: HPD1\n"); | |
e0df1ac5 AD |
3366 | } |
3367 | break; | |
3368 | case 1: | |
3369 | if (disp_int & DC_HPD2_INTERRUPT) { | |
3370 | disp_int &= ~DC_HPD2_INTERRUPT; | |
d4877cf2 AD |
3371 | queue_hotplug = true; |
3372 | DRM_DEBUG("IH: HPD2\n"); | |
e0df1ac5 AD |
3373 | } |
3374 | break; | |
3375 | case 4: | |
3376 | if (disp_int_cont & DC_HPD3_INTERRUPT) { | |
3377 | disp_int_cont &= ~DC_HPD3_INTERRUPT; | |
d4877cf2 AD |
3378 | queue_hotplug = true; |
3379 | DRM_DEBUG("IH: HPD3\n"); | |
e0df1ac5 AD |
3380 | } |
3381 | break; | |
3382 | case 5: | |
3383 | if (disp_int_cont & DC_HPD4_INTERRUPT) { | |
3384 | disp_int_cont &= ~DC_HPD4_INTERRUPT; | |
d4877cf2 AD |
3385 | queue_hotplug = true; |
3386 | DRM_DEBUG("IH: HPD4\n"); | |
e0df1ac5 AD |
3387 | } |
3388 | break; | |
3389 | case 10: | |
3390 | if (disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
5898b1f3 | 3391 | disp_int_cont2 &= ~DC_HPD5_INTERRUPT; |
d4877cf2 AD |
3392 | queue_hotplug = true; |
3393 | DRM_DEBUG("IH: HPD5\n"); | |
e0df1ac5 AD |
3394 | } |
3395 | break; | |
3396 | case 12: | |
3397 | if (disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
5898b1f3 | 3398 | disp_int_cont2 &= ~DC_HPD6_INTERRUPT; |
d4877cf2 AD |
3399 | queue_hotplug = true; |
3400 | DRM_DEBUG("IH: HPD6\n"); | |
e0df1ac5 AD |
3401 | } |
3402 | break; | |
3403 | default: | |
b042589c | 3404 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
e0df1ac5 AD |
3405 | break; |
3406 | } | |
3407 | break; | |
f2594933 CK |
3408 | case 21: /* HDMI */ |
3409 | DRM_DEBUG("IH: HDMI: 0x%x\n", src_data); | |
3410 | r600_audio_schedule_polling(rdev); | |
3411 | break; | |
d8f60cfc AD |
3412 | case 176: /* CP_INT in ring buffer */ |
3413 | case 177: /* CP_INT in IB1 */ | |
3414 | case 178: /* CP_INT in IB2 */ | |
3415 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
3416 | radeon_fence_process(rdev); | |
3417 | break; | |
3418 | case 181: /* CP EOP event */ | |
3419 | DRM_DEBUG("IH: CP EOP\n"); | |
3420 | break; | |
2031f77c AD |
3421 | case 233: /* GUI IDLE */ |
3422 | DRM_DEBUG("IH: CP EOP\n"); | |
3423 | rdev->pm.gui_idle = true; | |
3424 | wake_up(&rdev->irq.idle_queue); | |
3425 | break; | |
d8f60cfc | 3426 | default: |
b042589c | 3427 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
3428 | break; |
3429 | } | |
3430 | ||
3431 | /* wptr/rptr are in bytes! */ | |
0c45249f JG |
3432 | rptr += 16; |
3433 | rptr &= rdev->ih.ptr_mask; | |
d8f60cfc AD |
3434 | } |
3435 | /* make sure wptr hasn't changed while processing */ | |
3436 | wptr = r600_get_ih_wptr(rdev); | |
3437 | if (wptr != rdev->ih.wptr) | |
3438 | goto restart_ih; | |
d4877cf2 AD |
3439 | if (queue_hotplug) |
3440 | queue_work(rdev->wq, &rdev->hotplug_work); | |
d8f60cfc AD |
3441 | rdev->ih.rptr = rptr; |
3442 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
3443 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3444 | return IRQ_HANDLED; | |
3445 | } | |
3ce0a23d JG |
3446 | |
3447 | /* | |
3448 | * Debugfs info | |
3449 | */ | |
3450 | #if defined(CONFIG_DEBUG_FS) | |
3451 | ||
3452 | static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) | |
771fe6b9 | 3453 | { |
3ce0a23d JG |
3454 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3455 | struct drm_device *dev = node->minor->dev; | |
3456 | struct radeon_device *rdev = dev->dev_private; | |
3ce0a23d JG |
3457 | unsigned count, i, j; |
3458 | ||
3459 | radeon_ring_free_size(rdev); | |
d6840766 | 3460 | count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; |
3ce0a23d | 3461 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
d6840766 RM |
3462 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); |
3463 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); | |
3464 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); | |
3465 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); | |
3ce0a23d JG |
3466 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
3467 | seq_printf(m, "%u dwords in ring\n", count); | |
d6840766 | 3468 | i = rdev->cp.rptr; |
3ce0a23d | 3469 | for (j = 0; j <= count; j++) { |
3ce0a23d | 3470 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
d6840766 | 3471 | i = (i + 1) & rdev->cp.ptr_mask; |
3ce0a23d JG |
3472 | } |
3473 | return 0; | |
3474 | } | |
3475 | ||
3476 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) | |
3477 | { | |
3478 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3479 | struct drm_device *dev = node->minor->dev; | |
3480 | struct radeon_device *rdev = dev->dev_private; | |
3481 | ||
3482 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); | |
3483 | DREG32_SYS(m, rdev, VM_L2_STATUS); | |
3484 | return 0; | |
3485 | } | |
3486 | ||
3487 | static struct drm_info_list r600_mc_info_list[] = { | |
3488 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, | |
3489 | {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, | |
3490 | }; | |
3491 | #endif | |
3492 | ||
3493 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) | |
3494 | { | |
3495 | #if defined(CONFIG_DEBUG_FS) | |
3496 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); | |
3497 | #else | |
3498 | return 0; | |
3499 | #endif | |
771fe6b9 | 3500 | } |
062b389c JG |
3501 | |
3502 | /** | |
3503 | * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl | |
3504 | * rdev: radeon device structure | |
3505 | * bo: buffer object struct which userspace is waiting for idle | |
3506 | * | |
3507 | * Some R6XX/R7XX doesn't seems to take into account HDP flush performed | |
3508 | * through ring buffer, this leads to corruption in rendering, see | |
3509 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we | |
3510 | * directly perform HDP flush by writing register through MMIO. | |
3511 | */ | |
3512 | void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) | |
3513 | { | |
3514 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
3515 | } |