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drm/radeon/kms/r700: fix some typos in chip init
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/seq_file.h>
29#include <linux/firmware.h>
30#include <linux/platform_device.h>
771fe6b9 31#include "drmP.h"
3ce0a23d 32#include "radeon_drm.h"
771fe6b9 33#include "radeon.h"
3ce0a23d 34#include "radeon_mode.h"
3ce0a23d 35#include "r600d.h"
3ce0a23d 36#include "atom.h"
d39c3b89 37#include "avivod.h"
771fe6b9 38
3ce0a23d
JG		 39#define PFP_UCODE_SIZE 576
40#define PM4_UCODE_SIZE 1792
41#define R700_PFP_UCODE_SIZE 848
42#define R700_PM4_UCODE_SIZE 1360
43
44/* Firmware Names */
45MODULE_FIRMWARE("radeon/R600_pfp.bin");
46MODULE_FIRMWARE("radeon/R600_me.bin");
47MODULE_FIRMWARE("radeon/RV610_pfp.bin");
48MODULE_FIRMWARE("radeon/RV610_me.bin");
49MODULE_FIRMWARE("radeon/RV630_pfp.bin");
50MODULE_FIRMWARE("radeon/RV630_me.bin");
51MODULE_FIRMWARE("radeon/RV620_pfp.bin");
52MODULE_FIRMWARE("radeon/RV620_me.bin");
53MODULE_FIRMWARE("radeon/RV635_pfp.bin");
54MODULE_FIRMWARE("radeon/RV635_me.bin");
55MODULE_FIRMWARE("radeon/RV670_pfp.bin");
56MODULE_FIRMWARE("radeon/RV670_me.bin");
57MODULE_FIRMWARE("radeon/RS780_pfp.bin");
58MODULE_FIRMWARE("radeon/RS780_me.bin");
59MODULE_FIRMWARE("radeon/RV770_pfp.bin");
60MODULE_FIRMWARE("radeon/RV770_me.bin");
61MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62MODULE_FIRMWARE("radeon/RV730_me.bin");
63MODULE_FIRMWARE("radeon/RV710_pfp.bin");
64MODULE_FIRMWARE("radeon/RV710_me.bin");
65
66int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 67
1a029b76 68/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 69int r600_mc_wait_for_idle(struct radeon_device *rdev);
70void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 71void r600_fini(struct radeon_device *rdev);
771fe6b9 72
771fe6b9 73/*
3ce0a23d 74 * R600 PCIE GART
771fe6b9 75 */
3ce0a23d 76int r600_gart_clear_page(struct radeon_device *rdev, int i)
771fe6b9 77{
3ce0a23d
JG		 78 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
79 u64 pte;
771fe6b9 80
3ce0a23d
JG		 81 if (i < 0 || i > rdev->gart.num_gpu_pages)
82 return -EINVAL;
83 pte = 0;
84 writeq(pte, ((void __iomem *)ptr) + (i * 8));
85 return 0;
86}
771fe6b9 87
3ce0a23d
JG		 88void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
89{
90 unsigned i;
91 u32 tmp;
92
93 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
94 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
95 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
96 for (i = 0; i < rdev->usec_timeout; i++) {
97 /* read MC_STATUS */
98 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
99 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
100 if (tmp == 2) {
101 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
102 return;
103 }
104 if (tmp) {
105 return;
106 }
107 udelay(1);
108 }
109}
110
4aac0473 111int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 112{
4aac0473 113 int r;
3ce0a23d 114
4aac0473
JG		 115 if (rdev->gart.table.vram.robj) {
116 WARN(1, "R600 PCIE GART already initialized.\n");
117 return 0;
118 }
3ce0a23d
JG		 119 /* Initialize common gart structure */
120 r = radeon_gart_init(rdev);
4aac0473 121 if (r)
3ce0a23d 122 return r;
3ce0a23d 123 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 124 return radeon_gart_table_vram_alloc(rdev);
125}
126
127int r600_pcie_gart_enable(struct radeon_device *rdev)
128{
129 u32 tmp;
130 int r, i;
131
132 if (rdev->gart.table.vram.robj == NULL) {
133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
134 return -EINVAL;
771fe6b9 135 }
4aac0473
JG		 136 r = radeon_gart_table_vram_pin(rdev);
137 if (r)
138 return r;
bc1a631e 139
3ce0a23d
JG		 140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
150 ENABLE_WAIT_L2_QUERY;
151 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
152 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
153 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
154 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
155 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
156 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
157 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
158 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
159 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
160 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
161 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
162 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
163 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
164 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
165 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 166 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 167 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
168 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
169 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
170 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
171 (u32)(rdev->dummy_page.addr >> 12));
172 for (i = 1; i < 7; i++)
173 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 174
3ce0a23d
JG		 175 r600_pcie_gart_tlb_flush(rdev);
176 rdev->gart.ready = true;
771fe6b9
JG		 177 return 0;
178}
179
3ce0a23d 180void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 181{
3ce0a23d
JG		 182 u32 tmp;
183 int i;
771fe6b9 184
3ce0a23d
JG		 185 /* Disable all tables */
186 for (i = 0; i < 7; i++)
187 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 188
3ce0a23d
JG		 189 /* Disable L2 cache */
190 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
191 EFFECTIVE_L2_QUEUE_SIZE(7));
192 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
193 /* Setup L1 TLB control */
194 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
195 ENABLE_WAIT_L2_QUERY;
196 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
197 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
198 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
199 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
200 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
201 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
202 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
203 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
204 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
205 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
206 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
207 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473
JG		 210 if (rdev->gart.table.vram.robj) {
211 radeon_object_kunmap(rdev->gart.table.vram.robj);
212 radeon_object_unpin(rdev->gart.table.vram.robj);
213 }
214}
215
216void r600_pcie_gart_fini(struct radeon_device *rdev)
217{
218 r600_pcie_gart_disable(rdev);
219 radeon_gart_table_vram_free(rdev);
220 radeon_gart_fini(rdev);
771fe6b9
JG		 221}
222
1a029b76
JG		 223void r600_agp_enable(struct radeon_device *rdev)
224{
225 u32 tmp;
226 int i;
227
228 /* Setup L2 cache */
229 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
230 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
231 EFFECTIVE_L2_QUEUE_SIZE(7));
232 WREG32(VM_L2_CNTL2, 0);
233 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
234 /* Setup TLB control */
235 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
236 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
237 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
238 ENABLE_WAIT_L2_QUERY;
239 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
240 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
241 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
242 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
243 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
244 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
245 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
246 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
247 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
248 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
249 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
250 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
251 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
252 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
253 for (i = 0; i < 7; i++)
254 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
255}
256
771fe6b9
JG		 257int r600_mc_wait_for_idle(struct radeon_device *rdev)
258{
3ce0a23d
JG		 259 unsigned i;
260 u32 tmp;
261
262 for (i = 0; i < rdev->usec_timeout; i++) {
263 /* read MC_STATUS */
264 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
265 if (!tmp)
266 return 0;
267 udelay(1);
268 }
269 return -1;
771fe6b9
JG		 270}
271
a3c1945a 272static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 273{
a3c1945a 274 struct rv515_mc_save save;
3ce0a23d
JG		 275 u32 tmp;
276 int i, j;
771fe6b9 277
3ce0a23d
JG		 278 /* Initialize HDP */
279 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
280 WREG32((0x2c14 + j), 0x00000000);
281 WREG32((0x2c18 + j), 0x00000000);
282 WREG32((0x2c1c + j), 0x00000000);
283 WREG32((0x2c20 + j), 0x00000000);
284 WREG32((0x2c24 + j), 0x00000000);
285 }
286 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 287
a3c1945a 288 rv515_mc_stop(rdev, &save);
3ce0a23d 289 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 290 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 291 }
a3c1945a 292 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 293 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 294 /* Update configuration */
1a029b76
JG		 295 if (rdev->flags & RADEON_IS_AGP) {
296 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
297 /* VRAM before AGP */
298 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
299 rdev->mc.vram_start >> 12);
300 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
301 rdev->mc.gtt_end >> 12);
302 } else {
303 /* VRAM after AGP */
304 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
305 rdev->mc.gtt_start >> 12);
306 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
307 rdev->mc.vram_end >> 12);
308 }
309 } else {
310 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
311 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
312 }
3ce0a23d 313 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 314 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 315 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
316 WREG32(MC_VM_FB_LOCATION, tmp);
317 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
318 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1a029b76 319 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
3ce0a23d 320 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 321 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
322 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 323 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
324 } else {
325 WREG32(MC_VM_AGP_BASE, 0);
326 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
327 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
328 }
3ce0a23d 329 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 330 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 331 }
a3c1945a 332 rv515_mc_resume(rdev, &save);
698443d9
DA		 333 /* we need to own VRAM, so turn off the VGA renderer here
334 * to stop it overwriting our objects */
d39c3b89 335 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 336}
337
338int r600_mc_init(struct radeon_device *rdev)
771fe6b9 339{
3ce0a23d
JG		 340 fixed20_12 a;
341 u32 tmp;
5885b7a9 342 int chansize, numchan;
3ce0a23d 343 int r;
771fe6b9 344
3ce0a23d 345 /* Get VRAM informations */
771fe6b9 346 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 347 tmp = RREG32(RAMCFG);
348 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 349 chansize = 16;
3ce0a23d 350 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 351 chansize = 64;
352 } else {
353 chansize = 32;
354 }
5885b7a9
AD		 355 tmp = RREG32(CHMAP);
356 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
357 case 0:
358 default:
359 numchan = 1;
360 break;
361 case 1:
362 numchan = 2;
363 break;
364 case 2:
365 numchan = 4;
366 break;
367 case 3:
368 numchan = 8;
369 break;
771fe6b9 370 }
5885b7a9 371 rdev->mc.vram_width = numchan * chansize;
3ce0a23d
JG		 372 /* Could aper size report 0 ? */
373 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
374 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
375 /* Setup GPU memory space */
376 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
377 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
974b16e3
AD		 378
379 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
380 rdev->mc.mc_vram_size = rdev->mc.aper_size;
381
382 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
383 rdev->mc.real_vram_size = rdev->mc.aper_size;
384
3ce0a23d
JG		 385 if (rdev->flags & RADEON_IS_AGP) {
386 r = radeon_agp_init(rdev);
387 if (r)
388 return r;
389 /* gtt_size is setup by radeon_agp_init */
390 rdev->mc.gtt_location = rdev->mc.agp_base;
391 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
392 /* Try to put vram before or after AGP because we
393 * we want SYSTEM_APERTURE to cover both VRAM and
394 * AGP so that GPU can catch out of VRAM/AGP access
395 */
396 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
397 /* Enought place before */
398 rdev->mc.vram_location = rdev->mc.gtt_location -
399 rdev->mc.mc_vram_size;
400 } else if (tmp > rdev->mc.mc_vram_size) {
401 /* Enought place after */
402 rdev->mc.vram_location = rdev->mc.gtt_location +
403 rdev->mc.gtt_size;
404 } else {
405 /* Try to setup VRAM then AGP might not
406 * not work on some card
407 */
408 rdev->mc.vram_location = 0x00000000UL;
409 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
410 }
411 } else {
4d357abb
DA		 412 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
413 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
414 0xFFFF) << 24;
415 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
416 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
417 /* Enough place after vram */
418 rdev->mc.gtt_location = tmp;
419 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
420 /* Enough place before vram */
421 rdev->mc.gtt_location = 0;
422 } else {
423 /* Not enough place after or before shrink
424 * gart size
425 */
426 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
3ce0a23d 427 rdev->mc.gtt_location = 0;
4d357abb 428 rdev->mc.gtt_size = rdev->mc.vram_location;
3ce0a23d 429 } else {
4d357abb
DA		 430 rdev->mc.gtt_location = tmp;
431 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
3ce0a23d 432 }
3ce0a23d 433 }
4d357abb 434 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
3ce0a23d
JG		 435 }
436 rdev->mc.vram_start = rdev->mc.vram_location;
1a029b76 437 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
3ce0a23d 438 rdev->mc.gtt_start = rdev->mc.gtt_location;
1a029b76 439 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
3ce0a23d
JG		 440 /* FIXME: we should enforce default clock in case GPU is not in
441 * default setup
442 */
443 a.full = rfixed_const(100);
444 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
445 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
446 return 0;
771fe6b9
JG		 447}
448
3ce0a23d
JG		 449/* We doesn't check that the GPU really needs a reset we simply do the
450 * reset, it's up to the caller to determine if the GPU needs one. We
451 * might add an helper function to check that.
452 */
453int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 454{
a3c1945a 455 struct rv515_mc_save save;
3ce0a23d
JG		 456 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
457 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
458 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
459 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
460 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
461 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
462 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
463 S_008010_GUI_ACTIVE(1);
464 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
465 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
466 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
467 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
468 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
469 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
470 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
471 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
472 u32 srbm_reset = 0;
a3c1945a 473 u32 tmp;
771fe6b9 474
1a029b76
JG		 475 dev_info(rdev->dev, "GPU softreset \n");
476 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
477 RREG32(R_008010_GRBM_STATUS));
478 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 479 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 480 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
481 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 482 rv515_mc_stop(rdev, &save);
483 if (r600_mc_wait_for_idle(rdev)) {
484 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
485 }
3ce0a23d
JG		 486 /* Disable CP parsing/prefetching */
487 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
488 /* Check if any of the rendering block is busy and reset it */
489 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
490 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 491 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 492 S_008020_SOFT_RESET_DB(1) |
493 S_008020_SOFT_RESET_CB(1) |
494 S_008020_SOFT_RESET_PA(1) |
495 S_008020_SOFT_RESET_SC(1) |
496 S_008020_SOFT_RESET_SMX(1) |
497 S_008020_SOFT_RESET_SPI(1) |
498 S_008020_SOFT_RESET_SX(1) |
499 S_008020_SOFT_RESET_SH(1) |
500 S_008020_SOFT_RESET_TC(1) |
501 S_008020_SOFT_RESET_TA(1) |
502 S_008020_SOFT_RESET_VC(1) |
a3c1945a 503 S_008020_SOFT_RESET_VGT(1);
1a029b76 504 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 505 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
3ce0a23d
JG		 506 (void)RREG32(R_008020_GRBM_SOFT_RESET);
507 udelay(50);
508 WREG32(R_008020_GRBM_SOFT_RESET, 0);
509 (void)RREG32(R_008020_GRBM_SOFT_RESET);
510 }
511 /* Reset CP (we always reset CP) */
a3c1945a
JG		 512 tmp = S_008020_SOFT_RESET_CP(1);
513 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
514 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
3ce0a23d
JG		 515 (void)RREG32(R_008020_GRBM_SOFT_RESET);
516 udelay(50);
517 WREG32(R_008020_GRBM_SOFT_RESET, 0);
518 (void)RREG32(R_008020_GRBM_SOFT_RESET);
519 /* Reset others GPU block if necessary */
520 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
521 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
522 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
523 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
524 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
525 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
526 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
527 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
528 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
529 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
530 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
531 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
532 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
533 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
534 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
535 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
536 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
537 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
538 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
539 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
540 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
541 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
1a029b76
JG		 542 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
543 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
544 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
545 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
546 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
547 udelay(50);
548 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
549 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
3ce0a23d
JG		 550 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
551 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
552 udelay(50);
553 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
554 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
555 /* Wait a little for things to settle down */
556 udelay(50);
1a029b76
JG		 557 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
558 RREG32(R_008010_GRBM_STATUS));
559 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
560 RREG32(R_008014_GRBM_STATUS2));
561 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
562 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 563 /* After reset we need to reinit the asic as GPU often endup in an
564 * incoherent state.
565 */
566 atom_asic_init(rdev->mode_info.atom_context);
567 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 568 return 0;
569}
570
571int r600_gpu_reset(struct radeon_device *rdev)
572{
573 return r600_gpu_soft_reset(rdev);
574}
575
576static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
577 u32 num_backends,
578 u32 backend_disable_mask)
579{
580 u32 backend_map = 0;
581 u32 enabled_backends_mask;
582 u32 enabled_backends_count;
583 u32 cur_pipe;
584 u32 swizzle_pipe[R6XX_MAX_PIPES];
585 u32 cur_backend;
586 u32 i;
587
588 if (num_tile_pipes > R6XX_MAX_PIPES)
589 num_tile_pipes = R6XX_MAX_PIPES;
590 if (num_tile_pipes < 1)
591 num_tile_pipes = 1;
592 if (num_backends > R6XX_MAX_BACKENDS)
593 num_backends = R6XX_MAX_BACKENDS;
594 if (num_backends < 1)
595 num_backends = 1;
596
597 enabled_backends_mask = 0;
598 enabled_backends_count = 0;
599 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
600 if (((backend_disable_mask >> i) & 1) == 0) {
601 enabled_backends_mask |= (1 << i);
602 ++enabled_backends_count;
603 }
604 if (enabled_backends_count == num_backends)
605 break;
606 }
607
608 if (enabled_backends_count == 0) {
609 enabled_backends_mask = 1;
610 enabled_backends_count = 1;
611 }
612
613 if (enabled_backends_count != num_backends)
614 num_backends = enabled_backends_count;
615
616 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
617 switch (num_tile_pipes) {
618 case 1:
619 swizzle_pipe[0] = 0;
620 break;
621 case 2:
622 swizzle_pipe[0] = 0;
623 swizzle_pipe[1] = 1;
624 break;
625 case 3:
626 swizzle_pipe[0] = 0;
627 swizzle_pipe[1] = 1;
628 swizzle_pipe[2] = 2;
629 break;
630 case 4:
631 swizzle_pipe[0] = 0;
632 swizzle_pipe[1] = 1;
633 swizzle_pipe[2] = 2;
634 swizzle_pipe[3] = 3;
635 break;
636 case 5:
637 swizzle_pipe[0] = 0;
638 swizzle_pipe[1] = 1;
639 swizzle_pipe[2] = 2;
640 swizzle_pipe[3] = 3;
641 swizzle_pipe[4] = 4;
642 break;
643 case 6:
644 swizzle_pipe[0] = 0;
645 swizzle_pipe[1] = 2;
646 swizzle_pipe[2] = 4;
647 swizzle_pipe[3] = 5;
648 swizzle_pipe[4] = 1;
649 swizzle_pipe[5] = 3;
650 break;
651 case 7:
652 swizzle_pipe[0] = 0;
653 swizzle_pipe[1] = 2;
654 swizzle_pipe[2] = 4;
655 swizzle_pipe[3] = 6;
656 swizzle_pipe[4] = 1;
657 swizzle_pipe[5] = 3;
658 swizzle_pipe[6] = 5;
659 break;
660 case 8:
661 swizzle_pipe[0] = 0;
662 swizzle_pipe[1] = 2;
663 swizzle_pipe[2] = 4;
664 swizzle_pipe[3] = 6;
665 swizzle_pipe[4] = 1;
666 swizzle_pipe[5] = 3;
667 swizzle_pipe[6] = 5;
668 swizzle_pipe[7] = 7;
669 break;
670 }
671
672 cur_backend = 0;
673 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
674 while (((1 << cur_backend) & enabled_backends_mask) == 0)
675 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
676
677 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
678
679 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
680 }
681
682 return backend_map;
683}
684
685int r600_count_pipe_bits(uint32_t val)
686{
687 int i, ret = 0;
688
689 for (i = 0; i < 32; i++) {
690 ret += val & 1;
691 val >>= 1;
692 }
693 return ret;
771fe6b9
JG		 694}
695
3ce0a23d
JG		 696void r600_gpu_init(struct radeon_device *rdev)
697{
698 u32 tiling_config;
699 u32 ramcfg;
700 u32 tmp;
701 int i, j;
702 u32 sq_config;
703 u32 sq_gpr_resource_mgmt_1 = 0;
704 u32 sq_gpr_resource_mgmt_2 = 0;
705 u32 sq_thread_resource_mgmt = 0;
706 u32 sq_stack_resource_mgmt_1 = 0;
707 u32 sq_stack_resource_mgmt_2 = 0;
708
709 /* FIXME: implement */
710 switch (rdev->family) {
711 case CHIP_R600:
712 rdev->config.r600.max_pipes = 4;
713 rdev->config.r600.max_tile_pipes = 8;
714 rdev->config.r600.max_simds = 4;
715 rdev->config.r600.max_backends = 4;
716 rdev->config.r600.max_gprs = 256;
717 rdev->config.r600.max_threads = 192;
718 rdev->config.r600.max_stack_entries = 256;
719 rdev->config.r600.max_hw_contexts = 8;
720 rdev->config.r600.max_gs_threads = 16;
721 rdev->config.r600.sx_max_export_size = 128;
722 rdev->config.r600.sx_max_export_pos_size = 16;
723 rdev->config.r600.sx_max_export_smx_size = 128;
724 rdev->config.r600.sq_num_cf_insts = 2;
725 break;
726 case CHIP_RV630:
727 case CHIP_RV635:
728 rdev->config.r600.max_pipes = 2;
729 rdev->config.r600.max_tile_pipes = 2;
730 rdev->config.r600.max_simds = 3;
731 rdev->config.r600.max_backends = 1;
732 rdev->config.r600.max_gprs = 128;
733 rdev->config.r600.max_threads = 192;
734 rdev->config.r600.max_stack_entries = 128;
735 rdev->config.r600.max_hw_contexts = 8;
736 rdev->config.r600.max_gs_threads = 4;
737 rdev->config.r600.sx_max_export_size = 128;
738 rdev->config.r600.sx_max_export_pos_size = 16;
739 rdev->config.r600.sx_max_export_smx_size = 128;
740 rdev->config.r600.sq_num_cf_insts = 2;
741 break;
742 case CHIP_RV610:
743 case CHIP_RV620:
744 case CHIP_RS780:
745 case CHIP_RS880:
746 rdev->config.r600.max_pipes = 1;
747 rdev->config.r600.max_tile_pipes = 1;
748 rdev->config.r600.max_simds = 2;
749 rdev->config.r600.max_backends = 1;
750 rdev->config.r600.max_gprs = 128;
751 rdev->config.r600.max_threads = 192;
752 rdev->config.r600.max_stack_entries = 128;
753 rdev->config.r600.max_hw_contexts = 4;
754 rdev->config.r600.max_gs_threads = 4;
755 rdev->config.r600.sx_max_export_size = 128;
756 rdev->config.r600.sx_max_export_pos_size = 16;
757 rdev->config.r600.sx_max_export_smx_size = 128;
758 rdev->config.r600.sq_num_cf_insts = 1;
759 break;
760 case CHIP_RV670:
761 rdev->config.r600.max_pipes = 4;
762 rdev->config.r600.max_tile_pipes = 4;
763 rdev->config.r600.max_simds = 4;
764 rdev->config.r600.max_backends = 4;
765 rdev->config.r600.max_gprs = 192;
766 rdev->config.r600.max_threads = 192;
767 rdev->config.r600.max_stack_entries = 256;
768 rdev->config.r600.max_hw_contexts = 8;
769 rdev->config.r600.max_gs_threads = 16;
770 rdev->config.r600.sx_max_export_size = 128;
771 rdev->config.r600.sx_max_export_pos_size = 16;
772 rdev->config.r600.sx_max_export_smx_size = 128;
773 rdev->config.r600.sq_num_cf_insts = 2;
774 break;
775 default:
776 break;
777 }
778
779 /* Initialize HDP */
780 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
781 WREG32((0x2c14 + j), 0x00000000);
782 WREG32((0x2c18 + j), 0x00000000);
783 WREG32((0x2c1c + j), 0x00000000);
784 WREG32((0x2c20 + j), 0x00000000);
785 WREG32((0x2c24 + j), 0x00000000);
786 }
787
788 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
789
790 /* Setup tiling */
791 tiling_config = 0;
792 ramcfg = RREG32(RAMCFG);
793 switch (rdev->config.r600.max_tile_pipes) {
794 case 1:
795 tiling_config |= PIPE_TILING(0);
796 break;
797 case 2:
798 tiling_config |= PIPE_TILING(1);
799 break;
800 case 4:
801 tiling_config |= PIPE_TILING(2);
802 break;
803 case 8:
804 tiling_config |= PIPE_TILING(3);
805 break;
806 default:
807 break;
808 }
809 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
810 tiling_config |= GROUP_SIZE(0);
811 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
812 if (tmp > 3) {
813 tiling_config |= ROW_TILING(3);
814 tiling_config |= SAMPLE_SPLIT(3);
815 } else {
816 tiling_config |= ROW_TILING(tmp);
817 tiling_config |= SAMPLE_SPLIT(tmp);
818 }
819 tiling_config |= BANK_SWAPS(1);
820 tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
821 rdev->config.r600.max_backends,
822 (0xff << rdev->config.r600.max_backends) & 0xff);
823 tiling_config |= BACKEND_MAP(tmp);
824 WREG32(GB_TILING_CONFIG, tiling_config);
825 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
826 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
827
828 tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
829 WREG32(CC_RB_BACKEND_DISABLE, tmp);
830
831 /* Setup pipes */
832 tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
833 tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
834 WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
835 WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
836
837 tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
838 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
839 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
840
841 /* Setup some CP states */
842 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
843 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
844
845 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
846 SYNC_WALKER | SYNC_ALIGNER));
847 /* Setup various GPU states */
848 if (rdev->family == CHIP_RV670)
849 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
850
851 tmp = RREG32(SX_DEBUG_1);
852 tmp |= SMX_EVENT_RELEASE;
853 if ((rdev->family > CHIP_R600))
854 tmp |= ENABLE_NEW_SMX_ADDRESS;
855 WREG32(SX_DEBUG_1, tmp);
856
857 if (((rdev->family) == CHIP_R600) ||
858 ((rdev->family) == CHIP_RV630) ||
859 ((rdev->family) == CHIP_RV610) ||
860 ((rdev->family) == CHIP_RV620) ||
861 ((rdev->family) == CHIP_RS780)) {
862 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
863 } else {
864 WREG32(DB_DEBUG, 0);
865 }
866 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
867 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
868
869 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
870 WREG32(VGT_NUM_INSTANCES, 0);
871
872 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
873 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
874
875 tmp = RREG32(SQ_MS_FIFO_SIZES);
876 if (((rdev->family) == CHIP_RV610) ||
877 ((rdev->family) == CHIP_RV620) ||
878 ((rdev->family) == CHIP_RS780)) {
879 tmp = (CACHE_FIFO_SIZE(0xa) |
880 FETCH_FIFO_HIWATER(0xa) |
881 DONE_FIFO_HIWATER(0xe0) |
882 ALU_UPDATE_FIFO_HIWATER(0x8));
883 } else if (((rdev->family) == CHIP_R600) ||
884 ((rdev->family) == CHIP_RV630)) {
885 tmp &= ~DONE_FIFO_HIWATER(0xff);
886 tmp |= DONE_FIFO_HIWATER(0x4);
887 }
888 WREG32(SQ_MS_FIFO_SIZES, tmp);
889
890 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
891 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
892 */
893 sq_config = RREG32(SQ_CONFIG);
894 sq_config &= ~(PS_PRIO(3) |
895 VS_PRIO(3) |
896 GS_PRIO(3) |
897 ES_PRIO(3));
898 sq_config |= (DX9_CONSTS |
899 VC_ENABLE |
900 PS_PRIO(0) |
901 VS_PRIO(1) |
902 GS_PRIO(2) |
903 ES_PRIO(3));
904
905 if ((rdev->family) == CHIP_R600) {
906 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
907 NUM_VS_GPRS(124) |
908 NUM_CLAUSE_TEMP_GPRS(4));
909 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
910 NUM_ES_GPRS(0));
911 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
912 NUM_VS_THREADS(48) |
913 NUM_GS_THREADS(4) |
914 NUM_ES_THREADS(4));
915 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
916 NUM_VS_STACK_ENTRIES(128));
917 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
918 NUM_ES_STACK_ENTRIES(0));
919 } else if (((rdev->family) == CHIP_RV610) ||
920 ((rdev->family) == CHIP_RV620) ||
921 ((rdev->family) == CHIP_RS780)) {
922 /* no vertex cache */
923 sq_config &= ~VC_ENABLE;
924
925 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
926 NUM_VS_GPRS(44) |
927 NUM_CLAUSE_TEMP_GPRS(2));
928 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
929 NUM_ES_GPRS(17));
930 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
931 NUM_VS_THREADS(78) |
932 NUM_GS_THREADS(4) |
933 NUM_ES_THREADS(31));
934 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
935 NUM_VS_STACK_ENTRIES(40));
936 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
937 NUM_ES_STACK_ENTRIES(16));
938 } else if (((rdev->family) == CHIP_RV630) ||
939 ((rdev->family) == CHIP_RV635)) {
940 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
941 NUM_VS_GPRS(44) |
942 NUM_CLAUSE_TEMP_GPRS(2));
943 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
944 NUM_ES_GPRS(18));
945 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
946 NUM_VS_THREADS(78) |
947 NUM_GS_THREADS(4) |
948 NUM_ES_THREADS(31));
949 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
950 NUM_VS_STACK_ENTRIES(40));
951 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
952 NUM_ES_STACK_ENTRIES(16));
953 } else if ((rdev->family) == CHIP_RV670) {
954 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
955 NUM_VS_GPRS(44) |
956 NUM_CLAUSE_TEMP_GPRS(2));
957 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
958 NUM_ES_GPRS(17));
959 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
960 NUM_VS_THREADS(78) |
961 NUM_GS_THREADS(4) |
962 NUM_ES_THREADS(31));
963 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
964 NUM_VS_STACK_ENTRIES(64));
965 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
966 NUM_ES_STACK_ENTRIES(64));
967 }
968
969 WREG32(SQ_CONFIG, sq_config);
970 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
971 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
972 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
973 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
974 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
975
976 if (((rdev->family) == CHIP_RV610) ||
977 ((rdev->family) == CHIP_RV620) ||
978 ((rdev->family) == CHIP_RS780)) {
979 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
980 } else {
981 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
982 }
983
984 /* More default values. 2D/3D driver should adjust as needed */
985 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
986 S1_X(0x4) | S1_Y(0xc)));
987 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
988 S1_X(0x2) | S1_Y(0x2) |
989 S2_X(0xa) | S2_Y(0x6) |
990 S3_X(0x6) | S3_Y(0xa)));
991 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
992 S1_X(0x4) | S1_Y(0xc) |
993 S2_X(0x1) | S2_Y(0x6) |
994 S3_X(0xa) | S3_Y(0xe)));
995 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
996 S5_X(0x0) | S5_Y(0x0) |
997 S6_X(0xb) | S6_Y(0x4) |
998 S7_X(0x7) | S7_Y(0x8)));
999
1000 WREG32(VGT_STRMOUT_EN, 0);
1001 tmp = rdev->config.r600.max_pipes * 16;
1002 switch (rdev->family) {
1003 case CHIP_RV610:
1004 case CHIP_RS780:
1005 case CHIP_RV620:
1006 tmp += 32;
1007 break;
1008 case CHIP_RV670:
1009 tmp += 128;
1010 break;
1011 default:
1012 break;
1013 }
1014 if (tmp > 256) {
1015 tmp = 256;
1016 }
1017 WREG32(VGT_ES_PER_GS, 128);
1018 WREG32(VGT_GS_PER_ES, tmp);
1019 WREG32(VGT_GS_PER_VS, 2);
1020 WREG32(VGT_GS_VERTEX_REUSE, 16);
1021
1022 /* more default values. 2D/3D driver should adjust as needed */
1023 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1024 WREG32(VGT_STRMOUT_EN, 0);
1025 WREG32(SX_MISC, 0);
1026 WREG32(PA_SC_MODE_CNTL, 0);
1027 WREG32(PA_SC_AA_CONFIG, 0);
1028 WREG32(PA_SC_LINE_STIPPLE, 0);
1029 WREG32(SPI_INPUT_Z, 0);
1030 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1031 WREG32(CB_COLOR7_FRAG, 0);
1032
1033 /* Clear render buffer base addresses */
1034 WREG32(CB_COLOR0_BASE, 0);
1035 WREG32(CB_COLOR1_BASE, 0);
1036 WREG32(CB_COLOR2_BASE, 0);
1037 WREG32(CB_COLOR3_BASE, 0);
1038 WREG32(CB_COLOR4_BASE, 0);
1039 WREG32(CB_COLOR5_BASE, 0);
1040 WREG32(CB_COLOR6_BASE, 0);
1041 WREG32(CB_COLOR7_BASE, 0);
1042 WREG32(CB_COLOR7_FRAG, 0);
1043
1044 switch (rdev->family) {
1045 case CHIP_RV610:
1046 case CHIP_RS780:
1047 case CHIP_RV620:
1048 tmp = TC_L2_SIZE(8);
1049 break;
1050 case CHIP_RV630:
1051 case CHIP_RV635:
1052 tmp = TC_L2_SIZE(4);
1053 break;
1054 case CHIP_R600:
1055 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1056 break;
1057 default:
1058 tmp = TC_L2_SIZE(0);
1059 break;
1060 }
1061 WREG32(TC_CNTL, tmp);
1062
1063 tmp = RREG32(HDP_HOST_PATH_CNTL);
1064 WREG32(HDP_HOST_PATH_CNTL, tmp);
1065
1066 tmp = RREG32(ARB_POP);
1067 tmp |= ENABLE_TC128;
1068 WREG32(ARB_POP, tmp);
1069
1070 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1071 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1072 NUM_CLIP_SEQ(3)));
1073 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1074}
1075
1076
771fe6b9
JG		 1077/*
1078 * Indirect registers accessor
1079 */
3ce0a23d
JG		 1080u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1081{
1082 u32 r;
1083
1084 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1085 (void)RREG32(PCIE_PORT_INDEX);
1086 r = RREG32(PCIE_PORT_DATA);
1087 return r;
1088}
1089
1090void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1091{
1092 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1093 (void)RREG32(PCIE_PORT_INDEX);
1094 WREG32(PCIE_PORT_DATA, (v));
1095 (void)RREG32(PCIE_PORT_DATA);
1096}
1097
1098
1099/*
1100 * CP & Ring
1101 */
1102void r600_cp_stop(struct radeon_device *rdev)
1103{
1104 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1105}
1106
1107int r600_cp_init_microcode(struct radeon_device *rdev)
1108{
1109 struct platform_device *pdev;
1110 const char *chip_name;
1111 size_t pfp_req_size, me_req_size;
1112 char fw_name[30];
1113 int err;
1114
1115 DRM_DEBUG("\n");
1116
1117 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1118 err = IS_ERR(pdev);
1119 if (err) {
1120 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1121 return -EINVAL;
1122 }
1123
1124 switch (rdev->family) {
1125 case CHIP_R600: chip_name = "R600"; break;
1126 case CHIP_RV610: chip_name = "RV610"; break;
1127 case CHIP_RV630: chip_name = "RV630"; break;
1128 case CHIP_RV620: chip_name = "RV620"; break;
1129 case CHIP_RV635: chip_name = "RV635"; break;
1130 case CHIP_RV670: chip_name = "RV670"; break;
1131 case CHIP_RS780:
1132 case CHIP_RS880: chip_name = "RS780"; break;
1133 case CHIP_RV770: chip_name = "RV770"; break;
1134 case CHIP_RV730:
1135 case CHIP_RV740: chip_name = "RV730"; break;
1136 case CHIP_RV710: chip_name = "RV710"; break;
1137 default: BUG();
1138 }
1139
1140 if (rdev->family >= CHIP_RV770) {
1141 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1142 me_req_size = R700_PM4_UCODE_SIZE * 4;
1143 } else {
1144 pfp_req_size = PFP_UCODE_SIZE * 4;
1145 me_req_size = PM4_UCODE_SIZE * 12;
1146 }
1147
1148 DRM_INFO("Loading %s CP Microcode\n", chip_name);
1149
1150 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1151 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1152 if (err)
1153 goto out;
1154 if (rdev->pfp_fw->size != pfp_req_size) {
1155 printk(KERN_ERR
1156 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1157 rdev->pfp_fw->size, fw_name);
1158 err = -EINVAL;
1159 goto out;
1160 }
1161
1162 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1163 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1164 if (err)
1165 goto out;
1166 if (rdev->me_fw->size != me_req_size) {
1167 printk(KERN_ERR
1168 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1169 rdev->me_fw->size, fw_name);
1170 err = -EINVAL;
1171 }
1172out:
1173 platform_device_unregister(pdev);
1174
1175 if (err) {
1176 if (err != -EINVAL)
1177 printk(KERN_ERR
1178 "r600_cp: Failed to load firmware \"%s\"\n",
1179 fw_name);
1180 release_firmware(rdev->pfp_fw);
1181 rdev->pfp_fw = NULL;
1182 release_firmware(rdev->me_fw);
1183 rdev->me_fw = NULL;
1184 }
1185 return err;
1186}
1187
1188static int r600_cp_load_microcode(struct radeon_device *rdev)
1189{
1190 const __be32 *fw_data;
1191 int i;
1192
1193 if (!rdev->me_fw || !rdev->pfp_fw)
1194 return -EINVAL;
1195
1196 r600_cp_stop(rdev);
1197
1198 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1199
1200 /* Reset cp */
1201 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1202 RREG32(GRBM_SOFT_RESET);
1203 mdelay(15);
1204 WREG32(GRBM_SOFT_RESET, 0);
1205
1206 WREG32(CP_ME_RAM_WADDR, 0);
1207
1208 fw_data = (const __be32 *)rdev->me_fw->data;
1209 WREG32(CP_ME_RAM_WADDR, 0);
1210 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1211 WREG32(CP_ME_RAM_DATA,
1212 be32_to_cpup(fw_data++));
1213
1214 fw_data = (const __be32 *)rdev->pfp_fw->data;
1215 WREG32(CP_PFP_UCODE_ADDR, 0);
1216 for (i = 0; i < PFP_UCODE_SIZE; i++)
1217 WREG32(CP_PFP_UCODE_DATA,
1218 be32_to_cpup(fw_data++));
1219
1220 WREG32(CP_PFP_UCODE_ADDR, 0);
1221 WREG32(CP_ME_RAM_WADDR, 0);
1222 WREG32(CP_ME_RAM_RADDR, 0);
1223 return 0;
1224}
1225
1226int r600_cp_start(struct radeon_device *rdev)
1227{
1228 int r;
1229 uint32_t cp_me;
1230
1231 r = radeon_ring_lock(rdev, 7);
1232 if (r) {
1233 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1234 return r;
1235 }
1236 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1237 radeon_ring_write(rdev, 0x1);
1238 if (rdev->family < CHIP_RV770) {
1239 radeon_ring_write(rdev, 0x3);
1240 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1241 } else {
1242 radeon_ring_write(rdev, 0x0);
1243 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1244 }
1245 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1246 radeon_ring_write(rdev, 0);
1247 radeon_ring_write(rdev, 0);
1248 radeon_ring_unlock_commit(rdev);
1249
1250 cp_me = 0xff;
1251 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1252 return 0;
1253}
1254
1255int r600_cp_resume(struct radeon_device *rdev)
1256{
1257 u32 tmp;
1258 u32 rb_bufsz;
1259 int r;
1260
1261 /* Reset cp */
1262 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1263 RREG32(GRBM_SOFT_RESET);
1264 mdelay(15);
1265 WREG32(GRBM_SOFT_RESET, 0);
1266
1267 /* Set ring buffer size */
1268 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
d6f28938 1269 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 1270#ifdef __BIG_ENDIAN
d6f28938 1271 tmp |= BUF_SWAP_32BIT;
3ce0a23d 1272#endif
d6f28938 1273 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 1274 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1275
1276 /* Set the write pointer delay */
1277 WREG32(CP_RB_WPTR_DELAY, 0);
1278
1279 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 1280 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1281 WREG32(CP_RB_RPTR_WR, 0);
1282 WREG32(CP_RB_WPTR, 0);
1283 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1284 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1285 mdelay(1);
1286 WREG32(CP_RB_CNTL, tmp);
1287
1288 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1289 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1290
1291 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1292 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1293
1294 r600_cp_start(rdev);
1295 rdev->cp.ready = true;
1296 r = radeon_ring_test(rdev);
1297 if (r) {
1298 rdev->cp.ready = false;
1299 return r;
1300 }
1301 return 0;
1302}
1303
1304void r600_cp_commit(struct radeon_device *rdev)
1305{
1306 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1307 (void)RREG32(CP_RB_WPTR);
1308}
1309
1310void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1311{
1312 u32 rb_bufsz;
1313
1314 /* Align ring size */
1315 rb_bufsz = drm_order(ring_size / 8);
1316 ring_size = (1 << (rb_bufsz + 1)) * 4;
1317 rdev->cp.ring_size = ring_size;
1318 rdev->cp.align_mask = 16 - 1;
1319}
1320
1321
1322/*
1323 * GPU scratch registers helpers function.
1324 */
1325void r600_scratch_init(struct radeon_device *rdev)
1326{
1327 int i;
1328
1329 rdev->scratch.num_reg = 7;
1330 for (i = 0; i < rdev->scratch.num_reg; i++) {
1331 rdev->scratch.free[i] = true;
1332 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1333 }
1334}
1335
1336int r600_ring_test(struct radeon_device *rdev)
1337{
1338 uint32_t scratch;
1339 uint32_t tmp = 0;
1340 unsigned i;
1341 int r;
1342
1343 r = radeon_scratch_get(rdev, &scratch);
1344 if (r) {
1345 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1346 return r;
1347 }
1348 WREG32(scratch, 0xCAFEDEAD);
1349 r = radeon_ring_lock(rdev, 3);
1350 if (r) {
1351 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1352 radeon_scratch_free(rdev, scratch);
1353 return r;
1354 }
1355 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1356 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1357 radeon_ring_write(rdev, 0xDEADBEEF);
1358 radeon_ring_unlock_commit(rdev);
1359 for (i = 0; i < rdev->usec_timeout; i++) {
1360 tmp = RREG32(scratch);
1361 if (tmp == 0xDEADBEEF)
1362 break;
1363 DRM_UDELAY(1);
1364 }
1365 if (i < rdev->usec_timeout) {
1366 DRM_INFO("ring test succeeded in %d usecs\n", i);
1367 } else {
1368 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1369 scratch, tmp);
1370 r = -EINVAL;
1371 }
1372 radeon_scratch_free(rdev, scratch);
1373 return r;
1374}
1375
81cc35bf
JG		 1376void r600_wb_disable(struct radeon_device *rdev)
1377{
1378 WREG32(SCRATCH_UMSK, 0);
1379 if (rdev->wb.wb_obj) {
1380 radeon_object_kunmap(rdev->wb.wb_obj);
1381 radeon_object_unpin(rdev->wb.wb_obj);
1382 }
1383}
1384
1385void r600_wb_fini(struct radeon_device *rdev)
1386{
1387 r600_wb_disable(rdev);
1388 if (rdev->wb.wb_obj) {
1389 radeon_object_unref(&rdev->wb.wb_obj);
1390 rdev->wb.wb = NULL;
1391 rdev->wb.wb_obj = NULL;
1392 }
1393}
1394
1395int r600_wb_enable(struct radeon_device *rdev)
3ce0a23d
JG		 1396{
1397 int r;
1398
1399 if (rdev->wb.wb_obj == NULL) {
a77f1718 1400 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
81cc35bf 1401 RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj);
3ce0a23d 1402 if (r) {
81cc35bf 1403 dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r);
3ce0a23d
JG		 1404 return r;
1405 }
81cc35bf
JG		 1406 r = radeon_object_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1407 &rdev->wb.gpu_addr);
3ce0a23d 1408 if (r) {
81cc35bf
JG		 1409 dev_warn(rdev->dev, "failed to pin WB buffer (%d).\n", r);
1410 r600_wb_fini(rdev);
3ce0a23d
JG		 1411 return r;
1412 }
1413 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1414 if (r) {
81cc35bf
JG		 1415 dev_warn(rdev->dev, "failed to map WB buffer (%d).\n", r);
1416 r600_wb_fini(rdev);
3ce0a23d
JG		 1417 return r;
1418 }
1419 }
1420 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1421 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1422 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1423 WREG32(SCRATCH_UMSK, 0xff);
1424 return 0;
1425}
1426
3ce0a23d
JG		 1427void r600_fence_ring_emit(struct radeon_device *rdev,
1428 struct radeon_fence *fence)
1429{
1430 /* Emit fence sequence & fire IRQ */
1431 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1432 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1433 radeon_ring_write(rdev, fence->seq);
1434}
1435
1436int r600_copy_dma(struct radeon_device *rdev,
1437 uint64_t src_offset,
1438 uint64_t dst_offset,
1439 unsigned num_pages,
1440 struct radeon_fence *fence)
1441{
1442 /* FIXME: implement */
1443 return 0;
1444}
1445
1446int r600_copy_blit(struct radeon_device *rdev,
1447 uint64_t src_offset, uint64_t dst_offset,
1448 unsigned num_pages, struct radeon_fence *fence)
1449{
a77f1718
MT		 1450 r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1451 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d
JG		 1452 r600_blit_done_copy(rdev, fence);
1453 return 0;
1454}
1455
1456int r600_irq_process(struct radeon_device *rdev)
1457{
1458 /* FIXME: implement */
1459 return 0;
1460}
1461
1462int r600_irq_set(struct radeon_device *rdev)
1463{
1464 /* FIXME: implement */
1465 return 0;
1466}
1467
1468int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1469 uint32_t tiling_flags, uint32_t pitch,
1470 uint32_t offset, uint32_t obj_size)
1471{
1472 /* FIXME: implement */
1473 return 0;
1474}
1475
1476void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1477{
1478 /* FIXME: implement */
1479}
1480
1481
1482bool r600_card_posted(struct radeon_device *rdev)
1483{
1484 uint32_t reg;
1485
1486 /* first check CRTCs */
1487 reg = RREG32(D1CRTC_CONTROL) |
1488 RREG32(D2CRTC_CONTROL);
1489 if (reg & CRTC_EN)
1490 return true;
1491
1492 /* then check MEM_SIZE, in case the crtcs are off */
1493 if (RREG32(CONFIG_MEMSIZE))
1494 return true;
1495
1496 return false;
1497}
1498
fc30b8ef 1499int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 1500{
1501 int r;
1502
a3c1945a 1503 r600_mc_program(rdev);
1a029b76
JG		 1504 if (rdev->flags & RADEON_IS_AGP) {
1505 r600_agp_enable(rdev);
1506 } else {
1507 r = r600_pcie_gart_enable(rdev);
1508 if (r)
1509 return r;
1510 }
3ce0a23d 1511 r600_gpu_init(rdev);
bc1a631e
DA		 1512
1513 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1514 &rdev->r600_blit.shader_gpu_addr);
1515 if (r) {
1516 DRM_ERROR("failed to pin blit object %d\n", r);
1517 return r;
1518 }
1519
3ce0a23d
JG		 1520 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1521 if (r)
1522 return r;
1523 r = r600_cp_load_microcode(rdev);
1524 if (r)
1525 return r;
1526 r = r600_cp_resume(rdev);
1527 if (r)
1528 return r;
81cc35bf
JG		 1529 /* write back buffer are not vital so don't worry about failure */
1530 r600_wb_enable(rdev);
3ce0a23d
JG		 1531 return 0;
1532}
1533
fc30b8ef
DA		 1534int r600_resume(struct radeon_device *rdev)
1535{
1536 int r;
1537
1a029b76
JG		 1538 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1539 * posting will perform necessary task to bring back GPU into good
1540 * shape.
1541 */
fc30b8ef 1542 /* post card */
e7d40b9a 1543 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 1544 /* Initialize clocks */
1545 r = radeon_clocks_init(rdev);
1546 if (r) {
1547 return r;
1548 }
1549
1550 r = r600_startup(rdev);
1551 if (r) {
1552 DRM_ERROR("r600 startup failed on resume\n");
1553 return r;
1554 }
1555
62a8ea3f 1556 r = r600_ib_test(rdev);
fc30b8ef
DA		 1557 if (r) {
1558 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1559 return r;
1560 }
1561 return r;
1562}
1563
3ce0a23d
JG		 1564int r600_suspend(struct radeon_device *rdev)
1565{
1566 /* FIXME: we should wait for ring to be empty */
1567 r600_cp_stop(rdev);
bc1a631e 1568 rdev->cp.ready = false;
81cc35bf 1569 r600_wb_disable(rdev);
4aac0473 1570 r600_pcie_gart_disable(rdev);
bc1a631e
DA		 1571 /* unpin shaders bo */
1572 radeon_object_unpin(rdev->r600_blit.shader_obj);
3ce0a23d
JG		 1573 return 0;
1574}
1575
1576/* Plan is to move initialization in that function and use
1577 * helper function so that radeon_device_init pretty much
1578 * do nothing more than calling asic specific function. This
1579 * should also allow to remove a bunch of callback function
1580 * like vram_info.
1581 */
1582int r600_init(struct radeon_device *rdev)
771fe6b9 1583{
3ce0a23d 1584 int r;
771fe6b9 1585
3ce0a23d
JG		 1586 r = radeon_dummy_page_init(rdev);
1587 if (r)
1588 return r;
1589 if (r600_debugfs_mc_info_init(rdev)) {
1590 DRM_ERROR("Failed to register debugfs file for mc !\n");
1591 }
1592 /* This don't do much */
1593 r = radeon_gem_init(rdev);
1594 if (r)
1595 return r;
1596 /* Read BIOS */
1597 if (!radeon_get_bios(rdev)) {
1598 if (ASIC_IS_AVIVO(rdev))
1599 return -EINVAL;
1600 }
1601 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1602 if (!rdev->is_atom_bios) {
1603 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1604 return -EINVAL;
e7d40b9a 1605 }
3ce0a23d
JG		 1606 r = radeon_atombios_init(rdev);
1607 if (r)
1608 return r;
1609 /* Post card if necessary */
1610 if (!r600_card_posted(rdev) && rdev->bios) {
1611 DRM_INFO("GPU not posted. posting now...\n");
1612 atom_asic_init(rdev->mode_info.atom_context);
1613 }
1614 /* Initialize scratch registers */
1615 r600_scratch_init(rdev);
1616 /* Initialize surface registers */
1617 radeon_surface_init(rdev);
5e6dde7e 1618 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1619 r = radeon_clocks_init(rdev);
1620 if (r)
1621 return r;
1622 /* Fence driver */
1623 r = radeon_fence_driver_init(rdev);
1624 if (r)
1625 return r;
1626 r = r600_mc_init(rdev);
b574f251 1627 if (r)
3ce0a23d 1628 return r;
3ce0a23d
JG		 1629 /* Memory manager */
1630 r = radeon_object_init(rdev);
1631 if (r)
1632 return r;
1633 rdev->cp.ring_obj = NULL;
1634 r600_ring_init(rdev, 1024 * 1024);
1635
1636 if (!rdev->me_fw || !rdev->pfp_fw) {
1637 r = r600_cp_init_microcode(rdev);
1638 if (r) {
1639 DRM_ERROR("Failed to load firmware!\n");
1640 return r;
1641 }
1642 }
1643
4aac0473
JG		 1644 r = r600_pcie_gart_init(rdev);
1645 if (r)
1646 return r;
1647
733289c2 1648 rdev->accel_working = true;
bc1a631e
DA		 1649 r = r600_blit_init(rdev);
1650 if (r) {
1651 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1652 return r;
1653 }
1654
fc30b8ef 1655 r = r600_startup(rdev);
3ce0a23d 1656 if (r) {
75c81298
JG		 1657 r600_suspend(rdev);
1658 r600_wb_fini(rdev);
75c81298
JG		 1659 radeon_ring_fini(rdev);
1660 r600_pcie_gart_fini(rdev);
733289c2 1661 rdev->accel_working = false;
3ce0a23d 1662 }
733289c2
JG		 1663 if (rdev->accel_working) {
1664 r = radeon_ib_pool_init(rdev);
1665 if (r) {
1666 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1667 rdev->accel_working = false;
1668 }
62a8ea3f 1669 r = r600_ib_test(rdev);
733289c2
JG		 1670 if (r) {
1671 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1672 rdev->accel_working = false;
1673 }
3ce0a23d
JG		 1674 }
1675 return 0;
1676}
1677
1678void r600_fini(struct radeon_device *rdev)
1679{
1680 /* Suspend operations */
1681 r600_suspend(rdev);
1682
1683 r600_blit_fini(rdev);
1684 radeon_ring_fini(rdev);
81cc35bf 1685 r600_wb_fini(rdev);
4aac0473 1686 r600_pcie_gart_fini(rdev);
3ce0a23d
JG		 1687 radeon_gem_fini(rdev);
1688 radeon_fence_driver_fini(rdev);
1689 radeon_clocks_fini(rdev);
3ce0a23d
JG		 1690 if (rdev->flags & RADEON_IS_AGP)
1691 radeon_agp_fini(rdev);
3ce0a23d 1692 radeon_object_fini(rdev);
e7d40b9a 1693 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1694 kfree(rdev->bios);
1695 rdev->bios = NULL;
1696 radeon_dummy_page_fini(rdev);
1697}
1698
1699
1700/*
1701 * CS stuff
1702 */
1703void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1704{
1705 /* FIXME: implement */
1706 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1707 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1708 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1709 radeon_ring_write(rdev, ib->length_dw);
1710}
1711
1712int r600_ib_test(struct radeon_device *rdev)
1713{
1714 struct radeon_ib *ib;
1715 uint32_t scratch;
1716 uint32_t tmp = 0;
1717 unsigned i;
1718 int r;
1719
1720 r = radeon_scratch_get(rdev, &scratch);
1721 if (r) {
1722 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1723 return r;
1724 }
1725 WREG32(scratch, 0xCAFEDEAD);
1726 r = radeon_ib_get(rdev, &ib);
1727 if (r) {
1728 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1729 return r;
1730 }
1731 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1732 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1733 ib->ptr[2] = 0xDEADBEEF;
1734 ib->ptr[3] = PACKET2(0);
1735 ib->ptr[4] = PACKET2(0);
1736 ib->ptr[5] = PACKET2(0);
1737 ib->ptr[6] = PACKET2(0);
1738 ib->ptr[7] = PACKET2(0);
1739 ib->ptr[8] = PACKET2(0);
1740 ib->ptr[9] = PACKET2(0);
1741 ib->ptr[10] = PACKET2(0);
1742 ib->ptr[11] = PACKET2(0);
1743 ib->ptr[12] = PACKET2(0);
1744 ib->ptr[13] = PACKET2(0);
1745 ib->ptr[14] = PACKET2(0);
1746 ib->ptr[15] = PACKET2(0);
1747 ib->length_dw = 16;
1748 r = radeon_ib_schedule(rdev, ib);
1749 if (r) {
1750 radeon_scratch_free(rdev, scratch);
1751 radeon_ib_free(rdev, &ib);
1752 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1753 return r;
1754 }
1755 r = radeon_fence_wait(ib->fence, false);
1756 if (r) {
1757 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1758 return r;
1759 }
1760 for (i = 0; i < rdev->usec_timeout; i++) {
1761 tmp = RREG32(scratch);
1762 if (tmp == 0xDEADBEEF)
1763 break;
1764 DRM_UDELAY(1);
1765 }
1766 if (i < rdev->usec_timeout) {
1767 DRM_INFO("ib test succeeded in %u usecs\n", i);
1768 } else {
1769 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1770 scratch, tmp);
1771 r = -EINVAL;
1772 }
1773 radeon_scratch_free(rdev, scratch);
1774 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 1775 return r;
1776}
1777
3ce0a23d
JG		 1778
1779
1780
1781/*
1782 * Debugfs info
1783 */
1784#if defined(CONFIG_DEBUG_FS)
1785
1786static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 1787{
3ce0a23d
JG		 1788 struct drm_info_node *node = (struct drm_info_node *) m->private;
1789 struct drm_device *dev = node->minor->dev;
1790 struct radeon_device *rdev = dev->dev_private;
1791 uint32_t rdp, wdp;
1792 unsigned count, i, j;
1793
1794 radeon_ring_free_size(rdev);
1795 rdp = RREG32(CP_RB_RPTR);
1796 wdp = RREG32(CP_RB_WPTR);
1797 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1798 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1799 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1800 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1801 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1802 seq_printf(m, "%u dwords in ring\n", count);
1803 for (j = 0; j <= count; j++) {
1804 i = (rdp + j) & rdev->cp.ptr_mask;
1805 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1806 }
1807 return 0;
1808}
1809
1810static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1811{
1812 struct drm_info_node *node = (struct drm_info_node *) m->private;
1813 struct drm_device *dev = node->minor->dev;
1814 struct radeon_device *rdev = dev->dev_private;
1815
1816 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1817 DREG32_SYS(m, rdev, VM_L2_STATUS);
1818 return 0;
1819}
1820
1821static struct drm_info_list r600_mc_info_list[] = {
1822 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1823 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1824};
1825#endif
1826
1827int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1828{
1829#if defined(CONFIG_DEBUG_FS)
1830 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1831#else
1832 return 0;
1833#endif
771fe6b9 1834}
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